JP7521177B2 - Power Module - Google Patents

Description

This disclosure relates to a power module.

Conventionally, power modules are known in which power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) are mounted on a substrate, and the necessary circuits are configured using the substrate and bonding wires. In such power modules, it is important to optimize the layout of the power semiconductor elements in order to reduce wiring inductance, which causes noise (see Patent Document 1).

JP 2017-55610 A

On the other hand, GaN-FETs (Gallium Nitride Field-Effect Transistors), a power semiconductor element that has been developed in recent years, differ from IGBTs and power MOS (Metal-Oxide-Semiconductor) FETs used in conventional power modules in that all three electrodes are provided on the front surface.

Therefore, even if the layout within a power module optimized for IGBTs or power MOSFETs that also have electrodes on the back side is used as is, it is difficult to sufficiently reduce the wiring inductance that causes noise when a large current flows through the wiring pattern within the power module. In other words, it cannot be said that the chip layout on the power board has been sufficiently optimized in a power module equipped with GaN-FETs.

Therefore, this disclosure proposes a power module that can reduce noise generation by reducing wiring inductance.

A power module according to one aspect of the present disclosure includes a first switching element, a second switching element, a third switching element, a fourth switching element, and a circuit board. The first switching element is connected to a positive terminal and includes a GaN-based switching element. The second switching element is connected between the first switching element and a negative terminal and includes a GaN-based switching element. The third switching element is connected to the positive terminal and includes a GaN-based switching element. The fourth switching element is connected between the third switching element and the negative terminal and includes a GaN-based switching element. The first to fourth switching elements are mounted on the circuit board. The first to fourth switching elements are arranged to surround one point on the circuit board. The drain electrode of the first switching element and the drain electrode of the third switching element are arranged to face each other. The source electrode of the second switching element and the source electrode of the fourth switching element are arranged to face each other.

According to the present disclosure, it is possible to reduce wiring inductance. This makes it possible to reduce noise that occurs when a large current flows through the wiring pattern in the power module.

FIG. 1 is a diagram showing a circuit configuration of a switching element according to the first embodiment. FIG. 2 is a top view showing the configuration of the switching element according to the first embodiment. FIG. 3 is a diagram showing a circuit configuration of the power module according to the first embodiment. FIG. 4 is a diagram showing a circuit configuration of a DC-AC converter. FIG. 5 is a diagram showing a circuit configuration of an interleaved type AC-DC converter with built-in PFC. FIG. 6 is a diagram (1) for explaining points to be noted in order to reduce wiring inductance in the power module according to the first embodiment. FIG. 7 is a diagram (2) for explaining points to be noted in order to reduce the wiring inductance in the power module according to the first embodiment. FIG. 8 is a diagram (1) for explaining an optimal arrangement of the first to fourth switching elements and capacitors in the power module according to the first embodiment. FIG. 9 is a diagram (2) for explaining the optimum arrangement of the first to fourth switching elements and the capacitors in the power module according to the first embodiment. FIG. 10 is a cross-sectional view and a top view showing the configuration of the power module according to the first embodiment. FIG. 11 is a diagram for explaining that the power module according to the first embodiment realizes an optimal arrangement. FIG. 12 is a diagram for explaining the circuit loops L1-1 to L1-4 in the power module according to the first embodiment. FIG. 13 is a diagram for explaining the circuit loop L2 in the power module according to the first embodiment. FIG. 14 is a diagram for explaining the circuit loops L3-1 and L3-2 in the power module according to the first embodiment. FIG. 15 is a diagram (1) for explaining the common impedance in the power module according to the first embodiment. FIG. 16 is a diagram (2) for explaining the common impedance in the power module according to the first embodiment. FIG. 17 is a top view showing the configuration of a power module in a reference example. FIG. 18 is a diagram for explaining circuit loops L1-1 to L1-4 in the power module in the reference example. FIG. 19 is a diagram for explaining a circuit loop L2 in a power module in a reference example. FIG. 20 is a diagram for explaining circuit loops L3-1 and L3-2 in the power module in the reference example. FIG. 21 is a diagram for explaining a common impedance in a power module in a reference example. FIG. 22 is a cross-sectional view showing a configuration of a power module according to Modification 1 of the first embodiment. FIG. 23 is a top view showing the configuration of a power board in a power module according to Modification 1 of the first embodiment. FIG. 24 is a top view showing a configuration of a printed circuit board in a power module according to Modification 1 of the first embodiment. FIG. 25 is a diagram for explaining circuit loops L3-1 and L3-2 in a power module according to the first modification of the first embodiment. FIG. 26 is a top view showing the configuration of a power board in a power module according to Modification 2 of the first embodiment. FIG. 27 is a top view showing a configuration of a printed circuit board in a power module according to Modification 2 of the first embodiment. FIG. 28 is a diagram for explaining circuit loops L3-1 and L3-2 in a power module according to the second modification of the first embodiment. FIG. 29 is a diagram showing a circuit configuration of a power module according to the second embodiment. FIG. 30 is a cross-sectional view and a top view showing the configuration of a power module according to the second embodiment. FIG. 31 is a diagram in which the power module according to the second embodiment is divided into blocks for each circuit having high affinity. FIG. 32 is a diagram in which the power board of the power module according to the second embodiment is divided into blocks in the manner shown in FIG. FIG. 33 is a diagram in which the driver board of the power module according to the second embodiment is divided into blocks in the manner shown in FIG. FIG. 34 is a diagram showing blocks on a power board and blocks on a driver board of the power module according to the second embodiment superimposed on each other. FIG. 35 is a diagram in which the power board of the power module according to the third modification of the second embodiment is divided into blocks in the manner shown in FIG. FIG. 36 is a diagram in which blocks on a power board and blocks on a driver board of a power module according to Modification 3 of the second embodiment are superimposed on each other.

Below, an embodiment of the power module disclosed in the present application will be described in detail with reference to the attached drawings. Note that the present disclosure is not limited to the embodiment shown below. It should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from reality. Furthermore, there may be parts in which the dimensional relationships and ratios differ between the drawings.

Conventionally, power modules are known in which power semiconductor elements such as IGBTs are mounted on a power board, and the necessary circuits are configured using the power board and bonding wires. In such power modules, it is important to optimize the layout of the power semiconductor elements in order to reduce the wiring inductance that causes noise.

On the other hand, GaN-FETs, a power semiconductor element that has been developed in recent years, differ from IGBTs and power MOSFETs used in conventional power modules in that all three electrodes (drain electrode, source electrode, and gate electrode) are provided on the front surface.

Therefore, even if the layout within a power module optimized for IGBTs or power MOSFETs, which have electrodes on the back side, is used as is, it is difficult to sufficiently reduce wiring inductance. In other words, it cannot be said that the chip layout on the circuit board has been sufficiently optimized in power modules equipped with GaN-FETs.

This is because in conventional power semiconductor elements, where the collector electrode and drain electrode are provided on the back surface, wiring is formed to the electrodes on the back surface using the circuit pattern of the power board, whereas in GaN-FETs, where the drain electrode is provided on the front surface, wiring is formed to the drain electrode using a bonding wire.

Therefore, there is hope for technology that can reduce wiring inductance in power modules equipped with GaN-FETs.

<Configuration of switching element>
The present disclosure relates to a power module using a switching element that is a cascade GaN-FET. In order to facilitate understanding of each embodiment of the present disclosure, a cascade GaN-FET applicable to each embodiment will be described with reference to Figures 1 and 2. Figure 1 is a diagram showing a circuit configuration of a switching element Q according to a first embodiment.

The switching element Q according to the first embodiment is configured by cascading a high-voltage FET made of GaN (hereinafter also referred to as a GaN-FET) and a low-voltage FET made of Si (hereinafter also referred to as a Si-FET).

As shown in FIG. 1, inside switching element Q, the source terminal of the GaN-FET (GaN-based switching element) and the drain terminal of the Si-FET (Si-based switching element) are electrically connected, and the source terminal of the Si-FET and the gate terminal of the GaN-FET are electrically connected.

The drain terminal of the GaN-FET becomes the drain electrode D of the switching element Q, the source terminal of the Si-FET becomes the source electrode S of the switching element Q, and the gate terminal of the Si-FET becomes the gate electrode G of the switching element Q.

In a cascade GaN-FET with such a circuit configuration, a normally-on GaN-FET can be operated as a normally-off switching element.

That is, in a cascade GaN-FET, the entire switching element Q can be turned off by inputting a low-level signal to the gate electrode G of the switching element Q (i.e., the gate terminal of the Si-FET).

In addition, in a cascade GaN-FET, the entire switching element Q can be turned on by inputting a high-level signal to the gate electrode G of the switching element Q (i.e., the gate terminal of the Si-FET).

The cascade GaN-FET has high voltage resistance because it can utilize the voltage resistance characteristics of the GaN-FET. Furthermore, the cascade GaN-FET can utilize the characteristics of the low-voltage Si-FET to drive the gate, making it possible to drive the GaN-FET at high voltage without compromising the high speed of the GaN-FET.

Figure 2 is a top view showing the configuration of the switching element Q according to the first embodiment. The switching element Q according to the first embodiment is configured by stacking a rectangular GaN-FET and a rectangular Si-FET that is smaller than the GaN-FET.

The GaN-FET according to the first embodiment has long sides and short sides. A drain electrode D1 is provided on the front surface of the GaN-FET along one of the long sides, and a source electrode S1 is provided along the other long side. In addition, a pair of gate electrodes G1 are provided on the front surface of the GaN-FET near both ends of the source electrode S1.

In addition, a Si-FET according to the first embodiment is provided on the source electrode S1 of the GaN-FET. This Si-FET has a source electrode S2 and a gate electrode G2 on the front surface, and a drain electrode on the back surface.

The source electrode S1 provided on the front surface of the GaN-FET and the drain electrode provided on the back surface of the Si-FET are electrically and mechanically connected with a conductive bonding material such as solder or conductive adhesive. This allows the above-mentioned switching element Q to be configured, which has a drain electrode D, a source electrode S, and a gate electrode G.

The drain electrode D of the switching element Q corresponds to the drain electrode D1 of the GaN-FET, the source electrode S of the switching element Q corresponds to the source electrode S2 of the Si-FET, and the gate electrode G of the switching element Q corresponds to the gate electrode G2 of the Si-FET.

<Circuit configuration of power module (first embodiment)>
Next, the circuit configuration of the power module 1 according to the first embodiment will be described with reference to Fig. 3 to Fig. 9. Fig. 3 is a diagram showing the circuit configuration of the power module 1 according to the first embodiment.

As shown in FIG. 3, the power module 1 according to the first embodiment includes a first switching element Q1, a second switching element Q2, a third switching element Q3, a fourth switching element Q4, and a capacitor C1.

The first to fourth switching elements Q1 to Q4 are all configured with the switching element Q, which is the above-mentioned cascade-type GaN-FET, and have approximately the same breakdown voltage characteristics and switching characteristics.

The drain terminal of the first switching element Q1 is connected to the positive terminal P, and the source terminal of the first switching element Q1 is connected to the drain terminal of the second switching element Q2. In addition, the gate terminal of the first switching element Q1 is connected to the gate terminal Q1G, and the source terminal of the first switching element Q1 is connected to the source terminal Q1S.

The drain terminal of the second switching element Q2 is connected to the source terminal of the first switching element Q1, and the source terminal of the second switching element Q2 is connected to the negative terminal N. In addition, the gate terminal of the second switching element Q2 is connected to the gate terminal Q2G, and the source terminal of the second switching element Q2 is connected to the source terminal Q2S.

The drain terminal of the third switching element Q3 is connected to the positive terminal P, and the source terminal of the third switching element Q3 is connected to the drain terminal of the fourth switching element Q4. In addition, the gate terminal of the third switching element Q3 is connected to the gate terminal Q3G, and the source terminal of the third switching element Q3 is connected to the source terminal Q3S.

The drain terminal of the fourth switching element Q4 is connected to the source terminal of the third switching element Q3, and the source terminal of the fourth switching element Q4 is connected to the negative terminal N. In addition, the gate terminal of the fourth switching element Q4 is connected to the gate terminal Q4G, and the source terminal of the fourth switching element Q4 is connected to the source terminal Q4S.

Capacitor C1 is connected between positive terminal P and negative terminal N. Power module 1 also has output terminals OUT1 and OUT2.

The output terminal OUT1 is connected between the source terminal of the first switching element Q1 and the drain terminal of the second switching element Q2. The output terminal OUT2 is connected between the source terminal of the third switching element Q3 and the drain terminal of the fourth switching element Q4.

The power module 1 is also provided with a thermistor TH used as a temperature sensor. Two terminals TH1 and TH2 are connected to the thermistor TH.

The power module 1 having such a circuit configuration can be applied to power conversion devices having various circuit configurations. For example, by using the power module 1 according to the first embodiment in the DC-AC converter shown in FIG. 4, highly efficient DC-AC conversion can be achieved. FIG. 4 is a diagram showing the circuit configuration of the DC-AC converter.

In addition, highly efficient AC-DC conversion can be achieved by using the power module 1 according to the first embodiment in an AC-DC converter with built-in interleaved PFC as shown in FIG. 5. FIG. 5 is a diagram showing the circuit configuration of an AC-DC converter with built-in interleaved PFC.

In power conversion devices such as those shown in Figures 4 and 5, in order to reduce the noise generated by the large current intermittently caused by the on/off of the switching elements and to achieve more efficient power conversion, it is important to reduce the wiring inductance within the power module 1. Therefore, the points to be noted in order to reduce the wiring inductance within the power module 1 will be explained with reference to Figures 6 and 7.

Figure 6 is a diagram (1) for explaining points to be noted in order to reduce wiring inductance in the power module 1 according to the first embodiment. As shown in Figure 6, inside the power module 1, circuit loops of various paths are formed by the current flow shown by the dotted lines.

For example, within the power module 1, a circuit loop L1-1 is formed in which the current output from the drive circuit DR1 that drives the first switching element Q1 returns in the following order: the gate terminal of the first switching element Q1, the source terminal of the first switching element Q1, and the drive circuit DR1.

In addition, within the power module 1, a circuit loop L1-2 is formed in which the current output from the drive circuit DR2 that drives the second switching element Q2 returns in the following order: the gate terminal of the second switching element Q2, the source terminal of the second switching element Q2, and the drive circuit DR2.

In addition, within the power module 1, a circuit loop L1-3 is formed in which the current output from the drive circuit DR3 that drives the third switching element Q3 returns in the following order: the gate terminal of the third switching element Q3, the source terminal of the third switching element Q3, and the drive circuit DR3.

In addition, within the power module 1, a circuit loop L1-4 is formed in which the current output from the drive circuit DR4 that drives the fourth switching element Q4 returns in the following order: the gate terminal of the fourth switching element Q4, the source terminal of the fourth switching element Q4, and the drive circuit DR4.

In addition, within the power module 1, a circuit loop L2 is formed in which a current flows in sequence from the positive terminal P to the first switching element Q1, the second switching element Q2, the negative terminal N, the fourth switching element Q4, the third switching element Q3, and the positive terminal P.

In addition, within the power module 1, a circuit loop L3-1 is formed in which a current flows in sequence from the capacitor C1 to the positive terminal P, the first switching element Q1, the second switching element Q2, the negative terminal N, and the capacitor C1.

In addition, within the power module 1, a circuit loop L3-2 is formed in which a current flows in sequence from the capacitor C1 to the positive terminal P, the third switching element Q3, the fourth switching element Q4, the negative terminal N, and the capacitor C1.

In the power module 1 according to the first embodiment, the lengths of the circuit loops L1-1 to L1-4, L2, L3-1, and L3-2 described above are all made as short as possible, and the areas contained within these circuit loops (loop areas) are all made as small as possible, thereby reducing the wiring inductance.

Figure 7 is a diagram (2) for explaining points to be noted in order to reduce wiring inductance in the power module 1 according to the first embodiment. As shown in Figure 7, a large current line IL is formed in the first switching element Q1 in the power module 1, which passes a large current from the drain terminal to the source terminal.

In addition, a small current line IS is formed in the first switching element Q1 in the power module 1, which passes a control signal from the gate terminal to the source terminal.

In the power module 1 according to the first embodiment, the common impedance CI of the portion through which the large current line IL and the small current line IS flow in common is minimized, thereby reducing the wiring inductance.

Note that while the example in Figure 7 shows the first switching element Q1, the same can be said for the second switching element Q2 to the fourth switching element Q4. By making this common impedance CI as small as possible, the wiring inductance can be reduced.

Next, based on the points to be noted so far, specific means for reducing the wiring inductance within the power module 1 will be explained with reference to Figures 8 and 9.

Figure 8 is a diagram (1) for explaining the optimal arrangement of the first to fourth switching elements Q1 to Q4 and the capacitor C1 in the power module 1 according to the first embodiment. In this disclosure, as shown in Figure 8, the wiring section formed inside the power module 1 is divided into several parts.

Specifically, the wiring section extending from the capacitor C1 via the positive terminal P to the drain terminal of the first switching element Q1 or the drain terminal of the third switching element Q3 is defined as the network P-NET. In addition, the wiring section extending from the gate terminal Q1G to the source terminal Q1S via the gate terminal and source terminal of the first switching element Q1 is defined as the network Q1G-NET.

The wiring section extending from the output terminal OUT1 to the source terminal of the first switching element Q1 and the drain terminal of the second switching element Q2 is referred to as a network OUT1-NET. The wiring section extending from the gate terminal Q2G to the source terminal Q2S via the gate terminal and source terminal of the second switching element Q2 is referred to as a network Q2G-NET.

The wiring section extending from the gate terminal Q3G through the gate terminal and source terminal of the third switching element Q3 to the source terminal Q3S is referred to as a network Q3G-NET. The wiring section extending from the output terminal OUT2 to the source terminal of the third switching element Q3 and the drain terminal of the fourth switching element Q4 is referred to as a network OUT2-NET.

The wiring section that runs from the gate terminal Q4G through the gate terminal and source terminal of the fourth switching element Q4 to the source terminal Q4S is defined as a network Q4G-NET. The wiring section that runs from the capacitor C1 through the negative terminal N to the source terminal of the second switching element Q2 or the source terminal of the fourth switching element Q4 is defined as a network N-NET.

Figure 9 is a diagram (2) for explaining the optimal arrangement of the first to fourth switching elements Q1 to Q4 and the capacitor C1 in the power module 1 according to the first embodiment. As shown in Figure 9, in the power module 1 according to the first embodiment, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are arranged to surround a point on the surface (the upper surface of the power board 10 (see Figure 10) described later) on which the above-mentioned components are arranged. The capacitor C1 is then arranged at this point.

This point may be any position on the surface on which the above-mentioned components are arranged, but by making this point the center 4 of the power module 1, the width and length of the wiring pattern through which a large current flows on the power board 10 described below can be equalized, and the four switching elements, the first to fourth switching elements Q1 to Q4, can be arranged in a balanced manner, thereby suppressing an increase in wiring inductance due to an extremely long wiring pattern and ensuring a good current path for the flow of a large current. Note that each embodiment of the present invention describes an example in which each switching element and capacitor C1 are arranged based on this center 4.

If the first to fourth switching elements Q1 to Q4 are arranged to surround a point on the surface on which the above-mentioned components are arranged, in other words, if the first switching element Q1, the third switching element Q3, the fourth switching element Q4, and the second switching element Q2 are arranged in clockwise order at the four vertices of a rectangle, the capacitor C1 will be placed in the center of the rectangle (the point where the diagonals of the rectangle intersect).

Note that capacitor C1 does not necessarily have to be placed in the center of this rectangle; it can simply be placed so that capacitor C1 is surrounded by the first to fourth switching elements Q1 to Q4. This places C1 relatively close to and at equal distances from each switching element, suppressing the increase in wiring inductance caused by an extremely long wiring pattern and ensuring a good current path for passing large currents.

In addition, in the rectangle formed by the first to fourth switching elements Q1 to Q4, one side connecting the first switching element Q1 and the third switching element Q3 and another side connecting the second switching element Q2 and the fourth switching element Q4 are approximately parallel.

In addition, in the power module 1 according to the first embodiment, the drain electrode D of the first switching element Q1 and the drain electrode D of the third switching element Q3 are arranged to face each other.

In addition, in the power module 1 according to the first embodiment, the source electrode S of the second switching element Q2 and the source electrode S of the fourth switching element Q4 are arranged to face each other.

In the power module 1 according to the first embodiment, a network P-NET is arranged in the area sandwiched between the capacitor C1, the first switching element Q1, and the third switching element Q3. Also, a network N-NET is arranged in the area sandwiched between the capacitor C1, the second switching element Q2, and the fourth switching element Q4.

When the first switching element Q1 and the second switching element Q2 are used as references, the network OUT1-NET is disposed in the area opposite the capacitor C1. When the third switching element Q3 and the fourth switching element Q4 are used as references, the network OUT2-NET is disposed in the area opposite the capacitor C1.

The network Q1G-NET is placed in the area between the first switching element Q1, the network P-NET, and the network OUT1-NET. The network Q2G-NET is placed in the area between the second switching element Q2, the network N-NET, and the network OUT1-NET.

The network Q3G-NET is placed in the area between the third switching element Q3, the network P-NET, and the network OUT2-NET. The network Q4G-NET is placed in the area between the fourth switching element Q4, the network N-NET, and the network OUT2-NET.

Furthermore, the gate electrode G of the first switching element Q1 is arranged close to the network Q1G-NET, the gate electrode G of the second switching element Q2 is arranged close to the network Q2G-NET, the gate electrode G of the third switching element Q3 is arranged close to the network Q3G-NET, and the gate electrode G of the fourth switching element Q4 is arranged close to the network Q4G-NET.

<Configuration of Power Module (First Embodiment)>
Next, a power module 1 to which the optimum arrangement shown in Fig. 8 is applied will be described with reference to Fig. 10 and Fig. 11. Fig. 10 is a cross-sectional view (Fig. 10(a)) and a top view (Fig. 10(b)) showing the configuration of the power module 1 according to the first embodiment.

As shown in FIG. 10(a), the power module 1 according to the first embodiment includes a power board 10, a case 11, a lid portion 12, and a silicone gel 13. The power board 10 is an example of a circuit board.

The power board 10 is composed of a circuit board with high heat resistance and high heat dissipation properties, such as a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazing) board. The front surface of the power board 10 is equipped with the first to fourth switching elements Q1 to Q4, a capacitor C1, and the like.

The case 11 has a frame shape and is provided so as to surround the front surface of the power board 10. The case 11 houses the power board 10 and each element mounted on the power board 10. The case 11 also has mounting holes formed therein that are used, for example, when fixing the power module 1 inside the power conversion device.

The case 11 is made of, for example, polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin, etc.

The lid 12 covers the front surface of the power board 10 housed in the case 11 and is provided to close the upper part of the frame-shaped case 11. The lid 12 is formed, for example, from the same resin as the case 11. Silicon gel 13 is filled inside the case 11 and seals the various elements mounted on the front surface of the power board 10.

The power board 10 and the case 11, and the case 11 and the lid 12 are bonded together with an adhesive (not shown).

As shown in FIG. 10(b), a capacitor C1 and first to fourth switching elements Q1 to Q4 are mounted on the front surface of the power board 10. The capacitor C1 is disposed in the central portion 4 of the power board 10.

The power board 10 also has the first to fourth switching elements Q1 to Q4 arranged around the capacitor C1 arranged in the central portion 4. For example, if the first switching element Q1, the third switching element Q3, the fourth switching element Q4, and the second switching element Q2 are arranged in clockwise order at the four vertices of a trapezoid, the capacitor C1 is arranged in the central portion 4 where the diagonals of the trapezoid intersect.

In this trapezoid formed by the first to fourth switching elements Q1 to Q4, the first switching element Q1 and the third switching element Q3 are provided at both ends of the upper base, and the second switching element Q2 and the fourth switching element Q4 are provided at both ends of the lower base.

Also, as shown in FIG. 10(b), the drain electrode D of the first switching element Q1 (see FIG. 9) and the drain electrode D of the third switching element Q3 are arranged to face each other, and the source electrode S of the second switching element Q2 (see FIG. 9) and the source electrode S of the fourth switching element Q4 are arranged to face each other.

Circuit patterns 21 to 32 that form the wiring section are provided on the front surface of the power board 10. Note that since the circuit patterns 21 to 32 are provided on an insulating layer included in the power board 10, the circuit patterns 21 to 32 are not electrically connected to each other.

These circuit patterns 21 to 32 will be described with reference to FIG. 11. FIG. 11 is a diagram for explaining that the power module 1 according to the first embodiment achieves an optimal arrangement.

A circuit pattern 21 is arranged in the area between the capacitor C1, the first switching element Q1, and the third switching element Q3. This circuit pattern 21 corresponds to the network P-NET described above.

When the first switching element Q1 and the second switching element Q2 are used as references, a circuit pattern 22 is formed in the area opposite the capacitor C1. Most of this circuit pattern 22 corresponds to the network OUT1-NET described above.

Circuit patterns 23 and 24 are arranged in the area between the first switching element Q1 and circuit patterns 21 and 22. These circuit patterns 23 and 24 and the part of circuit pattern 22 adjacent to circuit pattern 24 are the parts that correspond to the network Q1G-NET described above.

A circuit pattern 25 is formed in the area between the capacitor C1, the second switching element Q2, and the fourth switching element Q4. Most of this circuit pattern 25 corresponds to the network N-NET described above.

Circuit patterns 26 and 27 are arranged in the area between the second switching element Q2, circuit pattern 25, and circuit pattern 22. Such circuit patterns 26 and 27 and a part of circuit pattern 25 adjacent to circuit patterns 26 and 27 correspond to the circuit network Q2G-NET described above.

When the third switching element Q3 and the fourth switching element Q4 are used as references, a circuit pattern 28 is arranged in the area opposite the capacitor C1. Most of this circuit pattern 28 corresponds to the network OUT2-NET described above.

Circuit patterns 29 and 30 are arranged in the area between the third switching element Q3, circuit pattern 21, and circuit pattern 28. Such circuit patterns 29 and 30 and the part of circuit pattern 28 adjacent to circuit pattern 30 are the parts corresponding to the network Q3G-NET described above.

Circuit patterns 31 and 32 are arranged in the area between the fourth switching element Q4, circuit pattern 25, and circuit pattern 28. These circuit patterns 31 and 32 and the part of circuit pattern 25 adjacent to circuit patterns 31 and 32 are the parts that correspond to the above-mentioned network Q4G-NET.

As explained above, in the power module 1 according to the first embodiment, the capacitor C1, the first to fourth switching elements Q1 to Q4, and each wiring section are arranged in the optimal manner shown in FIG. 9.

The specific wiring configuration for the circuit patterns 21 to 32 is as follows. A capacitor C1 is provided between the circuit patterns 21 and 25, and the circuit patterns 21 and 25 are electrically connected via the capacitor C1.

In addition, a pair of positive terminals P are provided on the opposite side of the circuit pattern 21 to the capacitor C1 (one of the long sides of the power board 10).

The drain electrode D of the first switching element Q1 (see FIG. 9) and the drain electrode D of the third switching element Q3 are electrically connected to the circuit pattern 21 via a bonding wire W (see FIG. 10(a)).

The source electrode S of the first switching element Q1 (see FIG. 9) and the gate electrode G1 of the GaN-FET included in the first switching element Q1 (see FIG. 2) are electrically connected to the circuit pattern 22 via a bonding wire W.

In addition, a source terminal Q1S is provided in a portion of circuit pattern 22 adjacent to circuit pattern 24, and a pair of output terminals OUT1 are provided in portions of circuit pattern 22 adjacent to circuit patterns 26 and 27.

In addition, the drain electrode D of the second switching element Q2 is electrically connected to a portion of the circuit pattern 22 adjacent to the output terminal OUT1 via a bonding wire W.

The gate electrode G of the first switching element Q1 (see FIG. 9) is electrically connected to the circuit pattern 23 via a bonding wire W. The gate electrode G of the first switching element Q1 is disposed adjacent to the network Q1G-NET.

In addition, a resistor R1 (see FIG. 10(b)) is provided between the circuit pattern 23 and the circuit pattern 22, and the circuit pattern 23 and the circuit pattern 22 are electrically connected via the resistor R1.

A gate terminal Q1G is provided on the circuit pattern 24. A resistor R1 is provided between the circuit pattern 24 and the circuit pattern 23, and the circuit pattern 24 and the circuit pattern 23 are electrically connected via the resistor R1.

A pair of negative terminals N are provided on the circuit pattern 25 on the side opposite the capacitor C1 (the other long side of the power board 10). In addition, source terminals Q2S and Q4S are provided on the circuit pattern 25 on the outside of the pair of negative terminals N.

The source electrode S of the second switching element Q2 and the gate electrode G1 of the GaN-FET included in the second switching element Q2 are also electrically connected to the circuit pattern 25 via a bonding wire W.

The source electrode S of the fourth switching element Q4 and the gate electrode G1 of the GaN-FET included in the fourth switching element Q4 are also electrically connected to the circuit pattern 25 via a bonding wire W.

The gate electrode G of the second switching element Q2 is electrically connected to the circuit pattern 26 via a bonding wire W. The gate electrode G of the second switching element Q2 is disposed close to the network Q2G-NET.

In addition, a resistor R2 (see FIG. 10(b)) is provided between the circuit patterns 26 and 25, and the circuit patterns 26 and 25 are electrically connected via the resistor R2.

A gate terminal Q2G is provided on the circuit pattern 27. A resistor R2 is provided between the circuit pattern 27 and the circuit pattern 26, and the circuit pattern 27 and the circuit pattern 26 are electrically connected via the resistor R2.

The source electrode S of the third switching element Q3 and the gate electrode G1 of the GaN-FET included in the third switching element Q3 are electrically connected to the circuit pattern 28 via a bonding wire W.

In addition, a source terminal Q3S is provided in a portion of circuit pattern 28 adjacent to circuit pattern 30, and a pair of output terminals OUT2 are provided in portions of circuit pattern 28 adjacent to circuit patterns 31 and 32.

The drain electrode D of the fourth switching element Q4 is electrically connected to a portion of the circuit pattern 28 adjacent to the output terminal OUT2 via a bonding wire W.

The gate electrode G of the third switching element Q3 is electrically connected to the circuit pattern 29 via a bonding wire W. The gate electrode G of the third switching element Q3 is disposed close to the network Q3G-NET.

In addition, a resistor R3 (see FIG. 10(b)) is provided between the circuit pattern 29 and the circuit pattern 28, and the circuit pattern 29 and the circuit pattern 28 are electrically connected via the resistor R3.

A gate terminal Q3G is provided on the circuit pattern 30. A resistor R3 is provided between the circuit pattern 30 and the circuit pattern 29, and the circuit pattern 30 and the circuit pattern 29 are electrically connected via the resistor R3.

The gate electrode G of the fourth switching element Q4 is electrically connected to the circuit pattern 31 via a bonding wire W. The gate electrode G of the fourth switching element Q4 is disposed close to the network Q4G-NET.

In addition, a resistor R4 (see FIG. 10(b)) is provided between the circuit pattern 31 and the circuit pattern 25, and the circuit pattern 31 and the circuit pattern 25 are electrically connected via the resistor R4.

A gate terminal Q4G is provided on the circuit pattern 32. A resistor R4 is provided between the circuit pattern 32 and the circuit pattern 31, and the circuit pattern 32 and the circuit pattern 31 are electrically connected via the resistor R4.

In addition, the area sandwiched between the pair of negative terminals N is provided with a thermistor TH and terminals TH1 and TH2 that are respectively connected to a pair of electrodes of the thermistor TH.

The positive terminal P, negative terminal N, output terminals OUT1, OUT2, gate terminals Q1G to Q4G, source terminals Q1S to Q4S, and terminals TH1 and TH2 are all made of conductive materials such as metal, and are electrically and mechanically connected to each circuit pattern with conductive bonding materials such as solder or conductive adhesive.

Figure 12 is a diagram for explaining the circuit loops L1-1 to L1-4 in the power module 1 according to the first embodiment. As shown in Figure 12, in the power module 1 according to the first embodiment, the lengths of the circuit loops L1-1 to L1-4 are made as short as possible, and the loop areas of the circuit loops L1-1 to L1-4 are made as small as possible.

Figure 13 is a diagram for explaining the circuit loop L2 in the power module 1 according to the first embodiment. As shown in Figure 13, in the power module 1 according to the first embodiment, the length of the circuit loop L2 is as short as possible, and the loop area of the circuit loop L2 is as small as possible.

As described above, the length of each of the circuit loops L1-1 to L1-4 and circuit loop L2 in the power module 1 is made as short as possible, and the loop area of each is made as small as possible. Note that since the circuit loops L1-1 to L1-4 and circuit loop L2 do not pass through the capacitor C1, the effect of reducing the wiring inductance in each circuit loop can be obtained even if the capacitor C1 is not installed.

Figure 14 is a diagram for explaining the circuit loops L3-1, L3-2 in the power module 1 according to the first embodiment. As shown in Figure 14, in the power module 1 according to the first embodiment, the lengths of the circuit loops L3-1, L3-2 passing through the capacitor C1 are made as short as possible, and the loop areas of the circuit loops L3-1, L3-2 are made as small as possible. Therefore, the power module 1 equipped with the capacitor C1 has the effect of reducing the wiring inductance in the circuit loops in addition to the above effects.

Figure 15 is a diagram (1) for explaining the common impedance CI within the power module 1 according to the first embodiment.

As shown in FIG. 15, in the first switching element Q1, the location where the bonding wire W (see FIG. 10(a)) extending from the source electrode S2 (see FIG. 2) of the Si-FET (i.e., the source electrode S (see FIG. 2) of the first switching element Q1) is connected to the circuit pattern 22 is defined as the first connection portion 41.

In addition, in the first switching element Q1, the location where the bonding wire W extending from the gate electrode G1 (see FIG. 2) of the GaN-FET is connected to the circuit pattern 22 is defined as the second connection portion 42.

In the first embodiment, the first connection portion 41 is preferably closer to the short side (left side in FIG. 15) of the power board 10 than the second connection portion 42. In other words, the first connection portion 41 is preferably located farther away from the first switching element Q1 to which they are connected than the second connection portion 42. This makes it possible to minimize the overlap (i.e., common impedance CI (see FIG. 7)) between the large current line IL flowing from the drain terminal to the source terminal of the first switching element Q1 and the small current line IS flowing from the gate electrode G1 to the source terminal of the GaN-FET included in the first switching element Q1.

Therefore, according to the first embodiment, it is possible to reduce the common impedance CI and reduce the effect of noise generated in the large current line IL on the small current line IS.

In addition, in the first embodiment, a notch 43 may be provided at a predetermined location in the circuit pattern 22 where the first connection portion 41 and the second connection portion 42 are provided.

The notch 43 is formed along the long side of the power board 10 and is provided so as to face the second connection part 42. In other words, the notch 43 is provided so as to extend between the first connection part 41 and the second connection part 42.

As a result, as shown in FIG. 15, the small current line IS flowing from the second connection part 42 toward the source terminal Q1S can be formed away from the first connection part 41 (so as to bypass the first connection part 41).

In other words, in the first embodiment, by providing a notch 43 in the circuit pattern 22, the overlap between the large current line IL and the small current line IS can be further reduced, thereby reducing the common impedance CI. Therefore, according to the first embodiment, the effect of noise generated in the large current line IL on the small current line IS can be reduced.

Note that while FIG. 15 shows the first switching element Q1, the common impedance CI can also be minimized for the third switching element Q3 by providing the first connection portion 41, the second connection portion 42, and the notch portion 43 in the circuit pattern 28.

Figure 16 is a diagram (2) for explaining the common impedance CI within the power module 1 according to the first embodiment.

As shown in FIG. 16, in the second switching element Q2, the location where the bonding wire W (see FIG. 10(a)) extending from the source electrode S2 (see FIG. 2) of the Si-FET (i.e., the source electrode S (see FIG. 2) of the second switching element Q2) is connected to the circuit pattern 25 is defined as the third connection portion 44.

In addition, in the second switching element Q2, the location where the bonding wire W extending from the gate electrode G1 (see FIG. 2) of the GaN-FET is connected to the circuit pattern 25 is defined as the fourth connection portion 45.

In the first embodiment, the third connection portion 44 is preferably closer to the center of the power board 10 than the fourth connection portion 45. In other words, the third connection portion 44 is preferably located farther away from the second switching element Q2 to which they are connected than the fourth connection portion 45. This makes it possible to minimize the overlap (i.e., common impedance CI (see FIG. 7)) between the large current line IL flowing from the drain terminal to the source terminal of the second switching element Q2 and the small current line IS flowing from the gate electrode G1 to the source terminal of the GaN-FET included in the second switching element Q2.

Therefore, according to the first embodiment, it is possible to reduce the common impedance CI and reduce the effect of noise generated in the large current line IL on the small current line IS.

In addition, in the first embodiment, a notch 46 may be provided at a predetermined location in the circuit pattern 25 where the third connection portion 44 and the fourth connection portion 45 are provided.

The notch 46 is formed toward the center of the power board 10 and is provided to face the fourth connection portion 45. In other words, the notch 46 is provided to extend between the third connection portion 44 and the fourth connection portion 45.

As a result, as shown in FIG. 16, the small current line IS flowing from the fourth connection part 45 toward the source terminal Q2S can be formed away from the third connection part 44 (so as to bypass the third connection part 44).

That is, in the first embodiment, by providing a notch 46 in the circuit pattern 25, the overlap between the large current line IL and the small current line IS can be further reduced, thereby reducing the common impedance CI. Therefore, according to the first embodiment, the common impedance CI can be reduced, and the effect of noise generated in the large current line IL on the small current line IS can be reduced.

Note that while FIG. 16 shows the second switching element Q2, the common impedance CI can also be minimized by providing the third connection portion 44, the fourth connection portion 45, and the notch portion 46 in the circuit pattern 25 in the fourth switching element Q4.

The power module 1 according to the first embodiment is preferably the same size as EasyPACK, which is known as a standard package on the market. This makes it possible to reduce wiring inductance in a power module 1 with a standard package on the market.

Next, we will compare the wiring inductance between the power module 1 according to the first embodiment described so far and a power module 100 according to a reference example that is arranged based on a different concept from that of the first embodiment. Figure 17 is a top view showing the configuration of the power module 100 according to the reference example.

This reference example differs significantly from the first embodiment in that the source electrode S (see FIG. 9) of the first switching element Q1 and the drain electrode D (see FIG. 9) of the second switching element Q2 face each other, and the source electrode S of the third switching element Q3 and the drain electrode D of the fourth switching element Q4 are arranged to face each other.

Figure 18 is a diagram for explaining the circuit loops L1-1 to L1-4 in the power module 100 in the reference example. As shown in Figure 18, in the power module 100 in the reference example, the lengths of the circuit loops L1-1 to L1-4 are longer than in the first embodiment, and the loop areas of the circuit loops L1-1 to L1-4 are larger.

Figure 19 is a diagram for explaining the circuit loop L2 in the power module 100 in the reference example. As shown in Figure 19, in the power module 100 in the reference example, the length of the circuit loop L2 is longer and the loop area of the circuit loop L2 is larger than in the first embodiment.

Figure 20 is a diagram for explaining the circuit loops L3-1 and L3-2 in the power module 100 in the reference example. As shown in Figure 20, in the power module 100 in the reference example, the lengths of the circuit loops L3-1 and L3-2 are longer than in the first embodiment, and the loop areas of the circuit loops L3-1 and L3-2 are larger.

That is, in the power module 1 according to the first embodiment, the lengths of the circuit loops L1-1 to L1-4, L2, L3-1, and L3-2 are shorter and the loop areas of these circuit loops are smaller than those of the power module 100 of the reference example. As a result, in the first embodiment, the wiring inductance of the power module 1 can be reduced.

Figure 21 is a diagram to explain the common impedance CI within the power module 100 in the reference example.

As shown in FIG. 20, in the reference example, in the first switching element Q1, a bonding wire W (see FIG. 10(a)) extending from the source electrode S2 (see FIG. 2) of the Si-FET and a bonding wire W extending from the gate electrode G1 (see FIG. 2) of the GaN-FET are joined in a line on the circuit pattern 22.

As a result, in the power module 100 of the reference example, the overlap between the large current line IL and the small current line IS (i.e., the common impedance CI) is greater than in the first embodiment.

That is, the power module 1 according to the first embodiment has a smaller common impedance CI than the power module 100 of the reference example. As a result, in the first embodiment, the wiring inductance of the power module 1 can be reduced.

<Modification of the First Embodiment>
Up to this point, an example has been shown in which the first to fourth switching elements Q1 to Q4 and the capacitor C1 are mounted on the same power board 10, but the first to fourth switching elements Q1 to Q4 and the capacitor C1 do not have to be mounted on the same power board 10. For example, the capacitor C1 may be provided outside the power module 1.

Figure 22 is a cross-sectional view showing the configuration of a power module 1 according to a first modified example of the first embodiment. In the following examples, the same parts as those in the first embodiment are designated by the same reference numerals, and redundant explanations will be omitted.

As shown in FIG. 22, the power module 1 according to the first modification includes a printed circuit board 2 in addition to the components constituting the power module 1 according to the first embodiment. The printed circuit board 2 is disposed so as to face the power board 10 via the lid portion 12.

Figure 23 is a top view showing the configuration of the power board 10 in the power module 1 according to Modification 1 of the first embodiment. As shown in Figure 23, the power board 10 according to Modification 1 does not have a capacitor C1.

Figure 24 is a top view showing the configuration of the printed circuit board 2 in the power module 1 according to the first modification of the first embodiment. As shown in Figure 24, in the power module 1 according to the first modification, a capacitor C1 is provided on the printed circuit board 2.

The capacitor C1 is provided in the central portion 4 of the power board 10 in a plan view. That is, in the first modification, the capacitor C1 is provided above the central portion 4 of the power board 10.

As in the first embodiment, the first to fourth switching elements Q1 to Q4 are arranged to surround the capacitor C1 located in the central portion 4 in a plan view.

On the printed circuit board 2, a circuit pattern 51 is provided at a position facing the circuit pattern 21 (see FIG. 23) of the power board 10, and a circuit pattern 52 is provided at a position facing the circuit pattern 25 (see FIG. 23) of the power board 10.

A capacitor C1 is provided between the circuit patterns 51 and 52, and the circuit patterns 51 and 52 are electrically connected via the capacitor C1. The circuit pattern 51 is also electrically connected to a pair of positive terminals P, and the circuit pattern 52 is electrically connected to a pair of negative terminals N.

Figure 25 is a diagram for explaining the circuit loops L3-1, L3-2 in the power module 1 according to the first modification of the first embodiment. As shown in Figure 25, in the power module 1 according to the first modification, the lengths of the circuit loops L3-1, L3-2 are shorter and the loop areas of the circuit loops L3-1, L3-2 are smaller than those of the power module 100 of the reference example.

In the power module 1 according to the first modification, the circuit loops L1-1 to L1-4 and the circuit loop L2 are the same as those shown in Figures 12 and 13.

In other words, in the power module 1 according to the first modification, the lengths of the circuit loops L1-1 to L1-4, L2, L3-1, and L3-2 are all shorter and the loop areas of these circuit loops are all smaller than in the power module 100 of the reference example. Therefore, according to the first modification, the wiring inductance of the power module 1 can be reduced.

Figure 26 is a top view showing the configuration of the power board 10 in the power module 1 according to the second modification of the first embodiment, and Figure 27 is a top view showing the configuration of the printed circuit board 2 in the power module 1 according to the second modification of the first embodiment.

As shown in FIG. 26, the power board 10 according to the second modification differs from the first modification in the locations where the pair of positive terminals P and the pair of negative terminals N are provided.

Specifically, a pair of positive terminals P are provided on the circuit pattern 21 at locations adjacent to the central portion 4 of the power board 10. Also, a pair of negative terminals N are provided on the circuit pattern 25 at locations adjacent to the central portion 4 of the power board 10.

This allows a pair of positive terminals P and a pair of negative terminals N to be placed close to the capacitor C1 on the printed circuit board 2, as shown in FIG. 27.

As a result, as shown in Figure 28, the length of the circuit loops L3-1 and L3-2 can be shortened as much as possible, and the loop area of the circuit loops L3-1 and L3-2 can be reduced as much as possible. Figure 28 is a diagram for explaining the circuit loops L3-1 and L3-2 in the power module 1 according to the second modification of the first embodiment.

That is, in the power module 1 according to the modified example 2, the lengths of the circuit loops L1-1 to L1-4, L2, L3-1, and L3-2 are all as short as possible, and the loop areas of these circuit loops are all as small as possible. Therefore, according to the modified example 2, the wiring inductance of the power module 1 can be further reduced compared to the power module 100 of the reference example.

Second Embodiment
Next, the power module 1 according to the second embodiment will be described with reference to Fig. 29 to Fig. 34. Fig. 29 is a diagram showing the circuit configuration of the power module 1 according to the second embodiment.

As shown in FIG. 29, the power module 1 of the second embodiment includes a power board 10 and a driver board 3. Note that the circuit configuration of the power board 10 is similar to that of the first embodiment, so a detailed description is omitted.

The driver board 3 has drive circuits DR1 to DR4 and an interface circuit IF.

The drive circuit DR1 is connected to the gate terminal Q1G and the source terminal Q1S, and drives the first switching element Q1 via the gate terminal Q1G and the source terminal Q1S. A predetermined control signal is input to the drive circuit DR1 from the interface circuit IF, and a predetermined control voltage is input from the power supply input terminal VU1.

The drive circuit DR2 is connected to the gate terminal Q2G and the source terminal Q2S, and drives the second switching element Q2 via the gate terminal Q2G and the source terminal Q2S. A predetermined control signal and a predetermined control voltage are input to the drive circuit DR2 from the interface circuit IF.

The drive circuit DR3 is connected to the gate terminal Q3G and the source terminal Q3S, and drives the third switching element Q3 via the gate terminal Q3G and the source terminal Q3S. A predetermined control signal is input to the drive circuit DR3 from the interface circuit IF, and a predetermined control voltage is input from the power supply input terminal VU2.

The drive circuit DR4 is connected to the gate terminal Q4G and the source terminal Q4S, and drives the fourth switching element Q4 via the gate terminal Q4G and the source terminal Q4S. A predetermined control signal and a predetermined control voltage are input to the drive circuit DR4 from the interface circuit IF.

A specific control signal is input to the interface circuit IF from the outside via interface terminals IF1 to IFn. A specific control voltage is also input to the interface circuit IF from the power supply input terminals VL1 and VL2. The specific control voltages input from the power supply input terminals VL1 and VL2 are voltages for driving the drive circuits DR2 and DR4, respectively.

Figure 30 is a cross-sectional view (Figure 30(a)) and a top view (Figure 30(b)) showing the configuration of a power module 1 according to the second embodiment. Note that since the configuration of the power board 10 is similar to that of the first embodiment described above, illustrations and detailed description are omitted.

As shown in FIG. 30(a), in the power module 1 according to the second embodiment, the driver board 3 is disposed between the power board 10 and the lid portion 12 and approximately parallel to the power board 10 and the lid portion 12. The inside of the case 11, including the driver board 3, is filled with silicone gel 13.

As shown in FIG. 30(b), the driver board 3 is provided with drive circuits DR1 to DR4, interface terminals IF1 to IFn, and power input terminals VU1, VU2, VL1, and VL2. Although not shown in FIG. 30, the driver board 3 is also provided with an interface circuit IF.

In the second embodiment, in a plan view, a drive circuit DR1 is provided near the first switching element Q1, a drive circuit DR2 is provided near the second switching element Q2, a drive circuit DR3 is provided near the third switching element Q3, and a drive circuit DR4 is provided near the fourth switching element Q4.

In the second embodiment, in a plan view, a power input terminal VU1 is provided near the drive circuit DR1, a power input terminal VL1 is provided near the drive circuit DR2, a power input terminal VU2 is provided near the drive circuit DR3, and a power input terminal VL2 is provided near the drive circuit DR4.

Furthermore, in the second embodiment, interface terminals IF1 to IFn are provided near the power supply input terminal VL1 and the power supply input terminal VL2 in a plan view. The reason for arranging each component mounted on the driver board 3 in this manner will be explained below.

Figure 31 is a diagram in which the power module 1 according to the second embodiment is divided into blocks according to the circuits with high affinity. As shown in Figure 31, the circuits formed in the power module 1 according to the second embodiment are divided into three blocks A, B, and C according to the circuits with high affinity.

Here, a "circuit with high affinity" refers to a circuit that is grouped together with a similar electric potential, and within this circuit with high affinity, malfunctions due to noise, etc. are unlikely to occur even if the various parts are placed close to each other. On the other hand, if circuits that belong to different blocks are placed close to each other, they are more likely to be affected by the different electric potentials and malfunctions due to noise, etc.

As shown in FIG. 31, block A includes a first switching element Q1, a drive circuit DR1, a gate terminal Q1G, a source terminal Q1S, an output terminal OUT1, and a power supply input terminal VU1.

This block A corresponds to one of the upper arms in the power module 1. Therefore, in this block A, the potential swings widely between a high voltage (e.g., 400 V) and a low voltage (e.g., 0 V) each time the first switching element Q1 is turned on and off.

Block B includes a third switching element Q3, a drive circuit DR3, a gate terminal Q3G, a source terminal Q3S, an output terminal OUT2, and a power supply input terminal VU2.

This block B corresponds to another one of the upper arms in the power module 1. Therefore, in this block B, the potential swings widely between a high voltage (e.g., 400 V) and a low voltage (e.g., 0 V) each time the third switching element Q3 is turned on and off.

Block C includes a second switching element Q2, a fourth switching element Q4, drive circuits DR2 and DR4, an interface circuit IF, gate terminals Q2G and Q4G, source terminals Q2S and Q4S, interface terminals IF1 to IFn, and power supply input terminals VL1 and VL2.

Although not shown in FIG. 31, the thermistor TH and terminals TH1 and TH2 are also included in block C.

Such block C corresponds to the two lower arms in the power module 1. Therefore, in such block C, even when the second switching element Q2 or the fourth switching element Q4 is turned on and off, the potential does not swing significantly between the high voltage and the low voltage, and the potential is maintained near the low voltage (for example, 0 V).

Figure 32 is a diagram in which the power board 10 of the power module 1 according to the second embodiment is divided into blocks using the method shown in Figure 30. As shown in Figure 32, in the power board 10, block A is arranged in a roughly L-shape along the left short side and the left portion of the upper long side.

In addition, in the power board 10, block B is arranged in a roughly L-shape along the right short side and the right part of the upper long side. Furthermore, in the power board 10, block C is arranged in a roughly rectangular shape in the lower half excluding the right and left sides.

Figure 33 is a diagram in which the driver board 3 of the power module 1 according to the second embodiment is divided into blocks using the method shown in Figure 30. As shown in Figure 33, in the driver board 3, block A is arranged in a substantially rectangular shape in the upper half of the left side.

In addition, on the driver board 3, block B is arranged in a roughly rectangular shape in the upper half of the right side. Furthermore, on the driver board 3, block C is arranged in a roughly rectangular shape in the lower half.

Figure 34 shows the blocks on the power board 10 and the blocks on the driver board 3 of the power module 1 according to the second embodiment superimposed on each other.

As shown in FIG. 34, in the power module 1 of the second embodiment, block A corresponding to one of the upper arms, block B corresponding to another of the upper arms, and block C corresponding to the two lower arms are arranged to overlap as much as possible in the thickness direction.

In the example of FIG. 34, blocks A and C overlap at the left edge of the lower half of the power board 10, and blocks B and C overlap at the right edge of the lower half of the power board 10, except that identical blocks overlap each other in the thickness direction.

This makes it possible to prevent circuits belonging to different blocks from being placed close to each other. Therefore, according to the second embodiment, malfunctions due to noise, etc. can be suppressed.

In addition, in the second embodiment, as shown in FIG. 33, etc., it is advisable to place the gate terminal Q1G and source terminal Q1S belonging to block A near a corner of the power board 10 (the upper left corner in the figure) away from different blocks B and C.

This makes it possible to prevent noise from different blocks B and C from being input to the gate terminal Q1G and source terminal Q1S. Therefore, according to the second embodiment, it is possible to prevent the first switching element Q1 from malfunctioning due to noise or the like.

In addition, in the second embodiment, the gate terminal Q3G and source terminal Q3S belonging to block B may be disposed near a corner of the power board 10 (the upper right corner in the figure) away from the different blocks A and C.

This makes it possible to prevent noise from different blocks A and C from being input to the gate terminal Q3G and source terminal Q3S. Therefore, according to the second embodiment, it is possible to prevent the third switching element Q3 from malfunctioning due to noise or the like.

In addition, in the second embodiment, the gate terminals Q2G, Q4G and the source terminals Q2S, Q4S belonging to block C may be disposed near a side of the power board 10 (the bottom side in the figure) that is away from the different blocks B and C.

This makes it possible to prevent noise from different blocks A and B from being input to the gate terminals Q2G and Q4G and the source terminals Q2S and Q4S. Therefore, according to the second embodiment, it is possible to prevent the second switching element Q2 and the fourth switching element Q4 from malfunctioning due to noise or the like.

The power module 1 according to the second embodiment is preferably the same size as EasyPACK, which is known as a standard package on the market. This makes it possible to suppress malfunctions caused by noise, etc., in power modules 1 with standard packages on the market.

Figure 35 is a diagram in which the power board 10 of the power module 1 according to Modification 3 of the second embodiment is divided into blocks using the method shown in Figure 30. As shown in Figure 35, in Modification 3, the output terminal OUT1 is moved to the source terminal Q1S side on the circuit pattern 22, and the output terminal OUT2 is moved to the source terminal Q3S side on the circuit pattern 28.

Furthermore, in the third modification, the portion of the circuit pattern 22 where the output terminal OUT1 was arranged in the first embodiment and the like is excluded, and the portion of the circuit pattern 28 where the output terminal OUT2 was arranged in the first embodiment and the like is excluded.

As a result, as shown in FIG. 36, in the third modification, the overlapping portion between blocks A and C in the thickness direction can be reduced, and the overlapping portion between blocks B and C in the thickness direction can be reduced. FIG. 36 is a diagram showing the overlapping of blocks on the power board 10 and blocks on the driver board 3 of the power module 1 according to the third modification of the second embodiment.

Therefore, according to the third modification, it is possible to further prevent circuits belonging to different blocks from being placed close to each other, thereby further preventing malfunctions due to noise, etc.

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure.

For example, in each of the above-described embodiments, a power module 1 using a cascade-type GaN-FET is shown, but the switching element Q used in the power module 1 is not limited to a cascade-type GaN-FET, and the first switching element Q1 to the fourth switching element Q4 may be configured by a single GaN-FET.

In addition, in each of the above-described embodiments, a chip-on-chip type switching element Q having a Si-FET on a GaN-FET is used, but the GaN-FET and the Si-FET may be arranged side by side on the power substrate 10.

In addition, in each of the above-described embodiments, an example in which capacitor C1 is composed of a single capacitor has been shown, but capacitor C1 does not have to be composed of a single capacitor. For example, capacitor C1 may be composed of multiple capacitors connected in series, or multiple capacitors connected in parallel. Capacitor C1 may also be composed of a capacitor and a resistor connected in series.

In addition, in each of the above-described embodiments, an example has been shown in which each electrode of the first to fourth switching elements Q1 to Q4 is connected to the corresponding circuit pattern by a bonding wire W, but the member connecting each electrode of the first to fourth switching elements Q1 to Q4 to the circuit pattern is not limited to the bonding wire W. For example, each electrode of the first to fourth switching elements Q1 to Q4 may be electrically connected to the circuit pattern by a lead frame or the like.

In the above-described second embodiment, an example was shown in which the capacitor C1 was mounted on the power board 10, but the capacitor C1 may be mounted on the driver board 3, or on a separately provided printed circuit board 2. In this case, the capacitor C1 only needs to be provided in the central portion 4 of the power board 10 in a plan view.

The power module 1 according to each embodiment includes a first switching element Q1, a second switching element Q2, a third switching element Q3, a fourth switching element Q4, a circuit board (power board 10), and a capacitor C1. The first switching element Q1 is connected to the positive terminal P and includes a GaN-based switching element (GaN-FET). The second switching element Q2 is connected between the first switching element Q1 and the negative terminal N and includes a GaN-based switching element (GaN-FET). The third switching element Q3 is connected to the positive terminal P and includes a GaN-based switching element (GaN-FET). The fourth switching element Q4 is connected between the third switching element Q3 and the negative terminal N and includes a GaN-based switching element (GaN-FET). The first to fourth switching elements Q1 to Q4 are mounted on the circuit board (power board 10). The first to fourth switching elements Q1 to Q4 are arranged to surround one point on the circuit board, for example, the central portion 4. The drain electrode D of the first switching element Q1 and the drain electrode D of the third switching element Q3 are arranged to face each other. The source electrode S of the second switching element Q2 and the source electrode S of the fourth switching element Q4 are arranged to face each other. This makes it possible to reduce the wiring inductance of the power module 1.

In addition, in the power module 1 according to each embodiment, the capacitor C1 is mounted at one point, for example, at the center 4, on the circuit board (power board 10) surrounded by the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4. This eliminates the need to provide a separate printed circuit board 2 to mount the capacitor C1, thereby reducing the manufacturing cost of the power module 1.

In the power module 1 according to each embodiment, the circuit board (power board 10) and the first to fourth switching elements Q1 to Q4 are rectangular with long and short sides. The first to fourth switching elements Q1 to Q4 have drain electrodes D and source electrodes S along the long sides, and the first to fourth switching elements Q1 to Q4 are arranged so that their short sides face the long sides of the circuit board (power board 10). This reduces the wiring inductance of the power module 1.

In the power module 1 according to each embodiment, the first to fourth switching elements Q1 to Q4 are cascade-type GaN-FETs in which a source electrode S1 arranged on the front surface of the GaN-based switching element (GaN-FET) is electrically and mechanically connected to a drain electrode arranged on the back surface of the Si-based switching element (Si-FET). This allows the normally-on GaN-FET to be driven as a normally-off switching element.

In the power module 1 according to each embodiment, in the first switching element Q1 and the third switching element Q3, if the bonding wire W extending from the source electrode S2 of the Si-based switching element (Si-FET) is connected to the circuit patterns 22, 28 of the circuit board (Si-FET) as the first connection 41, and the bonding wire W extending from the gate electrode G1 of the GaN-based switching element (GaN-FET) is connected to the circuit patterns 22, 28 of the circuit board (power board 10) as the second connection 42, the first connection 41 is arranged farther away from the first switching element Q1 or the third switching element Q3 to which both are connected than the second connection 42. This makes it possible to minimize the overlap between the large current line IL flowing from the drain terminal to the source terminal of the first switching element Q1 or the third switching element Q3 and the small current line IS flowing from the gate terminal to the source terminal.

In addition, in the power module 1 according to each embodiment, the circuit board (power board 10) is rectangular with long and short sides, and the circuit patterns 22, 28 of the circuit board (power board 10) having the first connection portion 41 and the second connection portion 42 are formed along the short sides of the circuit board (power board 10) and have a notch 43 arranged to face the second connection portion 42. This allows the small current line IS flowing from the second connection portion 42 toward the source terminals Q1S, Q3S to be formed away from the first connection portion 41.

In the power module 1 according to each embodiment, in the second switching element Q2 and the fourth switching element Q4, if the location where the bonding wire W extending from the source electrode S2 of the Si-based switching element (Si-FET) is connected to the circuit pattern 25 of the circuit board (Si-FET) is the third connection portion 44, and the location where the bonding wire W extending from the gate electrode G1 of the GaN-based switching element (GaN-FET) is connected to the circuit pattern 25 of the circuit board (power board 10) is the fourth connection portion 45, the third connection portion 44 is arranged farther away from the second switching element Q2 or the fourth switching element Q4 to which both are connected than the fourth connection portion 45. This makes it possible to minimize the overlap between the large current line IL flowing from the drain terminal to the source terminal of the second switching element Q2 or the fourth switching element Q4 and the small current line IS flowing from the gate terminal to the source terminal.

In addition, in the power module 1 according to each embodiment, the circuit board (power board 10) is rectangular with long and short sides, and the circuit pattern 25 of the circuit board (power board 10) having the third connection portion 44 and the fourth connection portion 45 is formed along the short side of the circuit board (power board 10) and has a notch 46 arranged to face the fourth connection portion 45. This allows the small current line IS flowing from the fourth connection portion 45 toward the source terminals Q2S and Q4S to be formed away from the third connection portion 44.

The power module 1 according to the second embodiment includes a first switching element Q1, a second switching element Q2, a third switching element Q3, a fourth switching element Q4, a circuit board (power board 10), and a driver board 3. The first switching element Q1 constitutes one of the upper arms. The second switching element Q2 constitutes one of the lower arms. The third switching element Q3 constitutes the other of the upper arms. The fourth switching element Q4 constitutes the other of the lower arms. The circuit board (power board 10) is mounted with the first to fourth switching elements Q1 to Q4. The driver board 3 is mounted with a plurality of drive circuits DR1 to DR4 that drive the first to fourth switching elements Q1 to Q4. The circuit board (power board 10) and the driver board 3 are arranged so as to overlap in the thickness direction. Then, an area on the circuit board corresponding to one of the upper arms overlaps with an area on the driver board 3 corresponding to one of the upper arms, an area on the circuit board corresponding to another of the upper arms overlaps with an area on the driver board 3 corresponding to another of the upper arms, and an area on the circuit board corresponding to the lower arm overlaps with an area on the driver board 3 corresponding to the lower arm. This makes it possible to prevent circuits from belonging to different blocks from being placed close to each other, thereby making it possible to prevent malfunctions due to noise, etc.

In addition, in the power module 1 according to the second embodiment, the gate terminal Q1G and source terminal Q1S belonging to one of the upper arms are arranged near a corner of the power board 10 away from the region corresponding to another one of the upper arms or the lower arm. This makes it possible to prevent the first switching element Q1 from malfunctioning due to noise, etc.

In addition, in the power module 1 according to the second embodiment, the gate terminal Q3G and the source terminal Q3S belonging to another one of the upper arms are arranged near a corner of the power board 10 away from the region corresponding to one of the upper arms or the lower arm. This makes it possible to prevent the third switching element Q3 from malfunctioning due to noise caused by a potential difference between its own region and another region.

In addition, in the power module 1 according to the second embodiment, the gate terminals Q2G, Q4G and the source terminals Q2S, Q4S belonging to the lower arm are disposed near a side of the power board 10 away from a region corresponding to one of the upper arms or another of the upper arms. This makes it possible to prevent the second switching element Q2 and the fourth switching element Q4 from malfunctioning due to noise or the like generated by a potential difference between their own region and another region.

The power module 1 according to the second embodiment is the same size as the EasyPACK. This makes it possible to suppress malfunctions caused by noise, etc. in power modules 1 with standard packages available on the market.

The embodiments disclosed herein should be considered in all respects as illustrative and not restrictive. Indeed, the above-described embodiments may be embodied in a variety of forms. Furthermore, the above-described embodiments may be omitted, substituted, or modified in various forms without departing from the scope and spirit of the appended claims.

REFERENCE SIGNS LIST 1 Power module 2 Printed circuit board 3 Driver board 4 Center section 10 Power board (an example of a circuit board)
21 to 32 Circuit pattern 41 First connection portion 42 Second connection portion 43 Notch portion P Positive electrode terminal N Negative electrode terminal C1 Capacitor Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element D Drain electrode S Source electrode G Gate electrode W Bonding wire

Claims (7)

a first switching element including a GaN-based switching element, the drain electrode of which is connected to a positive terminal;
a second switching element including a GaN-based switching element, the second switching element having a drain electrode connected to a source electrode of the first switching element and a source electrode connected to a negative terminal;
a third switching element including a GaN-based switching element, the drain electrode of which is connected to the positive terminal;
a fourth switching element including a GaN-based switching element, the fourth switching element having a drain electrode connected to a source electrode of the third switching element and a source electrode connected to the negative terminal;
a circuit board on which the first to fourth switching elements are mounted;
Equipped with
the drain electrodes, source electrodes and gate electrodes of the first to fourth switching elements are provided on front surfaces of the first to fourth switching elements,
the first to fourth switching elements are arranged to surround one point on the circuit board,
a capacitor connected between the positive terminal and the negative terminal at one point on the circuit board;
The circuit board includes:
a first circuit pattern located between the first switching element and the third switching element, the first circuit pattern connecting the positive terminal, a drain electrode of the first switching element, a drain electrode of the third switching element, and the capacitor;
a second circuit pattern located between the second switching element and the fourth switching element, the second circuit pattern being connected to the negative terminal, a source electrode of the second switching element, a source electrode of the fourth switching element, and the capacitor;
a drain electrode of the first switching element and a drain electrode of the third switching element are arranged to face each other,
a source electrode of the second switching element and a source electrode of the fourth switching element are arranged to face each other. The circuit board includes:
a third circuit pattern located on an opposite side of a point on the circuit board with respect to the first switching element and the second switching element, the third circuit pattern being connected to a source electrode of the first switching element and a drain electrode of the second switching element;
a fourth circuit pattern located on an opposite side of a point on the circuit board with respect to the third switching element and the fourth switching element, the fourth circuit pattern being connected to a source electrode of the third switching element and a drain electrode of the fourth switching element;
The power module of claim 1 further comprising: a first drive circuit that drives the first switching element;
a second drive circuit that drives the second switching element;
a third drive circuit that drives the third switching element;
a fourth drive circuit that drives the fourth switching element;
The power module according to claim 1 or 2, further comprising: a fifth circuit pattern, a sixth circuit pattern, and a first resistor, which are located on the opposite side of the second switching element with respect to the first switching element and connect the first drive circuit and a gate electrode of the first switching element;
a seventh circuit pattern, an eighth circuit pattern, and a second resistor, which are located on the opposite side of the second switching element from the first switching element and connect the second drive circuit and a gate electrode of the second switching element;
a ninth circuit pattern, a tenth circuit pattern, and a third resistor, which are located on the opposite side of the third switching element to the fourth switching element and connect the third drive circuit and a gate electrode of the third switching element;
an eleventh circuit pattern, a twelfth circuit pattern, and a fourth resistor, which are located on the opposite side of the fourth switching element to the third switching element and connect the fourth drive circuit and a gate electrode of the fourth switching element;
The power module according to claim 3 , further comprising: the circuit board and the first to fourth switching elements are rectangular having long and short sides,
The first to fourth switching elements each have a drain electrode and a source electrode provided along a long side,
5. The power module according to claim 1, wherein the first to fourth switching elements are arranged such that short sides of the first to fourth switching elements face long sides of the circuit board. the first to fourth switching elements are cascade GaN-FETs in which a source electrode disposed on a front surface of the GaN-based switching element is electrically and mechanically connected to a drain electrode disposed on a rear surface of a Si-based switching element;
the drain electrodes of the first to fourth switching elements are drain electrodes of the GaN-based switching elements;
the source electrodes of the first to fourth switching elements are source electrodes of the Si-based switching element,
the gate electrodes of the first to fourth switching elements are gate electrodes of the Si-based switching elements,
6. The power module according to claim 1, wherein a gate electrode of the GaN-based switching element is connected to a source electrode of the Si-based switching element. In the second switching element or the fourth switching element, when a portion where a bonding wire extending from a source electrode of the Si-based switching element is connected to the second circuit pattern of the circuit board is defined as a third connection portion, and a portion where a bonding wire extending from a gate electrode of the GaN-based switching element is connected to the second circuit pattern of the circuit board is defined as a fourth connection portion,
The power module according to claim 6 , wherein the third connection portion is disposed farther away from the second switching element or the fourth switching element, to which both are connected, than the fourth connection portion.

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