JP7516736B2 - Semiconductor Device - Google Patents

Description

This invention relates to a semiconductor device.

Traditionally, silicon (Si) has been used as a constituent material for power semiconductor devices that control high voltages and large currents. There are several types of power semiconductor devices, including bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to the application.

For example, bipolar transistors and IGBTs have a higher current density and can handle larger currents than MOSFETs, but they cannot be switched at high speeds. Specifically, bipolar transistors can only be used at switching frequencies of a few kHz, while IGBTs can only be used at switching frequencies of a few tens of kHz. On the other hand, power MOSFETs have a lower current density and are more difficult to handle at high currents than bipolar transistors and IGBTs, but they are capable of high-speed switching operations of up to a few MHz.

However, there is a strong demand in the market for power semiconductor devices that combine high current and high speed, and efforts have been made to improve IGBTs and power MOSFETs, with development currently approaching the material limit. From the perspective of power semiconductor devices, semiconductor materials to replace silicon are being considered, and silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to create (manufacture) next-generation power semiconductor devices with low on-voltage, high-speed characteristics, and excellent high-temperature characteristics.

Silicon carbide is a chemically very stable semiconductor material with a wide band gap of 3 eV, allowing it to be used extremely stably as a semiconductor even at high temperatures. In addition, silicon carbide has a maximum electric field strength that is at least one order of magnitude greater than that of silicon, making it a promising semiconductor material that can sufficiently reduce on-resistance. These characteristics of silicon carbide also apply to wide band gap semiconductors with wider band gaps than other silicons, such as gallium nitride (GaN). For this reason, the use of wide band gap semiconductors can be used to increase the voltage resistance of semiconductor devices.

The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. Therefore, compared to a planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, it is possible to increase the unit cell (element constituent unit) density per unit area, and increase the current density per unit area, which is advantageous in terms of cost. The planar gate structure is a MOS gate structure in which a MOS gate is provided in a flat plate shape on the front surface of a semiconductor substrate.

FIG. 12 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. FIG. 12 shows the structure of a silicon carbide semiconductor device formed on a silicon carbide semiconductor wafer and after being singulated. However, a dicing region 142 described later shows the structure before being singulated. As shown in FIG. 12, in a trench-type MOSFET 150, a MOS gate having a general trench gate structure is provided on the front surface (the surface on the p-type silicon carbide epitaxial layer 103 side) of a semiconductor substrate (hereinafter referred to as a silicon carbide semiconductor substrate) made of silicon carbide. The silicon carbide semiconductor substrate (semiconductor chip) is formed by epitaxially growing each silicon carbide layer, which becomes an n ^{-type silicon carbide epitaxial layer 102, an n-type high concentration region 106 which is a current diffusion region, and a p-type silicon carbide epitaxial layer 103, in order, on an n + -type} support substrate (hereinafter referred to as an n + -type silicon carbide substrate) 101 made of silicon carbide.

In the n-type high concentration region 106, a first p ⁺ -type base region 104 is selectively provided between adjacent trenches 118 (mesa portion). In addition, in the n-type high concentration region 106, a second p ⁺ -type base region 105 is selectively provided to partially cover the bottom surface of the trench 118. The second p ⁺ -type base region 105 and the first p ⁺ -type base region 104 may be formed simultaneously. The first p ⁺ -type base region 104 is provided so as to be in contact with the p-type silicon carbide epitaxial layer 103.

Reference numerals 107 to 111, 113, and 115 respectively denote an n ⁺ type source region, a p ⁺⁺ type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a source electrode pad. Further, a plating film 116, a solder 117, an external electrode pin 119, a first protective film 121, and a second protective film 123 are provided on the upper part of the source electrode pad 115. Further, a back surface electrode 114 is provided on the back surface side of the n ⁺ type silicon carbide substrate 101.

Furthermore, in the conventional silicon carbide semiconductor device, an edge termination region 141 is provided around the periphery of active region 140 through which a main current flows, surrounding active region 140 to maintain a breakdown voltage, and a dicing region 142 is provided outside edge termination region 141. JTE structure 124 and n ⁺ type semiconductor region 125 are provided in edge termination region 141. The silicon carbide semiconductor device is individualized by cutting (dicing) dicing region 142. In edge termination region 141 and dicing region 142, oxide film 130 is provided on the surface of the silicon carbide semiconductor substrate.

In addition, a silicon carbide semiconductor device is known that has a damage region in contact with the cut surface and suppresses the generation of distortion in the inward direction of the cut surface, thereby preventing a decrease in reliability even with long-term use (see, for example, Patent Document 1 below).

A semiconductor device is also known in which a first dummy metal layer, a second dummy metal layer, and a third dummy metal layer are stacked with a first interlayer insulating film, a second interlayer insulating film, and a third interlayer insulating film sandwiched therebetween, thereby preventing cracks from penetrating from the sidewalls of the semiconductor chip during dicing, thereby improving reliability (see, for example, Patent Document 2 below).

JP 2019-033141 A JP 2009-218504 A

Here, a wide band gap semiconductor substrate (e.g., a silicon carbide substrate) is harder than a silicon substrate. For this reason, the dicing blade deteriorates quickly, and it is necessary to replace the dicing blade frequently. Furthermore, the dicing blade is severely damaged during dicing, and the dicing line may become tilted from the start of dicing the substrate to the end of cutting one line. This often causes distortion on the cut surface. The distortion is a crack (scratches) or chipping that occurs in the substrate.

To prevent distortion, dicing can be temporarily stopped when the dicing blade is tilted and the tilt can be corrected. In this case, the dicing is temporarily stopped, which increases the time it takes to dicing. For this reason, a method is used in which the dicing area is made wider so that the semiconductor chip is not affected even if the dicing blade is tilted. In this case, the area of the dicing area on the substrate increases, and because the substrate is cut at an angle, distortion often occurs on the cut surface.

The distortion generated during this dicing does not have a significant effect on the various characteristics of the semiconductor device while it is on the cut surface. However, as the operating frequency and current density of the semiconductor device increases, the stress caused by continuous operation causes this distortion to grow from the edge termination region to the active region, causing fluctuations in the various characteristics of the semiconductor device and possibly resulting in operational malfunctions.

The purpose of this invention is to provide a semiconductor device whose reliability does not decrease even after long-term use by preventing the dicing blade from tilting during dicing or by preventing the growth of distortion on the cut surface in order to solve the problems of the conventional technology described above.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes an active region provided in a semiconductor substrate of a first conductivity type through which a main current flows, and a termination region disposed outside the active region and provided with a breakdown voltage structure. The active region includes a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side, a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side, a gate insulating film in contact with the second semiconductor layer, a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer, a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region, and a second electrode provided on a rear surface of the semiconductor substrate. The termination region includes the first semiconductor layer and a plating film provided on the surface of the first semiconductor layer opposite the semiconductor substrate side, at the end opposite the active region, up to a cut surface formed when individualizing the semiconductor device .

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes an active region provided in a semiconductor substrate of a first conductivity type through which a main current flows, and a termination region disposed outside the active region and provided with a breakdown voltage structure. The active region includes a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side, a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side, a gate insulating film in contact with the second semiconductor layer, a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer, a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region, and a second electrode provided on a rear surface of the semiconductor substrate. The termination region includes the first semiconductor layer and a plating film provided on an end of the first semiconductor layer on a surface opposite to the semiconductor substrate, the end being opposite to the active region. The plating film in the termination region is a NiP film.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes an active region provided in a semiconductor substrate of a first conductivity type through which a main current flows, and a termination region disposed outside the active region and provided with a breakdown voltage structure. The active region includes a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side, a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side, a gate insulating film in contact with the second semiconductor layer, a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer, a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region, and a second electrode provided on a rear surface of the semiconductor substrate. The termination region includes the first semiconductor layer and a plating film provided on an end of the first semiconductor layer on a surface opposite to the semiconductor substrate, the end being opposite to the active region. The plating film in the termination region is a NiB film.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. The semiconductor device includes an active region provided in a semiconductor substrate of a first conductivity type through which a main current flows, and a termination region disposed outside the active region and provided with a breakdown voltage structure. The active region includes a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate, a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate side, a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the semiconductor substrate side, a gate insulating film in contact with the second semiconductor layer, a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer, a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region, and a second electrode provided on a rear surface of the semiconductor substrate. The termination region includes the first semiconductor layer and a plating film provided on an end of the first semiconductor layer on a surface opposite to the semiconductor substrate side, the end being opposite to the active region, an oxide film and a metal film are provided between the first semiconductor layer and the plating film, and a protective film is selectively provided on a surface of the plating film.

In the semiconductor device according to the present invention, in the above-mentioned invention , the plating film surrounds the active region in a ring shape .

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it further comprises a trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer, and the gate electrode is provided inside the trench via the gate insulating film.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a second plating film is further provided on the first electrode.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second plating film is the same metal film as the plating film.

According to the above-mentioned invention, a second plating film is provided at the end of the edge termination region. This applies pressure to the silicon carbide semiconductor substrate, which can prevent the distortion generated during dicing from growing from the edge termination region. This prevents the reliability of the silicon carbide semiconductor device from decreasing even when it is used for a long period of time.

In addition, it is possible to detect when the dicing blade comes into contact with the second plating film, and the direction of the dicing blade can be calibrated based on the amount of contact between the dicing blade and the second plating film, making it possible to make the dicing blade parallel to the scribe line. This makes it possible to cut parallel to the scribe line, and suppresses distortion that occurs during dicing.

The semiconductor device of the present invention has the effect of preventing the dicing blade from tilting during dicing, or preventing the growth of distortion on the cut surface, thereby preventing a decrease in reliability even after long-term use.

1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment. 1 is a top view of a silicon carbide semiconductor device according to an embodiment before being cut out from a silicon carbide semiconductor wafer. 1 is an enlarged view of a top surface of a silicon carbide semiconductor device according to an embodiment before being cut out from a silicon carbide semiconductor wafer. FIG. 1 is a cross-sectional view showing another structure of a silicon carbide semiconductor device according to an embodiment (part 1). FIG. 2 is a cross-sectional view showing another structure of the silicon carbide semiconductor device according to the embodiment (part 2). 1A to 1C are cross-sectional views showing a state during manufacture of a silicon carbide semiconductor device according to an embodiment (part 1). 11A to 11C are cross-sectional views showing a state during manufacture of the silicon carbide semiconductor device according to the embodiment (part 2). 11A to 11C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 3). 4 is a cross-sectional view showing a state during manufacture of a silicon carbide semiconductor device according to an embodiment (part 4); 5 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment; FIG. 6 is a cross-sectional view showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment; FIG. FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device.

Below, with reference to the attached drawings, a preferred embodiment of the semiconductor device according to the present invention will be described in detail. In this specification and the attached drawings, in layers and regions marked with n or p, electrons or holes, respectively, are the majority carriers. In addition, + and - marked with n or p, respectively, indicate a higher impurity concentration and a lower impurity concentration than layers or regions without them. When the notations of n and p, including + and -, are the same, it indicates that the concentrations are close, but not necessarily the same. In the following description of the embodiment and the attached drawings, similar configurations are marked with the same reference numerals, and duplicate explanations will be omitted.

(Embodiment)
The semiconductor device according to the embodiment is configured using a semiconductor having a wider band gap than silicon (Si) (referred to as a wide band gap semiconductor). The structure of the semiconductor device according to the embodiment will be described using an example in which silicon carbide (SiC) is used as the wide band gap semiconductor. FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment.

Figure 1 shows the structure of a semiconductor device formed on a silicon carbide semiconductor wafer and after it has been singulated. However, the dicing region 42 described below is shown as the structure before singulation, since it will no longer exist after singulation. Figure 1 shows the configuration of an active region 40 in which an element structure is formed and a main current flows in the thickness direction of the substrate when in the on state, the configuration of an edge termination region 41 that surrounds the periphery of the active region 40 and maintains a breakdown voltage, and the configuration of a dicing region 42 outside the edge termination region 41. The dicing region 42 is the region that is cut when singulating a silicon carbide semiconductor device.

The silicon carbide semiconductor device according to the embodiment is a trench-type MOSFET 50 having a MOS gate with a trench gate structure on the front surface (the surface on the side of a p-type silicon carbide epitaxial layer 3 described later) of a semiconductor substrate. The silicon carbide semiconductor base is formed by epitaxially growing an n ^- type silicon carbide epitaxial layer (first semiconductor layer of a first conductivity type) 2 and a p-type silicon carbide epitaxial layer (second semiconductor layer of a second conductivity type) 3 in this order on an n + -type silicon carbide substrate (semiconductor substrate of a first conductivity type) 1 made of silicon carbide. An n-type high concentration region 6 may be epitaxially grown on the n-type silicon carbide epitaxial layer 2.

The MOS gate of the trench gate structure is composed of a p-type silicon carbide epitaxial layer 3 , an n ⁺ -type source region (first semiconductor region of a first conductivity type) 7 , p ⁺⁺ -type contact region 8 , a trench 18 , a gate insulating film 9 and a gate electrode 10 .

Specifically, the trenches 18 penetrate the p-type silicon carbide epitaxial layer 3 from the front surface of the semiconductor substrate in the depth direction z to reach the n-type high concentration region 6 (if the n-type high concentration region 6 is not provided, the n-type silicon carbide epitaxial layer 2, hereinafter referred to as (2)). The depth direction z is the direction from the front surface to the back surface of the semiconductor substrate. The trenches 18 are arranged, for example, in a stripe shape.

Inside the trench 18, a gate insulating film 9 is provided along the inner wall of the trench 18, and a gate electrode 10 is provided on the gate insulating film 9 so as to be embedded inside the trench 18. The gate electrode 10 in one trench 18 and adjacent mesa regions (regions between adjacent trenches 18) sandwiching the gate electrode 10 form one unit cell of the main semiconductor element. Although FIG. 1 shows only two trench MOS structures in one active region 40, many more trench-structured MOS gate (insulated gate made of metal-oxide film-semiconductor) structures may be arranged in parallel.

An n-type region (hereinafter referred to as n-type high concentration region) 6 may be provided in the surface layer on the source side (the source electrode 13 side described later) of the n-type silicon carbide epitaxial layer 2 so as to contact the p-type silicon carbide epitaxial layer 3. The n-type high concentration region 6 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. This n-type high concentration region 6 is provided uniformly in a direction parallel to the front surface of the substrate (front surface of the semiconductor substrate) so as to cover the inner wall of the trench 18, for example.

The n-type high concentration region 6 reaches a position deeper from the interface with the p-type silicon carbide epitaxial layer 3 toward the drain side (the back electrode 14 side described later) than the bottom surface of the trench 18. The first and second p ⁺ -type base regions 4 and 5 may be selectively provided inside the n-type high concentration region 6. The first p ⁺ -type base region 4 is provided between adjacent trenches 18 (mesa region) away from the second p ⁺ -type base region 5 and the trench 18, and contacts the p-type silicon carbide epitaxial layer 3. The second p ⁺ -type base region 5 covers at least the bottom surface of the bottom surface and the bottom surface corner portion of the trench 18. The bottom surface corner portion of the trench 18 is the boundary between the bottom surface and the side wall of the trench 18.

The pn junction between the first and 2p ⁺ type base regions 4, 5 and the n-type silicon carbide epitaxial layer 2 is formed at a position deeper on the drain side than the bottom surface of the trench 18. The first and 2p ⁺ type base regions 4, 5 may be provided inside the n-type silicon carbide epitaxial layer 2 without providing the n-type high concentration region 6. The depth position of the drain side end of the first and 2p ⁺ type base regions 4, 5 may be changed in various ways according to the design conditions as long as the pn junction between the first and 2p ⁺ type base regions 4, 5 and the n-type silicon carbide epitaxial layer 2 is deeper on the drain side than the bottom surface of the trench 18. The first and 2p ⁺ type base regions 4, 5 can prevent a high electric field from being applied to the gate insulating film 9 in the portion along the bottom surface of the trench 18.

An n ⁺ type source region 7 is selectively provided inside the p type silicon carbide epitaxial layer 3. A p ⁺⁺ type contact region 8 may be selectively provided so as to be in contact with the n ⁺ type source region 7. The n ⁺ type source region 7 is in contact with the gate insulating film 9 on the side wall of the trench 18, and faces the gate electrode 10 via the gate insulating film 9 on the side wall of the trench 18.

The interlayer insulating film 11 is provided over the entire front surface of the semiconductor substrate so as to cover the gate electrode 10. A contact hole is opened in the interlayer insulating film 11, penetrating the interlayer insulating film 11 in the depth direction z to reach the front surface of the substrate.

The source electrode (first electrode) 13 is in ohmic contact with the semiconductor substrate (n ⁺ type source region 7) in the contact hole, and is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad 15 is provided on the source electrode 13. When the p ⁺⁺ type contact region 8 is provided, the source electrode 13 is in ohmic contact with the p ⁺⁺ type contact region 8. When the p ⁺⁺ type contact region 8 is not provided, the source electrode 13 is in ohmic contact with the n ⁺ type source region 7.

One end of the external electrode pin 19 is joined onto the source electrode pad 15 via a plating film 16 and solder 17. The other end of the external electrode pin 19 is joined to a metal bar (not shown) arranged to face the front surface of the semiconductor substrate. The other end of the external electrode pin 19 is exposed to the outside of the case (not shown) in which the semiconductor chip is mounted, and is electrically connected to an external device (not shown).

The surface of the source electrode pad 15 other than the plating film 16 is covered with a first protective film 21. Specifically, the first protective film 21 is provided to cover the source electrode pad 15, and the plating film 16 is provided in the opening of the first protective film 21. An external electrode pin 19 is joined to the surface of the plating film 16 via solder 17. A second protective film 23 may be provided on the surface of the plating film 16 to limit the area of the solder 17. The first and second protective films 21 and 23 are, for example, polyimide films.

A back electrode (second electrode) 14 that serves as a drain electrode is provided on the back surface of the semiconductor substrate. A drain electrode pad (not shown) is provided on the back surface electrode 14.

Next, the edge termination region 41 and the dicing region 42 will be described. In the edge termination region 41, a junction termination extension (JTE) structure 24 is provided as a JTE structure in order to improve the breakdown voltage of the entire high-voltage semiconductor device by relaxing or dispersing the electric field. An n ⁺ type semiconductor region 25 functioning as a channel stopper is provided outside the JTE structure 24 (on the dicing region 42 side). An oxide film 30 is provided on the surfaces of the JTE structure 24 and the n ⁺ type semiconductor region 25. An interlayer insulating film 11 and a first protective film 21 are provided on the surface of the oxide film 30. A gate runner is provided between the edge termination region 41 and the active region 40, but is not shown.

In addition, in the dicing region 42, the oxide film 30 is not provided in the area where the dicing blade comes into contact. This prevents chipping of the dicing blade (fine chipping of the cutting edge) during cutting.

Furthermore, in the silicon carbide semiconductor device of the embodiment, a structure similar to the structure on source electrode pad 15 in active region 40 is provided at the surface end of interlayer insulating film 11 in edge termination region 41 outside n ⁺ type semiconductor region 25. Specifically, oxide film 30, interlayer insulating film 11, metal film 26 and second plating film 27 are provided in this order on the silicon carbide semiconductor substrate. In addition, second protective film 23 is provided on the interface between second plating film 27 and first protective film 21 to protect second plating film 27.

The metal film 26 may be composed of the same metal film as the source electrode pad 15. In this case, when forming the source electrode pad 15, a metal film is formed on the silicon carbide semiconductor substrate, and the metal film left in the active region 40 becomes the source electrode pad 15, and the metal film left in the edge termination region 41 becomes the metal film 26. When the metal film 26 is the same metal film as the source electrode pad 15, it may be an Al film or an Al alloy film such as an Al-Si film. When the metal film 26 is a metal film different from the source electrode pad 15, it may be a Ti film.

In addition, a second plating film 27 is provided on the metal film 26. The second plating film 27 may be made of the same metal film as the plating film 16. In this case, the second plating film 27 can be formed on the metal film 26 at the same time as forming the plating film 16 on the source electrode pad 15. This allows the second plating film 27 to be formed with a thickness similar to that of the plating film 16. If the second plating film 27 is the same metal film as the plating film 16, it is NiP (nickel phosphorus). The plating film 16 is required to have a stable resistance, so NiP is used, but the second plating film 27 is not required to have a stable resistance because it is not connected to an electrode such as the source electrode 13. Therefore, if the second plating film 27 is a metal film different from the plating film 16, NiB (nickel boride), which is harder than NiP and stable to heat treatment, can be used for the second plating film 27.

Figure 2 is a top view of a silicon carbide semiconductor device according to an embodiment before it is cut out from a silicon carbide semiconductor wafer. Also, Figure 3 is an enlarged view of the top surface of a silicon carbide semiconductor device according to an embodiment before it is cut out from a silicon carbide semiconductor wafer. In dicing, the silicon carbide semiconductor wafer is cut along scribe lines 31. Here, when attempting to cut a line along an AX-AY scribe line, due to the hardness of silicon carbide, linearity is poor, and dicing is performed obliquely at a certain angle.

This often results in distortion at the cut surface. The higher the operating frequency and current density of the silicon carbide semiconductor device, the more the distortion generated during dicing grows from the edge termination region 41 to the active region 40 due to stress caused by continuous operation. This growing distortion causes various characteristics of the silicon carbide semiconductor device to fluctuate, and further leads to operational malfunctions. For this reason, in the embodiment, a second plating film 27 is provided at the end of the edge termination region 41. The second plating film 27 has the function of applying pressure to the silicon carbide semiconductor substrate. This pressure can prevent the distortion generated during dicing from growing from the edge termination region 41.

As shown in FIG. 3, the second plating film 27 is provided in a ring shape that is connected in an annular manner and has no cut portions, surrounding the active region 40. This makes it possible to suppress the growth of distortion that occurs during dicing on all cut surfaces.

In addition, in the embodiment, by providing the second plating film 27 in the edge termination region 41, it is possible to detect when the dicing blade comes into contact with the second plating film 27. At this time, the direction of the dicing blade can be calibrated based on the amount of contact between the dicing blade and the second plating film 27, and the dicing blade can be made parallel to the scribe line 31. For example, if the inclination of the dicing blade is large, the amount of contact with the second plating film 27 increases, so the greater the amount of contact, the greater the amount of correction of the inclination of the dicing blade is. This makes it possible to cut parallel to the scribe line 31, and distortion that occurs during dicing can be suppressed.

The second plating film 27 also has a different hardness and color from the silicon carbide semiconductor substrate. Therefore, the difference in hardness and color of the second plating film 27 makes it possible to distinguish the area between the second plating films 27 from the dicing area 42, thereby reducing malfunctions during dicing.

4 and 5 are cross-sectional views showing other structures of the silicon carbide semiconductor device according to the embodiment. In FIGS. 3 to 5, the width of the dicing region 42 is approximately the same. The ends of the metal film 26 and the second plating film 27 on the dicing region 42 side may be in the edge termination region 41 as in FIG. 1, or may be at the boundary between the edge termination region 41 and the dicing region 42 as in FIG. 4. Furthermore, as shown in FIG. 5, the metal film 26 and the second plating film 27 may extend to the dicing region 42. In the embodiment of FIG. 5, the metal film 26 and the second plating film 27 are not provided in the region where the dicing blade comes into contact with the dicing blade. This is because it is not possible to detect the contact of the dicing blade with the second plating film 27. In addition, when the dicing blade scrapes the metal film 26 and the second plating film 27, metal pieces may also scatter into the active region 40.

(Method of Manufacturing Silicon Carbide Semiconductor Device According to an Embodiment)
Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described below. Figures 6 to 11 are cross-sectional views showing states during the manufacturing process of a silicon carbide semiconductor device according to an embodiment.

First, an n ⁺ type silicon carbide substrate 1 made of n type silicon carbide is prepared. Then, a first n type silicon carbide epitaxial layer 2a made of silicon carbide is epitaxially grown on a first main surface of the n ⁺ type silicon carbide substrate 1 to a thickness of, for example, about 30 μm while doping with n type impurities, for example, nitrogen atoms (N). The state up to this point is shown in FIG.

Next, an ion implantation mask having predetermined openings is formed on the surface of the first n-type silicon carbide epitaxial layer 2a by photolithography, for example, and p-type impurities such as aluminum are implanted into the openings in the oxide film to form the lower first p ⁺ type base region 4a and the second p ⁺ type base region 5 to a depth of about 0.5 μm.

The distance between the adjacent lower first p ⁺ type base region 4a and second p ⁺ type base region 5 is set to about 1.5 μm. The impurity concentrations of the lower first p ⁺ type base region 4a and second p ⁺ type base region 5 are set to about 5×10 ¹⁸ /cm ³ , for example.

Next, a part of the ion implantation mask may be removed, and an n-type impurity such as nitrogen may be ion-implanted into the opening to form a lower n-type high concentration region 6a having a depth of, for example, about 0.5 μm in a part of the surface region of the first n-type silicon carbide epitaxial layer 2a. The impurity concentration of the lower n-type high concentration region 6a is set to, for example, about 1×10 ¹⁷ /cm ^3. The state up to this point is shown in FIG.

Next, a second n-type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed on the surface of the first n-type silicon carbide epitaxial layer 2a to a thickness of about 0.5 μm. The impurity concentration of the second n-type silicon carbide epitaxial layer 2b is set to about 3×10 ¹⁵ /cm ^3. Thereafter, the first n-type silicon carbide epitaxial layer 2a and the second n-type silicon carbide epitaxial layer 2b are combined to form the n-type silicon carbide epitaxial layer 2.

Next, an ion implantation mask having a predetermined opening is formed on the surface of the second n-type silicon carbide epitaxial layer 2b by photolithography, for example, with an oxide film. Then, p-type impurities such as aluminum are implanted into the opening of the oxide film to form an upper first p ⁺ type base region 4b with a depth of about 0.5 μm so as to overlap the lower first p ⁺ type base region 4a. The lower first p ⁺ type base region 4a and the upper first p ⁺ type base region 4b form a continuous region, which becomes the first p ⁺ type base region 4. The impurity concentration of the upper first p ⁺ type base region 4b is set to about 5×10 ¹⁸ /cm ³ , for example.

Next, a part of the ion implantation mask is removed, and n-type impurities such as nitrogen are ion-implanted into the opening to form an upper n-type high concentration region 6b having a depth of, for example, about 0.5 μm in a part of the surface region of the second n-type silicon carbide epitaxial layer 2b. The impurity concentration of the upper n-type high concentration region 6b is set to, for example, about 1×10 ¹⁷ /cm ^3. The upper n-type high concentration region 6b and the lower n-type high concentration region 6a are formed so that at least a part of them are in contact with each other to form the n-type high concentration region 6. However, the n-type high concentration region 6 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in FIG. 8.

Next, a p-type silicon carbide epitaxial layer 3 is formed by epitaxial growth to a thickness of about 1.1 μm on the surface of the n-type silicon carbide epitaxial layer 2. The impurity concentration of the p-type silicon carbide epitaxial layer 3 is set to about 4×10 ¹⁷ /cm ^3. After the p-type silicon carbide epitaxial layer 3 is formed by epitaxial growth, a p-type impurity such as aluminum may be further ion-implanted into the channel region of the p-type silicon carbide epitaxial layer 2.

Next, an ion implantation mask having a predetermined opening is formed, for example, from an oxide film, on the surface of the p-type silicon carbide epitaxial layer 3 by photolithography. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into this opening to form an n ⁺ -type source region 7 in a part of the surface of the p-type silicon carbide epitaxial layer 3. Next, the ion implantation mask used to form the n ⁺ -type source region 7 is removed, and an ion implantation mask having a predetermined opening is formed in a similar manner, and p-type impurities such as phosphorus are ion-implanted into a part of the surface of the p-type silicon carbide epitaxial layer 3 to form a p ⁺⁺ -type contact region 8. The impurity concentration of the p ⁺⁺ -type contact region 8 is set to be higher than the impurity concentration of the p-type silicon carbide epitaxial layer 3. The state up to this point is shown in FIG. 9.

Next, p-type silicon carbide epitaxial layer 3 in edge termination region 41 is turned into an n-type region, and then selective ion implantation is performed to form p-type JTE structure 24 and n ⁺ type semiconductor region 25 in the outermost peripheral portion of JTE structure 24. Note that p-type silicon carbide epitaxial layer 3 may be removed by etching to form JTE structure 24 and n ⁺ type semiconductor region 25 on the surface of n-type epitaxial layer 2.

Next, a heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C. to activate the first p ⁺ type base region 4, the second p ⁺ type base region 5, the n ⁺ type source region 7, the p ⁺⁺ type contact region 8, the JTE structure 24, and the n ⁺ type semiconductor region 25. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or the heat treatment may be performed each time an ion implantation is performed.

Next, a trench forming mask having a predetermined opening is formed, for example, from an oxide film, by photolithography on the surface of the p-type silicon carbide epitaxial layer 3. Next, a trench 18 is formed by dry etching, penetrating the p-type silicon carbide epitaxial layer 3 and reaching the n-type high concentration region 6(2). The bottom of the trench 18 may reach the second p ⁺ -type base region 5 formed in the n-type high concentration region 6(2). Next, the trench forming mask is removed. The state up to this point is shown in FIG. 10.

Next, a gate insulating film 9 is formed along the surface of the n ⁺ type source region 7 and the bottom and sidewall of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000° C. in an oxygen atmosphere. This gate insulating film 9 may also be formed by a method of depositing it by a chemical reaction such as high temperature oxidation (High Temperature Oxide: HTO). By the thermal oxidation when forming the gate insulating film 9, an oxide film 30 is formed in the edge termination region 41 and the dicing region 42, and then the oxide film 30 in the dicing region 42 is selectively removed.

Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 18. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 18 to form the gate electrode 10.

Next, for example, phosphorus glass is formed to a thickness of about 1 μm so as to cover the gate insulating film 9, the oxide film 30, and the gate electrode 10, forming the interlayer insulating film 11. At this time, the interlayer insulating film 11 is also formed on the oxide film 30 in the edge termination region 41. Next, a barrier metal made of titanium (Ti), titanium nitride (TiN), or a laminate of titanium and titanium nitride may be formed so as to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography to form contact holes exposing the n ⁺ type source region 7 and the p ⁺⁺ type contact region 8. Then, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11. The state up to this point is shown in FIG. 11. Also, after forming the contact holes in the interlayer insulating film 11, a barrier metal made of titanium (Ti), titanium nitride (TiN), or a laminate of titanium and titanium nitride may be formed. In this case, contact holes exposing the n ⁺ type source region 7 and the p ⁺⁺ type contact region 8 are also provided in the barrier metal.

Next, a conductive film that becomes the source electrode 13 is formed in the contact hole provided in the interlayer insulating film 11 and on the interlayer insulating film 11. The conductive film is, for example, a nickel (Ni) film. A nickel (Ni) film is also formed on the second main surface of the n ⁺ type silicon carbide substrate 1 in the same manner. Thereafter, a heat treatment is performed at a temperature of, for example, about 970° C. to silicidize the nickel film inside the contact hole to become the source electrode 13. At the same time, the nickel film formed on the second main surface becomes the back electrode 14 that forms an ohmic junction with the n ⁺ type silicon carbide substrate 1. Thereafter, the unreacted nickel film is selectively removed to leave the source electrode 13 only in the contact hole, for example.

Next, for example by sputtering, a first TiN film, a first Ti film, a second TiN film, and a second Ti film are laminated in this order so as to cover the source electrode 13 and the interlayer insulating film 11 on the front surface of the silicon carbide semiconductor substrate, and an Al alloy film is then formed to a thickness of, for example, about 5 μm. The Al alloy film may be an Al film. The Al alloy film is, for example, an Al-Si film or an Al-Si-Cu film. This conductive film is patterned by photolithography and left in the active region 40 of the entire element to form the source electrode pad 15. Also, this conductive film is left in the end of the edge termination region 41 to form the metal film 26.

Next, a polyimide film is formed on the source electrode pad 15 and the interlayer insulating film 11 in the edge termination region 41, and then the polyimide film is selectively removed by photolithography and etching to form a first protective film 21 and form an opening in the first protective film 21. Next, a plating film 16 is formed on the source electrode pad 15 exposed in the opening in the first protective film 21. Similarly, in the edge termination region 41, an opening is formed in the first protective film 21, and a second plating film 27 is formed on the metal film 26 exposed in the opening in the first protective film 21.

Next, a second protective film 23 is formed to cover the boundary between the plating film 16 and the first protective film 21, and the boundary between the second plating film 27 and the first protective film 21. The second protective film 23 is, for example, a polyimide film. Silicon carbide semiconductor elements are then cut out from the silicon carbide semiconductor wafer, and external electrode pins 19 are formed on the plating film 16 of the individual silicon carbide semiconductor elements via solder 17. In this manner, the silicon carbide semiconductor device shown in FIG. 1 is completed.

As described above, according to the silicon carbide semiconductor device of the embodiment, a second plating film is provided at the end of the edge termination region. This applies pressure to the silicon carbide semiconductor substrate, which can prevent distortion generated during dicing from growing from the edge termination region. This prevents a decrease in reliability even when the silicon carbide semiconductor device is used for a long period of time.

In addition, it is possible to detect when the dicing blade comes into contact with the second plating film, and the direction of the dicing blade can be calibrated based on the amount of contact between the dicing blade and the second plating film, making it possible to make the dicing blade parallel to the scribe line. This makes it possible to cut parallel to the scribe line, and suppresses distortion that occurs during dicing.

The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-mentioned embodiments, for example, the dimensions of each part and the impurity concentration are set in various ways according to the required specifications. In addition, each of the above-mentioned embodiments has been described using silicon carbide as a wide band gap semiconductor, but it is also applicable to wide band gap semiconductors other than silicon carbide, such as gallium nitride (GaN). In addition, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type.

As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles.

REFERENCE SIGNS LIST 1, 101 n ⁺ type silicon carbide substrate 2, 102 n type silicon carbide epitaxial layer 2a first n type silicon carbide epitaxial layer 2b second n type silicon carbide epitaxial layer 3, 103 p type silicon carbide epitaxial layer 4, 104 first p ⁺ type base region 4a lower first p ⁺ type base region 4b upper first p ⁺ type base region 5, 105 second p ⁺ type base region 6, 106 n type high concentration region 6a lower n type high concentration region 6b upper n type high concentration region 7, 107 n ⁺ type source region 8, 108 p ⁺⁺ type contact region 9, 109 gate insulating film 10, 110 gate electrode 11, 111 interlayer insulating film 13, 113 source electrode 14, 114 back electrode 15, 115 Source electrode pad 16, 116 Plating film 17, 117 Solder 18, 118 Trench 19, 119 External electrode pin 21, 121 First protective film 23, 123 Second protective film 24, 124 JTE structure 25, 125 n ⁺ -type semiconductor region 26 Metal film 27 Second plating film 30, 130 Oxide film 31 Scribe line 40, 140 Active region 41, 141 Edge termination region 42, 142 Dicing region 50, 150 Trench-type MOSFET

Claims (8)

an active region through which a main current flows, the active region being provided in a semiconductor substrate of a first conductivity type;
a termination region disposed outside the active region and having a breakdown voltage structure;
Equipped with
The active region comprises:
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate;
a gate insulating film in contact with the second semiconductor layer;
a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer;
a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
A second electrode provided on a rear surface of the semiconductor substrate;
having
The termination region is
The first semiconductor layer;
a plating film provided on an end portion of the first semiconductor layer opposite to the active region on a surface of the first semiconductor layer opposite to the semiconductor substrate , the end portion extending to a cut surface formed when individualizing the semiconductor device ;
A semiconductor device comprising: an active region through which a main current flows, the active region being provided in a semiconductor substrate of a first conductivity type;
a termination region disposed outside the active region and having a breakdown voltage structure;
Equipped with
The active region comprises:
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate;
a gate insulating film in contact with the second semiconductor layer;
a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer;
a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
A second electrode provided on a rear surface of the semiconductor substrate;
having
The termination region is
The first semiconductor layer;
a plating film provided on an end portion of the first semiconductor layer on a surface opposite to the semiconductor substrate, the end portion being opposite to the active region;
having
4. A semiconductor device comprising: a first electrode formed on said first terminal region; a second electrode formed on said first terminal region; an active region through which a main current flows, the active region being provided in a semiconductor substrate of a first conductivity type;
a termination region disposed outside the active region and having a breakdown voltage structure;
Equipped with
The active region comprises:
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate;
a gate insulating film in contact with the second semiconductor layer;
a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer;
a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
A second electrode provided on a rear surface of the semiconductor substrate;
having
The termination region is
The first semiconductor layer;
a plating film provided on an end portion of the first semiconductor layer on a surface opposite to the semiconductor substrate, the end portion being opposite to the active region;
having
4. The semiconductor device according to claim 1, wherein the plating film in the termination region is a NiB film. an active region through which a main current flows, the active region being provided in a semiconductor substrate of a first conductivity type;
a termination region disposed outside the active region and having a breakdown voltage structure;
Equipped with
The active region comprises:
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a second semiconductor layer of a second conductivity type selectively provided on a surface of the first semiconductor layer opposite to the semiconductor substrate;
a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on the opposite side to the semiconductor substrate;
a gate insulating film in contact with the second semiconductor layer;
a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor layer;
a first electrode provided on a surface of the second semiconductor layer and the first semiconductor region;
A second electrode provided on a rear surface of the semiconductor substrate;
having
The termination region is
The first semiconductor layer;
a plating film provided on an end portion of the first semiconductor layer on a surface opposite to the semiconductor substrate, the end portion being opposite to the active region;
having
an oxide film and a metal film are provided between the first semiconductor layer and the plating film;
A semiconductor device comprising: a protective film selectively provided on a surface of the plating film. 5. The semiconductor device according to claim 1, wherein the plating film surrounds the active region in a ring shape. a trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer;
5. The semiconductor device according to claim 1 , wherein the gate electrode is provided inside the trench with the gate insulating film interposed therebetween. 5. The semiconductor device according to claim 1, further comprising a second plating film provided on the first electrode. The semiconductor device according to claim 7, characterized in that the second plating film is the same metal film as the plating film.

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