JP7509174B2 - Image pickup element and image pickup device - Google Patents

Description

The present invention relates to a solid-state imaging device and an imaging device using the same.

A region selection technique is known that allows an arbitrary region to be selected in an imaging device. However, with region selection techniques, it is not possible to read out multiple regions of the imaging region.

Japanese Patent Application Laid-Open No. 9-46600

The solid-state imaging element according to the first aspect has a plurality of photoelectric conversion units, a signal line through which a signal based on charges photoelectrically converted by the photoelectric conversion units is output, a first selection unit provided between the photoelectric conversion units and the signal line and outputting the signal of the selected photoelectric conversion unit, and a second selection unit provided between the first selection unit and the signal line and outputting the signal of the photoelectric conversion unit output from the first selection unit to the signal line.

The solid-state imaging device according to the second aspect is the first aspect, and is provided with a region setting section that selects the first selection section or the second selection section of a partial region of the imaging region in which the multiple photoelectric conversion sections are arranged.

In the solid-state imaging device according to the third aspect, in the second aspect, the imaging area is divided into a plurality of predetermined areas, the area setting unit supplies a selection control signal for each of the plurality of predetermined areas to collectively select or deselect the first selection unit or the second selection unit of the corresponding area, and the partial area is made up of one or more of the plurality of predetermined areas.

In the solid-state imaging device according to the fourth aspect, in the second aspect, the region setting unit has a holding unit that holds a selection control signal for selecting or deselecting the first selection unit or the second selection unit, a writing unit that writes the selection control signal into the holding unit in response to a write control signal, and a write control unit that supplies the write control signal to the writing unit.

The solid-state imaging device according to the fifth aspect is any one of the second to fourth aspects, and includes a control unit that has a plurality of partial regions, selects the second selection unit or the first selection unit for each row of the plurality of partial regions, and performs read control for the row selected by the second selection unit or the first selection unit.

The solid-state imaging device according to the sixth aspect has a plurality of photoelectric conversion units, a signal line through which a signal based on charges photoelectrically converted by the photoelectric conversion units is output, a selection unit provided between the photoelectric conversion units and the signal line and outputting the signal of the selected photoelectric conversion unit, an amplifier provided in series with the selection unit between the photoelectric conversion units and the signal line and outputting the signal of the photoelectric conversion unit, and a power supply control means for selectively supplying, as a power supply voltage for the amplifier unit, an effective voltage level that is effective for the operation of the amplifier unit or an ineffective voltage level that is not effective for the operation.

The solid-state imaging element according to the seventh aspect has a plurality of photoelectric conversion units, a signal line through which a signal based on charges photoelectrically converted by the photoelectric conversion units is output, a first selection unit provided in common to two or more of the plurality of photoelectric conversion units and outputting the signal of the two or more selected photoelectric conversion units, and a second selection unit provided between the first selection unit and the signal line and outputting the signal of the photoelectric conversion units output from the first selection unit to the signal line.

The solid-state imaging device according to the eighth aspect is the seventh aspect, and further includes a region setting section that selects the first selection section or the second selection section of a partial region of the imaging region in which the multiple photoelectric conversion sections are arranged.

In the solid-state imaging device according to the ninth aspect, in the eighth aspect, the imaging region is divided into a plurality of predetermined regions, the region setting unit supplies a selection control signal for each of the plurality of predetermined regions to collectively select or deselect the first selection unit or the second selection unit of the region, and the partial region is made up of one or more of the plurality of predetermined regions.

The solid-state imaging device according to the tenth aspect is the eighth aspect, in which the region setting unit has a holding unit that holds a selection control signal for selecting or deselecting the first selection unit or the second selection unit, a writing unit that writes the selection control signal into the holding unit in response to a write control signal, and a write control unit that supplies the write control signal to the writing unit.

The solid-state imaging device according to the eleventh aspect is any one of the eighth to tenth aspects, and includes a control unit that has a plurality of partial regions, selects the second selection unit or the first selection unit for each row of the plurality of partial regions, and performs read control for the row selected by the second selection unit or the first selection unit.

The solid-state imaging element according to the twelfth aspect has a plurality of photoelectric conversion units, a signal line through which a signal based on charges photoelectrically converted by the photoelectric conversion units is output, a selection unit provided in common to two or more of the plurality of photoelectric conversion units and outputting the signal of the selected two or more photoelectric conversion units, an amplifier provided in series with the selection unit between the two or more photoelectric conversion units and the signal line and outputting the signal of the two or more photoelectric conversion units, and a power supply control means for selectively supplying an effective voltage level that is effective for the operation of the amplifier unit or an ineffective voltage level that is not effective for the operation as a power supply voltage for the amplifier unit.

The imaging device according to the thirteenth aspect comprises a solid-state imaging element according to any one of the second to fifth and eighth to eleventh aspects, and a user interface for a user to specify the partial area, and the partial area is set according to an instruction from the user interface.

An imaging device according to a 14th aspect comprises a solid-state imaging element according to any one of the second to fifth and eighth to eleventh aspects, and a detection unit that detects the positions of a plurality of imaging targets in the imaging area based on an image signal from the solid-state imaging element, and the partial area is set according to the positions detected by the detection unit.
As a means for solving the above problem, the following aspects are also presented: An imaging element based on a first surface includes a plurality of photoelectric conversion units that are provided in a first direction and a second direction and photoelectrically convert light into electric charges, a signal line to which a signal based on the electric charges photoelectrically converted by the photoelectric conversion units is output, a plurality of first output units that are provided in the first direction and the second direction and output the signal to the signal line, a plurality of second output units that are provided in the first direction and the second direction and output the signal to the signal line via the first output units, a first control line that is provided in common to the plurality of first output units provided in the first direction and the second direction in a first region and controls the first output units, a second control line that is provided in common to the plurality of first output units provided in the first direction and the second direction in a second region different from the first region and controls the first output units, and a third control line that is provided in common to the plurality of second output units provided in the first direction in the first region and the second region and controls the second output units.
The imaging element with a second surface has a setting section that performs settings in the imaging element with the first surface to output the signal from at least one of the first output section provided in the first region and the first output section provided in the second region.
The imaging element with a third surface is an imaging element with the first or second surface, which has a power supply line that is provided in common to a plurality of second output sections provided in the first direction and the second direction, and which supplies a power supply voltage to the second output sections.
The fourth surface imaging element is an imaging element having any one of the first to third surfaces, further comprising a holding portion that holds a control signal for causing the first output portion to output a signal.
The fifth surface imaging element is the same as the fourth surface imaging element, in which the holding portion is provided for each of the first output portions.
The imaging element using the sixth surface includes a plurality of photoelectric conversion units arranged in a first direction and a second direction, which photoelectrically convert light into electric charges; a signal line to which a signal based on the electric charges photoelectrically converted by the photoelectric conversion units is output; a plurality of first output units arranged in the first direction and the second direction, which output the signal to the signal line; a plurality of second output units arranged in the first direction and the second direction, which output the signal to the signal line via the first output units; a power supply line arranged in common to the plurality of second output units arranged in the first direction in a first region and a second region different from the first region, which supplies a voltage to the second output units; a first control line arranged in common to the plurality of second output units arranged in the first direction and the second direction in the first region, which controls the second output units; and a second control line arranged in common to the plurality of second output units arranged in the first direction and the second direction in the second region, which controls the second output units.
The seventh surface imaging element is an imaging element having the sixth surface, which has a setting section that performs settings to output the signal from at least one of the second output section provided in the first region and the second output section provided in the second region.
The imaging element having an eighth surface includes a plurality of photoelectric conversion units arranged in a first direction and a second direction, which photoelectrically convert light into electric charges; a signal line through which a signal based on the electric charges photoelectrically converted by the photoelectric conversion units is output; a plurality of first output units arranged in the first direction and the second direction, which output a signal based on the electric charges photoelectrically converted by the photoelectric conversion units to the signal line; a first power supply line arranged in common to the plurality of first output units arranged in the first direction and the second direction in a first region, which supplies a voltage to the first output units; a second power supply line arranged in common to the plurality of first output units arranged in the first direction and the second direction in a second region different from the first region, which supplies a voltage to the first output units; and a control line arranged in common to the plurality of first output units arranged in the first direction in the first region and the second region, which controls the first output units.
The imaging element according to the ninth surface is the imaging element according to the eighth surface, further comprising a setting section that performs settings for supplying a voltage to the first power supply line and the second power supply line.
The imaging element according to the tenth surface has: a plurality of photoelectric conversion units provided in a first direction and a second direction, which photoelectrically convert light into electric charges; a signal line through which a signal based on the electric charges photoelectrically converted by the photoelectric conversion units is output; a first output unit provided in the first direction and the second direction, which outputs a signal based on the electric charges photoelectrically converted by the photoelectric conversion units; a power supply line provided in common to the plurality of first output units provided in the first direction in a first region, for supplying a voltage to the first output units; a second power supply line provided in common to the plurality of first output units provided in the first direction and the second direction in a second region different from the first region, for supplying a voltage to the first output units; a first control line provided in common to the plurality of first output units provided in the first direction and the second direction in the first region, for controlling the first output units; and a second control line provided in common to the plurality of first output units provided in the first direction and the second direction in the second region, for controlling the first output units.
The imaging element having an eleventh surface is an imaging element having the tenth surface, which has a setting section that performs settings to output the signal from at least one of the first output section provided in the first region and the first output section provided in the second region.
An imaging element having a 12th surface is an imaging element having the 10th or 11th surface, in which the power supply line is provided in common to a plurality of first output sections provided in the first direction in the first region and the second region.
The imaging element having a thirteenth surface is an imaging element having any one of the first to twelfth surfaces, further comprising a holding portion that holds a control signal for causing the first output portion to output a signal.
The fourteenth surface imaging element is the same as the thirteenth surface imaging element, in which the holding portion is provided for each of the first output portions.
An image sensor having a fifteenth surface is an image sensor having any one of the first to fourteenth surfaces, in which the first output section is provided in common to two or more photoelectric conversion sections.
The imaging device according to the 16th surface includes an imaging element according to any one of the 1st to 15th surfaces, and a designation unit capable of designating at least one of the first region and the second region in order to output the signal from at least one of the first region and the second region.
The imaging device according to the 17th aspect includes an imaging element according to any one of the 1st to 15th aspects, and a detection unit that detects a subject based on the signal from the imaging element in order to output the signal from at least one of the first area and the second area.

The present invention provides a solid-state imaging element capable of quickly reading out multiple desired partial areas of an imaging area, and an imaging device using the same.

1 is a schematic block diagram showing an electronic camera according to a first embodiment of the present invention; 2 is a circuit diagram showing a schematic configuration of a solid-state imaging element in FIG. 1 . FIG. 2 is a schematic plan view showing the solid-state imaging element in FIG. 1 . 2 is a circuit diagram showing a predetermined partial area forming a part of an imaging area of the solid-state imaging element in FIG. 1 . FIG. 5 is a circuit diagram illustrating an abstraction of the circuit shown in FIG. 4 . 2 is a diagram showing a schematic example of a setting of a partial region to be read out of an imaging region of the solid-state imaging element in FIG. 1; FIG. 7 is a diagram showing a selection control signal for realizing the setting example shown in FIG. 6 in the solid-state imaging element in FIG. 4 is a timing chart showing an example of read control in a partial area shooting mode of the solid-state imaging element in FIG. 1 . 1. FIG. 4 is a diagram showing another example of setting a partial region to be read out of the imaging region of the solid-state imaging element in FIG. 10 is a diagram showing a selection control signal for realizing the setting example shown in FIG. 9 in the solid-state imaging element in FIG. 1. FIG. 4 is a diagram showing a schematic diagram of still another setting example of a partial region to be read out of the imaging region of the solid-state imaging element in FIG. 12 is a diagram showing a selection control signal for implementing the setting example shown in FIG. 11; 10 is a timing chart showing another example of read control in the partial area shooting mode of the solid-state imaging element in FIG. 4 is a timing chart showing an example of read control in a full-area shooting mode of the solid-state imaging element in FIG. 1 . 4 is a schematic flowchart showing an example of an operation of the electronic camera shown in FIG. 1 in a first partial area shooting mode. 4 is a schematic flowchart showing an example of an operation of the electronic camera shown in FIG. 1 in a second partial area shooting mode. FIG. 11 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a second embodiment of the present invention. 18 is a circuit diagram showing a predetermined partial region that forms a part of the imaging region of the solid-state imaging element shown in FIG. 17. FIG. 19 is a circuit diagram illustrating an abstraction of the circuit illustrated in FIG. 18 . 18 is a diagram showing a power supply voltage signal for realizing the same setting as the setting example shown in FIG. 6 in the solid-state imaging element shown in FIG. 17 . FIG. 11 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a third embodiment of the present invention. 22 is a circuit diagram showing a predetermined partial area forming a part of the imaging area of the solid-state imaging element shown in FIG. 21. 22 is a timing chart showing an example of read control in a partial area imaging mode of the solid-state imaging element shown in FIG. 21. FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a fourth embodiment of the present invention. 25 is a circuit diagram showing a predetermined partial region that forms a part of the imaging region of the solid-state imaging element shown in FIG. 24. FIG. 26 is a circuit diagram illustrating an abstraction of the circuit shown in FIG. 25 . 25 is a timing chart showing an example of read control in a partial area imaging mode of the solid-state imaging element shown in FIG. 24. FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a fifth embodiment of the present invention. 29 is a circuit diagram showing a part of an imaging region of the solid-state imaging element shown in FIG. 28. 29 is a timing chart showing write control signals when an H signal and an L signal are written to a capacitor in the solid-state imaging element shown in FIG. 28. 29 is a timing chart showing write control signals for realizing the same settings as the setting example shown in FIG. 6 in the solid-state imaging element shown in FIG. 28 . FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a sixth embodiment of the present invention. 33 is a circuit diagram showing a part of an imaging region of the solid-state imaging element shown in FIG. 32. FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state imaging device used in an electronic camera according to a seventh embodiment of the present invention. 35 is a circuit diagram showing a part of an imaging region of the solid-state imaging element shown in FIG. 34. FIG. 13 is a circuit diagram showing a schematic configuration of a solid-state imaging element used in an electronic camera according to an eighth embodiment of the present invention. 37 is a circuit diagram showing one pixel of the solid-state imaging element shown in FIG. 36. 37 is a timing chart showing write control signals for realizing the same settings as the setting example shown in FIG. 6 in the solid-state imaging element shown in FIG. 36 .

The solid-state imaging element and imaging device according to the present invention will be described below with reference to the drawings.

[First embodiment]

Figure 1 is a schematic block diagram showing an electronic camera 1 as an imaging device according to a first embodiment of the present invention.

The electronic camera 1 according to this embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this and can be applied to various imaging devices such as other electronic cameras such as compact cameras, electronic cameras mounted on mobile phones, electronic cameras such as video cameras that capture moving images, surveillance cameras that capture monitoring videos, imaging devices built into microscopes to capture microscopic images, and imaging devices built into telescopes to capture telescopic images.

A photographing lens 2 is attached to the electronic camera 1. The focus and aperture of this photographing lens 2 are driven by a lens control unit 3. The imaging surface of a solid-state imaging device 4 is disposed in the image space of this photographing lens 2.

The solid-state imaging element 4 is driven by the command of the imaging control unit 5 and outputs a digital image signal. When taking a still image, the imaging control unit 5 controls the solid-state imaging element 4 to perform a predetermined readout operation after exposing the image with a mechanical shutter (not shown) after a so-called global reset in which all pixels are reset at the same time. In addition, in the electronic viewfinder mode or when taking a video (in the first and second partial area shooting modes and the full area shooting mode described later, etc.), the imaging control unit 5 controls the solid-state imaging element 4 to perform a predetermined readout operation while performing a so-called rolling electronic shutter. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state imaging element 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The lens control unit 3, the imaging control unit 5, the CPU 9, the display unit 10 such as a liquid crystal display panel, the recording unit 11, the image compression unit 12, and the image processing unit 13 are also connected to the bus 8. An operation unit 14 such as a release button is connected to the CPU 9. A recording medium 11a is removably attached to the recording unit 11.

When the electronic viewfinder mode, video shooting, still image shooting, etc. are instructed by the operation unit 14, the CPU 9 in the electronic camera 1 drives the imaging control unit 5 accordingly. At this time, the focus and aperture are adjusted appropriately by the lens control unit 3. The solid-state imaging element 4 is driven by the command of the imaging control unit 5 to output a digital image signal. The digital image signal from the solid-state imaging element 4 is stored in the memory 7 after being processed by the digital signal processing unit 6. The CPU 9 displays the image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal in the recording medium 11a during video shooting. In the case of still image shooting, etc., the CPU 9 performs the desired processing in the image processing unit 13 or image compression unit 12 as necessary based on the command of the operation unit 14 after the digital image signal from the solid-state imaging element 4 is processed by the digital signal processing unit 6 and stored in the memory 7, and has the recording unit 11 output the processed signal and record it on the recording medium 11a.

Figure 2 is a circuit diagram showing a schematic configuration of the solid-state imaging element 4 in Figure 1. In this embodiment, the solid-state imaging element 4 is configured as a CMOS type solid-state imaging element, but it may also be configured as, for example, another XY address type solid-state imaging element.

The solid-state imaging element 4 has pixels PX arranged in a two-dimensional matrix of N rows and M columns in the imaging region 21, a vertical scanning circuit 22, an area setting circuit 23, control lines 24-26 provided for each row of pixels PX, a plurality of (M) vertical signal lines 27 provided for each column of pixels PX and receiving signals from the pixels PX in the corresponding column, a constant current source 28 provided for each vertical signal line 27, a column amplifier 29 provided corresponding to each vertical signal line 27, a CDS circuit (correlated double sampling circuit) 30, and an A/D converter 31, a horizontal readout circuit 32, and a control line 33 provided for each predetermined partial area AR (see FIG. 3 described later) of the imaging region 21. The predetermined partial area AR is a predetermined part (partial area) of the imaging region 21.

The column amplifier 29 may be an analog amplifier or a so-called switched capacitor amplifier. Also, the column amplifier 29 does not necessarily have to be provided.

Figure 3 is a schematic plan view showing the solid-state imaging element 4 (particularly the imaging region 21) in Figure 1. In this embodiment, as shown in Figure 3, the imaging region 21 of the solid-state imaging element 4 is divided into J x K predefined partial regions AR arranged in a matrix and having J rows and K columns. When distinguishing between the predefined partial regions AR, the predefined partial region AR in the jth row and kth column is indicated by the symbol AR (j, k). As shown in Figures 4 and 5, each predefined partial region AR is made up of A x B pixels PX (A is an integer of 2 or more, and B is an integer of 1 or more) in A rows and B columns. In this embodiment, the size of each predefined partial region AR (number of rows A and number of columns B of pixels PX) is the same, but this is not limited to this in the present invention. However, it is preferable that the number of rows A of pixels PX in each predefined partial region AR is the same.

Figure 4 is a circuit diagram showing a predefined partial area AR that forms part of the imaging area 21 of the solid-state imaging element 4 in Figure 1. Figure 4 shows a predefined partial area AR (j, k) in the jth row and kth column, and a part of the predefined partial area AR (j-1, k) in the j-1th row and kth column adjacent thereto. The predefined partial area AR (j, k) is made up of A x B pixels PX in A rows and B columns arranged from the nth row to the (n+A-1)th row. For convenience of drawing notation, Figure 4 does not show the connection state of each control line 24 to 26, 33 and the power supply line 34 described later, but each control line 24 to 26 is commonly connected for each row of pixels PX, the control line 33 is commonly connected for each predefined partial area AR, and the power supply line 34 is commonly connected to all pixels PX.

In this embodiment, all pixels PX have the same circuit configuration. Unlike a typical CMOS image sensor, in this embodiment, each pixel PX has two selection transistors (SEL, ASEL) for selecting the pixel PX, but the other configurations of each pixel PX are the same as those of a typical CMOS image sensor.

That is, as shown in Fig. 4, each pixel PX has a photodiode PD as a photoelectric conversion unit that generates and accumulates a charge according to incident light, a floating capacitance unit FD as a charge-voltage conversion unit that receives the charge and converts the charge into a voltage, an amplification transistor AMP as an amplifier that outputs a signal according to the potential of the floating capacitance unit FD as an output signal of the pixel PX, a transfer transistor TX that transfers the charge from the photodiode PD to the floating capacitance unit FD, a reset transistor RST that resets the potential of the floating capacitance unit FD, a selection transistor SEL that serves as a selection switch as a first selection unit for selecting the pixel PX, and a selection transistor ASEL that serves as a selection switch as a second selection unit for selecting the pixel PX, and are connected as shown in Fig. 4. In this embodiment, the drains (point b in Fig. 4) of the amplification transistors AMP of all pixels PX are commonly connected by a power supply line 34, and an effective voltage level VDD that is effective for the operation of the amplification transistor AMP is fixedly supplied thereto as a power supply voltage of the amplification transistor AMP. This effective voltage level VDD is also supplied to the drain of the reset transistor RST of each pixel PX via a power supply line 34. Note that the power supply line 34 is not shown in FIG. 2.

In this embodiment, the output signal of each pixel PX is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction with respect to the pixel PX only when both the first and second selection units of the pixel PX are in the selected state. Specifically, in this embodiment, this is realized by connecting the selection transistors SEL and ASEL in series between the source of the amplification transistor AMP and the vertical signal line 27 corresponding to the pixel PX in each pixel PX. Only when both the selection transistors SEL and ASEL are on (in the selected state), the output signal of the pixel PX is output to the vertical signal line 27. Note that the connection order of the selection transistors SEL and ASEL between the amplification transistor AMP and the vertical signal line 27 may be reversed from that shown in FIG. 4.

Although not shown in the drawings, in this embodiment, multiple types of color filters that transmit light of different color components are arranged in a predetermined color array (e.g., Bayer array) on the light incident side of the photodiode PD of each pixel PX. The pixel PX outputs an electrical signal corresponding to each color through color separation by the color filters.

In this embodiment, the transistors TX, AMP, RST, SEL, and ASEL are all nMOS transistors.

The gates of the transfer transistors TX are commonly connected to a control line 25 for each row of pixels PX, and a control signal φTX is supplied to them from the vertical scanning circuit 22. The gates of the reset transistors RST are commonly connected to a control line 24 for each row of pixels PX, and a control signal φRST is supplied to them from the vertical scanning circuit 22. The gates of the selection transistors SEL are commonly connected to a control line 26 for each row, and a control signal φSEL is supplied to them from the vertical scanning circuit 22. When distinguishing between the control signals φTX for each row, the control signal φTX supplied to the gate of the transfer transistor TX of the pixel PX in the nth row is indicated by the symbol φTX(n). This also applies to the other control signals φRST and φSEL.

The gate of the selection transistor ASEL (point a in FIG. 4) is commonly connected to the control line 33 for each predefined partial area AR, and a control signal φASEL is supplied to it from the area setting circuit 23. FIG. 5 shows an abstracted view of the circuit shown in FIG. 4, focusing on the connection relationship of the gate (point a) of the selection transistor ASEL of each predefined partial area AR by the control line 33. When each control signal φASEL is distinguished for each predefined partial area AR, the control signal φASEL supplied to the gate of the selection transistor ASEL of the pixel PX in the jth row and kth column predefined partial area AR (j, k) is indicated by the symbol φASEL(j, k). Note that the layout of the area setting circuit 23 and the actual layout of the control line 33 (such as the route to be drawn) are not limited in any way.

Under the control of the imaging control unit 5 in FIG. 1, the area setting circuit 23 supplies a control signal φASEL as a selection control signal for collectively selecting or deselecting the selection transistors ASEL as the second selection units of the pixels PX in each of the predefined partial areas AR in the imaging area 21. As a result, the area setting circuit 23 sets the predefined partial area AR in which the selection transistor ASEL is in the selected state as the area from which the output signals of the pixels PX in the imaging area 21 are read out.

Under the control of the imaging control unit 5 in FIG. 1, the vertical scanning circuit 22 outputs control signals φTX, φRST, and φSEL for each row of pixels PX, and in conjunction with the area setting operation by the area setting circuit 23, realizes still image readout operations and video readout operations such as the first and second partial area shooting modes described below. Through this control, the signals (analog signals) of the pixels PX in the area set by the area setting circuit 23 are supplied to the corresponding vertical signal lines 27.

The signal read out to the vertical signal line 27 is amplified by the column amplifier 29 for each column, and then processed by the CDS circuit 30 to obtain the difference between the optical signal (a signal containing optical information photoelectrically converted by the pixel PX) and the dark signal (a difference signal containing a noise component to be subtracted from the optical signal), and then converted into a digital signal by the A/D converter 31, which then stores the digital signal. The digital image signal stored in each A/D converter 31 is horizontally scanned by the horizontal readout circuit 32, converted into a predetermined signal format as necessary, and output to the outside (digital signal processing unit 6 in FIG. 1).

The CDS circuit 30 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. 1, samples the output signal of the column amplifier 29 as a dark signal at the timing when φDARKC switches from high level (H) to low level (L), and receives an optical signal sampling signal φSIGC from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1, samples the output signal of the column amplifier 29 as an optical signal at the timing when φSIGC switches from high level to low level. Then, the CDS circuit 30 outputs a signal corresponding to the difference between the sampled dark signal and the optical signal based on the clock or pulse from the timing generation circuit. A known configuration can be adopted as the configuration of such a CDS circuit 30.

Figure 6 is a schematic diagram showing an example of setting a partial area to be read out of the imaging area 21 of the solid-state imaging element 4 in the partial area shooting mode. The partial area shooting mode is an operation mode in which the output signals of pixels PX of a desired partial area or desired multiple partial areas of the imaging area 21 of the solid-state imaging element 4 are selectively read out. For ease of understanding, in Figure 6, it is assumed that N = 9, M = 12, A = 3, and B = 3, the imaging area 21 is made up of 9 x 12 pixels PX in 9 rows and 12 columns, and each predefined partial area AR is made up of pixels PX in 3 rows and 3 columns. The following explanation is equally applicable even if the values of N, M, A, and B are other values.

In FIG. 6, the predefined partial areas AR(3,1), AR(1,2), AR(2,3), and AR(1,4) that are set as the four partial areas to be read are hatched. In this example, each partial area to be read consists of one predefined partial area AR.

Figure 7 shows the selection control signal φASEL that realizes the setting example shown in Figure 6 in the solid-state imaging element 4 in Figure 1. The selection control signals φASEL (3,1), φASEL (1,2), φASEL (2,3), and φASEL (1,4) supplied to the gates of the selection transistors ASEL in the predefined partial areas AR (3,1), AR (1,2), AR (2,3), and AR (1,4) are maintained at a high level (H), and the other selection control signals φASEL are maintained at a low level (L). As a result, the selection transistors ASEL in the predefined partial areas AR (3,1), AR (1,2), AR (2,3), and AR (1,4) are maintained on, while the selection transistors ASEL in the other predefined partial areas AR are maintained off.

In this embodiment, in the partial area shooting mode, when the partial area to be read out is set as shown in FIG. 6, for example, read control is performed as shown in FIG. 8. FIG. 8 is a timing chart showing an example of read control in the partial area shooting mode of the solid-state imaging element 4 in FIG. 1.

In the example shown in FIG. 8, the vertical scanning circuit 22 simultaneously controls readout of the first, fourth, and seventh rows of pixels PX in the imaging area 21 corresponding to the first row of pixels PX in each predefined partial area AR during the period T1, and simultaneously controls readout of the second, fifth, and eighth rows of pixels PX in the imaging area 21 corresponding to the second row of pixels PX in each predefined partial area AR during the next period T2, and simultaneously controls readout of the third, sixth, and ninth rows of pixels PX in the imaging area 21 corresponding to the third row of pixels PX in each predefined partial area AR during the next period T3, thereby completing the readout of one frame. By sequentially repeating the periods T1 to T3, multiple frames are read out by the rolling electronic shutter. For example, the exposure period of the first row of pixels PX is the period from when the control signal φTX(1) of the first row changed from high level to low level last time to when the control signal φTX(1) changes from high level to low level this time. Read control for each period T1 to T3 is described in detail below.

Just before the start of each period T1 to T3, the transistors SEL, RST, and TX of the pixels PX in all rows are off.

During period T1, φSEL(1) in the first row, φSEL(4) in the fourth row, and φSEL(7) in the seventh row are set to high level, and the selection transistors SEL(1), SEL(4), and SEL(7) of the pixels PX in the first, fourth, and seventh rows are turned on, and the pixels PX in the first, fourth, and seventh rows are selected. However, since the selection control signal φASEL is now as shown in FIG. 7 so that the setting example shown in FIG. 6 is realized, the selection transistors ASEL of the pixels PX in the hatched columns (4th to 6th columns, 10th to 12th columns) of the pixels PX in the first row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (1st to 3rd columns, 7th to 9th columns) of the pixels PX in the first row are turned off. In addition, the selection transistors ASEL of the pixels PX in the hatched columns (7th to 9th columns) of the pixels PX in the 4th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (1st to 6th columns, 10th to 12th columns) of the pixels PX in the 4th row are turned off. Furthermore, the selection transistors ASEL of the pixels PX in the hatched columns (1st to 3rd columns) of the pixels PX in the 7th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (4th to 12th columns) of the pixels PX in the 7th row are turned off.

Therefore, during period T1, only the pixels PX in which both the selection transistors SEL and ASEL are on (pixels PX in the 4th to 6th columns and the 10th to 12th columns in the 1st row, pixels PX in the 7th to 9th columns in the 4th row, and pixels PX in the 1st to 3rd columns in the 7th row) can output their output signals to the corresponding vertical signal lines 27.

For a certain period of time immediately after the start of period T1, the control signals φRST(1), φRST(4), and φRST(7) in the first, fourth, and seventh rows are set to high level, the reset transistors RST in the pixels PX in the first, fourth, and seventh rows are temporarily turned on, and the potential of the floating capacitance section FD (the potential of the gate of the amplification transistor AMP) is temporarily reset to the voltage level VDD.

By setting the dark signal sampling signal φDARKC to a high level for a certain period of time from time t1 thereafter during period T1, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the 4th to 6th and 10th to 12th columns in the 1st row, the pixels PX in the 7th to 9th columns in the 4th row, and the pixels PX in the 1st to 3rd columns in the 7th row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal.

For a certain period of time from time t2 after that in period T1, the control signals φTX(1), φTX(4), and φTX(7) of the first, fourth, and seventh rows are set to high level, and the transfer transistors TX of the pixels PX of the first, fourth, and seventh rows are turned on. As a result, the signal charges stored in the photodiodes PD of the pixels PX of the first, fourth, and seventh rows are transferred to the floating capacitance units FD of the pixels PX of the first, fourth, and seventh rows, respectively. The potentials of the floating capacitance units FD of the pixels PX of the first, fourth, and seventh rows (potentials of the gates of the amplification transistors AMP), excluding noise components, are proportional to the amount of each signal charge and the reciprocal of each capacitance value of the floating capacitance units FD of the pixels PX of the first, fourth, and seventh rows.

After that, from time t3 during period T1, the optical signal sampling signal φSIGC is set to a high level for a certain period of time, so that the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the 4th to 6th and 10th to 12th columns in the 1st row, the pixels PX in the 7th to 9th columns in the 4th row, and the pixels PX in the 1st to 3rd columns in the 7th row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal.

After that, after φSIGC goes low, the CDS circuit 30 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled light signal. The A/D converter 31 converts the signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A/D converter 31 is horizontally scanned by the horizontal readout circuit 32 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital image signal.

In period T2 after period T1, φSEL(2) in the second row, φSEL(5) in the fifth row, and φSEL(8) in the eighth row are set to high level, and the selection transistors SEL(2), SEL(5), and SEL(8) of the pixels PX in the second, fifth, and eighth rows are turned on, and the pixels PX in the second, fifth, and eighth rows are selected. However, since the selection control signal φASEL is now as shown in FIG. 7 so that the setting example shown in FIG. 6 is realized, the selection transistors ASEL of the pixels PX in the hatched columns (4th to 6th columns, 10th to 12th columns) of the pixels PX in the second row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (1st to 3rd columns, 7th to 9th columns) of the pixels PX in the second row are turned off. In addition, the selection transistors ASEL of the pixels PX in the hatched columns (7th to 9th columns) of the pixels PX in the 5th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (1st to 6th columns, 10th to 12th columns) of the pixels PX in the 5th row are turned off. Furthermore, the selection transistors ASEL of the pixels PX in the hatched columns (1st to 3rd columns) of the pixels PX in the 8th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (4th to 12th columns) of the pixels PX in the 8th row are turned off.

Therefore, during period T2, only the pixels PX in which both the selection transistors SEL and ASEL are on (the pixels PX in the 4th to 6th columns and the 10th to 12th columns in the 2nd row, the pixels PX in the 7th to 9th columns in the 5th row, and the pixels PX in the 1st to 3rd columns in the 8th row) can output their output signals to the corresponding vertical signal lines 27.

For a certain period of time immediately after the start of period T2, the control signals φRST(2), φRST(5), and φRST(8) in the second, fifth, and eighth rows are set to high level, the reset transistors RST in the pixels PX in the second, fifth, and eighth rows are temporarily turned on, and the potential of the floating capacitance section FD (the potential of the gate of the amplification transistor AMP) is temporarily reset to the voltage level VDD.

By setting the dark signal sampling signal φDARKC to a high level for a certain period of time from a later point in time during period T2, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the 4th to 6th and 10th to 12th columns in the 2nd row, the pixels PX in the 7th to 9th columns in the 5th row, and the pixels PX in the 1st to 3rd columns in the 8th row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal.

For a certain period from a later point in time during period T2, the control signals φTX(2), φTX(5), and φTX(8) of the second, fifth, and eighth rows are set to high level, and the transfer transistors TX of the pixels PX of the second, fifth, and eighth rows are turned on. As a result, the signal charges stored in the photodiodes PD of the pixels PX of the second, fifth, and eighth rows are transferred to the floating capacitance units FD of the pixels PX of the second, fifth, and eighth rows, respectively. The potentials of the floating capacitance units FD of the pixels PX of the second, fifth, and eighth rows (potentials of the gates of the amplification transistors AMP) are proportional to the amount of each signal charge and the reciprocal of each capacitance value of the floating capacitance units FD of the pixels PX of the second, fifth, and eighth rows, excluding noise components.

By setting the optical signal sampling signal φSIGC to a high level for a certain period of time from a later point in time during period T2, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the 4th to 6th and 10th to 12th columns in the 2nd row, the pixels PX in the 7th to 9th columns in the 5th row, and the pixels PX in the 1st to 3rd columns in the 8th row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal.

After that, after φSIGC goes low, the CDS circuit 30 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled light signal. The A/D converter 31 converts the signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A/D converter 31 is horizontally scanned by the horizontal readout circuit 32 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital image signal.

In period T3 after period T2, φSEL(3) in the third row, φSEL(6) in the sixth row, and φSEL(9) in the ninth row are set to high level, and the selection transistors SEL(3), SEL(6), and SEL(9) of the pixels PX in the third, sixth, and ninth rows are turned on, and the pixels PX in the third, sixth, and ninth rows are selected. However, since the selection control signal φASEL is now as shown in FIG. 7 so that the setting example shown in FIG. 6 is realized, the selection transistors ASEL of the pixels PX in the hatched columns (fourth to sixth columns, tenth to twelfth columns) of the pixels PX in the third row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (first to third columns, seventh to ninth columns) of the pixels PX in the third row are turned off. In addition, the selection transistors ASEL of the pixels PX in the hatched columns (7th to 9th columns) of the pixels PX in the 6th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (1st to 6th columns, 10th to 12th columns) of the pixels PX in the 6th row are turned off. Furthermore, the selection transistors ASEL of the pixels PX in the hatched columns (1st to 3rd columns) of the pixels PX in the 8th row are turned on, and the selection transistors ASEL of the pixels PX in the non-hatched columns (4th to 12th columns) of the pixels PX in the 9th row are turned off.

Therefore, during period T3, only the pixels PX in which both the selection transistors SEL and ASEL are on (pixels PX in the fourth to sixth columns and the tenth to twelfth columns in the third row, pixels PX in the seventh to ninth columns in the sixth row, and pixels PX in the first to third columns in the ninth row) can output their output signals to the corresponding vertical signal lines 27.

For a fixed period of time immediately after the start of period T3, the control signals φRST(3), φRST(6), and φRST(9) in the third, sixth, and ninth rows are set to high level, the reset transistors RST in the pixels PX in the third, sixth, and ninth rows are temporarily turned on, and the potential of the floating capacitance section FD (the potential of the gate of the amplification transistor AMP) is temporarily reset to the voltage level VDD.

By setting the dark signal sampling signal φDARKC to a high level for a certain period of time from a later point in time during period T3, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the fourth to sixth and tenth to twelfth columns in the third row, the pixels PX in the seventh to ninth columns in the sixth row, and the pixels PX in the first to third columns in the ninth row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal.

For a certain period from a later point in time during period T3, the control signals φTX(3), φTX(6), and φTX(9) of the third, sixth, and ninth rows are set to high level, and the transfer transistors TX of the pixels PX of the third, sixth, and ninth rows are turned on. As a result, the signal charges stored in the photodiodes PD of the pixels PX of the third, sixth, and ninth rows are transferred to the floating capacitance units FD of the pixels PX of the third, sixth, and ninth rows, respectively. The potentials of the floating capacitance units FD of the pixels PX of the third, sixth, and ninth rows (potentials of the gates of the amplification transistors AMP), excluding noise components, are proportional to the amount of each signal charge and the reciprocal of each capacitance value of the floating capacitance units FD of the pixels PX of the third, sixth, and ninth rows.

By setting the optical signal sampling signal φSIGC to a high level for a certain period of time from a later point in time during period T3, the potential appearing at the gate of the amplification transistor AMP of the pixels PX in the fourth to sixth and tenth to twelfth columns in the third row, the pixels PX in the seventh to ninth columns in the sixth row, and the pixels PX in the first to third columns in the ninth row is amplified by the amplification transistor AMP of the pixel PX, and then output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal.

After that, after φSIGC goes low, the CDS circuit 30 outputs a signal corresponding to the difference between the previously sampled dark signal and the previously sampled light signal. The A/D converter 31 converts the signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A/D converter 31 is horizontally scanned by the horizontal readout circuit 32 and output to the outside (digital signal processing unit 6 in FIG. 1) as a digital image signal.

In this way, the output signals of the pixels PX in the multiple partial regions set as shown in Figure 6 are read out.

Figure 9 is a diagram showing a schematic diagram of another setting example of a partial area to be read out of the imaging area 21 of the solid-state imaging element 4 in the partial area shooting mode, and corresponds to Figure 6. Figure 10 shows the selection control signal φASEL that realizes the setting example shown in Figure 9 in the solid-state imaging element 4 in Figure 1, and corresponds to Figure 7.

In FIG. 9, the predefined partial areas AR(1,1), AR(1,2), AR(2,3), and AR(2,4) that are set as the two partial areas to be read are hatched. In this example, one partial area to be read consists of the two predefined partial areas AR(1,1) and AR(1,2), and the other partial area to be read consists of the two predefined partial areas AR(2,3) and AR(2,4).

As described above, in this embodiment, each of the one or more partial areas to be read out may consist of one predefined partial area AR, or may consist of multiple predefined partial areas AR. Also, in this embodiment, when multiple partial areas are read out, each partial area does not necessarily have to consist of the same number of predefined partial areas AR, and the number of predefined partial areas AR that make up one partial area to be read out may be different from the number of predefined partial areas AR that make up another partial area to be read out.

In this embodiment, even when the partial area to be read out is set as shown in FIG. 9 in the partial area shooting mode, read control is performed as shown in FIG. 8 in the same way as when the partial area to be read out is set as shown in FIG. 6, for example.

Figure 11 is a diagram showing a schematic diagram of yet another setting example of a partial area to be read out of the imaging area 21 of the solid-state imaging element 4 in the partial area shooting mode, and corresponds to Figure 6. Figure 12 shows the selection control signal φASEL that realizes the setting example shown in Figure 11 in the solid-state imaging element 4 in Figure 1, and corresponds to Figure 7.

In FIG. 11, the predefined partial areas AR(3,1), AR(1,1), AR(2,3), and AR(1,4) that are set as the four partial areas to be read out are hatched. In the setting example shown in FIG. 6 and the setting example shown in FIG. 9, no two or more predefined partial areas AR are set as areas to be read out in any column of predefined partial areas AR, whereas in the setting example shown in FIG. 11, two predefined partial areas AR(3,1) and AR(1,1) are set as partial areas to be read out in the first column of predefined partial areas AR.

Therefore, in this embodiment, even if the partial area to be read out is set as shown in FIG. 11 in the partial area shooting mode, if read control is performed as shown in FIG. 8, the output signals of two or more pixels PX will be read out simultaneously to the same vertical signal line 27, causing interference between the two signals, and the output signals of the pixels PX cannot be read out properly. Specifically, in period T1 in FIG. 8, the output signals of the pixels PX in the first to third columns in the first row and the output signals of the pixels PX in the first to third columns in the seventh row are simultaneously read out to the same vertical signal line 27, causing interference between the two signals; in period T2 in FIG. 8, the output signals of the pixels PX in the first to third columns in the second row and the output signals of the pixels PX in the first to third columns in the eighth row are simultaneously read out to the same vertical signal line 27, causing interference between the two signals; and in period T3 in FIG. 8, the output signals of the pixels PX in the first to third columns in the third row and the output signals of the pixels PX in the first to third columns in the ninth row are simultaneously read out to the same vertical signal line 27, causing interference between the two signals.

Therefore, in this embodiment, if it is permitted that the partial area to be read out in the partial area shooting mode is set as shown in FIG. 11, the vertical scanning circuit 22 may perform, for example, the read control shown in FIG. 13 instead of the read control shown in FIG. 8. FIG. 13 is a timing chart showing another example of the read control in the partial area shooting mode of the solid-state imaging element 4 in FIG. 1, and corresponds to FIG. 8.

In the example shown in FIG. 13, the vertical scanning circuit 22 performs read control in accordance with the setting of the partial area shown in FIG. 11 to be read out, so that read control is performed simultaneously for as many pixel rows as possible, with the necessary condition that the output signals of two or more pixels PX are not simultaneously read out to the same vertical signal line 27.

Specifically, in the example shown in FIG. 13, the vertical scanning circuit 22 simultaneously controls the readout of the first and fourth rows of pixels PX in the imaging area 21 during period T1, simultaneously controls the readout of the second and fifth rows of pixels PX in the imaging area 21 during the next period T2, simultaneously controls the readout of the third and sixth rows of pixels PX in the imaging area 21 during the next period T3, simultaneously controls the readout of the seventh row of pixels PX in the imaging area 21 during the next period T4, simultaneously controls the readout of the eighth row of pixels PX in the imaging area 21 during the next period T5, and simultaneously controls the readout of the ninth row of pixels PX in the imaging area 21 during the next period T6, thereby completing the readout of one frame. By sequentially repeating periods T1 to T6, multiple frames are read out by the rolling electronic shutter.

In this embodiment, the region setting circuit 23 may be configured to arbitrarily set the region to be read out under the constraint that two or more predefined partial regions AR are not simultaneously set as regions to be read out in any column of the predefined partial regions AR in the partial region shooting mode, and the vertical scanning circuit 22 may be configured to always perform the read control shown in FIG. 8 in the partial region shooting mode. In the following description, such a configuration is called a "restricted partial region setting configuration." In this case, the region setting shown in FIG. 6 and the region setting shown in FIG. 9 are permitted, but the region setting shown in FIG. 11 is not permitted. Such a vertical scanning circuit 22 may be configured, for example, using a vertical shift register or a switch, or a decoder circuit using a memory, etc.

Alternatively, in this embodiment, the region setting circuit 23 may be configured to arbitrarily set the region to be read out without any constraints when setting the partial region to be read out in the partial region shooting mode, and the vertical scanning circuit 22 may be configured to perform read control such that read control is performed simultaneously for as many pixel rows as possible, with the necessary condition that the output signals of two or more pixels PX are not simultaneously read out to the same vertical signal line 27 in accordance with the partial region setting in the partial region shooting mode. In the following description, such a configuration is called a "configuration of partial region setting without constraints". In this case, not only the region setting shown in FIG. 6 or the region setting shown in FIG. 9, but also the region setting shown in FIG. 11 is allowed. In the case of the region setting shown in FIG. 6 or the region setting shown in FIG. 9, the vertical scanning circuit 22 performs, for example, the read control shown in FIG. 8, and in the case of the region setting shown in FIG. 11, the read control is performed, for example, as shown in FIG. 13. Such a vertical scanning circuit 22 can be configured using, for example, a decoder circuit using a memory or the like to realize the row selection required each time.

As can be seen from the above explanation, in this embodiment, the region setting circuit 23 constitutes a region setting unit that selects the selection transistors ASEL of the pixels PX in multiple desired partial regions of the imaging region 21. Also, in this embodiment, the vertical scanning circuit 22 constitutes a control unit that selects the selection transistors SEL of the pixels PX in each row of the multiple partial regions, while controlling the readout of the pixels PX in the row in which the selection transistor SEL is selected.

When the vertical scanning circuit 22 performs the readout control shown in FIG. 8 in the case of the region setting shown in FIG. 6 or the region setting shown in FIG. 9, or when the vertical scanning circuit 22 performs the readout control shown in FIG. 11 in the case of the region setting shown in FIG. 11, the selection transistors SEL of the pixels PX in one row of at least one of the partial regions (the multiple partial regions set as the readout region) and the selection transistors SEL of the pixels PX in one row different from the one row in at least one other partial region of the multiple partial regions are simultaneously selected, and the vertical scanning circuit 22 performs the readout control on the pixels PX in these rows. Here, any vertical signal line 27 that receives the output signal of the pixel PX in the at least one partial region is different from any vertical signal line 27 that receives the output signal of the pixel PX in the at least one other partial region.

When the vertical scanning circuit 22 performs the read control shown in FIG. 8 in the case of the region setting shown in FIG. 6 or the region setting shown in FIG. 9, the vertical scanning circuit 22 simultaneously selects the selection transistors SEL of the pixels PX in one row of each of the plurality of partial regions (the plurality of partial regions set as the read region) and performs read control on the pixels PX in these rows, and repeats this control sequentially for the pixels in the remaining rows of each of the plurality of partial regions. Here, the number of rows of the pixels PX in the plurality of partial regions is the same. Also, any row of the pixels PX in at least one of the plurality of partial regions is different from any row of the pixels PX in at least one other of the plurality of partial regions. Furthermore, any vertical signal line 27 that receives the output signal of the pixels PX in each of the plurality of partial regions is different from any vertical signal line 27 that receives the output signal of the pixels PX in a partial region other than the partial region among the plurality of partial regions.

Figure 14 is a timing chart showing an example of read control in the full-area shooting mode of the solid-state imaging element 4 in Figure 1, and corresponds to Figures 8 and 13. The full-area shooting mode is an operating mode in which the output signals of the pixels PX in the entire imaging area 21 of the solid-state imaging element 4 are read out.

In the full-area shooting mode, all selection control signals φASEL supplied to the gates of the selection transistors ASEL in all predefined partial areas AR are maintained at a high level (H). This keeps the selection transistors ASEL in the entire imaging area 21 (all predefined partial areas AR) on.

In this embodiment, in the full-area shooting mode, for example, read control is performed as shown in FIG. 14. In the example shown in FIG. 14, the vertical scanning circuit 22 performs sequential read control for each row from the first row of pixels PX in the imaging area 21 to the ninth row of pixels PX in each of the periods T1 to T9, thereby completing the readout of one frame. In the full-area shooting mode when shooting still images, exposure is performed by a mechanical shutter (not shown) after a so-called global reset that resets all pixels PX simultaneously, and then the periods T1 to T9 are performed once. In the full-area shooting mode when shooting moving images, the periods T1 to T9 are repeated sequentially, and multiple frames are read out by a rolling electronic shutter.

In this embodiment, each pixel PX of the solid-state imaging element 4 has a selection transistor ASEL in addition to the selection transistor SEL. Therefore, in the partial area shooting mode, when multiple partial areas are set as the readout area as shown in, for example, FIG. 6, FIG. 9, and FIG. 11, readout control can be performed as shown in FIG. 8 and FIG. 13, and multiple different rows of pixels PX can be read out simultaneously. Therefore, according to this embodiment, the time required to read out one frame of image signals can be shortened, and multiple desired partial areas can be read out at high speed. Specifically, in order to read out one frame of image signals, periods T1 to T9 are required in the full area shooting mode as shown in FIG. 14, whereas in the partial area shooting mode, only periods T1 to T3 are required in the case shown in FIG. 8, and only periods T1 to T6 are required in the case shown in FIG. 13.

In addition, in the imaging device disclosed in Patent Document 1, pixels PX of multiple different rows cannot be read out simultaneously, so when multiple partial areas are set as the readout area in partial area shooting mode, it takes a long time to read out one frame's worth of image signals compared to the present embodiment. For example, in the imaging device disclosed in Patent Document 1, when multiple partial areas are set as the readout area in partial area shooting mode, for example as shown in Figures 6 and 11, it ends up having to perform read control similar to the read control shown in Figure 14 in full area shooting mode, and it takes a long time to read out one frame's worth of image signals.

When the user commands the first partial area shooting mode via the operation unit 14, the electronic camera 1 according to this embodiment performs the operation shown in FIG. 15. FIG. 15 is a schematic flow chart showing an example of the operation of the electronic camera 1 shown in FIG. 1 in the first partial area shooting mode.

When the first partial area shooting mode is commanded by the operation unit 14, the CPU 9 first realizes automatic exposure control (AE) and automatic focus control (AF) (step S1). AE in step S1 is realized, for example, by the CPU 9 calculating the optimal exposure amount based on a photometry signal from an automatic exposure photometry sensor (not shown) provided separately from the solid-state image sensor 4, and controlling the lens control unit 3 so that the aperture of the photographing lens 2 becomes an aperture corresponding to this exposure amount. Also, AF in step S1 is realized, for example, by the CPU 9 calculating the defocus amount based on a signal from a focus detection sensor (not shown) provided separately from the solid-state image sensor 4, and the lens control unit 3 driving the focus of the photographing lens 2 according to this defocus amount to focus the photographing lens 2. Note that the output signal of the pixel PX of the solid-state image sensor 4 may be read out and used as the automatic exposure photometry signal. Also, the solid-state image sensor 4 may be configured to obtain a focus detection signal, and AF may be realized using the signal.

In addition, instead of performing AE and AF in step S1 and step S6 described later, the aperture, focus, etc. may be set in advance by the user in a so-called manual manner.

Next, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 to set all selection control signals φASEL supplied from the area setting circuit 23 to the gates of the selection transistors ASEL of all predefined partial areas AR at a high level, thereby setting the entire imaging area 21 as the readout area (step S2).

In this state, the CPU 9 controls the vertical scanning circuit 22 etc. via the imaging control unit 5 to realize the read control in the full-area shooting mode shown in FIG. 14, obtains image data of the entire area for one frame, and temporarily stores it in the memory 7 (step S3). Note that here, prior to the period T1 in FIG. 14, all pixels PX are simultaneously reset, that is, a so-called global reset, and then exposed to light by a mechanical shutter (not shown).

Next, the CPU 9 displays the image obtained in step S3 on the display unit 10 (step S4), and prompts the user to specify the desired partial area to be photographed. Note that the CPU 9 accepts only permitted area designations when the configuration of the restricted partial area setting is adopted, and accepts area designations without constraints when the configuration of the unrestricted partial area setting is adopted. When the user inputs designation of the desired partial area by the operation unit 14 while looking at the displayed image, and the CPU 9 accepts the designation, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 to selectively set the selection control signal φASEL supplied to the gate of the selection transistor ASEL of the predefined partial area AR corresponding to the designated one or more partial areas to a high level, and selectively sets one or more predefined partial areas AR as the readout area (step S5). In this embodiment, a user interface for commanding one or more desired partial areas of the imaging area 21 is constructed by the functions of the CPU 9, the display unit 10, and the operation unit 14.

Then, the CPU 9 performs AE and AF in the same manner as in step S1 (step S6). However, unlike step S1, step S6 is performed so that exposure and focusing are optimized for the partial area set in step S5.

Next, the CPU 9 controls the vertical scanning circuit 22 and the like via the imaging control unit 5 to realize the read control in the partial area shooting mode described above, obtains one frame of image data of the partial area and temporarily stores it in the memory 7, and causes the recording unit 11 to record this image as a moving image of the partial area on the recording medium 11a (step S7). Note that step S7 is repeated by the operation shown in FIG. 15 to realize a rolling electronic shutter.

Then, the CPU 9 determines whether or not a command to end partial area video shooting has been received from the operation unit 14 (step S8), and if no such command has been received, the process returns to step S7, whereas if such a command has been received, the series of operations in the first partial area shooting mode ends.

In this first partial area capture mode, a moving image of one or more desired partial areas arbitrarily set by the user can be obtained. As described above, according to this embodiment, the time required to read out one frame of image signals of the desired partial areas can be shortened, and the desired partial areas can be read out at high speed, so that a moving image of the desired partial areas arbitrarily set by the user can be obtained at a high frame rate.

Therefore, in this first partial area shooting mode, the user can specify multiple desired partial areas each including multiple arbitrary targets of interest, thereby obtaining a moving image that captures in detail the process of changes in the multiple targets of interest in the field of view (e.g., changes in shape, size, orientation, color, etc.), and the moving image allows the user to observe the changes in the multiple targets of interest in the field of view without missing anything. For example, if the electronic camera 1 according to this embodiment is an imaging device incorporated in a microscope and captures microscopic images, when the field of view is a petri dish in which cells are cultured, it is possible to obtain a moving image that captures in detail the process of changes in multiple cells (e.g., the state of cell division, the state of pulsation of cardiac muscle cells, etc.).

When the user commands the second partial area shooting mode via the operation unit 14, the electronic camera 1 according to this embodiment performs the operation shown in FIG. 16. FIG. 16 is a schematic flow chart showing an example of the operation of the electronic camera 1 shown in FIG. 1 in the second partial area shooting mode. The first partial area shooting mode is a mode in which the partial area is fixed to an area specified by the user, whereas the second partial area shooting mode is a mode in which the captured partial area automatically follows the movement of the target object.

When the second partial area shooting mode is commanded by the operation unit 14, the CPU 9 performs steps S11 to S13, which are the same as steps S1 to S3 in FIG. 15, respectively.

Next, the CPU 9 performs image recognition processing using a known image recognition method on the image stored in the memory 7 in step S13, recognizes the desired object of interest (e.g., a human body, a human face, a moving object, a cell, etc.), and detects the position, size, etc. on the image (step S14).

Next, the CPU 9 determines whether or not the target object has been recognized in step S14 (step S15), and if the target object has been recognized, the process proceeds to step S16, whereas if the target object has not been recognized, the process proceeds to step S27. In step S27, the CPU 9 determines whether or not a command to end partial area video recording has been received from the operation unit 14, and if no such command has been received, the process returns to step S11, whereas if the command has been received, the series of operations in the second partial area recording mode ends.

In step S16, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 to selectively set one or more predefined partial areas AR as readout areas according to the recognition result of step S14. Specifically, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 to selectively set the selection control signal φASEL supplied to the gate of the selection transistor ASEL of the predefined partial area AR corresponding to one or more partial areas including each target object recognized in step S14 and a certain extent of its surroundings to a high level.

Then, the CPU 9 performs AE and AF in the same manner as in step S11 (step S17). However, unlike step S11, step S17 is performed so that exposure and focusing are optimized for the partial area set in step S16.

Then, the CPU 9 resets the count value q to zero (step S18). This count value q indicates the number of frames captured after the partial area was set to the latest.

Next, the CPU 9 controls the vertical scanning circuit 22 etc. via the imaging control unit 5 to realize the read control in the partial area shooting mode described above, obtains one frame of image data of the partial area and temporarily stores it in the memory 7, and causes the recording unit 11 to record this image as a moving image of the currently set partial area on the recording medium 11a (step S19). Note that a rolling electronic shutter is realized by repeating step S19 by the operation shown in FIG. 16.

Next, the CPU 9 increments the count value q by 1 (step S20), and then determines whether or not a command to end partial area video shooting has been received from the operation unit 14 (step S21). If no such command has been received, the process proceeds to step S22. If such a command has been received, the process ends the series of operations in the second partial area shooting mode.

In step S22, the CPU 9 determines whether the current count value q is equal to or greater than the value Q. If q is not equal to or greater than Q, the process returns to step S19. If q is equal to or greater than Q, the process proceeds to step S23. The value Q is a value of 1 or greater that is arbitrarily set by the user via the operation unit 14 before the start of the second partial area shooting mode. The value Q is a value that determines the timing of resetting the partial area. As will be understood from the following explanation, when the number of frames shot in a partial area once set reaches the value Q, the partial area is reset. If the moving speed of the target of interest is high, the value Q is set to a relatively small value to improve tracking of the target of interest, and if the moving speed of the target of interest is low, the value Q is set to a relatively large value to reduce the time for steps S23, S26, etc., and to increase the overall frame rate.

In step S23, image recognition processing is performed using a known image recognition method on the image of each partial area of the frame most recently stored in memory 7 in step S19 to recognize the desired target object and detect its position, size, etc. on the image.

The CPU 9 then determines whether or not the target object has been recognized in step S23 (step S24), and if the target object has been recognized, the process proceeds to step S25, whereas if the target object has not been recognized, the process proceeds to step S27.

In step S25, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 to selectively set one or more predefined partial areas AR as readout areas according to the recognition result in step S23.

Then, the CPU 9 performs AE and AF in the same manner as in step S17 (step S26), and then returns to step S18. However, in step S26, unlike step S17, exposure and focusing are optimized for the partial area most recently set in step S25.

In this second partial area shooting mode, moving images of the multiple partial areas set by automatically following the movement of the target object can be obtained. According to this embodiment, the time required to read out one frame of image signals of the multiple desired partial areas can be shortened as described above, and the multiple desired partial areas can be read out at high speed, so that moving images of the partial areas set by automatically following the movement of the target object can be obtained at a high frame rate, and since the time required for AF, etc. can be secured even if the movement speed of the target object is high, a moving image in a focused state can be obtained, improving tracking ability.

Therefore, this second partial area shooting mode is effective, for example, when used as a surveillance camera with a person's whole body or face as the target of attention. If the process of changes in the whole body or face of multiple people can be captured in detail, the process of changes in posture, facial expression, and lip movement of multiple people can be known in detail, and advanced information can be obtained from the target of surveillance. For example, it is possible to get a detailed view of a fight between multiple people, or to use lip reading to know the content of a conversation between multiple people.

The second partial area shooting mode is also effective, for example, when the electronic camera 1 according to this embodiment is incorporated in a microscope and is an imaging device that captures a microscopic image. When observing cells, microorganisms, etc. as an object of interest, even if the moving speed is extremely slow, if the object of interest can move, in the first partial area shooting mode, after a long period of time, the object of interest may move away from the partial area set by the user. In contrast, the second partial area shooting mode can obtain moving images of multiple partial areas that are set by automatically following the movement of the object of interest, so that even such an object of interest can be captured at a high frame rate for a long period of time.

When the user commands still image shooting mode via the operation unit 14, the electronic camera 1 according to this embodiment performs the same still image shooting operation as a normal electronic camera, and when the user commands full-area shooting mode for video shooting via the operation unit 14, the corresponding operation is performed, but a description of this will be omitted here.

[Second embodiment]

Figure 17 is a circuit diagram showing the schematic configuration of a solid-state imaging element 41 used in an electronic camera according to a second embodiment of the present invention, and corresponds to Figure 2. Figure 18 is a circuit diagram showing a default partial area AR that forms part of the imaging area 21 of the solid-state imaging element 41 shown in Figure 17, and corresponds to Figure 4. Figure 19 is a circuit diagram showing an abstraction of the circuit shown in Figure 18, and corresponds to Figure 5. Figure 20 is a diagram showing a power supply voltage signal φVDD that realizes the same settings as the setting example shown in Figure 6 in the solid-state imaging element 41 shown in Figure 17, and corresponds to Figure 7.

In Figures 17 to 19, elements that are the same as or correspond to elements in Figures 2, 4, and 5 are given the same reference numerals, and duplicated explanations are omitted. The present embodiment differs from the first embodiment in the points described below.

In this embodiment, a solid-state image sensor 41 is used instead of the solid-state image sensor 4 in the electronic camera 1 according to the first embodiment.

In the first embodiment, a selection transistor ASEL is provided in each pixel PX of the imaging region 21, whereas in the present embodiment, the selection transistor ASEL and control line 33 are removed in each pixel PX of the imaging region 21, and the source of the selection transistor SEL is connected to the vertical signal line 27 corresponding to the pixel PX.

In the first embodiment, the drains of the amplifier transistors AMP of all pixels PX (point b in FIG. 4) are commonly connected by a power supply line 34, and a fixed effective voltage level VDD that is effective for the operation of the amplifier transistor AMP is supplied to the drain as the power supply voltage of the amplifier transistor AMP. In contrast, in the present embodiment, the power supply line 34 is electrically separated for each predefined partial area AR, and the drains of the amplifier transistors AMP of each pixel PX (point b in FIG. 18) are commonly connected to the drains by the power supply line 34 for each predefined partial area AR, and a power supply voltage signal φVDD is supplied to the drains from the area setting circuit 23 as the power supply voltage of the amplifier transistor AMP. The drains of the reset transistors RST of each pixel PX are connected to the drains of the amplifier transistors AMP of the pixel PX (point b in FIG. 18) by the power supply line 34.

Figure 19 shows an abstracted view of the circuit shown in Figure 18, focusing on the connection relationship of the drain (point b) of the amplification transistor AMP of each predefined partial area AR by the power supply line 34. When each power supply voltage signal φVDD is distinguished for each predefined partial area AR, the power supply voltage signal φVDD supplied to the drain of the amplification transistor AMP of the pixel PX in the jth row and kth column predefined partial area AR (j, k) is indicated by the symbol φVDD (j, k). Note that the actual arrangement (path for routing, etc.) of the power supply line 34 is not limited in any way.

In this embodiment, the area setting circuit 23 is configured as a power supply control circuit that outputs each power supply voltage signal φVDD instead of each control signal φASEL under the control of the imaging control unit 5. Each power supply voltage signal φVDD is an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or an ineffective voltage level (here, 0V, but not necessarily limited to 0V) that is not effective for the operation of the amplification transistor AMP, and the area setting circuit 23 selectively supplies VDD or 0V as the power supply voltage of the amplification transistor AMP of each pixel PX.

In this embodiment, the state in which the power supply voltage signal φVDD is VDD in each pixel PX and the amplification transistor AMP operates effectively, and the state in which the power supply voltage signal φVDD is 0 V and the amplification transistor AMP does not operate effectively are substantially the same as the state in which the control signal φASEL is at a high level in each pixel PX and the selection transistor ASEL is turned on, and the state in which the control signal φASEL is at a low level in each pixel PX and the selection transistor ASEL is turned off, in terms of whether or not the output signal of each pixel PX is output to the vertical signal line 27, in the first embodiment.

Therefore, in this embodiment, the output signal of each pixel PX is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction relative to the pixel PX only when the selection transistor SEL of the pixel PX is in the selected state (on state) and the power supply voltage signal φVDD supplied as the power supply voltage of the amplification transistor AMP of the pixel PX is at the effective voltage level VDD.

In this embodiment, the region setting circuit 23 supplies the effective voltage level VDD as each power supply voltage signal φVDD instead of supplying a high level signal as each φASEL in the first embodiment, and supplies 0 V as each power supply voltage signal φVDD instead of supplying a low level signal as each φASEL in the first embodiment, thereby realizing an operation similar to that of the first embodiment. For example, in this embodiment, to realize the same setting as the region setting example shown in FIG. 6, the region setting circuit 23 may output each power supply voltage signal φVDD as shown in FIG. 20.

This embodiment also provides the same advantages as the first embodiment. In addition, in this embodiment, since the selection transistor ASEL is not provided in each pixel PX, the configuration of each pixel PX is simplified.

[Third embodiment]

Figure 21 is a circuit diagram showing the schematic configuration of a solid-state imaging element 51 used in an electronic camera according to a third embodiment of the present invention, and corresponds to Figure 2. Figure 22 is a circuit diagram showing a default partial area AR that forms part of the imaging area 21 of the solid-state imaging element 51 shown in Figure 21, and corresponds to Figure 4. Figure 23 is a timing chart showing an example of read control in partial area shooting mode of the solid-state imaging element 51 shown in Figure 21, and corresponds to Figure 8.

21 to 23, elements that are the same as or correspond to elements in FIGS. 2, 4, and 8 are given the same reference numerals, and redundant explanations are omitted. This embodiment differs from the first embodiment in the points described below.

In this embodiment, a solid-state image sensor 51 is used instead of the solid-state image sensor 4 in the electronic camera 1 according to the first embodiment.

In the first embodiment, a selection transistor SEL is provided in each pixel PX of the imaging region 21, whereas in the present embodiment, the selection transistor SEL and the connection line 26 are removed from each pixel PX of the imaging region 21, and the drain of the selection transistor ASEL is connected to the source of the amplification transistor AMP of that pixel PX.

In the first embodiment, the drains of the amplifier transistors AMP of all pixels PX (point b in FIG. 4) are commonly connected by a power supply line 34, and an effective voltage level VDD that is effective for the operation of the amplifier transistors AMP is fixedly supplied thereto as a power supply voltage of the amplifier transistors AMP. In contrast, in the present embodiment, the power supply line 34 is electrically separated for each row of pixels PX, and the drains of the amplifier transistors AMP of each pixel PX (point b in FIG. 22) are commonly connected by a power supply line 34 for each row of pixels PX, and a power supply voltage signal φVDD is supplied thereto from the power supply control circuit 52 as a power supply voltage of the amplifier transistor AMP. When each power supply voltage signal φVDD is distinguished for each row of pixels PX, the power supply voltage signal φVDD supplied to the drain of the amplifier transistor AMP of the nth row of pixels PX is indicated by the symbol φVDD(n). The drain of the reset transistor RST of each pixel PX is connected to the drain of the amplification transistor AMP of that pixel PX (point b in Figure 22) by a power supply line 34.

In this embodiment, the power supply control circuit 52 is provided as part of the vertical scanning circuit 22, and outputs each power supply voltage signal φVDD instead of each control signal φSEL under the control of the imaging control unit 5. Each power supply voltage signal φVDD is at an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or at an ineffective voltage level (here, 0V, but not necessarily limited to 0V) that is not effective for the operation of the amplification transistor AMP, and the power supply control circuit 52 selectively supplies VDD or 0V as the power supply voltage for the amplification transistor AMP of each pixel PX.

In this embodiment, the state in which the power supply voltage signal φVDD is VDD in each pixel PX and the amplification transistor AMP is operating effectively, and the state in which the power supply voltage signal φVDD is 0 V and the amplification transistor AMP is not operating effectively are substantially the same as the state in which the control signal φSEL is at a high level in each pixel PX and the selection transistor SEL is turned on, and the state in which the control signal φSEL is at a low level in each pixel PX and the selection transistor SEL is turned off, in terms of whether or not the output signal of each pixel PX is output to the vertical signal line 27, in the first embodiment.

Therefore, in this embodiment, the output signal of each pixel PX is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction relative to the pixel PX only when the selection transistor ASEL of the pixel PX is in the selected state (on state) and the power supply voltage signal φVDD supplied as the power supply voltage of the amplification transistor AMP of the pixel PX is at the effective voltage level VDD.

In this embodiment, the power supply control circuit 52 supplies an effective voltage level VDD as each power supply voltage signal φVDD instead of supplying a high-level signal as each φSEL in the first embodiment, and supplies 0 V as each power supply voltage signal φVDD instead of supplying a low-level signal as each φSEL in the first embodiment, thereby achieving the same operation as in the first embodiment. For example, in this embodiment, in the partial area shooting mode, when the partial area to be read out is set as shown in FIG. 6, the vertical scanning circuit 22 may perform readout control as shown in FIG. 23.

This embodiment also provides the same advantages as the first embodiment. In addition, in this embodiment, since a selection transistor SEL is not provided in each pixel PX, the configuration of each pixel PX is simplified.

[Fourth embodiment]

Figure 24 is a circuit diagram showing the schematic configuration of a solid-state imaging element 61 used in an electronic camera according to a fourth embodiment of the present invention, and corresponds to Figure 2. Figure 25 is a circuit diagram showing a default partial area AR that forms part of the imaging area 21 of the solid-state imaging element 61 shown in Figure 24, and corresponds to Figure 4. Figure 26 is a circuit diagram showing an abstraction of the circuit shown in Figure 25, and corresponds to Figure 5. Figure 27 is a timing chart showing an example of read control in partial area shooting mode of the solid-state imaging element 61 shown in Figure 24, and corresponds to Figure 8. In Figures 24 to 27, elements that are the same as or correspond to elements in Figures 2, 4, 5, and 8 are given the same reference numerals, and duplicate explanations are omitted.

In this embodiment, a solid-state image sensor 61 is used instead of the solid-state image sensor 4 in the electronic camera 1 according to the first embodiment.

This embodiment differs from the first embodiment in that for every two adjacent pixels PX in the column direction, the two pixels PX share a set of floating capacitance section FD, amplification transistor AMP, reset transistor RST, and selection transistors SEL, ASEL, and that the vertical scanning circuit 22 is configured to output control signals φSEL, φRST, φTXA, φTXB as shown in FIG. 27 instead of the control signals φSEL, φRST, φTX as shown in FIG. 8.

In Figures 24 to 26, two pixels PX that share one set of floating capacitance unit FD, amplification transistor AMP, reset transistor RST, and selection transistors SEL and ASEL are shown as a pixel block BL. In addition, in Figures 24 and 25, the photodiode PD and transfer transistor TX of the lower pixel PX in the pixel block BL are indicated by the symbols PDA and TXA, respectively, and the photodiode PD and transfer transistor TX of the upper pixel PX in the pixel block BL are indicated by the symbols PDB and TXB, respectively, to distinguish between the two. In addition, the control signal supplied to the gate of the transfer transistor TXA is indicated as φTXA, and the control signal supplied to the gate electrode of the transfer transistor TXB is indicated as φTXB, to distinguish between the two.

In Fig. 2 and Fig. 4, N, n, etc. indicate pixel rows, but in Fig. 24 and Fig. 25, N, n, etc. indicate pixel block BL rows. One row of pixel block BL corresponds to two rows of pixels PX. In Fig. 4 and Fig. 5, each predefined partial area AR is composed of A x B pixels PX in A rows and B columns, but in Fig. 25 and Fig. 26, each predefined partial area AR is composed of A x B pixel blocks BL (2 x A x B pixels PX) in A rows and B columns. Note that the number of rows of photodiodes PD constituting each predefined partial area AR may be 2 or more and the number of columns of photodiodes PD may be 1 or more. In this embodiment, one pixel block BL has two photodiodes PD, so the number of rows of pixel blocks BL constituting each predefined partial area AR may be 1 or more and the number of columns of pixel blocks BL may be 1 or more.

In this embodiment, in the partial area shooting mode, when the partial area to be read out is set as shown in FIG. 6 or FIG. 9, for example, the read control shown in FIG. 27 is performed instead of the read control shown in FIG. 8. Note that here, n in FIG. 6 and FIG. 9 indicates the row of the pixel block BL, and m in FIG. 6 and FIG. 9 indicates the column of the pixel block BL.

In the example shown in FIG. 27, during period T1, the vertical scanning circuit 22 simultaneously controls the readout of the first, fourth, and seventh pixel blocks BL in the imaging area 21, which correspond to the first pixel block BL in each predefined partial area AR. During the next period T2, the vertical scanning circuit 22 simultaneously controls the readout of the second, fifth, and eighth pixel blocks BL in the imaging area 21, which correspond to the second pixel block BL in each predefined partial area AR. During the next period T3, the vertical scanning circuit 22 simultaneously controls the readout of the third, sixth, and ninth pixel blocks BL in the imaging area 21, which correspond to the third pixel block BL in each predefined partial area AR. This completes the readout of one frame. By sequentially repeating periods T1 to T3, multiple frames are read out by the rolling electronic shutter.

In this embodiment, in the partial area shooting mode, if it is also permitted that the partial area to be read out is set as shown in FIG. 11, the vertical scanning circuit 22 may perform, instead of the read control shown in FIG. 27, for example, a read control obtained by modifying the read control shown in FIG. 13 in the same manner as the read control shown in FIG. 8 is modified to the read control shown in FIG. 27. Note that here, n in FIG. 11 indicates the row of the pixel block BL, and m in FIG. 11 indicates the column of the pixel block BL.

In this example, the vertical scanning circuit 22 performs read control in accordance with the setting of the partial area shown in FIG. 11 to be read out, so that read control is performed simultaneously for as many rows of pixel blocks BL as possible, with the necessary condition that the output signals of two or more pixels PX are not simultaneously read out to the same vertical signal line 27.

In this embodiment, the area setting circuit 23 may be configured to arbitrarily set the area to be read out under the constraint that, when setting the partial area to be read out in the partial area shooting mode, two or more predefined partial areas AR are not set as the area to be read out at the same time in any column of the predefined partial areas AR, and the vertical scanning circuit 22 may be configured to always perform the read control shown in FIG. 27 in the partial area shooting mode. In the following description, this configuration will be referred to as a "configuration for partial area setting with constraints." In this case, area settings such as those shown in FIG. 6 and FIG. 9 are permitted, but area settings such as those shown in FIG. 11 are not permitted.

Alternatively, in this embodiment, the region setting circuit 23 may be configured to arbitrarily set the region to be read out without any constraints when setting the partial region to be read out in the partial region shooting mode, and the vertical scanning circuit 22 may be configured to perform read control such that read control is performed simultaneously for as many rows of pixel blocks BL as possible, with the necessary condition that the output signals of two or more pixels PX are not simultaneously read out to the same vertical signal line 27 in accordance with the setting of the partial region in the partial region shooting mode. In the following description, such a configuration is called a "configuration of partial region setting without constraints". In this case, not only the region setting shown in FIG. 6 and the region setting shown in FIG. 9, but also the region setting shown in FIG. 11 is allowed. In the case of the region setting shown in FIG. 6 or the region setting shown in FIG. 9, the vertical scanning circuit 22 performs, for example, the read control shown in FIG. 27, and in the case of the region setting shown in FIG. 11, for example, the read control shown in FIG. 13 is modified in the same manner as the read control shown in FIG. 8 is modified to the read control shown in FIG. 27.

In this embodiment, in the full-area shooting mode, for example, the read control shown in FIG. 14 is modified in the same way as the read control shown in FIG. 8 is modified to the read control shown in FIG. 27. In this example, the vertical scanning circuit 22 sequentially controls the read control for each row from the first pixel block BL to the ninth pixel block BL in the imaging area 21, thereby completing the readout of one frame. In the full-area shooting mode when shooting still images, exposure is performed by a mechanical shutter (not shown) after a so-called global reset that simultaneously resets all pixels PX, and then the pixel blocks BL of each row from the first row to the ninth row are read out. In the full-area shooting mode when shooting moving images, the readout of the pixel blocks BL of each row from the first row to the ninth row is repeated sequentially, and multiple frames are read out by a rolling electronic shutter.

This embodiment also provides the same advantages as the first embodiment. In this embodiment, for every two adjacent pixels PX in the column direction, the two pixels PX share a set of floating capacitance unit FD, amplification transistor AMP, reset transistor RST, and selection transistors SEL and ASEL. However, in the present invention, for example, for every predetermined number of pixels PX, three or more adjacent in the column direction, the predetermined number of pixels PX may share a set of floating capacitance unit FD, amplification transistor AMP, reset transistor RST, and selection transistors SEL and ASEL. In addition, in the present invention, a modification similar to that of the first embodiment modified to this embodiment may be applied to the second and third embodiments.

[Fifth embodiment]

Figure 28 is a circuit diagram showing the schematic configuration of a solid-state imaging element 71 used in an electronic camera according to a fifth embodiment of the present invention, and corresponds to Figure 2. Figure 29 is a circuit diagram showing a part of the imaging region 21 of the solid-state imaging element 71 shown in Figure 28, and corresponds to Figure 4.

In Figures 28 and 29, elements that are the same as or correspond to elements in Figures 2 and 4 are given the same reference numerals, and duplicated explanations are omitted. The present embodiment differs from the first embodiment in the points described below.

In this embodiment, a solid-state image sensor 71 is used instead of the solid-state image sensor 4 in the electronic camera 1 according to the first embodiment.

In this embodiment, the imaging area 21 is not divided into each of the predetermined partial areas AR. Also, in this embodiment, a row write control circuit 72 and a column write control circuit 73 are provided instead of the area setting circuit 23.

Furthermore, in this embodiment, a capacitor HC and a write transistor WT are added to each pixel PX. The capacitor HC of each pixel PX is connected between ground and the gate of the selection transistor ASEL of the pixel PX, and constitutes a holding unit that holds a selection control signal for setting the selection transistor ASEL of the pixel PX to a selected or unselected state. The write transistor WT of each pixel PX constitutes a writing unit that writes the selection control signal to the capacitor HC, which serves as the holding unit of the pixel PX, in response to write control signals φWTR and φWTC.

In this embodiment, the write transistor WT is an nMOS transistor. The source of the write transistor WT of each pixel PX is connected to the gate of the selection transistor ASEL of the pixel PX. The gates of the write transistor WT of each pixel PX are commonly connected to each row of the pixels PX by a control line 74, and a first write control signal φWTR is supplied from the row write control circuit 72 to the gates. The drains of the write transistor WT of each pixel PX are commonly connected to each column of the pixels PX, and a second write control signal φWTC is supplied from the column write control circuit 73 to the drains. The write transistor WT of each pixel PX constitutes an AND circuit that ANDs the first write control signal φWTR supplied to its gate and the second write control signal φWTC supplied to its drain and outputs the AND output to its source. Instead of the write transistor WT, for example, another AND circuit may be used as the write unit.

When each first write control signal φWTR is distinguished by row of pixels PX, the first write control signal φWTR supplied to the gate of the write transistor WT of the pixel PX in the nth row is indicated by the symbol φWTR(n). When each second write control signal φWTC is distinguished by column of pixels PX, the second write control signal φWTC supplied to the drain of the write transistor WT of the pixel PX in the mth column is indicated by the symbol φWTC(m).

Figure 30 (a) is a diagram showing the write control signals φWTR(n) and φWTC(m) when a high level signal (H signal) is written to the capacitor HC of the pixel PX in the nth row and mth column in the solid-state imaging device 71 shown in Figure 28. At time t21, the write control signal φWTR(n) for the nth row is raised to a high level, and at the following time t22, the write control signal φWTC(m) for the mth column is raised to a high level, and at the following time t23, the write control signal φWTR(n) is lowered to a low level, and at the following time t24, the write control signal φWTC is lowered. As a result, a high level signal is written and held in the capacitor HC of the pixel PX in the nth row and mth column. As a result, the selection transistor ASEL of the pixel PX in the nth row and mth column is held in the on state (selected state).

Figure 30 (b) is a diagram showing the write control signals φWTR(n) and φWTC(m) when a low level signal (L signal) is written to the capacitor HC of the pixel PX in the nth row and mth column in the solid-state imaging device 71 shown in Figure 28. While the write control signal φWTC(m) for the mth column is maintained at a low level, the write control signal φWTR(n) for the nth row is raised to a high level at time t21, and then the write control signal φWTR(n) is lowered to a low level at time t23. As a result, a low level signal is written and held in the capacitor HC of the pixel PX in the nth row and mth column. As a result, the selection transistor ASEL of the pixel PX in the nth row and mth column is held in an off state (unselected state).

The row write control circuit 72 supplies a first write control signal φWTR to each row of pixels PX under the control of the imaging control unit 5 in FIG. 1. The column write control circuit 73 supplies a second write control signal φWTC to each column of pixels PX under the control of the imaging control unit 5 in FIG. 1. The row write control circuit 72 and the column write control circuit 73 as a whole constitute a write control unit that supplies write control signals φWTR, φWTC to the write transistor WT as the write unit of each pixel PX.

In this embodiment, the row write control circuit 72, the column write control circuit 73, and the write transistor WT and capacitor HC of each pixel PX as a whole constitute an area setting unit that selects (turns on) the selection transistor ASEL of the pixel PX in one or more desired partial areas to be read out of the imaging area 21.

Figure 31 is a timing chart showing write control signals φWTR and φWTC that realize the same setting as the area setting example shown in Figure 6 in the solid-state imaging element 71 shown in Figure 28. Here, although it is not divided into each predefined partial area AR in Figure 6, the four hatched partial areas are the four partial areas to be read out.

In the example shown in Figure 31, first, a low-level signal is written to the capacitors HC of all pixels PX, and then pixels PX are selected row by row, and a high-level signal is written to the capacitors HC of the necessary pixels PX in that row, thereby setting the four partial areas hatched in Figure 6 as the areas to be read out.

Specifically, when the area setting period (the period for setting the area to be read out) starts, first, during period t31-t32, φWTR(1) to φWTR(9) are set to high level, while φWTC(1) to φWTC(12) are set to low level. As a result, as can be seen from Figure 30(b), a low level signal is written to the capacitors HC of all pixels PX.

Next, φWTR(1) is set to high level during period t33-t35, and φWTC(4)-φWTC(6) and φWTC(10)-φWTC(12) are set to high level during period t34-t36. As a result, as can be seen from FIG. 30(a), a high level signal is written to the capacitors HC of the pixels PX in columns 4-6 and 10-12 of the pixels PX in row 1.

Next, φWTR(2) is set to high level during the period t36-t38, and φWTC(4)-φWTC(6) and φWTC(10)-φWTC(12) are set to high level during the period t37-t39. This causes a high level signal to be written to the capacitors HC of the pixels PX in the 4th to 6th columns and the 10th to 12th columns of the pixels PX in the 2nd row.

Continuing, φWTR(3) is set to high level during period t39-t41, and φWTC(4)-φWTC(6) and φWTC(10)-φWTC(12) are set to high level during period t40-t42. This causes a high level signal to be written to the capacitors HC of the pixels PX in columns 4-6 and 10-12 of the pixels PX in row 3.

After that, φWTR(4) is set to high level during the period t42-t44, and φWTC(7) to φWTC(9) are set to high level during the period t43-t45. This causes a high level signal to be written to the capacitors HC of the pixels PX in the 7th to 9th columns of the pixels PX in the 4th row.

Next, φWTR(5) is set to high level during the period t45-t47, and φWTC(7) to φWTC(9) are set to high level during the period t46-t48. This causes a high level signal to be written to the capacitors HC of the pixels PX in the 7th to 9th columns of the pixels PX in the 5th row.

Next, φWTR(6) is set to high level during the period t48-t50, and φWTC(7) to φWTC(9) are set to high level during the period t49-t51. This causes a high level signal to be written to the capacitors HC of the pixels PX in the 7th to 9th columns of the pixels PX in the 6th row.

Continuing, φWTR(7) is set to high level during the period t51-t53, and φWTC(1) to φWTC(3) are set to high level during the period t52-t54. This causes a high level signal to be written to the capacitors HC of the pixels PX in the first to third columns of the pixels PX in the seventh row.

After that, φWTR(8) is set to high level during the period t54-t56, and φWTC(1) to φWTC(3) are set to high level during the period t55-t57. This causes a high level signal to be written to the capacitors HC of the pixels PX in the 1st to 3rd columns of the pixels PX in the 8th row.

Finally, φWTR(9) is set to high level during the period t57-t59, and φWTC(1) to φWTC(3) are set to high level during the period t58-t60. This causes a high level signal to be written to the capacitors HC of the pixels PX in the 1st to 3rd columns of the pixels PX in the 9th row.

In this way, a high-level signal is written to the capacitor HC of the pixel PX that is hatched in FIG. 6, the selection transistor ASEL of that pixel PX is maintained in the on state, and a low-level signal is written to the capacitor HC of the pixel PX that is not hatched in FIG. 6, the selection transistor ASEL of that pixel PX is maintained in the off state, and the area setting shown in FIG. 6 is realized.

In this embodiment, for example, as in FIG. 31, a low-level signal is first written to the capacitors HC of all pixels PX, and then pixels PX are sequentially selected row by row, and a high-level signal is written to the capacitors HC of desired pixels PX in the row, thereby setting any desired partial area or areas of the imaging area 21, or the entire imaging area 21, as the area to be read out.

If, after a region setting period has been performed, the next region setting period is not performed for a long period of time without changing the region setting, the high-level signal written to the capacitor HC may drop and may not be properly retained. Therefore, even if the region setting is not changed, it is preferable to perform a region setting period within a certain period of time after the region setting period has been performed to refresh the signal written to the capacitor HC.

The read control in this embodiment is the same as that in the first embodiment. Also, in this embodiment, a configuration similar to the configuration of the constrained partial region setting in the first embodiment may be adopted, or a configuration similar to the configuration of the unconstrained partial region setting in the first embodiment may be adopted.

This embodiment also provides the same advantages as the first embodiment. In the first embodiment, the readout area of the imaging area 21 is set depending on whether or not each predefined partial area AR is included in the readout area, whereas in this embodiment, the readout area of the imaging area 21 is set depending on whether or not each pixel PX is included in the readout area. Therefore, although the write transistor WT and capacitor HC are required in each pixel PX, this embodiment provides greater freedom in setting the readout area of the imaging area 21 compared to the first embodiment.

[Sixth embodiment]

Figure 32 is a circuit diagram showing the schematic configuration of a solid-state imaging element 81 used in an electronic camera according to a sixth embodiment of the present invention, and corresponds to Figure 28. Figure 33 is a circuit diagram showing a part of the imaging region 21 of the solid-state imaging element 81 shown in Figure 32, and corresponds to Figure 29.

In Figures 32 and 33, elements that are the same as or correspond to elements in Figures 28 and 29 are given the same reference numerals, and duplicated explanations are omitted. This embodiment differs from the fifth embodiment in the points described below.

In this embodiment, a solid-state image sensor 81 is used instead of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

In the fifth embodiment, a selection transistor SEL is provided in each pixel PX of the imaging region 21, whereas in the present embodiment, the selection transistor SEL and the connection line 26 are removed from each pixel PX of the imaging region 21, and the drain of the selection transistor ASEL is connected to the source of the amplification transistor AMP of that pixel PX.

In the fifth embodiment, the drains of the amplifier transistors AMP of all pixels PX (point b in FIG. 29) are commonly connected by a power supply line 34, and an effective voltage level VDD that is effective for the operation of the amplifier transistor AMP is fixedly supplied thereto as a power supply voltage of the amplifier transistor AMP. In contrast, in this embodiment, the power supply line 34 is electrically separated for each row of pixels PX, and the drains of the amplifier transistors AMP of each pixel PX (point b in FIG. 33) are commonly connected by a power supply line 34 for each row of pixels PX, and a power supply voltage signal φVDD is supplied thereto from the power supply control circuit 52 as a power supply voltage of the amplifier transistor AMP. When each power supply voltage signal φVDD is distinguished for each row of pixels PX, the power supply voltage signal φVDD supplied to the drain of the amplifier transistor AMP of the nth row of pixels PX is indicated by the symbol φVDD(n). The drain of the reset transistor RST of each pixel PX is connected to the drain of the amplification transistor AMP of that pixel PX (point b in Figure 33) by a power supply line 34.

In this embodiment, the power supply control circuit 52 is provided as part of the vertical scanning circuit 22, and outputs each power supply voltage signal φVDD instead of each control signal φSEL under the control of the imaging control unit 5. Each power supply voltage signal φVDD is at an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or at an ineffective voltage level (here, 0V, but not necessarily limited to 0V) that is not effective for the operation of the amplification transistor AMP, and the power supply control circuit 52 selectively supplies VDD or 0V as the power supply voltage for the amplification transistor AMP of each pixel PX.

In this embodiment, the state in which the power supply voltage signal φVDD is VDD in each pixel PX and the amplification transistor AMP is operating effectively, and the state in which the power supply voltage signal φVDD is 0 V and the amplification transistor AMP is not operating effectively are substantially the same as the state in which the control signal φSEL is at a high level in each pixel PX and the selection transistor SEL is turned on, and the state in which the control signal φSEL is at a low level in each pixel PX and the selection transistor SEL is turned off, in terms of whether or not the output signal of each pixel PX is output to the vertical signal line 27, in the fifth embodiment.

Therefore, in this embodiment, the output signal of each pixel PX is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction relative to the pixel PX only when the selection transistor ASEL of the pixel PX is in the selected state (on state) and the power supply voltage signal φVDD supplied as the power supply voltage of the amplification transistor AMP of the pixel PX is at the effective voltage level VDD.

In this embodiment, the power supply control circuit 52 supplies an effective voltage level VDD as each power supply voltage signal φVDD instead of supplying a high-level signal as each φSEL in the fifth embodiment, and supplies 0 V as each power supply voltage signal φVDD instead of supplying a low-level signal as each φSEL in the fifth embodiment, thereby achieving the same operation as the fifth embodiment.

This embodiment also provides the same advantages as the fifth embodiment. In addition, in this embodiment, since the selection transistor ASEL is not provided in each pixel PX, the configuration of each pixel PX is simplified.

[Seventh embodiment]

Figure 34 is a circuit diagram showing the schematic configuration of a solid-state imaging element 91 used in an electronic camera according to a seventh embodiment of the present invention, and corresponds to Figure 28. Figure 35 is a circuit diagram showing a part of the imaging region 21 of the solid-state imaging element 91 shown in Figure 34, and corresponds to Figure 29. In Figures 34 and 35, elements that are the same as or correspond to elements in Figures 28 and 29 are given the same reference numerals, and duplicate explanations will be omitted.

In this embodiment, a solid-state image sensor 91 is used instead of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

This embodiment differs from the fifth embodiment in that for every two adjacent pixels PX in the column direction, the two pixels PX share a set of floating capacitance unit FD, amplification transistor AMP, reset transistor RST, selection transistors SEL, ASEL, write transistor WT, and capacitor HC, and that the vertical scanning circuit 22 is configured to output control signals φSEL, φRST, φTXA, and φTXB as shown in FIG. 27 instead of the control signals φSEL, φRST, and φTX as shown in FIG. 8.

In Figures 34 and 35, two pixels PX that share a set of floating capacitance unit FD, amplification transistor AMP, reset transistor RST, selection transistors SEL, ASEL, write transistor WT, and capacitor HC are shown as a pixel block BL. In addition, in Figures 34 and 35, the photodiode PD and transfer transistor TX of the lower pixel PX in the pixel block BL are indicated by the symbols PDA and TXA, respectively, and the photodiode PD and transfer transistor TX of the upper pixel PX in the pixel block BL are indicated by the symbols PDB and TXB, respectively, to distinguish between the two. In addition, the control signal supplied to the gate of the transfer transistor TXA is indicated as φTXA, and the control signal supplied to the gate electrode of the transfer transistor TXB is indicated as φTXB, to distinguish between the two.

In Figures 28 and 29, N, n, etc. indicate pixel rows, but in Figures 34 and 35, N, n, etc. indicate rows of pixel blocks BL. One row of pixel block BL corresponds to two rows of pixels PX.

The read control in this embodiment is the same as that in the fourth embodiment. Also, in this embodiment, a configuration similar to the configuration of the constrained partial region setting in the fourth embodiment may be adopted, or a configuration similar to the configuration of the unconstrained partial region setting in the fourth embodiment may be adopted.

This embodiment also provides the same advantages as the fifth embodiment. In this embodiment, for every two adjacent pixels PX in the column direction, the two pixels PX share a set of the floating capacitance unit FD, the amplification transistor AMP, the reset transistor RST, the selection transistors SEL and ASEL, the write transistor WT, and the capacitor HC. However, in the present invention, for example, for every predetermined number of pixels PX, three or more adjacent in the column direction, the predetermined number of pixels PX may share a set of the floating capacitance unit FD, the amplification transistor AMP, the reset transistor RST, the selection transistors SEL and ASEL, the write transistor WT, and the capacitor HC. In addition, in the present invention, a modification similar to that of the fifth embodiment modified to this embodiment may be applied to the sixth embodiment.

[Eighth embodiment]

Figure 36 is a circuit diagram showing a schematic configuration of a solid-state imaging element 101 used in an electronic camera according to an eighth embodiment of the present invention, and corresponds to Figure 28. Figure 37 is a circuit diagram showing one pixel PX (pixel PX in the nth row and mth column) of the solid-state imaging element 101 shown in Figure 36, and corresponds to a part of Figure 29. Figure 38 is a timing chart showing write control signals that realize the same settings as the setting example shown in Figure 6 in the solid-state imaging element 101 shown in Figure 36, and corresponds to Figure 31.

In Figures 36 to 38, elements that are the same as or correspond to elements in Figures 28, 29, and 31 are given the same reference numerals, and duplicated explanations are omitted. This embodiment differs from the fifth embodiment in the points described below.

In this embodiment, a solid-state image sensor 101 is used instead of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

In this embodiment, in each pixel PX, an SR latch circuit 103 is provided instead of a capacitor HC as a holding unit that holds a selection control signal for setting the selection transistor ASEL of the pixel PX in a selected or unselected state. Also, in this embodiment, a reset write control circuit 102 is added to the solid-state imaging element 101, which supplies a reset signal φWTRST, which is part of the write control signal, to a reset input R of the SR latch circuit 103. The SR latch circuit 103 can be configured, for example, with a pair of cross-connected NOR gates, but is not limited to this.

The reset inputs R of the SR latch circuits 103 of all pixels PX are commonly connected by a control line 104, to which a reset signal φWTRST is supplied from the reset write control circuit 102. The set input S of the SR latch circuit 103 of each pixel PX is connected to the source of the write transistor WT of that pixel PX. The output Q of the SR latch circuit 103 of each pixel PX is connected to the gate of the select transistor ASEL of that pixel PX.

As can be seen from a comparison between FIG. 38 and FIG. 31, in this embodiment, in order to write a low-level signal as a signal held in the gate of the selection transistor ASEL of all pixels PX during period t31-t32, φWTR(1) to φWTR(9) are set to a high level while φWTC(1) to φWTC(12) are set to a low level, not only supplying a high level to the set input section S of the SR latch circuit 103 of all pixels PX, but also setting the reset signal φWTRST supplied to the reset input section R of the SR latch circuit 103 of all pixels PX to a high level. During other periods, the reset signal φWTRST is maintained at a low level.

In this embodiment, the row write control circuit 72, the column write control circuit 73, and the reset write control circuit 102 collectively constitute a write control unit that supplies write control signals φWTR, φWTC, and φWTRST to the write transistor WT, which serves as the write unit of each pixel PX.

In this embodiment, the row write control circuit 72, column write control circuit 73, reset write control circuit 102, and the write transistor WT and latch circuit 103 of each pixel PX constitute an area setting unit that selects (turns on) the selection transistor ASEL of the pixel PX in one or more desired partial areas to be read out of the imaging area 21.

This embodiment also provides the same advantages as the fifth embodiment. Note that this embodiment does not require the refresh operation described in the fifth embodiment.

In addition, in the present invention, the same modification as that of the fifth embodiment may be applied to the sixth and seventh embodiments. Also, instead of the capacitor HC or the SR latch circuit 103, other latch circuits or other memories may be used as the holding unit. Furthermore, a non-volatile memory may be used as the holding unit. In this case, when the power is cut off, the non-volatile memory of all pixels PX is configured to store information that sets the pixels as readout areas, so that the entire imaging area 21 can be initially set as the readout area immediately after power is turned on. In this way, for example, when still image shooting is performed immediately after power is turned on, the still image shooting can be started quickly, and the shutter opportunity is not missed.

Although the above describes various embodiments of the present invention and their variations, the present invention is not limited to these.

For example, in each of the above embodiments, each connection switch may be provided to turn on and off (electrically connect and disconnect) the gates of the amplification transistors AMP of each of two pixels PX adjacent in the column direction or each of two pixel blocks BL adjacent in the column direction.

In addition, in each of the above embodiments, the output signals of pixels PX arranged in the same column are configured to be output to the same vertical signal line 27, but the pixels PX arranged in the same column may be divided into multiple groups, and the pixel output signal may be output to a different vertical signal line 27 for each group.

Furthermore, in the present invention, the solid-state imaging element is not limited to one composed of a single chip, but may have a structure in which multiple chips are joined together.

In addition, in the present invention, the above-mentioned embodiments and their modified examples may be combined as appropriate.

REFERENCE SIGNS LIST 1 Electronic camera 4 Solid-state image sensor 21 Imaging area 22 Vertical scanning circuit 23 Area setting circuit 72 Row write control circuit 73 Column write control circuit PX Pixel PD Photodiode TX Transfer transistor AMP Amplification transistor RST Reset transistor FD Floating capacitance section SEL, ASEL Selection transistor AR Predefined partial area BL Pixel block WT Write transistor HC Capacitor

Claims (17)

A plurality of photoelectric conversion units arranged in a first direction and a second direction, which perform photoelectric conversion of light into electric charges;
a signal line through which a signal corresponding to the charge photoelectrically converted by the photoelectric conversion unit is output;
a plurality of first output portions provided in the first direction and the second direction for outputting the signal to the signal line;
a plurality of second output portions provided in the first direction and the second direction, for outputting the signal to the signal line via the first output portion;
a first control line provided in common to the first output units provided in the first direction and the second direction in a first region, the first control line being for controlling the first output units;
a second control line provided in common to the first output units provided in the first direction and the second direction in a second region different from the first region, the second control line being for controlling the first output units;
a third control line provided in common to the second output units provided in the first direction in the first region and the second region, for controlling the second output units;
An imaging element having 2. The imaging device according to claim 1,
An imaging element having a setting section that performs settings to output the signal from at least one of the first output section provided in the first region and the first output section provided in the second region. 3. The imaging device according to claim 1,
an imaging element having a power supply line provided in common to the second output sections provided in the first direction and the second direction, for supplying a power supply voltage to the second output sections; 4. The imaging device according to claim 1,
An imaging element having a holding portion that holds a control signal for causing the first output portion to output a signal. 5. The imaging device according to claim 4,
The holding section is an imaging element provided for each of the first output sections. A plurality of photoelectric conversion units arranged in a first direction and a second direction, which perform photoelectric conversion of light into electric charges;
a signal line through which a signal corresponding to the charge photoelectrically converted by the photoelectric conversion unit is output;
a plurality of first output portions provided in the first direction and the second direction for outputting the signal to the signal line;
a plurality of second output portions provided in the first direction and the second direction, for outputting the signal to the signal line via the first output portion;
a power supply line provided in common to the second output units provided in the first direction in a first region and a second region different from the first region, the power supply line supplying a voltage to the second output units;
a first control line provided in common to the second output units provided in the first direction and the second direction in the first region, the first control line being for controlling the second output units;
a second control line provided in common to the second output units provided in the first direction and the second direction in the second region, the second control line being for controlling the second output units;
An imaging element having 7. The imaging device according to claim 6,
An imaging element having a setting section that performs settings to output the signal from at least one of the second output section provided in the first region and the second output section provided in the second region. A plurality of photoelectric conversion units arranged in a first direction and a second direction, which perform photoelectric conversion of light into electric charges;
a signal line through which a signal corresponding to the charge photoelectrically converted by the photoelectric conversion unit is output;
a plurality of first output units provided in the first direction and the second direction, for outputting signals based on charges photoelectrically converted by the photoelectric conversion units to the signal lines;
a first power supply line provided in common to the first output units provided in the first direction and the second direction in the first region, for supplying a voltage to the first output units;
a second power supply line provided in common to the first output units provided in the first direction and the second direction in a second region different from the first region, for supplying a voltage to the first output units;
a control line provided in common to the first output units provided in the first direction in the first region and the second region, the control line being for controlling the first output units;
An imaging element having 9. The imaging device according to claim 8,
An imaging element having a setting unit that performs settings for supplying a voltage to the first power supply line and the second power supply line. A plurality of photoelectric conversion units arranged in a first direction and a second direction, which perform photoelectric conversion of light into electric charges;
a signal line through which a signal corresponding to the charge photoelectrically converted by the photoelectric conversion unit is output;
a first output section provided in the first direction and the second direction and configured to output a signal based on the charge photoelectrically converted by the photoelectric conversion section;
a power supply line provided in common to the first output units provided in the first direction in the first region, for supplying a voltage to the first output units;
a second power supply line provided in common to the first output units provided in the first direction and the second direction in a second region different from the first region, for supplying a voltage to the first output units;
a first control line provided in common to the first output units provided in the first direction and the second direction in the first region, the first control line being for controlling the first output units;
a second control line provided in common to the first output units provided in the first direction and the second direction in the second region, the second control line being for controlling the first output units;
An imaging element having The imaging device according to claim 10,
An imaging element having a setting section that performs settings to output the signal from at least one of the first output section provided in the first region and the first output section provided in the second region. 12. The imaging device according to claim 10,
The power supply line is provided in common to a plurality of first output sections provided in the first direction in the first region and the second region of the imaging element. 13. The imaging device according to claim 1,
An imaging element having a holding portion that holds a control signal for causing the first output portion to output a signal. 14. The imaging device according to claim 13,
The holding section is an imaging element provided for each of the first output sections. 15. The imaging device according to claim 1,
The first output unit is provided in common to two or more photoelectric conversion units of the imaging element. The imaging element according to claim 1 ,
a designation unit capable of designating at least one of the first region and the second region in order to output the signal from at least one of the first region and the second region;
An imaging device comprising: The imaging element according to claim 1 ,
a detection unit that detects a subject based on the signal from the imaging element so as to output the signal from at least one of the first area and the second area;
An imaging device comprising:

Images