JP7058933B2 - Image sensor and image sensor using it - Google Patents

Description

The present invention relates to a solid-state image sensor and an image pickup device using the same.

A region selection technique for selecting an arbitrary region in an image pickup apparatus is known. With the region selection technique, it was not possible to read out multiple regions of the imaging region.

Japanese Unexamined Patent Publication No. 9-46600

The solid-state image pickup device according to the first aspect is provided between a plurality of photoelectric conversion units, a signal line from which a signal due to the charge photoelectrically converted by the photoelectric conversion unit is output, and between the photoelectric conversion unit and the signal line. , The photoelectric conversion unit provided between the first selection unit that outputs the signal of the selected photoelectric conversion unit and the first selection unit and the signal line, and output from the first selection unit. It has a second selection unit that outputs a signal to the signal line.

In the first aspect, the solid-state image pickup device according to the second aspect selects the first selection unit or the second selection unit of a partial region of the image pickup region in which the plurality of photoelectric conversion units are arranged. It is provided with an area setting unit.

In the solid-state imaging device according to the third aspect, in the second aspect, the imaging region is divided into a plurality of predetermined regions, and the region setting unit is used for each of the plurality of predetermined regions. , A selection control signal for collectively selecting or not selecting the first selection unit or the second selection unit of the region is supplied, and the partial region is one or more of the plurality of predetermined regions. It consists of.

In the second aspect of the solid-state image pickup device according to the fourth aspect, the area setting unit holds a selection control signal for selecting or not selecting the first selection unit or the second selection unit. It has a writing unit that writes the selection control signal to the holding unit according to the writing control signal, and a writing control unit that supplies the writing control signal to the writing unit.

In any of the second to fourth aspects, the solid-state image sensor according to the fifth aspect has a plurality of the partial regions, and the second selection portion or the first selection portion of each row of the plurality of partial regions is used. While selecting, the second selection unit or the first selection unit includes a control unit that performs read control for the selected row.

The solid-state image pickup device according to the sixth aspect is provided between a plurality of photoelectric conversion units, a signal line from which a signal due to the charge photoelectrically converted by the photoelectric conversion unit is output, and between the photoelectric conversion unit and the signal line. , A selection unit that outputs the signal of the selected photoelectric conversion unit, and an amplification unit that is provided in series with the selection unit between the photoelectric conversion unit and the signal line and outputs the signal of the photoelectric conversion unit. And, as the power supply voltage of the amplification unit, it has a power supply control means for selectively supplying an effective voltage level effective for the operation of the amplification unit or a non-effective voltage level not effective for the operation.

The solid-state image sensor according to the seventh aspect includes a plurality of photoelectric conversion units, a signal line for which a signal due to the charge photoelectrically converted by the photoelectric conversion unit is output, and two or more of the plurality of photoelectric conversion units. The first selection unit, which is commonly provided in the photoelectric conversion unit and outputs the signal of the two or more selected photoelectric conversion units, and the first selection unit, which is provided between the first selection unit and the signal line, is the first. It has a second selection unit that outputs the signal of the photoelectric conversion unit output from the selection unit to the signal line.

In the seventh aspect, the solid-state image pickup device according to the eighth aspect selects the first selection unit or the second selection unit of a partial region of the image pickup region in which the plurality of photoelectric conversion units are arranged. It is provided with an area setting unit.

In the eighth aspect of the solid-state image pickup device according to the ninth aspect, the image pickup region is divided into a plurality of predetermined regions, and the region setting unit is used for each of the plurality of predetermined regions. , A selection control signal for collectively selecting or not selecting the first selection unit or the second selection unit of the region is supplied, and the partial region is one or more of the plurality of predetermined regions. It consists of.

In the eighth aspect of the solid-state image pickup device according to the tenth aspect, the area setting unit holds a selection control signal for selecting or not selecting the first selection unit or the second selection unit. It has a writing unit that writes the selection control signal to the holding unit according to the writing control signal, and a writing control unit that supplies the writing control signal to the writing unit.

In any of the eighth to tenth aspects, the solid-state image sensor according to the eleventh aspect has a plurality of the partial regions, and the second selection portion or the first selection portion of each row of the plurality of partial regions is used. While selecting, the second selection unit or the first selection unit includes a control unit that performs read control for the selected row.

The solid-state image pickup device according to the twelfth aspect includes a plurality of photoelectric conversion units, a signal line from which a signal due to the charge photoelectrically converted by the photoelectric conversion unit is output, and two or more of the plurality of photoelectric conversion units. A selection unit that is commonly provided in the photoelectric conversion unit and outputs the signal of the two or more selected photoelectric conversion units, and the selection unit between the two or more photoelectric conversion units and the signal line. The amplification unit provided in series and outputting the signal of the two or more photoelectric conversion units and the power supply voltage of the amplification unit are effective voltage levels effective for the operation of the amplification unit or not effective for the operation. It has a power supply control means for selectively supplying a non-active voltage level.

The image pickup device according to the thirteenth aspect includes a solid-state image pickup device according to any one of the second to fifth and eighth to eleventh aspects, and a user interface for the user to command the partial region. The partial area is set according to the instruction by the user interface.

The image pickup device according to the fourteenth aspect is a plurality of solid-state image pickup devices according to any one of the second to fifth and eighth to eleventh embodiments, and a plurality of image pickup devices in the image pickup region based on the image signals from the solid-state image pickup device. A detection unit for detecting the position of an image pickup target is provided, and the partial region is set according to the position detected by the detection unit.

According to the present invention, it is possible to provide a solid-state image pickup device capable of reading out a plurality of desired partial regions in an image pickup region at high speed, and an image pickup device using the solid-state image pickup device.

It is a schematic block diagram which shows the electronic camera by 1st Embodiment of this invention. It is a circuit diagram which shows the schematic structure of the solid-state image pickup device in FIG. It is a schematic plan view which shows typically the solid-state image pickup device in FIG. It is a circuit diagram which shows the predetermined partial area which forms a part of the image pickup area of the solid-state image pickup element in FIG. It is a circuit diagram which shows by abstracting the circuit shown in FIG. It is a figure which shows typically the setting example of the reading partial area in the image pickup area of the solid-state image sensor in FIG. 1. It is a figure which shows the selection control signal which realizes the setting example shown in FIG. 6 in the solid-state image sensor in FIG. It is a timing chart which shows an example of the read-out control in the partial area photographing mode of the solid-state image sensor in FIG. It is a figure which shows the other setting example of the partial area to read out of the image pickup area of the solid-state image sensor in FIG. 1 schematically. It is a figure which shows the selection control signal which realizes the setting example shown in FIG. 9 in the solid-state image sensor in FIG. It is a figure which shows the other setting example of the partial area to read out of the image pickup area of the solid-state image sensor in FIG. 1 schematically. It is a figure which shows the selection control signal which realizes the setting example shown in FIG. 6 is a timing chart showing another example of readout control in the partial region imaging mode of the solid-state image sensor in FIG. 1. It is a timing chart which shows an example of the read-out control in the whole area image pickup mode of the solid-state image sensor in FIG. It is a schematic flowchart which shows an example of the operation in the 1st partial area photography mode of the electronic camera shown in FIG. It is a schematic flowchart which shows an example of the operation in the 2nd partial area photography mode of the electronic camera shown in FIG. It is a circuit diagram which shows the schematic structure of the solid-state image sensor used in the electronic camera by the 2nd Embodiment of this invention. It is a circuit diagram which shows the predetermined partial area which forms a part of the image pickup area of the solid-state image sensor shown in FIG. It is a circuit diagram which shows by abstracting the circuit shown in FIG. It is a figure which shows the power supply voltage signal which realizes the same setting as the setting example shown in FIG. 6 in the solid-state image sensor shown in FIG. It is a circuit diagram which shows the schematic structure of the solid-state image sensor used in the electronic camera by the 3rd Embodiment of this invention. It is a circuit diagram which shows the predetermined partial area which forms a part of the image pickup area of the solid-state image sensor shown in FIG. FIG. 21 is a timing chart showing an example of readout control in the partial region imaging mode of the solid-state image sensor shown in FIG. 21. It is a circuit diagram which shows the schematic structure of the solid-state image sensor used in the electronic camera by 4th Embodiment of this invention. It is a circuit diagram which shows the predetermined partial area which forms a part of the image pickup area of the solid-state image sensor shown in FIG. 24. It is a circuit diagram which shows by abstracting the circuit shown in FIG. It is a timing chart which shows an example of the read-out control in the partial area photographing mode of the solid-state image sensor shown in FIG. 24. It is a circuit diagram which shows the schematic structure of the solid-state image sensor used in the electronic camera by the 5th Embodiment of this invention. It is a circuit diagram which shows a part of the image pickup region of the solid-state image sensor shown in FIG. 28. FIG. 8 is a timing chart showing a write control signal when an H signal is written to a capacitor and when an L signal is written in the solid-state image sensor shown in FIG. 28. It is a timing chart which shows the write control signal which realizes the same setting as the setting example shown in FIG. 6 in the solid-state image sensor shown in FIG. 28. It is a circuit diagram which shows the schematic structure of the solid-state image sensor used in the electronic camera by the 6th Embodiment of this invention. It is a circuit diagram which shows a part of the image pickup region of the solid-state image sensor shown in FIG. 32. It is a circuit diagram which shows the schematic structure of the solid-state image sensor used in the electronic camera by 7th Embodiment of this invention. It is a circuit diagram which shows a part of the image pickup region of the solid-state image sensor shown in FIG. 34. It is a circuit diagram which shows the schematic structure of the solid-state image sensor used in the electronic camera by 8th Embodiment of this invention. It is a circuit diagram which shows one pixel of the solid-state image sensor shown in FIG. 36. It is a timing chart which shows the write control signal which realizes the same setting as the setting example shown in FIG. 6 in the solid-state image sensor shown in FIG. 36.

Hereinafter, the solid-state image pickup device and the image pickup apparatus according to the present invention will be described with reference to the drawings.

[First Embodiment]

FIG. 1 is a schematic block diagram showing an electronic camera 1 as an image pickup apparatus according to the first embodiment of the present invention.

The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera, but the imaging device according to the present invention is not limited to this, and is mounted on other electronic cameras such as compact cameras and mobile phones. An electronic camera such as an electronic camera or a video camera that captures a moving image, a surveillance camera that captures a moving image for surveillance, an imaging device incorporated in a microscope to capture a microscope image, or an imaging device incorporated in a telescope to capture a telescope image. It can be applied to various imaging devices such as devices.

A photographing lens 2 is attached to the electronic camera 1. The focus and aperture of the photographing lens 2 are driven by the lens control unit 3. The image pickup surface of the solid-state image pickup device 4 is arranged in the image space of the photographing lens 2.

The solid-state image sensor 4 is driven by a command from the image pickup control unit 5 and outputs a digital image signal. At the time of still image shooting, for example, the image pickup control unit 5 controls the solid-state image pickup element 4 so as to perform a predetermined readout operation after exposure with a mechanical shutter (not shown) after a so-called global reset that resets all pixels at the same time. .. Further, in the electronic viewfinder mode or when shooting a moving image (in the first and second partial area shooting modes described later, in the full area shooting mode, etc.), the image pickup control unit 5 performs, for example, a so-called rolling electronic shutter. The solid-state image sensor 4 is controlled so as to perform a predetermined readout operation. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state image sensor 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. A lens control unit 3, an image pickup control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like are also connected to the bus 8. An operation unit 14 such as a release button is connected to the CPU 9. A recording medium 11a is detachably attached to the recording unit 11.

When the electronic viewfinder mode, moving image shooting, still image shooting, or the like is instructed by the operation of the operation unit 14, the CPU 9 in the electronic camera 1 drives the image pickup control unit 5. At this time, the lens control unit 3 appropriately adjusts the focus and the aperture. The solid-state image sensor 4 is driven by a command from the image pickup control unit 5 and outputs a digital image signal. The digital image signal from the solid-state image sensor 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. The CPU 9 causes the display unit 10 to display the image signal in the electronic viewfinder mode, and records the image signal in the recording medium 11a when shooting a moving image. In the case of still image shooting, the CPU 9 is required based on the command of the operation unit 14 after the digital image signal from the solid-state image sensor 4 is processed by the digital signal processing unit 6 and stored in the memory 7. Accordingly, the image processing unit 13 and the image compression unit 12 perform desired processing, and the recording unit 11 outputs the processed signal and records it on the recording medium 11a.

FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state image pickup device 4 in FIG. In the present embodiment, the solid-state image sensor 4 is configured as a CMOS-type solid-state image sensor, but may be configured as another XY address-type solid-state image sensor, for example.

The solid-state image sensor 4 includes a pixel PX arranged in a two-dimensional matrix in N rows and M columns in the image pickup region 21, a vertical scanning circuit 22, an area setting circuit 23, and a control line provided for each row of the pixel PX. 24 to 26, a plurality of (M) vertical signal lines 27 provided for each row of pixel PX and receiving signals from the corresponding row of pixels PX, and a constant current source 28 provided for each vertical signal line 27. A column amplifier 29, a CDS circuit (correlated double sampling circuit) 30, an A / D converter 31, a horizontal readout circuit 32, and a default partial area of the image pickup area 21 provided corresponding to each vertical signal line 27. It has a control line 33 provided for each AR (see FIG. 3 described later). The default partial region AR is a predetermined partial region (partial region) of the imaging region 21.

As the column amplifier 29, an analog amplifier may be used, or a so-called switched capacitor amplifier may be used. Further, the column amplifier 29 does not necessarily have to be provided.

FIG. 3 is a schematic plan view schematically showing the solid-state image sensor 4 (particularly, the image pickup region 21 thereof) in FIG. In the present embodiment, as shown in FIG. 3, the image pickup region 21 of the solid-state image pickup device 4 is arranged in a matrix and is divided into J × K predetermined partial region ARs of J rows and K columns. There is. When distinguishing each default partial area AR, the default partial area AR in the jth row and the kth column is indicated by the reference numeral AR (j, k). As shown in FIGS. 4 and 5, each default partial region AR is composed of A × B pixels (A is an integer of 2 or more and B is an integer of 1 or more) in rows A and columns B. In the present embodiment, the sizes of the predetermined partial regions AR (the number of rows A and the number of columns B of the pixel PX) are the same as each other, but the present invention is not limited to this. However, it is preferable that the number of rows A of the pixels PX of each predetermined partial region AR is the same as each other.

FIG. 4 is a circuit diagram showing a default partial region AR forming a part of the imaging region 21 of the solid-state imaging device 4 in FIG. 1. In FIG. 4, one of the default partial area AR (j, k) in the jth row and the kth column and the default partial area AR (j-1, k) in the j-1st row and the kth column adjacent thereto. Shows the part. The default partial area AR (j, k) is composed of A × B pixels PX in rows A and columns A arranged from the nth row to the (n + A-1) th row. In FIG. 4, for convenience of drawing notation, the connection states of the control lines 24 to 26, 33 and the feeder line 34 described later are not shown, but the control lines 24 to 26 are commonly connected for each line of the pixel PX. The control line 33 is commonly connected to each default partial region AR, and the feeder line 34 is commonly connected to all pixels PX.

In this embodiment, all the pixels PX have the same circuit configuration. In the present embodiment, unlike a general CMOS image sensor, each pixel PX has two selection transistors (SEL, ASEL) for selecting the pixel PX, but other pixels PX have other elements. The configuration is the same as that of a general CMOS image sensor.

That is, as shown in FIG. 4, each pixel PX has a photodiode PD as a photoelectric conversion unit that generates and stores an electric charge according to incident light, and a charge-voltage conversion that receives the electric charge and converts the electric charge into a voltage. Floating capacitance section FD as a unit, amplification transistor AMP as an amplification section that outputs a signal corresponding to the potential of the floating capacitance section FD as an output signal of the pixel PX, and charge transfer from the photodiode PD to the floating capacitance section FD. The transfer transistor TX, the reset transistor RST that resets the potential of the floating capacitance portion FD, the selection transistor SEL that forms a selection switch as the first selection unit for selecting the pixel PX, and the pixel PX are selected. It has a selection transistor ASEL that serves as a selection switch as a second selection unit for the purpose, and is connected as shown in FIG. In the present embodiment, the drain of the amplification transistor AMP of all pixels PX (point b in FIG. 4) is commonly connected by the feeder line 34, and the power supply voltage of the amplification transistor AMP is used as the power supply voltage of the amplification transistor AMP. The active voltage level VDD, which is effective for operation, is fixedly supplied. This active voltage level VDD is also supplied to the drain of the reset transistor RST of each pixel PX by the feeder line 34. In FIG. 2, the feeder line 34 is not shown.

In the present embodiment, the output signal of each pixel PX is applied to the output signal of the pixel PX and the pixel PX only when both the first and second selection units of the pixel PX are in the selected state. It is output to the vertical signal line 27 that receives the output signals of the pixels PX arranged in the column direction. Specifically, in the present embodiment, in each pixel PX, the selection transistors SEL and ASEL are connected in series between the source of the amplification transistor AMP and the vertical signal line 27 corresponding to the pixel PX. It is realized by doing so. Only when both the selection transistors SEL and ASEL are on (in the selected state), the output signal of the pixel PX is output to the vertical signal line 27. The connection order of the selection transistor SEL and the selection transistor ASEL between the amplification transistor AMP and the vertical signal line 27 may be reversed from the order shown in FIG.

Although not shown in the drawings, in the present embodiment, a plurality of types of color filters that transmit light having different color components are arranged in a predetermined color on the light incident side of the photodiode PD of each pixel PX. (For example, Bayer arrangement). The pixel PX outputs an electric signal corresponding to each color by color separation by a color filter.

In this embodiment, the transistors TX, AMP, RST, SEL, and ASEL are all nMOS transistors.

The gate of the transfer transistor TX is commonly connected to the control line 25 for each row of the pixel PX, to which the control signal φTX is supplied from the vertical scanning circuit 22. The gate of the reset transistor RST is commonly connected to the control line 24 for each row of the pixel PX, to which the control signal φRST is supplied from the vertical scanning circuit 22. The gate of the selection transistor SEL is commonly connected to the control line 26 line by line, and the control signal φSEL is supplied to the control line 26 from the vertical scanning circuit 22. When each control signal φTX is distinguished for each row, the control signal φTX supplied to the gate of the transfer transistor TX of the pixel PX in the nth row is indicated by the reference numeral φTX (n). This point is the same for other control signals φRST and φSEL.

The gate of the selection transistor ASEL (point a in FIG. 4) is commonly connected to the control line 33 for each predetermined partial region AR, and the control signal φASEL is supplied from the region setting circuit 23 to the control line 33. FIG. 5 is an abstraction of the circuit shown in FIG. 4, focusing on the connection relationship of the gate (point a) of the selection transistor ASEL of each predetermined partial region AR by the control line 33. When each control signal φASEL is distinguished for each default partial region AR, the control signal φASEL supplied to the gate of the selection transistor ASEL of the pixel PX of the default partial region AR (j, k) in the jth row and the kth column is a code. It is shown by φASEL (j, k). The arrangement of the area setting circuit 23 and the actual arrangement of the control lines 33 (routes to be routed, etc.) are not limited in any way.

Under the control of the image pickup control unit 5 in FIG. 1, the area setting circuit 23 serves as the second selection unit of the pixel PX of the default partial area AR for each of the default partial area ARs in the image pickup area 21. The control signal φASEL as a selection control signal for collectively setting the selection transistor ASEL in the selection state or the non-selection state is supplied. As a result, the area setting circuit 23 sets the default partial area AR in which the selection transistor ASEL is selected as the area for reading the output signal of the pixel PX in the image pickup area 21.

The vertical scanning circuit 22 outputs control signals φTX, φRST, and φSEL for each row of the pixel PX under the control of the image pickup control unit 5 in FIG. 1, and is combined with the area setting operation by the area setting circuit 23. Therefore, a still image reading operation and a moving image reading operation such as the first and second partial area shooting modes described later are realized. By this control, the signal (analog signal) of the pixel PX of the region set by the region setting circuit 23 is supplied to the corresponding vertical signal line 27.

The signal read out to the vertical signal line 27 is amplified by the column amplifier 29 for each column, and further, an optical signal (a signal including optical information photoelectrically converted by the pixel PX) and a dark signal (optical) are amplified by the CDS circuit 30. After processing to obtain the difference from the difference signal including the noise component to be subtracted from the signal), it is converted into a digital signal by the A / D converter 31, and the digital signal is held in the A / D converter 31. Will be done. The digital image signal held in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32, converted into a predetermined signal format as necessary, and externally (digital signal processing unit 6 in FIG. 1). ) Is output.

The CDS circuit 30 receives the dark signal sampling signal φDARKC from the timing generation circuit (not shown) under the control of the image pickup control unit 5 in FIG. 1, and the φDARKC changes from high level (H) to low level (L). The output signal of the column amplifier 29 is sampled as a dark signal at the switching timing, and the optical signal sampling signal φSIGC is received from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1, and the φSIGC is from high level to low level. The output signal of the column amplifier 29 is sampled as an optical signal at the timing of switching to. Then, the CDS circuit 30 outputs a signal corresponding to the difference between the sampled dark signal and the optical signal based on the clock or pulse from the timing generation circuit. As the configuration of such a CDS circuit 30, a known configuration can be adopted.

FIG. 6 is a diagram schematically showing a setting example of a partial region to be read out of the imaging region 21 of the solid-state image sensor 4 in the partial region photographing mode. The partial region photographing mode is an operation mode for selectively reading out the output signal of the pixel PX of a desired one or a plurality of desired partial regions in the imaging region 21 of the solid-state imaging device 4. For ease of understanding, in FIG. 6, it is assumed that N = 9, M = 12, A = 3 and B = 3, and the imaging region 21 is composed of 9 × 12 pixels PX with 9 rows and 12 columns. It is assumed that each default partial area AR consists of 3 rows and 3 columns of pixels PX. Even if the values of N, M, A, and B are other values, the following description is similarly applicable.

In FIG. 6, the default partial areas AR (3,1), AR (1,2), AR (2,3), and AR (1,4) set as the four partial areas to be read are hatched. ing. In this example, each one subregion to be read consists of one default subregion AR.

FIG. 7 shows a selection control signal φASEL that realizes the setting example shown in FIG. 6 in the solid-state image sensor 4 in FIG. The selection control signal φASEL (3,1) supplied to the gate of the selection transistor ASEL of the default partial regions AR (3,1), AR (1,2), AR (2,3), AR (1,4), φASEL (1,2), φASEL (2,3), φASEL (1,4) are maintained at a high level (H), and other selection control signals φASEL are maintained at a low level (L). As a result, the selection transistor ASEL of the default partial region AR (3,1), AR (1,2), AR (2,3), AR (1,4) is kept on, while the other default portions. The selection transistor ASEL in region AR is kept off.

In the present embodiment, when the partial area to be read is set as shown in FIG. 6 in the partial area photographing mode, the reading control is performed as shown in FIG. 8, for example. FIG. 8 is a timing chart showing an example of readout control in the partial region imaging mode of the solid-state image sensor 4 in FIG. 1.

In the example shown in FIG. 8, the vertical scanning circuit 22 causes the first row, the fourth row, and the seventh row in the imaging region 21 corresponding to the row of the pixel PX in the first row in each predetermined partial region AR in the period T1. Read control is performed simultaneously for the rows of the pixel PX, and in the next period T2, the second row, the fifth row, and the eighth row in the imaging region 21 corresponding to the row of the second row of the pixel PX in each predetermined partial region AR. Read control is performed simultaneously for the row of the pixel PX of the eye, and in the next period T3, the third row, the sixth row, and the third row in the imaging region 21 corresponding to the row of the third row of the pixel PX in each predetermined partial area AR are performed. Read control is performed simultaneously for the 9th row of the pixel PX, whereby reading for one frame is completed. By sequentially repeating the periods T1 to T3, a plurality of frames are read out by the rolling electronic shutter. For example, during the exposure period of the pixel PX in the first row, the control signal φTX (1) changes from the high level to the low level this time from the time when the control signal φTX (1) in the first line changed from the high level to the low level last time. It will be the period until the point. The read control of each period T1 to T3 will be described in detail below.

Immediately before the start of each period T1 to T3, the transistors SEL, RST, and TX of the pixels PX in all rows are turned off.

In the period T1, the φSEL (1) in the first row, the φSEL (4) in the fourth row, and the φSEL (7) in the seventh row are set to a high level, and the pixels PX in the first row, the fourth row, and the seventh row are set to high levels. The selection transistors SEL (1), SEL (4), and SEL (7) are turned on, and the pixels PX in the first row, the fourth row, and the seventh row are selected. However, now that the selection control signal φASEL is shown in FIG. 7 so that the setting example shown in FIG. 6 is realized, the column (4) in which the hatching is attached to the pixel PX in the first row. The selection transistor ASEL of the pixel PX of the 6th column to the 6th column, the 10th column to the 12th column is turned on, and the column (1st column to the 3rd column) of the pixel PX in the 1st row without hatching is turned on. , 7th to 9th columns), the selection transistor ASEL of the pixel PX is turned off. Further, the selection transistor ASEL of the pixel PX in the column (7th to 9th columns) to which the hatching of the pixel PX in the 4th row is attached is turned on, and the hatching of the pixel PX in the 4th row is attached. The selection transistor ASEL of the pixel PX in the columns not set (1st to 6th columns, 10th to 12th columns) is turned off. Further, the selection transistor ASEL of the pixel PX in the column (1st to 3rd columns) to which the hatch of the pixel PX in the 7th row is attached is turned on, and the hatching of the pixel PX in the 7th row is attached. The selection transistor ASEL of the pixel PX in the columns (4th to 12th columns) that are not set is turned off.

Therefore, in the period T1, the pixel PX in which both the selection transistors SEL and ASEL are turned on (the pixel PX in the 4th to 6th columns and the 10th to 12th columns in the 1st row, and the 7th column in the 4th row). The output signal of only the pixel PX in the 9th column and the pixel PX in the 1st to 3rd columns in the 7th row) can be output to the corresponding vertical signal line 27.

The control signals φRST (1), φRST (4), and φRST (7) on the 1st, 4th, and 7th lines are set to high levels for a certain period of time immediately after the start of the period T1, and the 1st, 4th, and 4th lines are set to high levels. The reset transistor RST of the pixel PX in the 7th and 7th rows is once turned on, and the potential of the floating capacitance portion FD (the potential of the gate of the amplification transistor AMP) is temporarily reset to the voltage level VDD.

By setting the dark signal sampling signal φDARKC to a high level for a certain period from the subsequent time point t1 during the period T1, the pixels PX in the 4th to 6th columns and the 10th to 12th columns in the first row, The potential appearing at the gate of the amplification transistor AMP of the pixel PX in the 7th to 9th columns in the 4th row and the pixel PX in the 1st to 3rd columns in the 7th row is the amplification transistor AMP of the pixel PX. After being amplified, it is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal. To.

The control signals φTX (1), φTX (4), and φTX (7) on the 1st, 4th, and 7th lines are set to high levels for a certain period from the subsequent time point t2 in the period T1, and the 1st line is set. The transfer transistor TX of the pixels PX in the 4th and 7th rows is turned on. As a result, the signal charge stored in the photodiode PD of the pixels PX in the 1st, 4th, and 7th rows is transferred to the floating capacitance portion FD of the pixels PX in the 1st, 4th, and 7th rows. Each is transferred. The potential of the floating capacitance part FD of the pixels PX in the 1st, 4th, and 7th rows (the potential of the gate of the amplification transistor AMP) is the amount of each signal charge and the 1st row, 4th row, excluding the noise component. The value is proportional to the inverse of each capacity value of the floating capacity portion FD of the pixels PX in the rows and the seventh row.

By setting the optical signal sampling signal φSIGC to a high level for a certain period from the subsequent time point t3 in the period T1, the pixels PX in the 4th to 6th columns and the 10th to 12th columns in the first row, The potential appearing at the gate of the amplification transistor AMP of the pixel PX in the 7th to 9th columns in the 4th row and the pixel PX in the 1st to 3rd columns in the 7th row is the amplification transistor AMP of the pixel PX. After being amplified, it is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal. To.

After that, after the φSIGC becomes low level, the CDS circuit 30 outputs a signal corresponding to the difference between the dark signal sampled earlier and the optical signal sampled earlier. The A / D converter 31 converts the signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32 and output as a digital signal image signal to the outside (digital signal processing unit 6 in FIG. 1).

In the period T2 after the period T1, the φSEL (2) in the second line, the φSEL (5) in the fifth line, and the φSEL (8) in the eighth line are set to high levels, and the second line, the fifth line, and the eighth line are set to high levels. Selection of Pixel PX of the Eye The transistors SEL (2), SEL (5), and SEL (8) are turned on, and the pixels PX of the second row, the fifth row, and the eighth row are selected. However, since the selection control signal φASEL is now shown in FIG. 7 so that the setting example shown in FIG. 6 is realized, the column (4) in which the hatching is attached to the pixel PX in the second row. The selection transistor ASEL of the pixel PX of the 6th column to the 6th column, the 10th column to the 12th column is turned on, and the column (1st column to the 3rd column) of the pixel PX in the second row without hatching is turned on. , 7th to 9th columns), the selection transistor ASEL of the pixel PX is turned off. Further, the selection transistor ASEL of the pixel PX in the column (7th to 9th columns) to which the hatching of the pixel PX in the 5th row is attached is turned on, and the hatching of the pixel PX in the 5th row is attached. The selection transistor ASEL of the pixel PX in the columns not set (1st to 6th columns, 10th to 12th columns) is turned off. Further, the selection transistor ASEL of the pixel PX in the column (1st to 3rd columns) to which the hatch of the pixel PX in the 8th row is attached is turned on, and the hatching of the pixel PX in the 8th row is attached. The selection transistor ASEL of the pixel PX in the columns (4th to 12th columns) that are not set is turned off.

Therefore, in the period T2, the pixel PX in which both the selection transistors SEL and ASEL are turned on (the pixel PX in the 4th to 6th columns and the 10th to 12th columns in the 2nd row, and the 7th column in the 5th row). The output signal of only the pixel PX in the 9th column and the pixel PX in the 1st to 3rd columns in the 8th row) can be output to the corresponding vertical signal line 27.

The control signals φRST (2), φRST (5), and φRST (8) on the 2nd, 5th, and 8th lines are set to high levels for a certain period of time immediately after the start of the period T2, and the 2nd, 5th, and 5th lines are set. The reset transistor RST of the pixel PX in the 8th row and the 8th row is turned on once, and the potential of the floating capacitance portion FD (the potential of the gate of the amplification transistor AMP) is temporarily reset to the voltage level VDD.

By setting the dark signal sampling signal φDARKC to a high level for a certain period from a subsequent point in time during the period T2, the pixels PX, 5 in the 4th to 6th columns and the 10th to 12th columns in the second row. The potential appearing at the gate of the amplification transistor AMP of the pixel PX in the 7th to 9th columns in the row and the pixel PX in the 1st to 3rd columns in the 8th row is amplified by the amplification transistor AMP of the pixel PX. After that, it is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal. ..

The control signals φTX (2), φTX (5), φTX (8) on the 2nd, 5th, and 8th lines are set to high levels for a certain period from the subsequent time point in the period T2, and the 2nd line, The transfer transistor TX of the pixel PX on the 5th and 8th rows is turned on. As a result, the signal charge accumulated in the photodiode PD of the pixels PX in the second, fifth, and eighth rows is transferred to the floating capacitance portion FD of the pixels PX in the second, fifth, and eighth rows. Each is transferred. The potential of the floating capacitance part FD of the pixels PX in the 2nd, 5th, and 8th rows (the potential of the gate of the amplification transistor AMP) is the amount of each signal charge and the 2nd and 5th rows, excluding the noise component. The value is proportional to the inverse of each capacity value of the floating capacity portion FD of the pixels PX in the rows and the eighth row.

By setting the optical signal sampling signal φSIGC to a high level for a certain period from the subsequent time point in the period T2, the pixels PX, 5 in the 4th to 6th columns and the 10th to 12th columns in the second row. The potential appearing at the gate of the amplification transistor AMP of the pixel PX in the 7th to 9th columns in the row and the pixel PX in the 1st to 3rd columns in the 8th row is amplified by the amplification transistor AMP of the pixel PX. After that, it is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal. ..

After that, after the φSIGC becomes low level, the CDS circuit 30 outputs a signal corresponding to the difference between the dark signal sampled earlier and the optical signal sampled earlier. The A / D converter 31 converts the signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32 and output as a digital signal image signal to the outside (digital signal processing unit 6 in FIG. 1).

In the period T3 after the period T2, the φSEL (3) in the 3rd line, the φSEL (6) in the 6th line, and the φSEL (9) in the 9th line are set to high levels, and the 3rd line, the 6th line, and the 9th line are set to high levels. Selection of Pixel PX of Eyes The transistors SEL (3), SEL (6), and SEL (9) are turned on, and the pixels PX of the third row, the sixth row, and the ninth row are selected. However, now that the selection control signal φASEL is shown in FIG. 7 so that the setting example shown in FIG. 6 is realized, the column (4) in which the hatching is attached to the pixel PX in the third row. The selection transistor ASEL of the pixel PX of the 6th column to the 6th column, the 10th column to the 12th column is turned on, and the column (1st column to the 3rd column) of the pixel PX in the 3rd row without hatching is turned on. , 7th to 9th columns), the selection transistor ASEL of the pixel PX is turned off. Further, the selection transistor ASEL of the pixel PX in the column (7th to 9th columns) to which the hatching of the pixel PX in the 6th row is attached is turned on, and the hatching of the pixel PX in the 6th row is attached. The selection transistor ASEL of the pixel PX in the columns not set (1st to 6th columns, 10th to 12th columns) is turned off. Further, the selection transistor ASEL of the pixel PX in the column (1st to 3rd columns) to which the hatch of the pixel PX in the 8th row is attached is turned on, and the hatching of the pixel PX in the 9th row is attached. The selection transistor ASEL of the pixel PX in the columns (4th to 12th columns) that are not set is turned off.

Therefore, in the period T3, the pixel PX in which both the selection transistors SEL and ASEL are turned on (the pixel PX in the 4th to 6th columns and the 10th to 12th columns in the 3rd row, and the 7th column in the 6th row). The output signal of only the pixel PX in the 9th column and the pixel PX in the 1st to 3rd columns in the 9th row) can be output to the corresponding vertical signal line 27.

The control signals φRST (3), φRST (6), and φRST (9) on the 3rd, 6th, and 9th lines are set to high levels for a certain period of time immediately after the start of the period T3, and the 3rd, 6th, and 6th lines are set to high levels. The reset transistor RST of the pixel PX in the eyes and the ninth row is turned on once, and the potential of the floating capacitance portion FD (the potential of the gate of the amplification transistor AMP) is temporarily reset to the voltage level VDD.

By setting the dark signal sampling signal φDARKC to a high level for a certain period from a subsequent time point in the period T3, the pixels PX, 6 in the 4th to 6th columns and the 10th to 12th columns in the 3rd row. The potential appearing at the gate of the amplification transistor AMP of the pixel PX in the 7th to 9th columns in the row and the pixel PX in the 1st to 3rd columns in the 9th row is amplified by the amplification transistor AMP of the pixel PX. After that, it is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal. ..

The control signals φTX (3), φTX (6), φTX (9) on the 3rd, 6th, and 9th lines are set to high levels for a certain period from the subsequent time point in the period T3, and the 3rd line, The transfer transistor TX of the pixel PX on the 6th and 9th rows is turned on. As a result, the signal charge stored in the photodiode PD of the pixels PX in the 3rd, 6th, and 9th rows is transferred to the floating capacitance portion FD of the pixels PX in the 3rd, 6th, and 9th rows. Each is transferred. The potential of the floating capacitance part FD of the pixel PX in the 3rd, 6th, and 9th rows (the potential of the gate of the amplification transistor AMP) is the amount of each signal charge and the 3rd and 6th rows, excluding the noise component. The value is proportional to the inverse of each capacity value of the floating capacity portion FD of the pixels PX in the rows and the ninth row.

By setting the optical signal sampling signal φSIGC to a high level for a certain period from the subsequent time point in the period T3, the pixels PX, 6 in the 4th to 6th columns and the 10th to 12th columns in the 3rd row. The potential appearing at the gate of the amplification transistor AMP of the pixel PX in the 7th to 9th columns in the row and the pixel PX in the 1st to 3rd columns in the 9th row is amplified by the amplification transistor AMP of the pixel PX. After that, it is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal. ..

After that, after the φSIGC becomes low level, the CDS circuit 30 outputs a signal corresponding to the difference between the dark signal sampled earlier and the optical signal sampled earlier. The A / D converter 31 converts the signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32 and output as a digital signal image signal to the outside (digital signal processing unit 6 in FIG. 1).

In this way, the output signals of the pixels PX of the plurality of partial regions set as shown in FIG. 6 are read out.

FIG. 9 is a diagram schematically showing another setting example of the partial region to be read out of the imaging region 21 of the solid-state image sensor 4 in the partial region photographing mode, and corresponds to FIG. FIG. 10 shows a selection control signal φASEL that realizes the setting example shown in FIG. 9 in the solid-state image sensor 4 in FIG. 1, and corresponds to FIG. 7.

In FIG. 9, the default partial areas AR (1,1), AR (1,2), AR (2,3), and AR (2,4) set as the two partial areas to be read are hatched. ing. In this example, one partial area to be read consists of two default partial areas AR (1,1) and AR (1,2), and the other one partial area to be read is two default partial areas AR (2, 2). 3), AR (2,4).

As described above, in the present embodiment, each of the one or more partial regions to be read may be composed of one default partial region AR or may be composed of a plurality of default partial region ARs. Further, in the present embodiment, when reading a plurality of partial areas, each partial area does not necessarily have to consist of the same number of default partial areas AR, and the number of default partial area ARs constituting one partial area to be read is read out. It may be different from the number of default partial area ARs constituting another one partial area.

In the present embodiment, even when the partial area to be read is set as shown in FIG. 9 in the partial area photographing mode, for example, as in the case where the partial area to be read is set as shown in FIG. Read control is performed as shown.

FIG. 11 is a diagram schematically showing still another setting example of the read partial region in the image pickup region 21 of the solid-state image sensor 4 in the partial region shooting mode, and corresponds to FIG. FIG. 12 shows a selection control signal φASEL that realizes the setting example shown in FIG. 11 in the solid-state image sensor 4 in FIG. 1, and corresponds to FIG. 7.

In FIG. 11, the default partial areas AR (3,1), AR (1,1), AR (2,3), and AR (1,4) set as the four partial areas to be read are hatched. ing. In the setting example shown in FIG. 6 and the setting example shown in FIG. 9, two or more default partial area ARs are not set as read areas in any of the columns of the default partial area AR, whereas the setting example shown in FIG. 11 shows. In the setting example, in the first column of the default partial area AR, two default partial areas AR (3, 1) and AR (1, 1) are set as the partial areas to be read.

Therefore, in the present embodiment, even when the partial area to be read is set as shown in FIG. 11 in the partial area photographing mode, if the read control is performed as shown in FIG. 8, two or more. The output signal of the pixel PX is simultaneously read out to the same vertical signal line 27, and both signals interfere with each other, so that the output signal of the pixel PX cannot be properly read out. Specifically, in the period T1 in FIG. 8, the output signal of the pixel PX in the first to third columns in the first row and the output signal of the pixel PX in the first to third columns in the seventh row are At the same time, they are read out to the same vertical signal line 27, and both signals interfere with each other. In the period T2 in FIG. 8, the output signal of the pixels PX in the first to third columns in the second row and the eighth row. The output signals of the pixels PX in the first to third columns in the above are simultaneously read out to the same vertical signal line 27, and both signals interfere with each other. The output signal of the pixel PX in the third column to the third column and the output signal of the pixel PX in the first to third columns in the ninth row are simultaneously read out to the same vertical signal line 27, and both signals interfere with each other. It ends up.

Therefore, in the present embodiment, in the partial area photographing mode, when it is allowed to set the reading partial area as shown in FIG. 11, the vertical scanning circuit 22 replaces the reading control shown in FIG. For example, the read control shown in FIG. 13 may be performed. FIG. 13 is a timing chart showing another example of readout control in the partial region imaging mode of the solid-state image sensor 4 in FIG. 1, and corresponds to FIG. 8.

In the example shown in FIG. 13, the vertical scanning circuit 22 needs to prevent the output signals of the two or more pixel PXs from being simultaneously read out to the same vertical signal line 27 depending on the setting of the partial region shown in FIG. 11 to be read out. As a condition, read control is performed so that read control is performed simultaneously for as many pixel rows as possible.

Specifically, in the example shown in FIG. 13, the vertical scanning circuit 22 simultaneously performs read-out control for the first row and the fourth row of the pixel PX in the imaging region 21 in the period T1, and the next period. In T2, read control is performed simultaneously for the rows of the pixel PX in the second and fifth rows in the imaging region 21, and in the next period T3, the rows of the pixel PX in the third and sixth rows in the imaging region 21 are performed. At the same time, read control is performed for the row of the pixel PX in the 7th row in the imaging region 21 in the next period T4, and in the next period T5, the pixel in the 8th row in the imaging region 21 is performed. Read control is performed for the row of PX, and in the next period T6, read control is performed for the row of pixel PX in the ninth row in the imaging region 21, whereby reading for one frame is completed. By sequentially repeating the periods T1 to T6, a plurality of frames are read out by the rolling electronic shutter.

In the present embodiment, the area setting circuit 23 simultaneously sets two or more default partial area ARs as read areas in any column of the default partial area AR when setting the partial area to be read in the partial area shooting mode. The reading area may be arbitrarily set under the constraint that the reading area is not set, and the vertical scanning circuit 22 may be configured to always perform the reading control shown in FIG. 8 in the partial area photographing mode. In the following description, such a configuration is referred to as a "restricted partial area setting configuration". In this case, the area setting as shown in FIG. 6 and the area setting as shown in FIG. 9 are permitted, but the area setting as shown in FIG. 11 is not permitted. Such a vertical scanning circuit 22 can be configured by using, for example, a vertical shift register, a switch, or the like, or can be configured by using a decoder circuit using a memory or the like.

Alternatively, in the present embodiment, the area setting circuit 23 allows the area to be read to be arbitrarily set without any restriction when setting the partial area to be read in the partial area photographing mode, and the vertical scanning circuit 22 is used. In the partial area shooting mode, as many pixel rows as possible are required that the output signals of two or more pixel PXs are not simultaneously read out to the same vertical signal line 27 depending on the setting of the partial area. It may be configured to perform read control so that read control is performed at the same time. In the following description, such a configuration is referred to as "configuration of unconstrained partial area setting". In this case, not only the area setting as shown in FIG. 6 and the area setting as shown in FIG. 9 but also the area setting as shown in FIG. 11 is permitted. The vertical scanning circuit 22 performs read control as shown in FIG. 8 in the case of the area setting as shown in FIG. 6 or the area setting as shown in FIG. 9, and in the case of the area setting as shown in FIG. Performs read control as shown in FIG. 13, for example. Such a vertical scanning circuit 22 can be configured by using, for example, a decoder circuit using a memory or the like so as to realize the required row selection each time.

As can be seen from the above description, in the present embodiment, the region setting circuit 23 constitutes a region setting unit that selects the selection transistor ASEL of the pixel PX of a plurality of desired partial regions in the imaging region 21. There is. Further, in the present embodiment, the vertical scanning circuit 22 sets the selection transistor SEL of the pixel PX in each row of the plurality of partial regions in the selected state, and the selection transistor SEL is in the selected state with respect to the pixel PX in the row. It constitutes a control unit that performs read control.

Then, the vertical scanning circuit 22 performs the read control shown in FIG. 8 in the case of the area setting as shown in FIG. 6 or the area setting as shown in FIG. 9, or in the case of the area setting as shown in FIG. When the read control shown in FIG. 11 is performed, the selection transistor SEL of the pixel PX in one row of at least one subregion of the plurality of subregions (plural subregions set as the read region) and the selection transistor SEL. , While simultaneously selecting the selection transistor SEL of the pixel PX of one row different from the one row of the other at least one subregion of the plurality of subregions, with respect to the pixel PX of these rows. Read control will be performed. Here, any vertical signal line 27 that receives the output signal of the pixel PX of the at least one partial region is different from any vertical signal line 27 that receives the output signal of the pixel PX of the other at least one partial region.

Further, the vertical scanning circuit 22 sets the plurality of partial areas (set as a read area) when the read control shown in FIG. 8 is performed in the case of the area setting as shown in FIG. 6 or the area setting as shown in FIG. Read control is performed for the pixel PX of these rows while simultaneously selecting the selection transistor SEL of the pixel PX of one row of each partial region of each subregion), and this control is performed in the plurality of partial regions. It will be repeated sequentially for the pixels in the remaining rows of each subregion of. Here, the number of rows of the pixels PX in the plurality of partial regions is the same as each other. Further, any row of the pixel PX of at least one partial region in the plurality of partial regions is different from any row of the pixel PX of the other at least one partial region in the plurality of partial regions. Further, any vertical signal line 27 that receives the output signal of the pixel PX of each partial region of the plurality of partial regions receives the output signal of the pixel PX of the partial region other than the partial region of the plurality of partial regions. It is different from any vertical signal line 27.

FIG. 14 is a timing chart showing an example of readout control in the full-area image pickup mode of the solid-state image sensor 4 in FIG. 1, and corresponds to FIGS. 8 and 13. The all-region shooting mode is an operation mode for reading out the output signal of the pixel PX in the entire region of the imaging region 21 of the solid-state image sensor 4.

In the full area shooting mode, any selection control signal φASEL supplied to the gate of the selection transistor ASEL of all the default partial areas AR is maintained at the high level (H). As a result, the selection transistor ASEL in the entire region (all default partial regions AR) of the imaging region 21 is kept on.

In the present embodiment, in the full area photographing mode, for example, read control is performed as shown in FIG. In the example shown in FIG. 14, the vertical scanning circuit 22 sequentially reads out one row at a time from the row of the pixel PX in the first row to the row of the pixel PX in the ninth row in the imaging region 21 in each period of the periods T1 to T9. Control is performed, and this completes reading for one frame. In the full area shooting mode during still image shooting, exposure is performed by a mechanical shutter (not shown) after a so-called global reset that simultaneously resets all pixels PX, and then periods T1 to T9 are performed once. In the full area shooting mode at the time of moving image shooting, the periods T1 to T9 are sequentially repeated, and a plurality of frames are read out by the rolling electronic shutter.

In the present embodiment, since each pixel PX of the solid-state image sensor 4 has the selection transistor ASEL in addition to the selection transistor SEL, for example, FIGS. 6, 9, and 11 show the regions to be read out in the partial region photographing mode. When a plurality of partial regions are set as shown, the read control can be performed as shown in FIGS. 8 and 13, and the pixels PX of a plurality of different rows can be read out at the same time. Therefore, according to the present embodiment, the time required to read the image signal for one frame can be shortened, and a desired plurality of partial regions can be read out at high speed. Specifically, in order to read the image signal for one frame, the periods T1 to T9 are required in the full area shooting mode as shown in FIG. 14, whereas in the partial area shooting mode, the case shown in FIG. 8 is required. Requires only periods T1 to T3 and, in the case shown in FIG. 13, only periods T1 to T6.

Since the image pickup apparatus disclosed in Patent Document 1 cannot simultaneously read out a plurality of pixels PX in different rows, when a plurality of partial areas are set as read-out areas in the partial area shooting mode, one frame is required. It takes a long time to read out the image signal of the above as compared with the present embodiment. For example, in the image pickup apparatus disclosed in Patent Document 1, when a plurality of partial regions are set as reading regions in the partial region shooting mode, for example, as shown in FIGS. 6 and 11, after all, in the full region shooting mode, It is inevitable to perform the same read control as the read control shown in FIG. 14, and it takes a long time to read the image signal for one frame.

When the user commands the first partial region photographing mode via the operation unit 14, the electronic camera 1 according to the present embodiment performs the operation shown in FIG. FIG. 15 is a schematic flowchart showing an example of the operation of the electronic camera 1 shown in FIG. 1 in the first partial region photographing mode.

When the operation unit 14 commands the first partial region shooting mode, the CPU 9 first realizes automatic exposure control (AE) and automatic focus control (AF) (step S1). In the AE in step S1, for example, the CPU 9 calculates the optimum exposure amount based on the photometric signal from the photometric sensor for automatic exposure (not shown) provided separately from the solid-state image sensor 4, and the aperture of the photographing lens 2 is set. Is realized by controlling the lens control unit 3 so that the aperture is set according to the exposure amount. Further, in the AF in step S1, for example, the CPU 9 calculates the defocus amount based on the signal from the focus detection sensor (not shown) provided separately from the solid-state image sensor 4, and responds to the defocus amount. This is realized by the lens control unit 3 driving the focus of the photographing lens 2 to bring the photographing lens 2 into focus. The output signal of the pixel PX of the solid-state image sensor 4 may be read out and the signal may be used as a photometric signal for automatic exposure. Further, the solid-state image sensor 4 may be configured to obtain a focus detection signal, and AF may be realized by using the signal.

Instead of performing AE and AF in step S1 or step S6 described later, the aperture, focusing, and the like may be manually set by the user in advance.

Next, the CPU 9 controls the region setting circuit 23 via the image pickup control unit 5 to send all the selection control signals φASEL supplied from the region setting circuit 23 to the gates of the selection transistors ASEL of all the default partial region ARs. The level is set to a high level, and the entire area of the image pickup area 21 is set as a read area (step S2).

In this state, the CPU 9 controls the vertical scanning circuit 22 and the like via the image pickup control unit 5 to realize the read control in the full area shooting mode shown in FIG. 14, and obtains the image data of the entire area for one frame. Obtained and temporarily stored in the memory 7 (step S3). Here, prior to the period T1 in FIG. 14, after a so-called global reset in which all pixels PX are reset at the same time, exposure is performed with a mechanical shutter (not shown).

Next, the CPU 9 causes the display unit 10 to display the image obtained in step S3 (step S4), and prompts the user to specify a desired partial area to be photographed. It should be noted that the CPU 9 accepts only the allowable area designation when the configuration of the restricted partial area setting is adopted, and has no restriction when the configuration of the unconstrained partial area setting is adopted. Accepts area designation. While the user looks at the displayed image, the operation unit 14 makes an input to specify the partial area desired by the user, and when the CPU 9 accepts the input, the CPU 9 controls the area setting circuit 23 via the image pickup control unit 5. Then, the selection control signal φASEL supplied to the gate of the selection transistor ASEL of the default partial region AR corresponding to the one or more partial regions according to the designation is selectively set to a high level, and one or a plurality of default partial regions are selected. AR is selectively set as a read area (step S5). In the present embodiment, these functions of the CPU 9, the display unit 10, and the operation unit 14 construct a user interface for instructing a desired one or a plurality of subregions in the imaging region 21.

Subsequently, the CPU 9 causes AE and AF to be performed in the same manner as in step S1 (step S6). However, in step S6, unlike step S1, exposure and focusing are optimized for the partial region set in step S5.

Next, the CPU 9 controls the vertical scanning circuit 22 and the like via the image pickup control unit 5 to realize the read control in the partial area shooting mode described above, obtains the image data of the partial area for one frame, and stores the memory. It is temporarily stored in 7, and the recording unit 11 records this image on the recording medium 11a as a moving image of a partial region (step S7). The rolling electronic shutter is realized by repeating step S7 by the operation shown in FIG.

After that, the CPU 9 determines whether or not a command to end partial area moving image shooting has been obtained from the operation unit 14 (step S8), and returns to step S7 if there is no such command, while the first portion if there is such a command. Ends a series of operations in the area shooting mode.

In this first partial region photographing mode, it is possible to acquire a moving image of one or a plurality of desired partial regions arbitrarily set by the user in this way. Further, according to the present embodiment, as described above, the time required to read the image signal for one frame of the desired plurality of partial regions can be shortened, and the desired plurality of partial regions can be read out at high speed. Therefore, it is possible to acquire a moving image of a plurality of desired partial regions arbitrarily set by the user at a high frame rate.

Therefore, in this first partial region photographing mode, the user specifies a desired plurality of partial regions including each of a plurality of arbitrary objects of interest, so that changes in the plurality of objects of interest in the field of view (for example, a shape or a shape) can be obtained. It is possible to acquire a moving image that captures the process of changes in size, orientation, color, etc. in detail, and the moving image allows observation without overlooking changes in a plurality of objects of interest in the field of view. For example, in the case where the electronic camera 1 according to the present embodiment is an imaging device incorporated in a microscope and captures a microscope image, a process of change of a plurality of cells (for example, when a petri dish in which cells are cultured is used as a visual field). , The state of cell division, the state of beating of cardiomyocytes, etc.) can be acquired in detail.

When the user commands the second partial region photographing mode via the operation unit 14, the electronic camera 1 according to the present embodiment performs the operation shown in FIG. FIG. 16 is a schematic flowchart showing an example of the operation of the electronic camera 1 shown in FIG. 1 in the second partial region photographing mode. The first partial area shooting mode is a mode in which the partial area is fixed to the area specified by the user, whereas in the second partial area shooting mode, the partial area to be shot is moved to the target of interest. This mode automatically follows.

When the operation unit 14 commands the second partial region photographing mode, the CPU 9 performs the same steps S11 to S13 as steps S1 to S3 in FIG. 15, respectively.

Next, the CPU 9 performs image recognition processing on the image stored in the memory 7 in step S13 by a known image recognition method, and a desired target of interest (for example, a whole body of a person, a face of a person, a moving body, a cell). Etc.) and detect the position, size, etc. on the image (step S14).

Next, the CPU 9 determines whether or not the target of interest has been recognized in step S14 (step S15), and if the target of interest is recognized, the process proceeds to step S16, and if the target of interest is not recognized, the process proceeds to step S27. do. In step S27, the CPU 9 determines whether or not a command to end partial area moving image shooting has been obtained from the operation unit 14, and returns to step S11 if there is no such command, while if there is such a command, the second partial area shooting is performed. Ends a series of operations in the mode.

In step S16, the CPU 9 controls the area setting circuit 23 via the image pickup control unit 5, and selectively sets one or a plurality of default partial areas AR as the read area according to the recognition result in step S14. .. Specifically, the CPU 9 controls the region setting circuit 23 via the image pickup control unit 5 to correspond to one or a plurality of partial regions including each target of interest recognized in step S14 and its surroundings to some extent. The selection control signal φASEL supplied to the gate of the selection transistor ASEL in the default partial region AR is selectively set to a high level.

Subsequently, the CPU 9 causes AE and AF to be performed in the same manner as in step S11 (step S17). However, unlike step S11, step S17 is performed so that the exposure and focusing are optimized for the partial region set in step S16.

After that, the CPU 9 resets the count value q to zero (step S18). This count value q indicates the number of frames taken after the partial area is set to the latest.

Next, the CPU 9 controls the vertical scanning circuit 22 and the like via the image pickup control unit 5 to realize the read control in the partial area shooting mode described above, obtains the image data of the partial area for one frame, and stores the memory. It is temporarily stored in 7, and the recording unit 11 records this image on the recording medium 11a as a moving image of a partial region currently set (step S19). The rolling electronic shutter is realized by repeating step S19 by the operation shown in FIG.

Next, the CPU 9 increments the count value q by 1 (step S20), and then determines whether or not a command to end partial area moving image shooting has been obtained from the operation unit 14 (step S21). If there is no such command, the CPU 9 steps. Transition to S22 On the other hand, if there is a command, the series of operations of the second partial area shooting mode is terminated.

In step S22, the CPU 9 determines whether or not the current count value q is equal to or greater than the value Q, and if q ≧ Q, the process returns to step S19, while if q ≧ Q, the process proceeds to step S23. This value Q is a value of 1 or more arbitrarily set by the user via the operation unit 14 before the start of the second partial region photographing mode. The value Q is a value that determines the timing of resetting the partial area. As can be seen from the following explanation, when the number of frames shot in the once set partial area reaches the value Q, the partial area is reset. When the moving speed of the target of interest is high, the value Q is set to a relatively small value in order to improve the followability to the target of interest, and when the moving speed of the target of interest is low, the time of steps S23, S26, etc. is reduced. The value Q is set to a relatively large value in order to increase the overall frame rate.

In step S23, an image recognition process is performed on the image of each partial region of the frame most recently stored in the memory 7 by a known image recognition method in step S19, a desired target of interest is recognized, and a position on the image or a position on the image is obtained. Detect the size etc.

Subsequently, the CPU 9 determines whether or not the target of interest has been recognized by step S23 (step S24), and if the target of interest is recognized, the process proceeds to step S25, while if the target of interest is not recognized, the process proceeds to step S27. Transition.

In step S25, the CPU 9 controls the area setting circuit 23 via the image pickup control unit 5, and selectively sets one or a plurality of default partial areas AR as the read area according to the recognition result of step S23. ..

After that, the CPU 9 performs AE and AF in the same manner as in step S17 (step S26), and then returns to step S18. However, unlike step S17, step S26 is performed so that the exposure and focusing are optimized for the partial region most recently set in step S25.

In this second partial region shooting mode, it is possible to acquire moving images of a plurality of partial regions set by automatically following the movement of the target of interest in this way. Further, according to the present embodiment, as described above, the time required to read the image signal for one frame of the desired plurality of partial regions can be shortened, and the desired plurality of partial regions can be read out at high speed. Therefore, it is possible to acquire a moving image of a partial region set by automatically following the movement of the target of interest at a high frame rate, and the time required for AF or the like even if the moving speed of the target of interest is high. Since it is possible to secure a moving image in a focused state, it is possible to obtain a moving image in a focused state and the followability is improved.

Therefore, this second partial region photographing mode is effective, for example, when it is used as a surveillance camera in which the target of interest is the whole body or face of a person. If the process of changes in the whole body or face of multiple people can be photographed in detail, it is possible to know in detail the process of changes in posture, facial expressions, and lip movements of multiple people, and advanced information can be obtained from the monitored object. Obtainable. For example, you can know the details of the fighting of multiple people, or you can use lip reading to know the content of conversations between multiple people.

Further, the second partial region photographing mode is also effective, for example, when the electronic camera 1 according to the present embodiment is incorporated in a microscope and is an imaging device for capturing a microscope image. When observing cells, microorganisms, etc. as the object of interest, even if the moving speed is extremely slow, if the object of interest can move, a long time has elapsed in the first partial region photographing mode. Later, there is a possibility that the target of interest will be out of the partial area set by the user. On the other hand, the second partial area shooting mode is such a target of interest because it can acquire moving images of a plurality of partial regions set by automatically following the movement of the target of interest. However, it is possible to take an image at a high frame rate for a long time.

In the electronic camera 1 according to the present embodiment, when the user commands the still image shooting mode via the operation unit 14, the still image shooting operation similar to that of a normal electronic camera is performed, and the user controls the operation unit 14. When the whole area shooting mode at the time of moving image shooting is instructed via, the operation is performed, but the description thereof is omitted here.

[Second Embodiment]

FIG. 17 is a circuit diagram showing a schematic configuration of a solid-state image sensor 41 used in an electronic camera according to a second embodiment of the present invention, and corresponds to FIG. 2. FIG. 18 is a circuit diagram showing a default partial region AR forming a part of the imaging region 21 of the solid-state imaging device 41 shown in FIG. 17, and corresponds to FIG. 4. FIG. 19 is a circuit diagram showing an abstraction of the circuit shown in FIG. 18, and corresponds to FIG. FIG. 20 is a diagram showing a power supply voltage signal φ VDD that realizes the same settings as the setting example shown in FIG. 6 in the solid-state image sensor 41 shown in FIG. 17, and corresponds to FIG. 7.

In FIGS. 17 to 19, the same or corresponding elements as the elements in FIGS. 2, 4 and 5 are designated by the same reference numerals, and the overlapping description thereof will be omitted. The difference between the present embodiment and the first embodiment is described below.

In the present embodiment, in the electronic camera 1 according to the first embodiment, the solid-state image sensor 41 is used instead of the solid-state image sensor 4.

In the first embodiment, the selection transistor ASEL is provided in each pixel PX of the imaging region 21, whereas in the present embodiment, the selection transistor ASEL and the control line 33 are provided in each pixel PX of the imaging region 21. Is removed, and the source of the selection transistor SEL is connected to the vertical signal line 27 corresponding to the pixel PX.

In the first embodiment, the drain of the amplification transistor AMP of all pixels PX (point b in FIG. 4) is commonly connected by the feeder line 34, and is amplified as the power supply voltage of the amplification transistor AMP. The active voltage level VDD, which is effective for the operation of the transistor AMP, is fixedly supplied. On the other hand, in the present embodiment, the feeder line 34 is electrically separated for each predetermined partial region AR, and the drain of the amplification transistor AMP of each pixel PX (point b in FIG. 18) is the default partial region AR. Each is connected in common by a feeder line 34, and a power supply voltage signal φ VDD is supplied from the area setting circuit 23 as a power supply voltage of the amplification transistor AMP. The drain of the reset transistor RST of each pixel PX is connected to the drain of the amplification transistor AMP of the pixel PX (point b in FIG. 18) by the feeder line 34.

FIG. 19 is an abstraction of the circuit shown in FIG. 18 by focusing on the connection relationship of the drain (point b) of the amplification transistor AMP of each predetermined partial region AR by the feeder line 34. When each power supply voltage signal φ VDD is distinguished for each default partial region AR, the power supply voltage signal φ VDD supplied to the drain of the amplification transistor AMP of the pixel PX of the default partial region AR (j, k) in the jth row and the kth column. Is indicated by the reference numeral φ VDD (j, k). The actual arrangement of the feeder lines 34 (routes to be routed, etc.) is not limited at all.

In the present embodiment, the area setting circuit 23 is configured as a power supply control circuit that outputs each power supply voltage signal φ VDD instead of each control signal φASEL under the control of the image pickup control unit 5. Each power supply voltage signal φ VDD is an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or a non-effective voltage level that is not effective for the operation of the amplification transistor AMP (here, 0V, but is not necessarily limited to 0V). ), And the area setting circuit 23 selectively supplies VDD or 0V as the power supply voltage of the amplifier transistor AMP of each pixel PX.

In the present embodiment, the state in which the power supply voltage signal φ VDD becomes VDD and the amplification transistor AMP operates effectively in each pixel PX and the state in which the power supply voltage signal φ VDD becomes 0V and the amplification transistor AMP does not operate effectively are each. Regarding whether or not the output signal of the pixel PX can be output to the vertical signal line 27, in the first embodiment, the control signal φASEL is at a high level in each pixel PX and the selection transistor ASEL is turned on and the control signal φASEL. Is substantially the same as the state in which the selection transistor ASEL is turned off at the low level.

Therefore, in the present embodiment, the output signal of each pixel PX is a power supply voltage signal supplied as the power supply voltage of the amplification transistor AMP of the pixel PX while the selection transistor SEL of the pixel PX is in the selected state (on state). Only when φ VDD is the effective voltage level VDD, it is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixels PX arranged in the column direction with respect to the pixel PX.

In the present embodiment, the area setting circuit 23 supplies the effective voltage level VDD as each power supply voltage signal φ VDD instead of supplying the high level signal as each φASEL in the first embodiment, and the first embodiment is described. By supplying 0V as each power supply voltage signal φ VDD instead of supplying the low level signal as each φASEL in the above embodiment, the same operation as that of the first embodiment is realized. For example, in the present embodiment, when the same setting as the area setting example shown in FIG. 6 is realized, the area setting circuit 23 may output each power supply voltage signal φ VDD shown in FIG. 20.

The present embodiment also has the same advantages as the first embodiment. Further, in the present embodiment, since the selection transistor ASEL is not provided in each pixel PX, the configuration of each pixel PX is simplified.

[Third Embodiment]

FIG. 21 is a circuit diagram showing a schematic configuration of a solid-state image sensor 51 used in an electronic camera according to a third embodiment of the present invention, and corresponds to FIG. 2. FIG. 22 is a circuit diagram showing a default partial region AR forming a part of the imaging region 21 of the solid-state imaging device 51 shown in FIG. 21, and corresponds to FIG. FIG. 23 is a timing chart showing an example of readout control in the partial region photographing mode of the solid-state image sensor 51 shown in FIG. 21, and corresponds to FIG. 8.

In FIGS. 21 to 23, the same or corresponding elements as the elements in FIGS. 2, 4 and 8 are designated by the same reference numerals, and the overlapping description thereof will be omitted. The difference between the present embodiment and the first embodiment is described below.

In the present embodiment, in the electronic camera 1 according to the first embodiment, the solid-state image sensor 51 is used instead of the solid-state image sensor 4.

In the first embodiment, the selection transistor SEL is provided in each pixel PX of the imaging region 21, whereas in the present embodiment, the selection transistor SEL and the connecting line 26 are provided in each pixel PX of the imaging region 21. Is removed, and the drain of the selection transistor ASEL is connected to the source of the amplification transistor AMP of the pixel PX.

In the first embodiment, the drain of the amplification transistor AMP of all pixels PX (point b in FIG. 4) is commonly connected by the feeder line 34, and is amplified as the power supply voltage of the amplification transistor AMP. The active voltage level VDD, which is effective for the operation of the transistor AMP, is fixedly supplied. On the other hand, in the present embodiment, the feeding line 34 is electrically separated for each row of the pixel PX, and the drain of the amplification transistor AMP of each pixel PX (point b in FIG. 22) is for each row of the pixel PX. The power supply line 34 is commonly connected to the power supply line 34, and a power supply voltage signal φ VDD is supplied from the power supply control circuit 52 as the power supply voltage of the amplification transistor AMP. When each power supply voltage signal φ VDD is distinguished for each row of the pixel PX, the power supply voltage signal φ VDD supplied to the drain of the amplification transistor AMP of the pixel PX in the nth row is indicated by the reference numeral φ VDD (n). The drain of the reset transistor RST of each pixel PX is connected to the drain of the amplification transistor AMP of the pixel PX (point b in FIG. 22) by the feeder line 34.

In the present embodiment, the power supply control circuit 52 is provided as a part of the vertical scanning circuit 22, and outputs each power supply voltage signal φ VDD instead of each control signal φSEL under the control of the image pickup control unit 5. Each power supply voltage signal φ VDD is an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or a non-effective voltage level that is not effective for the operation of the amplification transistor AMP (here, 0V, but is not necessarily limited to 0V). The power supply control circuit 52 selectively supplies VDD or 0V as the power supply voltage of the amplifier transistor AMP of each pixel PX.

In the present embodiment, the state in which the power supply voltage signal φ VDD becomes VDD and the amplification transistor AMP operates effectively in each pixel PX and the state in which the power supply voltage signal φ VDD becomes 0V and the amplification transistor AMP does not operate effectively are each. Regarding whether or not the output signal of the pixel PX can be output to the vertical signal line 27, in the first embodiment, the control signal φSEL is at a high level in each pixel PX and the selection transistor SEL is turned on and the control signal φSEL. Is substantially the same as the state in which the selection transistor SEL is turned off at the low level.

Therefore, in the present embodiment, the output signal of each pixel PX is a power supply voltage signal supplied as a power supply voltage of the amplification transistor AMP of the pixel PX while the selection transistor ASEL of the pixel PX is in the selected state (on state). Only when φ VDD is the effective voltage level VDD, it is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixels PX arranged in the column direction with respect to the pixel PX.

In the present embodiment, the power supply control circuit 52 supplies an effective voltage level VDD as each power supply voltage signal φ VDD instead of supplying a high level signal as each φSEL in the first embodiment, and the first embodiment is described. By supplying 0V as each power supply voltage signal φ VDD instead of supplying the low level signal as each φSEL in the above embodiment, the same operation as that of the first embodiment is realized. For example, in the present embodiment, when the partial area to be read is set as shown in FIG. 6 in the partial area photographing mode, the vertical scanning circuit 22 may perform read control as shown in FIG. 23.

The present embodiment also has the same advantages as the first embodiment. Further, in the present embodiment, since the selection transistor SEL is not provided in each pixel PX, the configuration of each pixel PX is simplified.

[Fourth Embodiment]

FIG. 24 is a circuit diagram showing a schematic configuration of the solid-state image sensor 61 used in the electronic camera according to the fourth embodiment of the present invention, and corresponds to FIG. 2. FIG. 25 is a circuit diagram showing a default partial region AR forming a part of the imaging region 21 of the solid-state imaging device 61 shown in FIG. 24, and corresponds to FIG. FIG. 26 is a circuit diagram showing an abstraction of the circuit shown in FIG. 25, and corresponds to FIG. FIG. 27 is a timing chart showing an example of readout control in the partial region photographing mode of the solid-state image sensor 61 shown in FIG. 24, and corresponds to FIG. 8. In FIGS. 24 to 27, the same or corresponding elements as those in FIGS. 2, 4, 5 and 8 are designated by the same reference numerals, and the overlapping description thereof will be omitted.

In the present embodiment, in the electronic camera 1 according to the first embodiment, the solid-state image sensor 61 is used instead of the solid-state image sensor 4.

The difference between the present embodiment and the first embodiment is that for each of the two pixels PX adjacent to each other in the column direction, the two pixels PX are a set of a floating capacitance portion FD, an amplification transistor AMP, and a reset transistor RST. And the point that the selection transistors SEL and ASEL are shared, and the vertical scanning circuit 22 replaces the control signals φSEL, φRST and φTX as shown in FIG. 8, and the control signals φSEL, φRST and φTXA as shown in FIG. 27. , ΦTXB is configured to be output.

In FIGS. 24 to 26, two pixels PX sharing a set of a floating capacitance portion FD, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL and ASEL are shown as a pixel block BL. Further, in FIGS. 24 and 25, the photodiode PD and the transfer transistor TX of the lower pixel PX in the pixel block BL are indicated by the symbols PDA and TXA, respectively, and the photodiode PD and the photodiode PD of the upper pixel PX in the pixel block BL are shown. The transfer transistor TX is indicated by the reference numerals PDB and TXB, respectively, and both are distinguished. Further, the control signal supplied to the gate of the transfer transistor TXA is defined as φTXA, and the control signal supplied to the gate electrode of the transfer transistor TXB is defined as φTXB to distinguish between the two.

In FIGS. 2 and 4, N, n and the like indicate a pixel row, but in FIGS. 24 and 25, N, n and the like indicate a row of the pixel block BL. One line of the pixel block BL corresponds to two lines of the pixel PX. In FIGS. 4 and 5, each default subregion AR consists of A × B pixels PX in rows A and B, whereas in FIGS. 25 and 26, each default subregion AR is A × B in rows A and B. It is composed of pixel block BL (2 × A × B pixels PX). The number of rows of the photodiode PD constituting each predetermined partial region AR may be 2 or more, and the number of columns of the photodiode PD may be 1 or more. In the present embodiment, one pixel block BL is two photos. Since the diode PD is provided, the number of rows of the pixel block BL constituting each predetermined partial region AR may be 1 or more, and the number of columns of the pixel block BL may be 1 or more.

In the present embodiment, when the partial area to be read is set as shown in FIGS. 6 and 9 in the partial area photographing mode, for example, the read control shown in FIG. 27 is replaced with the read control shown in FIG. Is done. Here, n in FIGS. 6 and 9 indicates a row of the pixel block BL, and m in FIGS. 6 and 9 indicates a column of the pixel block BL.

In the example shown in FIG. 27, the vertical scanning circuit 22 causes the first row, the fourth row, and the seventh row in the imaging region 21 corresponding to the row of the pixel block BL in the first row in each predetermined partial region AR in the period T1. Read control is performed simultaneously for the row of the pixel block BL of the above, and in the next period T2, the second row and the fifth row in the imaging region 21 corresponding to the row of the second row of the pixel block BL in each predetermined partial area AR. And the row of the pixel block BL in the 8th row is read-controlled at the same time, and in the next period T3, the third row in the imaging region 21 corresponding to the row of the pixel block BL in the third row in each predetermined partial region AR. , The 6th row and the 9th row of the pixel block BL are simultaneously read and controlled, so that the reading for one frame is completed. By sequentially repeating the periods T1 to T3, a plurality of frames are read out by the rolling electronic shutter.

In the present embodiment, in the partial region photographing mode, when it is also allowed that the partial region to be read is set as shown in FIG. 11, the vertical scanning circuit 22 replaces the read control shown in FIG. 27, for example. , The read control shown in FIG. 8 may be modified to the read control shown in FIG. 27, and the read control shown in FIG. 13 may be modified to perform the read control. Here, n in FIG. 11 indicates the row of the pixel block BL, and m in FIG. 11 indicates the column of the pixel block BL.

In this example, the vertical scanning circuit 22 requires that the output signals of the two or more pixels PX are not simultaneously read out to the same vertical signal line 27 depending on the setting of the partial region shown in FIG. 11 to be read out. Read control is performed so that read control is performed simultaneously for as many rows of the pixel block BL as possible.

In the present embodiment, the area setting circuit 23 simultaneously sets two or more default partial area ARs as read areas in any column of the default partial area AR when setting the partial area to be read in the partial area shooting mode. The reading area may be arbitrarily set under the constraint that the reading area is not set, and the vertical scanning circuit 22 may be configured to always perform the reading control shown in FIG. 27 in the partial area photographing mode. In the following description, such a configuration is referred to as a "restricted partial area setting configuration". In this case, the area setting as shown in FIG. 6 and the area setting as shown in FIG. 9 are permitted, but the area setting as shown in FIG. 11 is not permitted.

Alternatively, in the present embodiment, the area setting circuit 23 allows the area to be read to be arbitrarily set without any restriction when setting the partial area to be read in the partial area photographing mode, and the vertical scanning circuit 22 is used. In the partial area shooting mode, as many pixel blocks as possible BL are required that the output signals of two or more pixel PXs are not simultaneously read out to the same vertical signal line 27 depending on the setting of the partial area. It may be configured to perform read control so that read control is performed simultaneously for the rows of. In the following description, such a configuration is referred to as "configuration of unconstrained partial area setting". In this case, not only the area setting as shown in FIG. 6 and the area setting as shown in FIG. 9 but also the area setting as shown in FIG. 11 is permitted. The vertical scanning circuit 22 performs read control as shown in FIG. 27 in the case of the area setting as shown in FIG. 6 or the area setting as shown in FIG. 9, and in the case of the area setting as shown in FIG. For example, read control is performed by transforming the read control shown in FIG. 13 in the same manner as the read control shown in FIG. 8 is transformed into the read control shown in FIG. 27.

In the present embodiment, in the full area photographing mode, for example, the read control obtained by changing the read control shown in FIG. 14 is performed in the same manner as the read control shown in FIG. 8 is changed to the read control shown in FIG. 27. In this example, the vertical scanning circuit 22 sequentially performs read-out control for each row from the row of the pixel block BL in the first row to the row of the pixel block BL in the ninth row in the imaging region 21, for one frame. Is finished reading. In the full area shooting mode when shooting a still image, exposure is performed by a mechanical shutter (not shown) after a so-called global reset that resets all pixels PX at the same time, and then the pixel blocks of each row from the first row to the ninth row. The BL is read out. In the full area shooting mode at the time of moving image shooting, the reading of the pixel block BL of each line from the first line to the ninth line is sequentially repeated, and a plurality of frames are read out by the rolling electronic shutter.

The present embodiment also has the same advantages as the first embodiment. In the present embodiment, for each of the two pixels PX adjacent to each other in the column direction, the two pixels PX share a set of a floating capacitance portion FD, an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL, ASEL. However, in the present invention, for example, for each of three or more predetermined number of pixels PX adjacent to each other in the column direction, the predetermined number of pixels PX is a set of a floating capacitance unit FD, an amplification transistor AMP, a reset transistor RST, and the like. The selection transistors SEL and ASEL may be shared. Further, in the present invention, the same modification as the modification of the first embodiment to the present embodiment may be applied to the second and third embodiments.

[Fifth Embodiment]

FIG. 28 is a circuit diagram showing a schematic configuration of the solid-state image sensor 71 used in the electronic camera according to the fifth embodiment of the present invention, and corresponds to FIG. 2. FIG. 29 is a circuit diagram showing a part of the image pickup region 21 of the solid-state image pickup device 71 shown in FIG. 28, and corresponds to FIG.

In FIGS. 28 and 29, the same or corresponding elements as the elements in FIGS. 2 and 4 are designated by the same reference numerals, and the overlapping description thereof will be omitted. The difference between the present embodiment and the first embodiment is described below.

In the present embodiment, in the electronic camera 1 according to the first embodiment, the solid-state image sensor 71 is used instead of the solid-state image sensor 4.

In the present embodiment, the imaging region 21 is not divided into each predetermined partial region AR. Further, in the present embodiment, the row write control circuit 72 and the column write control circuit 73 are provided in place of the area setting circuit 23.

Further, in the present embodiment, a capacitor HC and a write transistor WT are added to each pixel PX. The capacitor HC of each pixel PX is connected between the ground and the gate of the selection transistor ASEL of the pixel PX, and holds a selection control signal for setting the selection transistor ASEL of the pixel PX to the selected state or the non-selection state. It constitutes a holding part. The write transistor WT of each pixel PX constitutes a write unit that writes the selection control signal to the capacitor HC as the holding unit of the pixel PX according to the write control signals φWTR and φWTC.

In this embodiment, the write transistor WT is an nMOS transistor. The source of the write transistor WT of each pixel PX is connected to the gate of the selection transistor ASEL of the pixel PX. The gate of the write transistor WT of each pixel PX is commonly connected by a control line 74 for each row of the pixel PX, and a first write control signal φWTR is supplied from the row write control circuit 72 to the gate. The drain of the write transistor WT of each pixel PX is commonly connected to each row of pixels PX, to which a second write control signal φWTC is supplied from the row write control circuit 73. The write transistor WT of each pixel PX takes an AND of a first write control signal φWTR supplied to its gate and a second write control signal φWTC supplied to its drain, and its AND output is used as its source. It constitutes an output and circuit. As the writing unit, for example, another AND circuit may be used instead of the writing transistor WT.

When each first write control signal φWTR is distinguished for each row of the pixel PX, the first write control signal φWTR supplied to the gate of the write transistor WT of the pixel PX in the nth row is indicated by the reference numeral φWTR (n). .. When each second write control signal φWTC is distinguished for each column of the pixel PX, the second write control signal φWTC supplied to the drain of the write transistor WT of the pixel PX in the mth column is indicated by the reference numeral φWTC (m). ..

FIG. 30A shows a write control signal φWTR (n) in the solid-state image sensor 71 shown in FIG. 28 when a high level signal (H signal) is written to the capacitor HC of the pixel PX in the nth row and the mth column. It is a figure which shows φWTC (m). At the time point t21, the write control signal φWTR (n) on the nth row is raised to a high level, at the subsequent time point t22, the write control signal φWTC (m) on the mth column is raised to a high level, and at the subsequent time point t23, writing is performed. The control signal φWTR (n) is lowered to a low level, and the write control signal φWTC is lowered at the subsequent time point t24. As a result, the high level signal is written and held in the capacitor HC of the pixel PX in the nth row and the mth column. As a result, the selection transistor ASEL of the pixel PX in the nth row and the mth column is held in the on state (selection state).

FIG. 30B shows a write control signal φWTR (n) in the solid-state image sensor 71 shown in FIG. 28 when a low level signal (L signal) is written to the capacitor HC of the pixel PX in the nth row and the mth column. It is a figure which shows φWTC (m). While maintaining the write control signal φWTC (m) in the mth column at a low level, the write control signal φWTR (n) in the nth row is raised to a high level at the time point t21, and the write control signal φWTR (n) is raised at the subsequent time point t23. Lower n) to a low level. As a result, the low level signal is written and held in the capacitor HC of the pixel PX in the nth row and the mth column. As a result, the selection transistor ASEL of the pixel PX in the nth row and the mth column is held in the off state (non-selection state).

The row write control circuit 72 supplies a first write control signal φWTR for each row of the pixel PX under the control of the image pickup control unit 5 in FIG. The column write control circuit 73 supplies a second write control signal φWTC for each row of pixels PX under the control of the image pickup control unit 5 in FIG. The row write control circuit 72 and the column write control circuit 73 together constitute a write control unit that supplies write control signals φWTR and φWTC to the write transistor WT as the write unit of each pixel PX.

In the present embodiment, the row write control circuit 72, the column write control circuit 73, and the write transistor WT and the capacitor HC of each pixel PX are, as a whole, one or more desired portions of the image pickup region 21 to be read. It constitutes a region setting unit that sets the selection transistor ASEL of the pixel PX of the region to the selection state (on state).

FIG. 31 is a timing chart showing write control signals φWTR and φWTC that realize the same settings as the region setting example shown in FIG. 6 in the solid-state image sensor 71 shown in FIG. 28. Here, in FIG. 6, it is assumed that each predetermined partial area AR is not divided, but the four hatched partial areas are defined as the four partial areas to be read.

In the example shown in FIG. 31, first, a low level signal is written to the capacitor HC of all the pixels PX, and then the pixel PX of each row is sequentially selected and the high level is applied to the capacitor HC of the required pixel PX in the row. By writing a signal, the four partial areas hatched in FIG. 6 are set as read areas.

Specifically, when the area setting period (the period for setting the area to be read) starts, first, in the period t31-t32, φWTR (1) to φWTR (9) are set to a high level, while φWTC (1). ~ ΦWTC (12) is set to low level. As a result, as can be understood from FIG. 30B, a low level signal is written to the capacitor HC of the all-pixel PX.

Next, in the period t33-t35, φWTR (1) is set to a high level, and in the period t34-t36, φWTC (4) to φWTC (6) and φWTC (10) to φWTC (12) are set to a high level. As a result, as can be understood from FIG. 30A, a high level signal is written to the capacitor HC of the pixel PX in the 4th to 6th columns and the 10th to 12th columns of the pixel PX in the first row.

Then, in the period t36-t38, φWTR (2) is brought to a high level, and in the period t37-t39, φWTC (4) to φWTC (6) and φWTC (10) to φWTC (12) are brought to a high level. As a result, the high level signal is written to the capacitor HC of the pixel PX in the 4th to 6th columns and the 10th to 12th columns of the pixel PX in the second row.

Subsequently, φWTR (3) is set to a high level in the period t39-t41, and φWTC (4) to φWTC (6) and φWTC (10) to φWTC (12) are set to a high level in the period t40-t42. As a result, the high level signal is written to the capacitor HC of the pixel PX in the 4th to 6th columns and the 10th to 12th columns of the pixel PX in the 3rd row.

Then, in the period t42-t44, φWTR (4) is set to a high level, and in the period t43-t45, φWTC (7) to φWTC (9) are set to a high level. As a result, a high level signal is written to the capacitor HC of the pixel PX in the 7th to 9th columns of the pixel PX in the 4th row.

Next, φWTR (5) is set to a high level in the period t45-t47, and φWTC (7) to φWTC (9) are set to a high level in the period t46-t48. As a result, a high level signal is written to the capacitor HC of the pixel PX in the 7th to 9th columns of the pixel PX in the 5th row.

Then, in the period t48-t50, φWTR (6) is made high level, and in the period t49-t51, φWTC (7) to φWTC (9) are made high level. As a result, the high level signal is written to the capacitor HC of the pixel PX in the 7th to 9th columns of the pixel PX in the 6th row.

Subsequently, φWTR (7) is made high level in the period t51-t53, and φWTC (1) to φWTC (3) are made high level in the period t52-t54. As a result, the high level signal is written to the capacitor HC of the pixel PX in the first to third columns of the pixel PX in the seventh row.

After that, φWTR (8) is set to a high level in the period t54-t56, and φWTC (1) to φWTC (3) are set to a high level in the period t55-t57. As a result, the high level signal is written to the capacitor HC of the pixel PX in the first to third columns of the pixel PX in the eighth row.

Finally, in the period t57-t59, φWTR (9) is brought to a high level, and in the period t58-t60, φWTC (1) to φWTC (3) are brought to a high level. As a result, the high level signal is written to the capacitor HC of the pixel PX in the first to third columns of the pixel PX in the ninth row.

In this way, a high level signal is written to the capacitor HC of the pixel PX with the hatch in FIG. 6, the selection transistor ASEL of the pixel PX is maintained in the ON state, and the hatch in FIG. 6 is added. A low-level signal is written to the capacitor HC of the pixel PX that has not been used, the selection transistor ASEL of the pixel PX is maintained in the off state, and the area setting shown in FIG. 6 is realized.

In the present embodiment, for example, as in FIG. 31, first, a low-level signal is written to the capacitor HC of all the pixels PX, and then the pixel PX of each row is sequentially selected, and the desired pixel in the row is selected. By writing a high-level signal to the capacitor HC of the PX, any one or more desired partial regions of the imaging region 21 or the entire region of the imaging region 21 can be set as a region to be read.

If the area setting period is once performed and then the next area setting period is not performed for a long time without changing the area setting, the high level signal written to the capacitor HC will drop. It may not be held properly. Therefore, even when the area setting is not changed, it is preferable to perform the area setting period within a certain period of time after once performing the area setting period to refresh the signal written in the capacitor HC.

The read control is the same as that of the first embodiment in the present embodiment. Further, also in the present embodiment, the same configuration as the configuration of the restricted partial region setting in the first embodiment may be adopted, or the configuration of the unrestricted partial region setting in the first embodiment may be adopted. A configuration similar to the configuration may be adopted.

The present embodiment also has the same advantages as the first embodiment. Further, in the first embodiment, the read area in the imaging area 21 is set depending on whether or not each predetermined partial area AR is included in the read area, whereas in the present embodiment, the read area is set. The area to be read out of the imaging area 21 is set depending on whether or not each pixel PX is included in the image area 21. Therefore, according to the present embodiment, although the write transistor WT and the capacitor HC are required in each pixel PX, the degree of freedom in setting the read area in the image pickup area 21 is increased as compared with the first embodiment. ..

[Sixth Embodiment]

FIG. 32 is a circuit diagram showing a schematic configuration of the solid-state image sensor 81 used in the electronic camera according to the sixth embodiment of the present invention, and corresponds to FIG. 28. FIG. 33 is a circuit diagram showing a part of the image pickup region 21 of the solid-state image pickup device 81 shown in FIG. 32, and corresponds to FIG. 29.

In FIGS. 32 and 33, the same or corresponding elements as the elements in FIGS. 28 and 29 are designated by the same reference numerals, and the overlapping description thereof will be omitted. The difference between the present embodiment and the fifth embodiment is described below.

In the present embodiment, in the electronic camera according to the fifth embodiment, the solid-state image sensor 81 is used instead of the solid-state image sensor 71.

In the fifth embodiment, the selection transistor SEL is provided in each pixel PX of the imaging region 21, whereas in the present embodiment, the selection transistor SEL and the connecting line 26 are provided in each pixel PX of the imaging region 21. Is removed, and the drain of the selection transistor ASEL is connected to the source of the amplification transistor AMP of the pixel PX.

In the fifth embodiment, the drain of the amplification transistor AMP of all pixels PX (point b in FIG. 29) is commonly connected by the feeder line 34, and is amplified as the power supply voltage of the amplification transistor AMP. The active voltage level VDD, which is effective for the operation of the transistor AMP, is fixedly supplied. On the other hand, in the present embodiment, the feeding line 34 is electrically separated for each row of the pixel PX, and the drain of the amplification transistor AMP of each pixel PX (point b in FIG. 33) is for each row of the pixel PX. The power supply line 34 is commonly connected to the power supply line 34, and a power supply voltage signal φ VDD is supplied from the power supply control circuit 52 as the power supply voltage of the amplification transistor AMP. When each power supply voltage signal φ VDD is distinguished for each row of the pixel PX, the power supply voltage signal φ VDD supplied to the drain of the amplification transistor AMP of the pixel PX in the nth row is indicated by the reference numeral φ VDD (n). The drain of the reset transistor RST of each pixel PX is connected to the drain of the amplification transistor AMP of the pixel PX (point b in FIG. 33) by the feeder line 34.

In the present embodiment, the power supply control circuit 52 is provided as a part of the vertical scanning circuit 22, and outputs each power supply voltage signal φ VDD instead of each control signal φSEL under the control of the image pickup control unit 5. Each power supply voltage signal φ VDD is an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or a non-effective voltage level that is not effective for the operation of the amplification transistor AMP (here, 0V, but is not necessarily limited to 0V). The power supply control circuit 52 selectively supplies VDD or 0V as the power supply voltage of the amplifier transistor AMP of each pixel PX.

In the present embodiment, the state in which the power supply voltage signal φ VDD becomes VDD and the amplification transistor AMP operates effectively in each pixel PX and the state in which the power supply voltage signal φ VDD becomes 0V and the amplification transistor AMP does not operate effectively are each. Regarding whether or not the output signal of the pixel PX can be output to the vertical signal line 27, in the fifth embodiment, the control signal φSEL is at a high level in each pixel PX and the selection transistor SEL is turned on and the control signal φSEL. Is substantially the same as the state in which the selection transistor SEL is turned off at the low level.

Therefore, in the present embodiment, the output signal of each pixel PX is a power supply voltage signal supplied as a power supply voltage of the amplification transistor AMP of the pixel PX while the selection transistor ASEL of the pixel PX is in the selected state (on state). Only when φ VDD is the effective voltage level VDD, it is output to the vertical signal line 27 that receives the output signal of the pixel PX and the output signal of the pixels PX arranged in the column direction with respect to the pixel PX.

In the present embodiment, the power supply control circuit 52 supplies an effective voltage level VDD as each power supply voltage signal φ VDD instead of supplying a high level signal as each φSEL in the fifth embodiment, and the fifth embodiment. By supplying 0V as each power supply voltage signal φ VDD instead of supplying the low level signal as each φSEL in the above embodiment, the same operation as that of the fifth embodiment is realized.

The present embodiment also has the same advantages as the fifth embodiment. Further, in the present embodiment, since the selection transistor ASEL is not provided in each pixel PX, the configuration of each pixel PX is simplified.

[7th Embodiment]

FIG. 34 is a circuit diagram showing a schematic configuration of the solid-state image sensor 91 used in the electronic camera according to the seventh embodiment of the present invention, and corresponds to FIG. 28. FIG. 35 is a circuit diagram showing a part of the image pickup region 21 of the solid-state image pickup device 91 shown in FIG. 34, and corresponds to FIG. 29. In FIGS. 34 and 35, the same or corresponding elements as those in FIGS. 28 and 29 are designated by the same reference numerals, and the overlapping description thereof will be omitted.

In the present embodiment, the solid-state image sensor 91 is used instead of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

The difference between the present embodiment and the fifth embodiment is that for each of the two pixels PX adjacent to each other in the column direction, the two pixel PXs are a set of a floating capacitance portion FD, an amplification transistor AMP, and a reset transistor RST. , The selection transistor SEL, ASEL, the writing transistor WT and the capacitor HC are shared, and the vertical scanning circuit 22 replaces the control signals φSEL, φRST, φTX as shown in FIG. 8, as shown in FIG. 27. The point is that the control signals φSEL, φRST, φTXA, and φTXB are output.

In FIGS. 34 and 35, two pixels PX sharing a set of a floating capacitance portion FD, an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, ASEL, a write transistor WT, and a capacitor HC are shown as a pixel block BL. There is. Further, in FIGS. 34 and 35, the photodiode PD and the transfer transistor TX of the lower pixel PX in the pixel block BL are indicated by the symbols PDA and TXA, respectively, and the photodiode PD and the photodiode PD of the upper pixel PX in the pixel block BL are shown. The transfer transistor TX is indicated by the reference numerals PDB and TXB, respectively, and both are distinguished. Further, the control signal supplied to the gate of the transfer transistor TXA is defined as φTXA, and the control signal supplied to the gate electrode of the transfer transistor TXB is defined as φTXB to distinguish between the two.

In FIGS. 28 and 29, N, n and the like indicate a pixel row, but in FIGS. 34 and 35, N, n and the like indicate a row of the pixel block BL. One line of the pixel block BL corresponds to two lines of the pixel PX.

The read control is the same as that of the fourth embodiment in the present embodiment. Further, also in the present embodiment, the same configuration as the configuration of the restricted partial region setting in the fourth embodiment may be adopted, or the configuration of the unrestricted partial region setting in the fourth embodiment may be adopted. A configuration similar to the configuration may be adopted.

The present embodiment also has the same advantages as the fifth embodiment. In this embodiment, for each of the two pixels PX adjacent to each other in the column direction, the two pixels PX are a set of a floating capacitive unit FD, an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, ASEL, and a write transistor. Although the WT and the capacitor HC are shared, in the present invention, for example, for each of three or more predetermined number of pixels PX adjacent to each other in the column direction, the predetermined number of pixels PX is a set of floating capacitance portions FD and amplification. The transistor AMP, the reset transistor RST, the selection transistor SEL, ASEL, the write transistor WT, and the capacitor HC may be shared. Further, in the present invention, the same modification as the modification of the fifth embodiment to the present embodiment may be applied to the sixth embodiment.

[Eighth Embodiment]

FIG. 36 is a circuit diagram showing a schematic configuration of the solid-state image sensor 101 used in the electronic camera according to the eighth embodiment of the present invention, and corresponds to FIG. 28. FIG. 37 is a circuit diagram showing one pixel PX (pixel PX in the nth row and mth column) of the solid-state image sensor 101 shown in FIG. 36, and corresponds to a part of FIG. 29. FIG. 38 is a timing chart showing a write control signal that realizes the same settings as the setting example shown in FIG. 6 in the solid-state image sensor 101 shown in FIG. 36, and corresponds to FIG. 31.

In FIGS. 36 to 38, the same or corresponding elements as those in FIGS. 28, 29 and 31 are designated by the same reference numerals, and the overlapping description thereof will be omitted. The difference between the present embodiment and the fifth embodiment is described below.

In the present embodiment, in the electronic camera according to the fifth embodiment, the solid-state image sensor 101 is used instead of the solid-state image sensor 71.

In the present embodiment, in each pixel PX, the SR latch circuit 103 replaces the capacitor HC as a holding unit for holding the selection control signal for setting the selection transistor ASEL of the pixel PX to the selected state or the non-selected state. It is provided. Further, in the present embodiment, in the solid-state image sensor 101, a reset write control circuit 102 that supplies a reset signal φWTRST that forms a part of the write control signal to the reset input unit R of the SR latch circuit 103 is added. The SR latch circuit 103 can be composed of, for example, a set of NOR gates, but is not limited to this.

The reset input unit R of the SR latch circuit 103 of all pixels PX is commonly connected by the control line 104, and the reset signal φWTRST from the reset write control circuit 102 is supplied to the reset input unit R. The set input unit S of the SR latch circuit 103 of each pixel PX is connected to the source of the write transistor WT of the pixel PX. The output unit Q of the SR latch circuit 103 of each pixel PX is connected to the gate of the selection transistor ASEL of the pixel PX.

As can be seen from the comparison between FIGS. 38 and 31, in the present embodiment, in order to write a low level signal as a signal held at the gate of the selection transistor ASEL of all pixels PX in the period t31-t32, φWTR ( 1) -φWTR (9) is set to a high level, while φWTC (1) to φWTC (12) are set to a low level, and only a high level is supplied to the set input unit S of the SR latch circuit 103 of the all-pixel PX. Instead, the reset signal φWTRST supplied to the reset input unit R of the SR latch circuit 103 of all pixels PX is set to a high level. During the other period, the reset signal φWTRST is maintained at a low level.

In the present embodiment, the row write control circuit 72, the column write control circuit 73, and the reset write control circuit 102 as a whole supply write control signals φWTR, φWTC, φWTRST to the write transistor WT as the write unit of each pixel PX. It constitutes a write control unit.

In the present embodiment, the row write control circuit 72, the column write control circuit 73, the reset write control circuit 102, and the write transistor WT and latch circuit 103 of each pixel PX are one of the desired reading areas 21. Alternatively, a region setting unit for setting the selection transistor ASEL of the pixel PX of a plurality of partial regions to the selected state (on state) is configured.

The present embodiment also has the same advantages as the fifth embodiment. In this embodiment, the refresh operation described in the fifth embodiment is unnecessary.

In the present invention, the same modification as the modification of the fifth embodiment to the present embodiment may be applied to the sixth and seventh embodiments. Further, as the holding portion, another latch circuit or other memory may be used instead of the capacitor HC or the SR latch circuit 103. Further, a non-volatile memory may be used as the holding unit. In this case, when the power is cut off, the non-volatile memory of all the pixels PX is stored in the information that uses the pixel as the read area, so that the entire area of the image pickup area 21 is read out immediately after the power is turned on. It can be in a state of being an area. By doing so, for example, when still image shooting is performed immediately after the power is turned on, the still image shooting can be started quickly, and a photo opportunity is not missed.

Although the embodiments of the present invention and variations thereof have been described above, the present invention is not limited thereto.

For example, in each of the above-described embodiments, the gates of the amplification transistors AMPs of the two pixel PXs adjacent to each other in the column direction or the amplification transistors AMPs of the two pixel blocks BL adjacent to each other in the column direction are turned on and off (electrically connected and disconnected). A connection switch may be provided.

Further, in each of the above-described embodiments, the output signals of the pixels PX arranged in the same row are configured to be output to the same vertical signal line 27, but the pixels PX arranged in the same row are divided into a plurality of groups. The pixel output signal may be output to the vertical signal line 27, which is different for each group.

Further, in the present invention, the solid-state image pickup device is not limited to the one composed of a single chip, and may have a structure in which a plurality of chips are joined.

In the present invention, each item of the above-described embodiments and modifications thereof may be combined as appropriate.

1 Electronic camera 4 Solid-state image sensor 21 Image sensor 22 Vertical scanning circuit 23 Area setting circuit 72-row write control circuit 73 Column write control circuit PX pixel PD photodiode TX transfer transistor AMP amplification transistor RST reset transistor FD floating capacitance part SEL, ASEL selection Transistor AR Default partial area BL pixel block WT write transistor HC capacitor

Claims (9)

A plurality of photoelectric conversion units provided in the row direction and the column direction to photoelectrically convert light into electric charges,
A signal line to which a signal due to the electric charge converted by the photoelectric conversion unit is output, and
A first output unit provided between the photoelectric conversion unit and the signal line for outputting the signal, and a first output unit.
A second output unit provided between the first output unit and the signal line for outputting the signal output from the first output unit to the signal line.
A plurality of first output units provided in the row direction , which are commonly connected to the plurality of first output units and are provided for each row in order to simultaneously select the plurality of the first output units provided in the plurality of rows. 1 control line and
A plurality of the second output units provided in the row direction and the column direction are commonly connected to each of a predetermined part of the imaging region, and the plurality of the second output units are connected to the part of the second output unit. A plurality of second control lines provided for each of the partial areas in order to collectively set the selected state or the non-selected state for each area , and
An image sensor having. A plurality of photoelectric conversion units provided in the row direction and the column direction to photoelectrically convert light into electric charges,
A signal line to which a signal due to the electric charge converted by the photoelectric conversion unit is output, and
A first output unit provided between the photoelectric conversion unit and the signal line and outputting a signal due to the electric charge photoelectrically converted by the photoelectric conversion unit, and
A second output unit provided between the first output unit and the signal line for outputting the signal output from the first output unit to the signal line.
Commonly connected to a plurality of the first output units provided in the row direction , the power supply voltage of the first output unit is supplied , and the plurality of the first output units provided in the plurality of rows are effectively enabled at the same time. Multiple feeders provided for each line to make it work ,
A plurality of the second output units provided in the row direction and the column direction are commonly connected to each of a predetermined part of the imaging region, and the plurality of the second output units are connected to the part of the second output unit. A plurality of control lines provided for each of the partial areas in order to collectively set the selected state or the non-selected state for each area , and
An image sensor having. A plurality of photoelectric conversion units provided in the row direction and the column direction to photoelectrically convert light into electric charges,
A signal line to which a signal due to the electric charge converted by the photoelectric conversion unit is output, and
A first output unit provided between the photoelectric conversion unit and the signal line and outputting a signal due to the electric charge photoelectrically converted by the photoelectric conversion unit, and
A second output unit provided between the first output unit and the signal line for outputting the signal output from the first output unit to the signal line.
A plurality of the first output units provided in the row direction and the column direction are commonly connected to each of a predetermined part of the imaging region, and the power supply voltage of the first output unit is supplied . A plurality of feeder lines provided in each of the partial regions in order to make the plurality of first output units collectively effective or ineffective in each of the partial regions.
A plurality of controls provided for each row so as to be connected in common to a plurality of the second output units provided in the row direction and simultaneously select a plurality of the second output units provided in the plurality of rows. Lines and,
An image sensor having. In the image pickup device according to claim 3 ,
The first output unit is an image sensor commonly provided in two or more photoelectric conversion units. In the image pickup device according to claim 1 or 2.
The first output unit is an image sensor commonly provided in two or more photoelectric conversion units. In the image pickup device according to any one of claims 1, 2, and 5 .
An image pickup device having a holding unit that holds a control signal for outputting a signal to the second output unit. In the image pickup device according to claim 6 ,
The holding unit is an image pickup element provided for each of the second output units. The image pickup device according to any one of claims 1 to 7 .
A plurality of the second output units are provided in the row direction and the column direction in the first region of the plurality of the partial regions and the second region different from the first region.
An image pickup device having a setting unit for setting to output the signal from at least one of the second output unit provided in the first region and the second output unit provided in the second region. The image pickup device according to claim 8 and
A detection unit that detects a subject based on the signal from the image sensor,
Equipped with
The setting unit is an image pickup device that makes settings for outputting the signal from at least one of the first region and the second region based on the position of the subject detected by the detection unit.

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