JP2017204679A - Solid state imaging device and imaging apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read a plurality of desired partial regions in an imaging region at high speed.SOLUTION: A solid state imaging device includes: a plurality of photoelectric conversion units PD; signal lines 27 from which signals on the basis of electric charges photoelectrically converted by the photoelectric conversion units PD are output; first selection units SEL provided between the photoelectric conversion units PD and the signal lines 27 and outputting signals of selected photoelectric conversion units PD; and second selection units ASEL provided between the first selection units SEL and the signal lines 27 and outputting the signals of the photoelectric conversion units PD output from the first selection units SEL to the signal lines 27.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus using the same.

  An area selection technique for selecting an arbitrary area in an imaging apparatus is known. In the area selection technique, it is impossible to read out a plurality of areas in the imaging area.

JP 9-46600 A

  The solid-state imaging device according to the first aspect is provided between a plurality of photoelectric conversion units, a signal line that outputs a signal based on charges photoelectrically converted by the photoelectric conversion unit, and the photoelectric conversion unit and the signal line. A first selection unit that outputs the signal of the selected photoelectric conversion unit; and the photoelectric conversion unit that is provided between the first selection unit and the signal line and that is output from the first selection unit. And a second selection unit that outputs a signal to the signal line.

  In the first aspect, the solid-state imaging device according to the second aspect selects the first selection unit or the second selection unit of the partial region of the imaging region where the plurality of photoelectric conversion units are arranged. An area setting unit is provided.

  In the solid-state imaging device according to a third aspect, in the second aspect, the imaging region is divided into a plurality of predetermined regions, and the region setting unit is provided for each of the predetermined regions. Supplying a selection control signal for collectively selecting or deselecting the first selection unit or the second selection unit of the region, wherein the partial region is one or more of the plurality of predetermined regions It consists of

  In the solid-state imaging device according to a fourth aspect, in the second aspect, the region setting unit holds a selection control signal for selecting or deselecting the first selection unit or the second selection unit. And a writing unit that writes the selection control signal to the holding unit in accordance with a writing control signal, and a writing control unit that supplies the writing control signal to the writing unit.

  The solid-state imaging device according to a fifth aspect is the solid state imaging device according to any one of the second to fourth aspects, wherein there are a plurality of the partial regions, and the second selection unit or the first selection unit in each row of the plurality of partial regions. While selecting, the control part which performs read-out control with respect to the row where the said 2nd selection part or the said 1st selection part was selected is provided.

  A solid-state imaging device according to a sixth aspect is provided between a plurality of photoelectric conversion units, a signal line that outputs a signal based on charges photoelectrically converted by the photoelectric conversion unit, and the photoelectric conversion unit and the signal line. A selection unit that outputs the signal of the selected photoelectric conversion unit, and an amplification unit that is provided in series with the selection unit between the photoelectric conversion unit and the signal line and outputs the signal of the photoelectric conversion unit Power supply control means for selectively supplying an effective voltage level that is effective for the operation of the amplifying unit or an ineffective voltage level that is not effective for the operation as the power supply voltage of the amplifying unit.

  A solid-state imaging device according to a seventh aspect includes a plurality of photoelectric conversion units, a signal line that outputs a signal based on charges photoelectrically converted by the photoelectric conversion unit, and two or more of the plurality of photoelectric conversion units A first selection unit that is provided in common with the photoelectric conversion unit and outputs the signals of the two or more selected photoelectric conversion units; and is provided between the first selection unit and the signal line, A second selection unit that outputs the signal of the photoelectric conversion unit output from the one selection unit to the signal line.

  In the seventh aspect, the solid-state imaging device according to the eighth aspect selects the first selection unit or the second selection unit of the partial region of the imaging region in which the plurality of photoelectric conversion units are arranged. An area setting unit is provided.

  In the solid-state imaging device according to a ninth aspect, in the eighth aspect, the imaging area is divided into a plurality of predetermined areas, and the area setting unit is provided for each of the predetermined plurality of areas. Supplying a selection control signal for collectively selecting or deselecting the first selection unit or the second selection unit of the region, wherein the partial region is one or more of the plurality of predetermined regions It consists of

  The solid-state imaging device according to a tenth aspect is the storage section according to the eighth aspect, wherein the region setting section holds a selection control signal for selecting or deselecting the first selection section or the second selection section. And a writing unit that writes the selection control signal to the holding unit in accordance with a writing control signal, and a writing control unit that supplies the writing control signal to the writing unit.

  In the solid-state imaging device according to an eleventh aspect, in any one of the eighth to tenth aspects, the plurality of partial regions are provided, and the second selection unit or the first selection unit in each row of the plurality of partial regions is provided. While selecting, the control part which performs read-out control with respect to the row where the said 2nd selection part or the said 1st selection part was selected is provided.

  A solid-state imaging device according to a twelfth aspect includes a plurality of photoelectric conversion units, a signal line that outputs a signal based on charges photoelectrically converted by the photoelectric conversion unit, and two or more of the plurality of photoelectric conversion units A selection unit that is provided in common with the photoelectric conversion unit and outputs the signals of the selected two or more photoelectric conversion units; and the selection unit between the two or more photoelectric conversion units and the signal line; An amplification unit that is provided in series and outputs the signal of the two or more photoelectric conversion units, and an effective voltage level that is effective for the operation of the amplification unit as a power supply voltage of the amplification unit, or is not effective for the operation Power supply control means for selectively supplying an ineffective voltage level.

  An imaging apparatus according to a thirteenth aspect includes the solid-state imaging element according to any one of the second to fifth and eighth to eleventh aspects, and a user interface for a user to command the partial area, The partial area is set in accordance with an instruction from the user interface.

  An imaging device according to a fourteenth aspect includes a plurality of solid-state imaging elements according to any one of the second to fifth and eighth to eleventh aspects, and a plurality of imaging regions in the imaging region based on image signals from the solid-state imaging element. A detection unit that detects a position of the imaging target, and the partial region is set according to the position detected by the detection unit.

  ADVANTAGE OF THE INVENTION According to this invention, the solid-state image sensor which can read out the desired several partial area | region of an imaging area at high speed, and an imaging device using the same can be provided.

1 is a schematic block diagram showing an electronic camera according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of the solid-state image sensor in FIG. It is a schematic plan view which shows typically the solid-state image sensor in FIG. FIG. 2 is a circuit diagram illustrating a predetermined partial region that forms a part of an imaging region of the solid-state imaging device in FIG. 1. FIG. 5 is a circuit diagram showing an abstraction of the circuit shown in FIG. 4. It is a figure which shows typically the example of a setting of the partial area | region to read out among the imaging areas of the solid-state image sensor in FIG. FIG. 7 is a diagram showing a selection control signal for realizing the setting example shown in FIG. 6 in the solid-state imaging device in FIG. 1. 2 is a timing chart illustrating an example of readout control in a partial area imaging mode of the solid-state imaging device in FIG. 1. It is a figure which shows typically the other example of a setting of the partial area | region to read out among the imaging areas of the solid-state image sensor in FIG. It is a figure which shows the selection control signal which implement | achieves the example of a setting shown in FIG. 9 in the solid-state image sensor in FIG. It is a figure which shows typically the further another example of a setting of the partial area | region to read out among the imaging areas of the solid-state image sensor in FIG. It is a figure which shows the selection control signal which implement | achieves the example of a setting shown in FIG. 6 is a timing chart illustrating another example of readout control in the partial area imaging mode of the solid-state imaging device in FIG. 1. 2 is a timing chart illustrating an example of readout control when the solid-state imaging device in FIG. 3 is a schematic flowchart illustrating an example of an operation of the electronic camera illustrated in FIG. 1 in a first partial area shooting mode. 6 is a schematic flowchart illustrating an example of an operation of the electronic camera illustrated in FIG. 1 in a second partial area shooting mode. It is a circuit diagram which shows schematic structure of the solid-state image sensor used with the electronic camera by the 2nd Embodiment of this invention. FIG. 18 is a circuit diagram illustrating a predetermined partial region that forms a part of an imaging region of the solid-state imaging device illustrated in FIG. 17. FIG. 19 is a circuit diagram abstractly showing the circuit shown in FIG. 18. It is a figure which shows the power supply voltage signal which implement | achieves the same setting as the setting example shown in FIG. 6 in the solid-state image sensor shown in FIG. It is a circuit diagram which shows schematic structure of the solid-state image sensor used with the electronic camera by the 3rd Embodiment of this invention. FIG. 22 is a circuit diagram showing a predetermined partial region that forms a part of the imaging region of the solid-state imaging device shown in FIG. 21. FIG. 22 is a timing chart illustrating an example of readout control in the partial area imaging mode of the solid-state imaging device illustrated in FIG. 21. It is a circuit diagram which shows schematic structure of the solid-state image sensor used with the electronic camera by the 4th Embodiment of this invention. FIG. 25 is a circuit diagram illustrating a predetermined partial region that forms a part of an imaging region of the solid-state imaging device illustrated in FIG. 24. FIG. 26 is a circuit diagram abstractly showing the circuit shown in FIG. 25. FIG. 25 is a timing chart illustrating an example of readout control in the partial area imaging mode of the solid-state imaging device illustrated in FIG. 24. It is a circuit diagram which shows schematic structure of the solid-state image sensor used with the electronic camera by the 5th Embodiment of this invention. It is a circuit diagram which shows a part of imaging region of the solid-state image sensor shown in FIG. FIG. 29 is a timing chart showing a write control signal when an H signal is written to a capacitor and when an L signal is written in the solid-state imaging device shown in FIG. 28. FIG. 29 is a timing chart showing a write control signal for realizing the same setting as the setting example shown in FIG. 6 in the solid-state imaging device shown in FIG. 28. It is a circuit diagram which shows schematic structure of the solid-state image sensor used with the electronic camera by the 6th Embodiment of this invention. It is a circuit diagram which shows a part of imaging region of the solid-state imaging device shown in FIG. It is a circuit diagram which shows schematic structure of the solid-state image sensor used with the electronic camera by the 7th Embodiment of this invention. FIG. 35 is a circuit diagram showing a part of an imaging region of the solid-state imaging device shown in FIG. 34. It is a circuit diagram which shows schematic structure of the solid-state image sensor used with the electronic camera by the 8th Embodiment of this invention. FIG. 37 is a circuit diagram showing one pixel of the solid-state imaging device shown in FIG. 36. 37 is a timing chart showing a write control signal for realizing the same setting as the setting example shown in FIG. 6 in the solid-state imaging device shown in FIG. 36.

  Hereinafter, a solid-state imaging device and an imaging apparatus according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a schematic block diagram showing an electronic camera 1 as an imaging device according to the first embodiment of the present invention.

  The electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera. However, the imaging apparatus according to the present invention is not limited to this, and is mounted on another electronic camera such as a compact camera or a mobile phone. An electronic camera, an electronic camera such as a video camera that captures moving images, a surveillance camera that captures moving images for monitoring, an imaging device that is incorporated into a microscope and captures a microscope image, and an imaging device that is incorporated into a telescope to capture a telescope image The present invention can be applied to various imaging devices such as a device.

  A photographing lens 2 is attached to the electronic camera 1. The photographing lens 2 is driven by a lens control unit 3 for focus and diaphragm. In the image space of the photographic lens 2, the imaging surface of the solid-state imaging device 4 is arranged.

  The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. At the time of still image shooting or the like, the imaging control unit 5 controls the solid-state imaging device 4 so as to perform a predetermined readout operation after exposure with a mechanical shutter (not shown) after so-called global reset that resets all pixels simultaneously, for example. . Further, in the electronic viewfinder mode or in moving image shooting (in the first and second partial area shooting modes and in the whole area shooting mode described later), the imaging control unit 5 performs, for example, a so-called rolling electronic shutter. The solid-state imaging device 4 is controlled so as to perform a predetermined reading operation. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on the digital image signal output from the solid-state imaging device 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. The bus 8 is also connected with a lens control unit 3, an imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12 and an image processing unit 13. An operation unit 14 such as a release button is connected to the CPU 9. A recording medium 11a is detachably attached to the recording unit 11.

  When an electronic viewfinder mode, moving image shooting, still image shooting, or the like is instructed by operation of the operation unit 14, the CPU 9 in the electronic camera 1 drives the imaging control unit 5 accordingly. At this time, the lens controller 3 appropriately adjusts the focus and the aperture. The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. A digital image signal from the solid-state imaging device 4 is processed by the digital signal processing unit 6 and then stored in the memory 7. The CPU 9 displays the image signal on the display unit 10 in the electronic viewfinder mode, and records the image signal in the recording medium 11a during moving image shooting. In the case of still image shooting or the like, after the digital image signal from the solid-state imaging device 4 is processed by the digital signal processing unit 6 and accumulated in the memory 7, the CPU 9 is necessary based on a command from the operation unit 14. In response, the image processing unit 13 or the image compression unit 12 performs desired processing, and the recording unit 11 outputs the processed signal and records it on the recording medium 11a.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 4 in FIG. In the present embodiment, the solid-state imaging device 4 is configured as a CMOS type solid-state imaging device, but may be configured as another XY address type solid-state imaging device, for example.

  The solid-state imaging device 4 includes a pixel PX arranged in a two-dimensional matrix in N rows and M columns in the imaging region 21, a vertical scanning circuit 22, a region setting circuit 23, and a control line provided for each row of the pixels PX. 24-26, a plurality of (M) vertical signal lines 27 provided for each column of the pixels PX and receiving signals from the pixels PX in the corresponding column, and a constant current source 28 provided for each vertical signal line 27 A column amplifier 29, a CDS circuit (correlated double sampling circuit) 30 and an A / D converter 31, a horizontal readout circuit 32, and a predetermined partial area of the imaging area 21 provided corresponding to each vertical signal line 27. And a control line 33 provided for each AR (see FIG. 3 described later). The predetermined partial area AR is a predetermined partial area (partial area) of the imaging area 21.

  The column amplifier 29 may be an analog amplifier or a so-called switched capacitor amplifier. Further, the column amplifier 29 is not necessarily provided.

  FIG. 3 is a schematic plan view schematically showing the solid-state imaging device 4 (particularly, its imaging region 21) in FIG. In the present embodiment, as shown in FIG. 3, the imaging area 21 of the solid-state imaging device 4 is divided into J × K predetermined partial areas AR arranged in a matrix and having predetermined J rows and K columns. Yes. When distinguishing each predetermined partial area AR, the predetermined partial area AR in the j-th row and the k-th column is indicated by a symbol AR (j, k). As shown in FIGS. 4 and 5, each predetermined partial area AR is composed of A × B (A is an integer of 2 or more, B is an integer of 1 or more) pixels PX of A rows and B columns. In the present embodiment, the sizes of the predetermined partial areas AR (the number of rows A and the number of columns B of the pixels PX) are the same, but the present invention is not limited to this. However, the number of rows A of the pixels PX in each predetermined partial area AR is preferably the same.

  FIG. 4 is a circuit diagram showing a predetermined partial area AR that forms a part of the imaging area 21 of the solid-state imaging device 4 in FIG. In FIG. 4, a predetermined partial area AR (j, k) in the j-th row and the k-th column and a predetermined partial region AR (j−1, k) in the j−1-th row and the k-th column adjacent thereto are shown. Shows the part. The predetermined partial area AR (j, k) is composed of A × B pixels PX of A rows and B columns arranged from the nth row to the (n + A−1) th row. In FIG. 4, for convenience of drawing notation, connection states of the control lines 24 to 26 and 33 and a power supply line 34 to be described later are not shown, but the control lines 24 to 26 are connected in common for each row of the pixels PX. The control line 33 is commonly connected to each predetermined partial area AR, and the power supply line 34 is commonly connected to all the pixels PX.

  In the present embodiment, all the pixels PX have the same circuit configuration. In this embodiment, each pixel PX has two selection transistors (SEL, ASEL) for selecting the pixel PX, unlike a general CMOS image sensor. The configuration is the same as that of a general CMOS image sensor.

  That is, as shown in FIG. 4, each pixel PX includes a photodiode PD as a photoelectric conversion unit that generates and accumulates charge according to incident light, and charge-voltage conversion that receives the charge and converts the charge into a voltage. Charge is transferred from the photodiode PD to the floating capacitor FD, the floating capacitor FD serving as the pixel, the amplifier transistor AMP serving as the output signal of the pixel PX, and a signal corresponding to the potential of the floating capacitor FD A transfer transistor TX to be reset, a reset transistor RST to reset the potential of the floating capacitor FD, a selection transistor SEL serving as a selection switch as a first selection unit for selecting the pixel PX, and the pixel PX. Selection transistor as a second selection unit for the selection switch Has ASEL, are connected as shown in FIG. In the present embodiment, the drains (points b in FIG. 4) of the amplification transistors AMP of all the pixels PX are connected in common by the feeder line 34, and there are the power supply voltages of the amplification transistors AMP as the power supply voltage of the amplification transistors AMP. An effective voltage level VDD that is effective for the operation is fixedly supplied. This effective voltage level VDD is also supplied to the drain of the reset transistor RST of each pixel PX by the power supply line 34. In FIG. 2, illustration of the feeder line 34 is omitted.

  In the present embodiment, the output signal of each pixel PX is output from the output signal of the pixel PX and the pixel PX only when both the first and second selection units of the pixel PX are selected. Are output to the vertical signal lines 27 that receive the output signals of the pixels PX arranged in the column direction. Specifically, in this embodiment, in each pixel PX, the selection transistors SEL and ASEL are connected in series between the source of the amplification transistor AMP and the vertical signal line 27 corresponding to the pixel PX. Has been realized. The output signal of the pixel PX is output to the vertical signal line 27 only when both the selection transistors SEL and ASEL are on (in a selected state). Note that the connection order of the selection transistor SEL and the selection transistor ASEL between the amplification transistor AMP and the vertical signal line 27 may be reverse to the order shown in FIG.

  Although not shown in the drawings, in the present embodiment, a plurality of types of color filters that transmit light of different color components are arranged in a predetermined color array on the light incident side of the photodiode PD of each pixel PX. (For example, a Bayer array). The pixel PX outputs an electrical signal corresponding to each color by color separation with a color filter.

  In the present embodiment, the transistors TX, AMP, RST, SEL, and ASEL are all nMOS transistors.

  The gate of the transfer transistor TX is commonly connected to the control line 25 for each row of the pixels PX, and a control signal φTX is supplied thereto from the vertical scanning circuit 22. The gate of the reset transistor RST is commonly connected to the control line 24 for each row of the pixels PX, and a control signal φRST is supplied from the vertical scanning circuit 22 thereto. The gates of the selection transistors SEL are commonly connected to the control line 26 for each row, and a control signal φSEL is supplied from the vertical scanning circuit 22 thereto. When distinguishing each control signal φTX for each row, the control signal φTX supplied to the gate of the transfer transistor TX of the pixel PX in the n-th row is indicated by a symbol φTX (n). The same applies to the other control signals φRST and φSEL.

  The gate (point a in FIG. 4) of the selection transistor ASEL is commonly connected to the control line 33 for each predetermined partial area AR, and a control signal φASEL is supplied from the area setting circuit 23 thereto. FIG. 5 shows an abstraction of the circuit shown in FIG. 4 while focusing on the connection relationship between the gates (points a) of the selection transistors ASEL in the predetermined partial areas AR by the control lines 33. When each control signal φASEL is distinguished for each predetermined partial area AR, the control signal φASEL supplied to the gate of the selection transistor ASEL of the pixel PX in the predetermined partial area AR (j, k) in the j-th row and the k-th column is a sign. This is indicated by φASEL (j, k). The arrangement of the area setting circuit 23 and the actual arrangement of the control lines 33 (routes to be routed) are not limited at all.

  The area setting circuit 23 serves as the second selection unit for the pixels PX of the predetermined partial area AR for each predetermined partial area AR in the imaging area 21 under the control of the imaging control unit 5 in FIG. A control signal φASEL is supplied as a selection control signal for bringing the selection transistors ASEL together into a selected state or a non-selected state. Thereby, the area setting circuit 23 sets the predetermined partial area AR in which the selection transistor ASEL is selected as an area for reading the output signal of the pixel PX in the imaging area 21.

  The vertical scanning circuit 22 outputs control signals φTX, φRST, and φSEL for each row of the pixels PX under the control of the imaging control unit 5 in FIG. 1, and is combined with the region setting operation by the region setting circuit 23. Thus, a still image reading operation and a moving image reading operation such as first and second partial area shooting modes described later are realized. By this control, the signal (analog signal) of the pixel PX in the region set by the region setting circuit 23 is supplied to the corresponding vertical signal line 27.

  The signal read out to the vertical signal line 27 is amplified for each column by the column amplifier 29, and further, the optical signal (the signal including optical information photoelectrically converted by the pixel PX) and the dark signal (light) by the CDS circuit 30. After being subjected to a process for obtaining a difference from a signal (difference signal including a noise component to be subtracted from the signal), it is converted into a digital signal by the A / D converter 31, and the digital signal is held in the A / D converter 31. Is done. The digital image signal held in each A / D converter 31 is horizontally scanned by a horizontal readout circuit 32, converted into a predetermined signal format as necessary, and externally (digital signal processing unit 6 in FIG. 1). ).

  The CDS circuit 30 receives a dark signal sampling signal φDARKC from a timing generation circuit (not shown) under the control of the imaging control unit 5 in FIG. 1, and φDARKC is changed from a high level (H) to a low level (L). The output signal of the column amplifier 29 is sampled as a dark signal at the switching timing, and receives the optical signal sampling signal φSIGC from the timing generation circuit under the control of the imaging control unit 5 in FIG. 1, and φSIGC is changed from the high level to the low level. The output signal of the column amplifier 29 is sampled as an optical signal at the timing of switching to. Then, the CDS circuit 30 outputs a signal corresponding to the difference between the sampled dark signal and the optical signal based on the clock and pulse from the timing generation circuit. As the configuration of such a CDS circuit 30, a known configuration can be adopted.

  FIG. 6 is a diagram schematically illustrating a setting example of a partial area to be read out of the imaging area 21 of the solid-state imaging device 4 in the partial area imaging mode. The partial area imaging mode is an operation mode in which the output signal of the pixel PX in one or more desired partial areas in the imaging area 21 of the solid-state imaging device 4 is selectively read out. For ease of understanding, in FIG. 6, it is assumed that N = 9, M = 12, A = 3, and B = 3, and the imaging region 21 is composed of 9 × 12 pixels PX in 9 rows and 12 columns, Each predetermined partial area AR is assumed to be composed of pixels PX of 3 rows and 3 columns. Even if the values of N, M, A, and B are other values, the following description is similarly applicable.

  In FIG. 6, the predetermined partial areas AR (3, 1), AR (1, 2), AR (2, 3), and AR (1, 4) set as the four partial areas to be read are hatched. ing. In this example, each partial area to be read is composed of one predetermined partial area AR.

  FIG. 7 shows a selection control signal φASEL for realizing the setting example shown in FIG. 6 in the solid-state imaging device 4 in FIG. Selection control signal φASEL (3,1), supplied to the gates of the selection transistors ASEL of the predetermined partial areas AR (3,1), AR (1,2), AR (2,3), AR (1,4), φASEL (1,2), φASEL (2,3), φASEL (1,4) are maintained at a high level (H), and other selection control signals φASEL are maintained at a low level (L). As a result, the selection transistors ASEL in the predetermined partial areas AR (3, 1), AR (1, 2), AR (2, 3), and AR (1, 4) are kept on, while other predetermined parts The selection transistor ASEL in the area AR is kept off.

  In the present embodiment, when the partial area to be read is set as shown in FIG. 6 in the partial area shooting mode, for example, reading control is performed as shown in FIG. FIG. 8 is a timing chart showing an example of readout control in the partial area shooting mode of the solid-state imaging device 4 in FIG.

  In the example shown in FIG. 8, the vertical scanning circuit 22 causes the first, fourth, and seventh rows in the imaging region 21 corresponding to the row of the first pixel PX in each predetermined partial region AR in the period T1. The readout control is simultaneously performed for the row of the pixels PX, and in the next period T2, the second row, the fifth row, and the eighth row in the imaging region 21 corresponding to the row of the second pixel PX in each predetermined partial region AR. The readout control is simultaneously performed for the row of the pixel PX, and in the next period T3, the third row, the sixth row in the imaging region 21 corresponding to the row of the third pixel PX in each predetermined partial region AR, and Read control is simultaneously performed on the ninth row of pixels PX, thereby completing reading for one frame. By sequentially repeating the periods T1 to T3, a plurality of frames are read by the rolling electronic shutter. For example, during the exposure period of the pixel PX in the first row, the control signal φTX (1) changes from the current high level to the low level from the time when the control signal φTX (1) in the first row changes from the previous high level to the low level. This is the period up to the point in time. The read control during each period T1 to T3 will be described in detail below.

  Immediately before the start of each of the periods T1 to T3, the transistors SEL, RST, TX of the pixels PX in all rows are turned off.

  In the period T1, the first row φSEL (1), the fourth row φSEL (4), and the seventh row φSEL (7) are set to the high level, and the first row, fourth row, and seventh row pixels PX are set. The selection transistors SEL (1), SEL (4), and SEL (7) are turned on, and the pixels PX in the first, fourth, and seventh rows are selected. However, since the selection control signal φASEL is now as shown in FIG. 7 so that the setting example shown in FIG. 6 is realized, the hatched column (4 The selection transistors ASEL of the pixels PX in the first to sixth columns, the tenth to twelfth columns) are turned on, and the non-hatched columns (first to third columns) among the pixels PX in the first row. , 7th column to 9th column) the selection transistor ASEL of the pixel PX is off. In addition, the selection transistor ASEL of the pixel PX in the column (the seventh column to the ninth column) in the fourth row of pixels PX is turned on, and the hatching of the pixel PX in the fourth row is added. The selection transistors ASEL of the pixels PX in the non-applied columns (1st to 6th columns, 10th to 12th columns) are turned off. Further, the selection transistor ASEL of the pixel PX in the column (the first column to the third column) in the hatched pixel PX in the seventh row is turned on, and the hatching in the pixel PX in the seventh row is added. The selection transistors ASEL of the pixels PX in the non-applied columns (fourth to twelfth columns) are turned off.

  Accordingly, in the period T1, the pixels PX in which both the selection transistors SEL and ASEL are on (the fourth column to the sixth column in the first row, the pixel PX in the tenth column to the twelfth column, the seventh column in the fourth row). The output signals of only the pixels PX of the first to ninth columns and the pixels PX of the first to third columns in the seventh row can be output to the corresponding vertical signal lines 27.

  The control signals φRST (1), φRST (4), φRST (7) of the first row, the fourth row, and the seventh row are set to the high level for a certain time immediately after the start of the period T1, and the first row, the fourth row The reset transistors RST of the pixels PX in the first and seventh rows are once turned on, and the potential of the floating capacitor FD (the potential of the gate of the amplification transistor AMP) is once reset to the voltage level VDD.

  The dark signal sampling signal φDARKC is set to a high level only for a certain period from the subsequent time point t1 in the period T1, whereby the pixels PX in the fourth to sixth columns and the tenth to twelfth columns in the first row, The potentials appearing at the gates of the amplification transistors AMP of the pixels PX in the seventh to ninth columns in the fourth row and the pixels PX in the first to third columns in the seventh row are the amplification transistors AMP of the pixels PX. After being amplified, the signal is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal. The

  The control signals φTX (1), φTX (4), φTX (7) in the first row, the fourth row, and the seventh row are set to the high level for a certain period from the subsequent time t2 in the period T1, and the first row. The transfer transistors TX of the pixels PX in the fourth and seventh rows are turned on. Thereby, the signal charges accumulated in the photodiodes PD of the pixels PX in the first row, the fourth row, and the seventh row are transferred to the floating capacitance portions FD of the pixels PX in the first row, the fourth row, and the seventh row. Each is forwarded. The potentials of the floating capacitor portions FD of the pixels PX in the first row, the fourth row, and the seventh row (the potential of the gate of the amplification transistor AMP) are the amount of each signal charge and the first row, This value is proportional to the reciprocal of each capacitance value of the floating capacitance portions FD of the pixels PX in the rows and the seventh row.

  Since the optical signal sampling signal φSIGC is set to a high level for a certain period from the subsequent time point t3 in the period T1, the pixels PX in the fourth to sixth columns and the tenth to twelfth columns in the first row, The potentials appearing at the gates of the amplification transistors AMP of the pixels PX in the seventh to ninth columns in the fourth row and the pixels PX in the first to third columns in the seventh row are the amplification transistors AMP of the pixels PX. After amplification, the signal is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal. The

  Thereafter, after φSIGC becomes low level, the CDS circuit 30 outputs a signal corresponding to the difference between the dark signal sampled earlier and the optical signal sampled earlier. The A / D converter 31 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32 and is output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  In the period T2 after the period T1, the second row φSEL (2), the fifth row φSEL (5), and the eighth row φSEL (8) are set to the high level, and the second row, the fifth row, and the eighth row. The selection transistors SEL (2), SEL (5), and SEL (8) of the pixel PX in the eye are turned on, and the pixels PX in the second row, the fifth row, and the eighth row are selected. However, since the selection control signal φASEL is now as shown in FIG. 7 so that the setting example shown in FIG. 6 is realized, the hatched column (4) of the pixels PX in the second row is provided. The selection transistors ASEL of the pixels PX in the columns 6 to 10 and the columns PX of the second row are not hatched (the 1st to 3rd columns). , 7th column to 9th column) the selection transistor ASEL of the pixel PX is off. In addition, the selection transistor ASEL of the pixel PX in the column (7th to 9th columns) to which hatching is applied among the pixels PX in the 5th row is turned on, and hatching is applied to the pixels PX in the 5th row. The selection transistors ASEL of the pixels PX in the non-applied columns (1st to 6th columns, 10th to 12th columns) are turned off. Further, the selection transistor ASEL of the pixel PX in the column (the first column to the third column) of the eighth row of pixels PX is turned on, and the hatching of the eighth row of pixels PX is performed. The selection transistors ASEL of the pixels PX in the non-applied columns (fourth to twelfth columns) are turned off.

  Therefore, in the period T2, the pixels PX in which both the selection transistors SEL and ASEL are on (the fourth column to the sixth column in the second row, the pixel PX in the tenth column to the twelfth column, and the seventh column in the fifth row). The output signals of only the pixels PX in the first to ninth columns and the pixels PX in the first to third columns in the eighth row can be output to the corresponding vertical signal lines 27.

  The control signals φRST (2), φRST (5), φRST (8) of the second row, the fifth row, and the eighth row are set to the high level for a certain time immediately after the start of the period T2, and the second row, the fifth row The reset transistors RST of the pixels PX in the first and eighth rows are once turned on, and the potential of the floating capacitor FD (the potential of the gate of the amplification transistor AMP) is once reset to the voltage level VDD.

  Since the dark signal sampling signal φDARKC is set to a high level for a certain period from the subsequent time point in the period T2, the pixels PX, 5 in the 4th to 6th columns and 10th to 12th columns in the 2nd row The potentials appearing at the gates of the amplification transistors AMP of the pixels PX in the seventh column to the ninth column in the row and the pixels PX in the first column to the third column in the eighth row are amplified by the amplification transistor AMP of the pixel PX. After that, the signal is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal. .

  The control signals φTX (2), φTX (5), φTX (8) of the second row, the fifth row, and the eighth row are set to the high level for a certain period from the subsequent time point in the period T2, and the second row, The transfer transistors TX of the pixels PX in the fifth and eighth rows are turned on. As a result, the signal charges accumulated in the photodiodes PD of the pixels PX in the second row, the fifth row, and the eighth row are transferred to the floating capacitance portions FD of the pixels PX in the second row, the fifth row, and the eighth row. Each is forwarded. The potentials of the floating capacitance portions FD of the pixels PX in the second row, the fifth row, and the eighth row (the potential of the gate of the amplification transistor AMP) are the same as the amount of each signal charge, excluding the noise component. The value is proportional to the reciprocal of each capacitance value of the floating capacitance portions FD of the pixels PX in the rows and the eighth row.

  Since the optical signal sampling signal φSIGC is set to a high level for a certain period from the subsequent time point in the period T2, the pixels PX, 5 in the 4th to 6th columns and 10th to 12th columns in the 2nd row The potentials appearing at the gates of the amplification transistors AMP of the pixels PX in the seventh column to the ninth column in the row and the pixels PX in the first column to the third column in the eighth row are amplified by the amplification transistor AMP of the pixel PX. Then, the signal is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal. .

  Thereafter, after φSIGC becomes low level, the CDS circuit 30 outputs a signal corresponding to the difference between the dark signal sampled earlier and the optical signal sampled earlier. The A / D converter 31 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32 and is output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  In the period T3 after the period T2, the third row φSEL (3), the sixth row φSEL (6), and the ninth row φSEL (9) are set to the high level, and the third row, the sixth row, and the ninth row The selection transistors SEL (3), SEL (6), and SEL (9) of the pixel PX in the eye are turned on, and the pixels PX in the third, sixth, and ninth rows are selected. However, since the selection control signal φASEL is now as shown in FIG. 7 so that the setting example shown in FIG. 6 is realized, the hatched column (4) of the pixels PX in the third row The selection transistors ASEL of the pixels PX in the columns 6 to 10 and the columns PX in the 3rd row are not hatched (the 1st to 3rd columns). , 7th column to 9th column) the selection transistor ASEL of the pixel PX is off. Further, the selection transistor ASEL of the pixel PX in the column (seventh to ninth columns) in the sixth row of pixels PX is turned on, and the hatching of the pixel PX in the sixth row is added. The selection transistors ASEL of the pixels PX in the non-applied columns (1st to 6th columns, 10th to 12th columns) are turned off. Further, the selection transistor ASEL of the pixel PX in the column (the first column to the third column) of the eighth row of pixels PX is turned on, and the hatching of the pixel PX of the ninth row is added. The selection transistors ASEL of the pixels PX in the non-applied columns (fourth to twelfth columns) are turned off.

  Therefore, in the period T3, the pixels PX in which both the selection transistors SEL and ASEL are on (the fourth column to the sixth column and the tenth column to the twelfth column PX in the third row, the seventh column in the sixth row) The output signals of only the pixels PX of the first to ninth columns and the pixels PX of the first to third columns in the ninth row can be output to the corresponding vertical signal lines 27.

  The control signals φRST (3), φRST (6), φRST (9) of the third row, the sixth row, and the ninth row are set to the high level for a certain time immediately after the start of the period T3, and the third row, the sixth row The reset transistors RST of the pixels PX in the ninth and ninth rows are once turned on, and the potential of the floating capacitor FD (the potential of the gate of the amplification transistor AMP) is once reset to the voltage level VDD.

  The dark signal sampling signal φDARKC is set to a high level only for a certain period from the subsequent time point in the period T3, whereby the pixels PX, 6 in the fourth to sixth columns and the tenth to twelfth columns in the third row. The potentials appearing at the gates of the amplification transistors AMP of the pixels PX in the seventh column to the ninth column in the row and the pixels PX in the first column to the third column in the ninth row are amplified by the amplification transistor AMP of the pixel PX. After that, the signal is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as a dark signal. .

  The control signals φTX (3), φTX (6), φTX (9) of the third row, the sixth row, and the ninth row are set to the high level for a certain period from the subsequent time point in the period T3, and the third row, The transfer transistors TX of the pixels PX in the sixth and ninth rows are turned on. As a result, the signal charges accumulated in the photodiodes PD of the pixels PX in the third, sixth, and ninth rows are transferred to the floating capacitance portions FD of the pixels PX in the third, sixth, and ninth rows. Each is forwarded. The potentials of the floating capacitor portions FD of the pixels PX in the third, sixth, and ninth rows (the potential of the gate of the amplification transistor AMP) are the same as the amount of each signal charge, excluding the noise component. This value is proportional to the reciprocal of each capacitance value of the floating capacitance portion FD of the pixels PX in the rows and 9th row.

  Since the optical signal sampling signal φSIGC is set to a high level for a certain period from the subsequent time point in the period T3, the pixels PX, 6 in the fourth to sixth columns and the tenth to twelfth columns in the third row The potentials appearing at the gates of the amplification transistors AMP of the pixels PX in the seventh column to the ninth column in the row and the pixels PX in the first column to the third column in the ninth row are amplified by the amplification transistor AMP of the pixel PX. Then, the signal is output to the vertical signal line 27 corresponding to the pixel PX via the selection transistors SEL and ASEL of the pixel PX, amplified by the column amplifier 29, and then sampled by the CDS circuit 30 as an optical signal. .

  Thereafter, after φSIGC becomes low level, the CDS circuit 30 outputs a signal corresponding to the difference between the dark signal sampled earlier and the optical signal sampled earlier. The A / D converter 31 converts a signal corresponding to this difference into a digital signal and holds it. The digital image signal held in each A / D converter 31 is horizontally scanned by the horizontal readout circuit 32 and is output to the outside (digital signal processing unit 6 in FIG. 1) as a digital signal image signal.

  In this way, the output signals of the pixels PX in the plurality of partial areas set as shown in FIG. 6 are read out.

  FIG. 9 is a diagram schematically illustrating another setting example of the partial area to be read out of the imaging area 21 of the solid-state imaging device 4 in the partial area imaging mode, and corresponds to FIG. 6. FIG. 10 shows a selection control signal φASEL for realizing the setting example shown in FIG. 9 in the solid-state imaging device 4 in FIG. 1, and corresponds to FIG.

  In FIG. 9, the predetermined partial areas AR (1,1), AR (1,2), AR (2,3), and AR (2,4) set as two partial areas to be read are hatched. ing. In this example, one partial area to be read is composed of two predetermined partial areas AR (1, 1) and AR (1, 2), and the other one partial area to be read is two predetermined partial areas AR (2, 3) and AR (2, 4).

  Thus, in the present embodiment, each of the one or more partial areas to be read may be composed of one predetermined partial area AR, or may be composed of a plurality of predetermined partial areas AR. In the present embodiment, when reading out a plurality of partial areas, each partial area does not necessarily have the same number of predetermined partial areas AR, and the number of predetermined partial areas AR constituting one partial area to be read is read out. The number may be different from the number of the predetermined partial areas AR constituting the other partial area.

  In the present embodiment, even when the partial area to be read is set as shown in FIG. 9 in the partial area shooting mode, for example, FIG. 8 is the same as when the partial area to be read is set as shown in FIG. Read control is performed as shown.

  FIG. 11 is a diagram schematically illustrating still another setting example of the partial area to be read out of the imaging area 21 of the solid-state imaging device 4 in the partial area imaging mode, and corresponds to FIG. 6. FIG. 12 shows a selection control signal φASEL that realizes the setting example shown in FIG. 11 in the solid-state imaging device 4 in FIG. 1, and corresponds to FIG.

  In FIG. 11, the predetermined partial areas AR (3, 1), AR (1, 1), AR (2, 3), and AR (1, 4) set as four partial areas to be read are hatched. ing. In the setting example shown in FIG. 6 and the setting example shown in FIG. 9, two or more default partial areas AR are not set as areas to be read in any column of the default partial area AR. In the setting example, in the first column of the predetermined partial area AR, two predetermined partial areas AR (3, 1) and AR (1, 1) are set as partial areas to be read.

  Therefore, in the present embodiment, even when the partial area to be read is set as shown in FIG. 11 in the partial area shooting mode, if the read control is performed as shown in FIG. The output signal of the pixel PX is simultaneously read out to the same vertical signal line 27 and the two signals interfere with each other, so that the output signal of the pixel PX cannot be read out appropriately. Specifically, in the period T1 in FIG. 8, the output signals of the pixels PX in the first to third columns in the first row and the output signals of the pixels PX in the first to third columns in the seventh row are At the same time, the signals are read out to the same vertical signal line 27 and the two signals interfere with each other, and in the period T2 in FIG. 8, the output signals of the pixels PX in the first to third columns in the second row and the eighth row Output signals of the pixels PX in the first to third columns at the same time are simultaneously read out to the same vertical signal line 27 and the two signals interfere with each other, and in the period T3 in FIG. The output signals of the pixels PX in the columns 3 to 3 and the output signals of the pixels PX in the first column to the third column in the 9th row are simultaneously read out to the same vertical signal line 27, and the two signals interfere with each other. End up.

  Therefore, in the present embodiment, when the partial area to be read is allowed to be set as shown in FIG. 11 in the partial area shooting mode, the vertical scanning circuit 22 replaces the read control shown in FIG. For example, the reading control shown in FIG. 13 may be performed. FIG. 13 is a timing chart showing another example of the readout control in the partial area photographing mode of the solid-state imaging device 4 in FIG. 1, and corresponds to FIG.

  In the example shown in FIG. 13, the vertical scanning circuit 22 needs not to simultaneously read out the output signals of two or more pixels PX to the same vertical signal line 27 in accordance with the setting of the partial area shown in FIG. As a condition, readout control is performed so that readout control is simultaneously performed for as many pixel rows as possible.

  Specifically, in the example illustrated in FIG. 13, the vertical scanning circuit 22 performs readout control simultaneously on the first row and the fourth row of pixels PX in the imaging region 21 in the period T1, and the next period. At T2, readout control is simultaneously performed for the second and fifth pixels PX in the imaging region 21, and in the next period T3, the third and sixth pixels PX in the imaging region 21 are controlled. In the next period T4, readout control is performed for the row of the seventh pixel PX in the imaging region 21, and in the next period T5, the eighth row of pixels in the imaging region 21 is performed. Read control is performed for the row of PX, and in the next period T6, read control is performed for the row of the pixel PX of the ninth row in the imaging region 21. We, thereby one frame read is completed. By sequentially repeating the periods T1 to T6, a plurality of frames are read by the rolling electronic shutter.

  In the present embodiment, the area setting circuit 23 sets two or more predetermined partial areas AR simultaneously as read areas in any column of the predetermined partial areas AR when setting the partial areas to be read in the partial area shooting mode. The vertical scanning circuit 22 may be configured to always perform the readout control shown in FIG. 8 in the partial area imaging mode by allowing the readout area to be arbitrarily set under the restriction of not. In the following description, such a configuration is referred to as a “constrained partial region setting configuration”. In this case, the area setting as shown in FIG. 6 and the area setting as shown in FIG. 9 are allowed, but the area setting as shown in FIG. 11 is not allowed. Such a vertical scanning circuit 22 can be configured using, for example, a vertical shift register, a switch, or the like, or can be configured using a decoder circuit using a memory or the like.

  Alternatively, in the present embodiment, the area setting circuit 23 can arbitrarily set an area to be read without any restriction when setting the partial area to be read in the partial area shooting mode, and the vertical scanning circuit 22 In the partial area shooting mode, the output signals of two or more pixels PX are not simultaneously read out to the same vertical signal line 27 according to the setting of the partial area. You may comprise so that read-out control in which read-out control is performed simultaneously may be performed. In the following description, such a configuration is referred to as a “configuration of unconstrained partial region setting”. In this case, not only the area setting shown in FIG. 6 and the area setting shown in FIG. 9, but also the area setting shown in FIG. 11 is allowed. In the case of the area setting as shown in FIG. 6 or the area setting as shown in FIG. 9, the vertical scanning circuit 22 performs the read control shown in FIG. 8, for example, in the case of the area setting as shown in FIG. For example, read control as shown in FIG. 13 is performed. Such a vertical scanning circuit 22 can be configured using, for example, a decoder circuit using a memory or the like so as to realize necessary row selection each time.

  As can be seen from the above description, in the present embodiment, the region setting circuit 23 configures a region setting unit that selects the selection transistors ASEL of the pixels PX in a plurality of desired partial regions in the imaging region 21. Yes. Further, in the present embodiment, the vertical scanning circuit 22 selects the selection transistors SEL of the pixels PX in each row in the plurality of partial regions, and selects the pixels PX in the rows in which the selection transistors SEL are in the selection state. A control unit that performs read control is configured.

  The vertical scanning circuit 22 performs the readout control shown in FIG. 8 in the case of the region setting as shown in FIG. 6 or the region setting as shown in FIG. 9, or in the case of the region setting as shown in FIG. When the readout control shown in FIG. 11 is performed, the selection transistors SEL of the pixels PX in one row of at least one of the plurality of partial regions (a plurality of partial regions set as the readout region), and The selection transistors SEL of pixels PX in one row different from the one row in other at least one partial region of the plurality of partial regions are simultaneously selected, and the pixels PX in these rows are selected. Thus, read control is performed. Here, any vertical signal line 27 that receives the output signal of the pixel PX of the at least one partial region is different from any vertical signal line 27 that receives the output signal of the pixel PX of the other partial region.

  Further, the vertical scanning circuit 22 sets the plurality of partial areas (set as read areas) when performing the read control shown in FIG. 8 in the area setting shown in FIG. 6 or the area setting shown in FIG. Read control is performed on the pixels PX in these rows while simultaneously selecting the selection transistors SEL of the pixels PX in one row in each partial region. Are sequentially repeated for the pixels in the remaining rows of the partial regions. Here, the number of rows of the pixels PX in the plurality of partial regions is the same. In addition, any row of the pixels PX of at least one partial region of the plurality of partial regions is different from any row of the pixels PX of at least one partial region of the plurality of partial regions. Further, any vertical signal line 27 that receives the output signal of the pixel PX of each partial region of the plurality of partial regions receives the output signal of the pixel PX of the partial region other than the partial region of the plurality of partial regions. It is different from any vertical signal line 27.

  FIG. 14 is a timing chart showing an example of readout control when the solid-state imaging device 4 in FIG. 1 is in the all-region imaging mode, and corresponds to FIGS. 8 and 13. The all region imaging mode is an operation mode in which the output signal of the pixel PX in the entire region of the imaging region 21 of the solid-state imaging device 4 is read.

  In the all area photographing mode, any selection control signal φASEL supplied to the gates of the selection transistors ASEL in all the predetermined partial areas AR is maintained at the high level (H). As a result, the selection transistors ASEL in the entire area of the imaging area 21 (all the predetermined partial areas AR) are kept on.

  In the present embodiment, in the all-region shooting mode, for example, readout control is performed as shown in FIG. In the example illustrated in FIG. 14, the vertical scanning circuit 22 sequentially reads out each row from the row of the first pixel PX to the row of the ninth pixel PX in the imaging region 21 in each of the periods T1 to T9. Control is performed, whereby reading for one frame is completed. In the all-region shooting mode at the time of still image shooting, exposure is performed by a mechanical shutter (not shown) after so-called global reset that simultaneously resets all the pixels PX, and thereafter, the periods T1 to T9 are performed once. In the whole area shooting mode at the time of moving image shooting, the periods T1 to T9 are sequentially repeated, and a plurality of frames are read by the rolling electronic shutter.

  In the present embodiment, since each pixel PX of the solid-state imaging device 4 also has a selection transistor ASEL in addition to the selection transistor SEL, in the partial area imaging mode, for example, in FIG. 6, FIG. 9 and FIG. When a plurality of partial regions are set as shown in FIG. 8, readout control can be performed as shown in FIGS. 8 and 13, and a plurality of pixels PX in different rows can be read out simultaneously. Therefore, according to the present embodiment, it is possible to reduce the time required to read out an image signal for one frame, and it is possible to read out a desired plurality of partial areas at high speed. Specifically, in order to read out an image signal for one frame, the whole area shooting mode requires periods T1 to T9 as shown in FIG. 14, whereas in the partial area shooting mode, as shown in FIG. Requires only the periods T1 to T3, and in the case shown in FIG. 13, only the periods T1 to T6 are required.

  In the imaging apparatus disclosed in Patent Document 1, a plurality of pixels PX in different rows cannot be read out simultaneously. Therefore, when a plurality of partial areas are set as areas to be read out in the partial area shooting mode, one frame is required. It takes a longer time to read out the image signal than in this embodiment. For example, in the imaging device disclosed in Patent Document 1, when a plurality of partial areas are set as areas to be read out in the partial area shooting mode, for example, as shown in FIGS. Read control similar to the read control shown in FIG. 14 must be performed, and it takes a long time to read an image signal for one frame.

  The electronic camera 1 according to the present embodiment performs the operation shown in FIG. 15 when the user commands the first partial area shooting mode via the operation unit 14. FIG. 15 is a schematic flowchart showing an example of the operation of the electronic camera 1 shown in FIG. 1 in the first partial area shooting mode.

  When the first partial area photographing mode is instructed by the operation unit 14, the CPU 9 first realizes automatic exposure control (AE) and automatic focus control (AF) (step S1). In AE in step S1, for example, the CPU 9 calculates an optimum exposure amount based on a photometric signal from an automatic exposure photometric sensor (not shown) provided separately from the solid-state image sensor 4, and the aperture of the photographing lens 2 is calculated. Is realized by controlling the lens control unit 3 so as to have an aperture according to the exposure amount. Further, in the AF in step S1, for example, the CPU 9 calculates a defocus amount based on a signal from a focus detection sensor (not shown) provided separately from the solid-state image sensor 4, and according to the defocus amount. This is realized by the lens controller 3 driving the focus of the taking lens 2 to focus the taking lens 2. Note that the output signal of the pixel PX of the solid-state image sensor 4 may be read out and used as a photometric signal for automatic exposure. Further, the solid-state imaging device 4 may be configured to obtain a focus detection signal, and AF may be realized using the signal.

  Instead of performing AE and AF in step S1 or step S6 described later, the diaphragm, focusing, etc. may be set manually by the user in advance.

  Next, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 and outputs all selection control signals φASEL supplied from the area setting circuit 23 to the gates of the selection transistors ASEL in all the predetermined partial areas AR. The high level is set, and the entire area of the imaging area 21 is set as a readout area (step S2).

  In this state, the CPU 9 controls the vertical scanning circuit 22 and the like via the imaging control unit 5 to realize readout control in the all-area shooting mode shown in FIG. Obtained and temporarily stored in the memory 7 (step S3). Here, prior to a period T1 in FIG. 14, exposure is performed with a mechanical shutter (not shown) after so-called global reset in which all the pixels PX are reset simultaneously.

  Next, the CPU 9 displays the image obtained in step S3 on the display unit 10 (step S4), and prompts the user to specify a desired partial area to be photographed. Note that the CPU 9 accepts only an allowable area designation when the configuration of the limited partial area setting is adopted, and has no restriction when the configuration of the partial area setting without restriction is adopted. Accept area specification. When the user performs input for designating a desired partial area by the operation unit 14 while viewing the displayed image, and the CPU 9 accepts the designation, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5. Then, the selection control signal φASEL supplied to the gate of the selection transistor ASEL of the predetermined partial area AR corresponding to one or a plurality of partial areas according to the designation is selectively set to the high level, and the one or more predetermined partial areas AR is selectively set as a read area (step S5). In the present embodiment, a user interface for instructing one or more desired partial regions in the imaging region 21 is constructed by these functions of the CPU 9, the display unit 10, and the operation unit 14.

  Subsequently, the CPU 9 performs AE and AF similarly to step S1 (step S6). However, in step S6, unlike step S1, exposure and focusing are performed so as to optimize the partial area set in step S5.

  Next, the CPU 9 controls the vertical scanning circuit 22 and the like via the imaging control unit 5 to realize the readout control in the partial area shooting mode described above, obtains image data of the partial area for one frame, and stores the memory. 7 is temporarily stored, and this image is recorded on the recording medium 11a as a moving image of the partial area by the recording unit 11 (step S7). In addition, a rolling electronic shutter is implement | achieved by repeating step S7 by the operation | movement shown in FIG.

  Thereafter, the CPU 9 determines whether or not a command to end the partial area moving image shooting is obtained from the operation unit 14 (step S8). If there is no command, the process returns to step S7. The series of operations in the area shooting mode is finished.

  In the first partial area photographing mode, it is possible to acquire a moving image of one or more desired partial areas arbitrarily set by the user in this way. According to the present embodiment, as described above, it is possible to reduce the time required to read out an image signal for one frame of a desired plurality of partial areas, and to read out the desired plurality of partial areas at high speed. Therefore, it is possible to acquire moving images of desired partial areas arbitrarily set by the user at a high frame rate.

  Therefore, in the first partial area shooting mode, the user designates a plurality of desired partial areas each including any of a plurality of target objects, thereby changing a plurality of target objects in the field of view (for example, shape and A moving image that captures the process of changes in size, orientation, color, and the like) can be acquired, and the moving image can be observed without missing changes in a plurality of objects of interest in the field of view. For example, when the electronic camera 1 according to the present embodiment is an imaging device that is incorporated in a microscope and captures a microscopic image, when a petri dish in which cells are cultured is used as a field of view, a plurality of cell change processes (for example, In addition, it is possible to acquire a moving image that captures the details of cell division, cardiac pulsation, and the like.

  The electronic camera 1 according to the present embodiment performs the operation shown in FIG. 16 when the user instructs the second partial area shooting mode via the operation unit 14. FIG. 16 is a schematic flowchart showing an example of the operation of the electronic camera 1 shown in FIG. 1 in the second partial area shooting mode. The first partial area shooting mode is a mode in which the partial area is fixed to the area specified by the user, whereas the second partial area shooting mode is a mode in which the captured partial area is used to move the target object. This mode automatically follows.

  When the second partial region shooting mode is instructed by the operation unit 14, the CPU 9 performs the same steps S11 to S13 as steps S1 to S3 in FIG.

  Next, the CPU 9 performs image recognition processing by a known image recognition method on the image stored in the memory 7 in step S13 to obtain a desired target of interest (for example, a human whole body, a human face, a moving body, a cell, etc.). Etc.) and the position, size, etc. on the image are detected (step S14).

  Next, the CPU 9 determines whether or not the target object is recognized in step S14 (step S15). If the target object is recognized, the process proceeds to step S16. If the target object is not recognized, the process proceeds to step S27. To do. In step S27, the CPU 9 determines whether or not a command for ending the partial area moving image shooting is obtained from the operation unit 14, and if there is no such command, the process returns to step S11. Ends the series of operations in the mode.

  In step S <b> 16, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 and selectively sets one or a plurality of predetermined partial areas AR as readout areas according to the recognition result in step S <b> 14. . Specifically, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5 and corresponds to one or a plurality of partial areas including each target object recognized in step S14 and its surroundings to some extent. The selection control signal φASEL supplied to the gate of the selection transistor ASEL in the predetermined partial area AR is selectively set to the high level.

  Subsequently, the CPU 9 performs AE and AF similarly to step S11 (step S17). However, in step S17, unlike step S11, exposure and focusing are performed so as to optimize the partial area set in step S16.

  Thereafter, the CPU 9 resets the count value q to zero (step S18). The count value q indicates the number of frames shot after the partial area is set to the latest.

  Next, the CPU 9 controls the vertical scanning circuit 22 and the like via the imaging control unit 5 to realize the readout control in the partial area shooting mode described above, obtains image data of the partial area for one frame, and stores the memory. 7 is temporarily stored, and the recording unit 11 records this image on the recording medium 11a as a moving image of the currently set partial area (step S19). In addition, a rolling electronic shutter is implement | achieved by repeating step S19 by the operation | movement shown in FIG.

  Next, after incrementing the count value q by 1 (step S20), the CPU 9 determines whether or not a command to end partial area moving image shooting is obtained from the operation unit 14 (step S21). On the other hand, the process proceeds to S22, and if there is an instruction, the series of operations in the second partial area photographing mode is terminated.

  In step S22, the CPU 9 determines whether or not the current count value q is equal to or greater than the value Q. If q ≧ Q, the process returns to step S19, while if q ≧ Q, the process proceeds to step S23. This value Q is one or more values arbitrarily set in advance by the user via the operation unit 14 before the start of the second partial area photographing mode. The value Q is a value that determines the timing of resetting the partial area. As will be understood from the following description, the partial area is reset when the number of frames shot in the partial area once set reaches the value Q. When the moving speed of the target object is high, the value Q is set to a relatively small value in order to improve the followability to the target object. When the moving speed of the target object is low, the time of steps S23 and S26 is reduced. In order to increase the overall frame rate, the value Q is set to a relatively large value.

  In step S23, image recognition processing by a known image recognition method is performed on the image of each partial area of the frame stored in the memory 7 in step S19, so that a desired target of interest is recognized. Detect size etc.

  Subsequently, the CPU 9 determines whether or not the target object is recognized in step S23 (step S24). If the target object is recognized, the process proceeds to step S25. If the target object is not recognized, the process proceeds to step S27. Transition.

  In step S25, the CPU 9 controls the area setting circuit 23 via the imaging control unit 5, and selectively sets one or a plurality of predetermined partial areas AR as readout areas according to the recognition result in step S23. .

  Thereafter, the CPU 9 performs AE and AF as in step S17 (step S26), and then returns to step S18. However, in step S26, unlike in step S17, the exposure and focusing are performed so as to optimize the partial area set in the latest in step S25.

  In the second partial area shooting mode, it is possible to acquire moving images of a plurality of partial areas set in such a manner as to automatically follow the movement of the target object. According to the present embodiment, as described above, it is possible to reduce the time required to read out an image signal for one frame of a desired plurality of partial areas, and to read out the desired plurality of partial areas at high speed. As a result, it is possible to acquire a moving image of a partial area that is set by automatically following the movement of the target object at a high frame rate, and the time required for AF or the like even if the movement speed of the target object is high Therefore, a moving image in an in-focus state can be obtained and followability is improved.

  Therefore, this second partial area shooting mode is effective, for example, when used as a surveillance camera in which the subject of interest is the whole body or face of a person. Capturing the details of the changes in the whole body or face of multiple people allows you to know in detail the process of changes in posture, facial expression, and lip movement of multiple people. Can be obtained. For example, it is possible to know in detail the state of the fighting of multiple people, or to know the content of the conversation of multiple people using lip reading.

  The second partial area photographing mode is also effective when, for example, the electronic camera 1 according to the present embodiment is an imaging device that is incorporated in a microscope and captures a microscope image. When observing cells or microorganisms as a target of interest, even if the movement speed is extremely low, if the target of interest can move, a long time has passed in the first partial area imaging mode. Later, there is a possibility that the target of interest will deviate from the partial area set by the user. On the other hand, the second partial area shooting mode can acquire moving images of a plurality of partial areas set automatically following the movement of the target object. However, imaging can be performed at a high frame rate for a long time.

  In the electronic camera 1 according to the present embodiment, when the user instructs the still image shooting mode via the operation unit 14, a still image shooting operation similar to that of a normal electronic camera is performed, and the user operates the operation unit 14 The operation is performed when an all-region shooting mode at the time of moving image shooting is instructed via, but the description thereof is omitted here.

  [Second Embodiment]

  FIG. 17 is a circuit diagram showing a schematic configuration of the solid-state imaging device 41 used in the electronic camera according to the second embodiment of the present invention, and corresponds to FIG. FIG. 18 is a circuit diagram showing a predetermined partial area AR that forms a part of the imaging area 21 of the solid-state imaging device 41 shown in FIG. 17, and corresponds to FIG. FIG. 19 is a circuit diagram abstractly showing the circuit shown in FIG. 18, and corresponds to FIG. FIG. 20 is a diagram showing the power supply voltage signal φVDD that realizes the same setting as the setting example shown in FIG. 6 in the solid-state imaging device 41 shown in FIG. 17, and corresponds to FIG.

  17 to 19, elements that are the same as or correspond to those in FIGS. 2, 4, and 5 are assigned the same reference numerals, and redundant descriptions thereof are omitted. This embodiment is different from the first embodiment in the points described below.

  In the present embodiment, in the electronic camera 1 according to the first embodiment, a solid-state image sensor 41 is used instead of the solid-state image sensor 4.

  In the first embodiment, the selection transistor ASEL is provided in each pixel PX of the imaging region 21, whereas in this embodiment, the selection transistor ASEL and the control line 33 are provided in each pixel PX of the imaging region 21. Is removed, and the source of the selection transistor SEL is connected to the vertical signal line 27 corresponding to the pixel PX.

  In the first embodiment, the drains (points b in FIG. 4) of the amplification transistors AMP of all the pixels PX are connected in common by the power supply line 34, and are amplified as the power supply voltage of the amplification transistors AMP. An effective voltage level VDD that is effective for the operation of the transistor AMP is fixedly supplied. On the other hand, in the present embodiment, the feeder line 34 is electrically separated for each predetermined partial area AR, and the drain (point b in FIG. 18) of the amplification transistor AMP of each pixel PX is connected to the predetermined partial area AR. The power supply line 34 is commonly connected to each other, and a power supply voltage signal φVDD is supplied from the region setting circuit 23 as a power supply voltage of the amplification transistor AMP. Note that the drain of the reset transistor RST of each pixel PX is connected to the drain of the amplification transistor AMP (point b in FIG. 18) of the pixel PX by a power supply line 34.

  FIG. 19 shows an abstraction of the circuit shown in FIG. 18 by paying attention to the connection relationship between the drains (points b) of the amplification transistors AMP in the predetermined partial regions AR by the feeder lines 34. When each power supply voltage signal φVDD is distinguished for each predetermined partial area AR, the power supply voltage signal φVDD supplied to the drain of the amplification transistor AMP of the pixel PX in the jth and kth predetermined partial area AR (j, k). Is represented by the symbol φVDD (j, k). In addition, the actual arrangement of the power supply line 34 (route to be routed) is not limited at all.

  In the present embodiment, the region setting circuit 23 is configured as a power supply control circuit that outputs each power supply voltage signal φVDD instead of each control signal φASEL under the control of the imaging control unit 5. Each power supply voltage signal φVDD is an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or an ineffective voltage level that is not effective for the operation of the amplification transistor AMP (here, 0V, but is not necessarily limited to 0V). The region setting circuit 23 selectively supplies VDD or 0V as the power supply voltage of the amplification transistor AMP of each pixel PX.

  In the present embodiment, in each pixel PX, the power supply voltage signal φVDD becomes VDD and the amplification transistor AMP operates effectively, and the power supply voltage signal φVDD becomes 0 V and the amplification transistor AMP does not operate effectively. Regarding whether or not the output signal of the pixel PX can be output to the vertical signal line 27, in the first embodiment, the control signal φASEL becomes high level in each pixel PX and the selection transistor ASEL is turned on and the control signal φASEL. Is substantially the same as a state in which the selection transistor ASEL is turned off.

  Therefore, in the present embodiment, the output signal of each pixel PX is the power supply voltage signal supplied as the power supply voltage of the amplification transistor AMP of the pixel PX while the selection transistor SEL of the pixel PX is in the selected state (ON state). Only when φVDD is the effective voltage level VDD, the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction with respect to the pixel PX are output to the vertical signal line 27.

  In the present embodiment, the area setting circuit 23 supplies an effective voltage level VDD as each power supply voltage signal φVDD instead of supplying a high level signal as each φASEL in the first embodiment, and the first embodiment. In this embodiment, by supplying 0V as each power supply voltage signal φVDD instead of supplying a low level signal as each φASEL, an operation similar to that of the first embodiment is realized. For example, in the present embodiment, when the same setting as the region setting example shown in FIG. 6 is realized, the region setting circuit 23 may output each power supply voltage signal φVDD shown in FIG.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained. In the present embodiment, since the selection transistor ASEL is not provided in each pixel PX, the configuration of each pixel PX is simplified.

  [Third Embodiment]

  FIG. 21 is a circuit diagram showing a schematic configuration of the solid-state imaging device 51 used in the electronic camera according to the third embodiment of the present invention, and corresponds to FIG. FIG. 22 is a circuit diagram showing a predetermined partial area AR that forms part of the imaging area 21 of the solid-state imaging device 51 shown in FIG. 21, and corresponds to FIG. FIG. 23 is a timing chart showing an example of readout control in the partial area photographing mode of the solid-state imaging device 51 shown in FIG. 21, and corresponds to FIG.

  21 to 23, elements that are the same as or correspond to those in FIGS. 2, 4, and 8 are given the same reference numerals, and redundant descriptions thereof are omitted. This embodiment is different from the first embodiment in the points described below.

  In the present embodiment, a solid-state imaging device 51 is used in place of the solid-state imaging device 4 in the electronic camera 1 according to the first embodiment.

  In the first embodiment, the selection transistor SEL is provided in each pixel PX in the imaging region 21, whereas in this embodiment, the selection transistor SEL and the connection line 26 are provided in each pixel PX in the imaging region 21. Is removed, and the drain of the selection transistor ASEL is connected to the source of the amplification transistor AMP of the pixel PX.

  In the first embodiment, the drains (points b in FIG. 4) of the amplification transistors AMP of all the pixels PX are connected in common by the power supply line 34, and are amplified as the power supply voltage of the amplification transistors AMP. An effective voltage level VDD that is effective for the operation of the transistor AMP is fixedly supplied. On the other hand, in the present embodiment, the feed line 34 is electrically separated for each row of the pixels PX, and the drain (point b in FIG. 22) of the amplification transistor AMP of each pixel PX is set for each row of the pixel PX. Are connected in common by a power supply line 34, and a power supply voltage signal φVDD is supplied from the power supply control circuit 52 as a power supply voltage of the amplification transistor AMP. When each power supply voltage signal φVDD is distinguished for each row of the pixels PX, the power supply voltage signal φVDD supplied to the drain of the amplification transistor AMP of the pixel PX in the n-th row is indicated by a symbol φVDD (n). Note that the drain of the reset transistor RST of each pixel PX is connected to the drain (point b in FIG. 22) of the amplification transistor AMP of the pixel PX by a feeder line 34.

  In the present embodiment, the power supply control circuit 52 is provided as a part of the vertical scanning circuit 22 and outputs each power supply voltage signal φVDD instead of each control signal φSEL under the control of the imaging control unit 5. Each power supply voltage signal φVDD is an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or an ineffective voltage level that is not effective for the operation of the amplification transistor AMP (here, 0V, but is not necessarily limited to 0V). The power supply control circuit 52 selectively supplies VDD or 0 V as the power supply voltage of the amplification transistor AMP of each pixel PX.

  In the present embodiment, in each pixel PX, the power supply voltage signal φVDD becomes VDD and the amplification transistor AMP operates effectively, and the power supply voltage signal φVDD becomes 0 V and the amplification transistor AMP does not operate effectively. Regarding whether or not the output signal of the pixel PX can be output to the vertical signal line 27, in the first embodiment, in each pixel PX, the control signal φSEL becomes high level and the selection transistor SEL is turned on and the control signal φSEL. Is substantially the same as the state in which the select transistor SEL is turned off.

  Therefore, in the present embodiment, the output signal of each pixel PX is the power supply voltage signal supplied as the power supply voltage of the amplification transistor AMP of the pixel PX while the selection transistor ASEL of the pixel PX is in the selected state (ON state). Only when φVDD is the effective voltage level VDD, the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction with respect to the pixel PX are output to the vertical signal line 27.

  In the present embodiment, the power supply control circuit 52 supplies an effective voltage level VDD as each power supply voltage signal φVDD instead of supplying a high level signal as each φSEL in the first embodiment, and the first embodiment. In this embodiment, by supplying 0 V as each power supply voltage signal φVDD instead of supplying a low level signal as each φSEL, the same operation as in the first embodiment is realized. For example, in the present embodiment, when the partial area to be read is set as shown in FIG. 6 in the partial area shooting mode, the vertical scanning circuit 22 may perform the read control as shown in FIG.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained. In the present embodiment, since the selection transistor SEL is not provided in each pixel PX, the configuration of each pixel PX is simplified.

  [Fourth Embodiment]

  FIG. 24 is a circuit diagram showing a schematic configuration of the solid-state imaging device 61 used in the electronic camera according to the fourth embodiment of the present invention, and corresponds to FIG. FIG. 25 is a circuit diagram showing a predetermined partial area AR that forms part of the imaging area 21 of the solid-state imaging device 61 shown in FIG. 24, and corresponds to FIG. FIG. 26 is a circuit diagram abstractly showing the circuit shown in FIG. 25, and corresponds to FIG. FIG. 27 is a timing chart showing an example of readout control in the partial area shooting mode of the solid-state imaging device 61 shown in FIG. 24, and corresponds to FIG. 24 to 27, elements that are the same as or correspond to those in FIGS. 2, 4, 5, and 8 are given the same reference numerals, and redundant descriptions thereof are omitted.

  In the present embodiment, in the electronic camera 1 according to the first embodiment, a solid-state image sensor 61 is used instead of the solid-state image sensor 4.

  The present embodiment is different from the first embodiment in that, for each of two pixels PX adjacent in the column direction, the two pixels PX include one set of a floating capacitor FD, an amplification transistor AMP, and a reset transistor RST. In addition, the vertical scanning circuit 22 uses the control signals φSEL, φRST, φTXA as shown in FIG. 27 instead of the control signals φSEL, φRST, φTX as shown in FIG. , ΦTXB is output.

  In FIG. 24 to FIG. 26, two pixels PX sharing one set of the floating capacitor FD, the amplification transistor AMP, the reset transistor RST, and the selection transistors SEL and ASEL are shown as a pixel block BL. In FIGS. 24 and 25, the photodiode PD and the transfer transistor TX of the lower pixel PX in the pixel block BL are indicated by symbols PDA and TXA, respectively, and the photodiode PD of the upper pixel PX in the pixel block BL and The transfer transistors TX are indicated by symbols PDB and TXB, respectively, to distinguish them. Further, the control signal supplied to the gate of the transfer transistor TXA is φTXA, and the control signal supplied to the gate electrode of the transfer transistor TXB is φTXB to distinguish them.

  In FIGS. 2 and 4, N, n, etc. indicate pixel rows, but in FIGS. 24, 25, N, n, etc. indicate rows of the pixel block BL. One row of the pixel block BL corresponds to two rows of the pixels PX. 4 and 5, each predetermined partial area AR is composed of A × B pixels PX of A rows and B columns. In FIGS. 25 and 26, each predetermined partial area AR is A × B of A rows and B columns. The pixel block BL (2 × A × B pixels PX). Note that the number of rows of photodiodes PD constituting each predetermined partial area AR may be two or more and the number of columns of photodiodes PD may be one or more. In the present embodiment, one pixel block BL includes two photo diodes. Since the diode PD is included, the number of rows of the pixel block BL constituting each predetermined partial area AR may be one or more and the number of columns of the pixel block BL may be one or more.

  In the present embodiment, when the partial area to be read is set as shown in FIGS. 6 and 9 in the partial area shooting mode, for example, instead of the read control shown in FIG. 8, the read control shown in FIG. Is done. Here, n in FIGS. 6 and 9 indicates the row of the pixel block BL, and m in FIGS. 6 and 9 indicates the column of the pixel block BL.

  In the example shown in FIG. 27, the vertical scanning circuit 22 performs the first row, the fourth row, and the seventh row in the imaging region 21 corresponding to the row of the first pixel block BL in each predetermined partial region AR in the period T1. In the next period T2, the readout control is simultaneously performed for the rows of the pixel blocks BL, and the second row and the fifth row in the imaging region 21 corresponding to the row of the second pixel block BL in each predetermined partial region AR. The readout control is simultaneously performed for the rows of the pixel blocks BL in the eighth row, and in the next period T3, the third row in the imaging region 21 corresponding to the row of the pixel blocks BL in the third row in each predetermined partial region AR. The readout control is performed simultaneously on the sixth and ninth pixel block BL rows, thereby completing the readout for one frame. By sequentially repeating the periods T1 to T3, a plurality of frames are read by the rolling electronic shutter.

  In the present embodiment, when the partial region to be read is allowed to be set as shown in FIG. 11 in the partial region shooting mode, the vertical scanning circuit 22 replaces the read control shown in FIG. The readout control shown in FIG. 13 may be modified in the same manner as the readout control shown in FIG. 8 is transformed into the readout control shown in FIG. Here, n in FIG. 11 indicates a row of the pixel block BL, and m in FIG. 11 indicates a column of the pixel block BL.

  In this example, the vertical scanning circuit 22 requires that the output signals of two or more pixels PX are not simultaneously read out to the same vertical signal line 27 according to the setting of the partial area shown in FIG. The readout control is performed so that the readout control is simultaneously performed on as many rows of the pixel blocks BL as possible.

  In the present embodiment, the area setting circuit 23 sets two or more predetermined partial areas AR simultaneously as read areas in any column of the predetermined partial areas AR when setting the partial areas to be read in the partial area shooting mode. The vertical scanning circuit 22 may be configured to always perform the readout control shown in FIG. 27 in the partial area imaging mode by allowing the readout area to be arbitrarily set under the restriction of not. In the following description, such a configuration is referred to as a “constrained partial region setting configuration”. In this case, the area setting as shown in FIG. 6 and the area setting as shown in FIG. 9 are allowed, but the area setting as shown in FIG. 11 is not allowed.

  Alternatively, in the present embodiment, the area setting circuit 23 can arbitrarily set an area to be read without any restriction when setting the partial area to be read in the partial area shooting mode, and the vertical scanning circuit 22 In the partial area shooting mode, as a necessary condition, the output signals of two or more pixels PX are not simultaneously read out to the same vertical signal line 27 according to the setting of the partial area. The read control may be performed such that the read control is simultaneously performed on the rows. In the following description, such a configuration is referred to as a “configuration of unconstrained partial region setting”. In this case, not only the area setting shown in FIG. 6 and the area setting shown in FIG. 9, but also the area setting shown in FIG. 11 is allowed. In the case of the area setting as shown in FIG. 6 or the area setting as shown in FIG. 9, the vertical scanning circuit 22 performs, for example, the read control shown in FIG. 27 and the area setting as shown in FIG. For example, the read control shown in FIG. 8 is modified to the read control shown in FIG. 27, and the read control shown in FIG. 13 is modified.

  In the present embodiment, in the all-region imaging mode, for example, the readout control modified from the readout control illustrated in FIG. 14 is performed in the same manner as the readout control illustrated in FIG. 8 is modified to the readout control illustrated in FIG. In this example, the vertical scanning circuit 22 sequentially performs readout control for each row from the row of the first pixel block BL to the row of the ninth pixel block BL in the imaging region 21, thereby Is read out. In the all-area shooting mode at the time of still image shooting, exposure is performed by a mechanical shutter (not shown) after so-called global reset that resets all pixels PX at the same time, and then pixel blocks in each row from the first row to the ninth row. BL is read. In the whole area shooting mode at the time of moving image shooting, the reading of the pixel blocks BL of each row from the first row to the ninth row is sequentially repeated, and a plurality of frames are read by the rolling electronic shutter.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained. In this embodiment, for every two pixels PX that are adjacent in the column direction, the two pixels PX share a set of floating capacitor FD, amplification transistor AMP, reset transistor RST, and selection transistors SEL, ASEL. However, in the present invention, for example, for every three or more predetermined number of pixels PX that are adjacent in the column direction, the predetermined number of pixels PX includes one set of floating capacitance unit FD, amplification transistor AMP, reset transistor RST, The selection transistors SEL and ASEL may be shared. In the present invention, a modification similar to the modification of the first embodiment to the present embodiment may be applied to the second and third embodiments.

  [Fifth Embodiment]

  FIG. 28 is a circuit diagram showing a schematic configuration of a solid-state imaging device 71 used in an electronic camera according to the fifth embodiment of the present invention, and corresponds to FIG. FIG. 29 is a circuit diagram showing a part of the imaging region 21 of the solid-state imaging device 71 shown in FIG. 28, and corresponds to FIG.

  28 and 29, the same or corresponding elements as those in FIGS. 2 and 4 are denoted by the same reference numerals, and redundant description thereof is omitted. This embodiment is different from the first embodiment in the points described below.

  In the present embodiment, in the electronic camera 1 according to the first embodiment, a solid-state image sensor 71 is used instead of the solid-state image sensor 4.

  In the present embodiment, the imaging area 21 is not divided into the predetermined partial areas AR. In this embodiment, a row write control circuit 72 and a column write control circuit 73 are provided instead of the region setting circuit 23.

  Further, in the present embodiment, a capacitor HC and a write transistor WT are added to each pixel PX. The capacitor HC of each pixel PX is connected between the ground and the gate of the selection transistor ASEL of the pixel PX, and holds a selection control signal for setting the selection transistor ASEL of the pixel PX to a selected state or a non-selected state. The holding part is configured. The write transistor WT of each pixel PX constitutes a write unit that writes the selection control signal to the capacitor HC as the holding unit of the pixel PX in accordance with the write control signals φWTR and φWTC.

  In the present embodiment, the write transistor WT is an nMOS transistor. The source of the writing transistor WT of each pixel PX is connected to the gate of the selection transistor ASEL of the pixel PX. The gates of the write transistors WT of the respective pixels PX are connected in common by a control line 74 for each row of the pixels PX, and a first write control signal φWTR is supplied from the row write control circuit 72 thereto. The drain of the write transistor WT of each pixel PX is commonly connected to each column of the pixels PX, and a second write control signal φWTC is supplied from the column write control circuit 73 thereto. The write transistor WT of each pixel PX takes the AND of the first write control signal φWTR supplied to its gate and the second write control signal φWTC supplied to its drain, and uses the AND output as its source. An AND circuit to output is configured. As the writing unit, for example, another AND circuit may be used instead of the writing transistor WT.

  When distinguishing each first write control signal φWTR for each row of the pixels PX, the first write control signal φWTR supplied to the gate of the write transistor WT of the pixel PX in the n-th row is indicated by a symbol φWTR (n). . When each second write control signal φWTC is distinguished for each column of the pixels PX, the second write control signal φWTC supplied to the drain of the write transistor WT of the pixel PX in the m-th column is indicated by a symbol φWTC (m). .

  FIG. 30A shows a write control signal φWTR (n), when writing a high level signal (H signal) to the capacitor HC of the pixel PX in the n-th row and the m-th column in the solid-state imaging device 71 shown in FIG. It is a figure which shows (phi) WTC (m). At time t21, the write control signal φWTR (n) of the n-th row is raised to a high level, and then the write control signal φWTC (m) of the m-th column is raised to a high level at a time t22, and then the write is performed at time t23. The control signal φWTR (n) is lowered to a low level, and then the write control signal φWTC is lowered at time t24. As a result, the high level signal is written and held in the capacitor HC of the pixel PX in the n-th row and the m-th column. As a result, the selection transistor ASEL of the pixel PX in the nth row and the mth column is held in the on state (selected state).

  FIG. 30B shows a write control signal φWTR (n), when writing a low level signal (L signal) to the capacitor HC of the pixel PX in the nth row and the mth column in the solid-state imaging device 71 shown in FIG. It is a figure which shows (phi) WTC (m). While the write control signal φWTC (m) of the m-th column is maintained at the low level, the write control signal φWTR (n) of the n-th row is raised to the high level at time t21, and then the write control signal φWTR ( n) falls to the low level. As a result, the low level signal is written and held in the capacitor HC of the pixel PX in the n-th row and the m-th column. As a result, the selection transistor ASEL of the pixel PX in the n-th row and the m-th column is held in the off state (non-selected state).

  The row write control circuit 72 supplies the first write control signal φWTR for each row of the pixels PX under the control of the imaging control unit 5 in FIG. The column writing control circuit 73 supplies the second writing control signal φWTC for each column of the pixels PX under the control of the imaging control unit 5 in FIG. The row write control circuit 72 and the column write control circuit 73 constitute a write control unit that supplies write control signals φWTR and φWTC to the write transistor WT as the write unit of each pixel PX as a whole.

  In the present embodiment, the row write control circuit 72, the column write control circuit 73, and the write transistor WT and the capacitor HC of each pixel PX as a whole read out one or more desired portions of the imaging region 21. An area setting unit is configured to set the selection transistor ASEL of the pixel PX in the area to the selected state (ON state).

  FIG. 31 is a timing chart showing write control signals φWTR and φWTC that realize the same setting as the region setting example shown in FIG. 6 in the solid-state imaging device 71 shown in FIG. Here, in FIG. 6, although not divided into each predetermined partial area AR, the four partial areas with hatching are set as four partial areas to be read.

  In the example shown in FIG. 31, first, a low level signal is written to the capacitors HC of all the pixels PX, and then the pixels PX are sequentially selected one by one, and the high level is applied to the capacitors HC of the necessary pixels PX in the row. By writing the signal, the four partial areas hatched in FIG. 6 are set as areas to be read.

  Specifically, when an area setting period (a period for setting an area to be read) starts, first, φWTR (1) to φWTR (9) are set to a high level during a period t31 to t32, while φWTC (1) ˜φWTC (12) is set to the low level. Thereby, as can be understood from FIG. 30B, a low level signal is written to the capacitors HC of all the pixels PX.

  Next, φWTR (1) is set to a high level during a period t33 to t35, and φWTC (4) to φWTC (6) and φWTC (10) to φWTC (12) are set to a high level during a period t34 to t36. As a result, as can be understood from FIG. 30A, a high level signal is written to the capacitor HC of the pixels PX in the fourth to sixth columns and the tenth to twelfth columns of the pixels PX in the first row.

  Next, φWTR (2) is set to a high level during a period t36 to t38, and φWTC (4) to φWTC (6) and φWTC (10) to φWTC (12) are set to a high level during a period t37 to t39. As a result, a high level signal is written to the capacitor HC of the pixels PX in the fourth to sixth columns and the tenth to twelfth columns of the pixels PX in the second row.

  Subsequently, φWTR (3) is set to a high level during a period t39 to t41, and φWTC (4) to φWTC (6) and φWTC (10) to φWTC (12) are set to a high level during a period t40 to t42. Accordingly, a high level signal is written to the capacitor HC of the pixels PX in the 4th to 6th columns and the 10th to 12th columns of the pixels PX in the third row.

  Thereafter, φWTR (4) is set to a high level during a period t42 to t44, and φWTC (7) to φWTC (9) are set to a high level during a period t43 to t45. As a result, a high level signal is written to the capacitor HC of the pixels PX in the seventh to ninth columns of the pixels PX in the fourth row.

  Next, φWTR (5) is set to a high level during a period t45 to t47, and φWTC (7) to φWTC (9) are set to a high level during a period t46 to t48. As a result, a high level signal is written to the capacitor HC of the pixels PX in the seventh to ninth columns of the pixels PX in the fifth row.

  Next, φWTR (6) is set to a high level during a period t48 to t50, and φWTC (7) to φWTC (9) are set to a high level during a period t49 to t51. As a result, a high level signal is written to the capacitor HC of the pixels PX in the seventh to ninth columns of the pixels PX in the sixth row.

  Subsequently, φWTR (7) is set to a high level during a period t51-t53, and φWTC (1) to φWTC (3) are set to a high level during a period t52-t54. As a result, a high level signal is written to the capacitor HC of the pixels PX in the first to third columns of the pixels PX in the seventh row.

  Thereafter, φWTR (8) is set to a high level during a period t54 to t56, and φWTC (1) to φWTC (3) are set to a high level during a period t55 to t57. As a result, a high level signal is written to the capacitor HC of the pixels PX in the first to third columns of the pixels PX in the eighth row.

  Finally, φWTR (9) is set to a high level during a period t57-t59, and φWTC (1) to φWTC (3) are set to a high level during a period t58-t60. As a result, a high level signal is written to the capacitor HC of the pixels PX in the first to third columns of the pixels PX in the ninth row.

  In this manner, a high level signal is written to the capacitor HC of the pixel PX that is hatched in FIG. 6, the selection transistor ASEL of the pixel PX is maintained in the ON state, and the hatching in FIG. 6 is applied. A low level signal is written to the capacitor HC of the non-pixel PX, the selection transistor ASEL of the pixel PX is maintained in the OFF state, and the region setting shown in FIG. 6 is realized.

  In the present embodiment, for example, as in FIG. 31, first, after writing a low level signal to the capacitors HC of all the pixels PX, the pixels PX are sequentially selected one by one, and a desired pixel in the row is selected. By writing a high level signal to the capacitor HC of PX, any desired one or a plurality of partial areas in the imaging area 21 or the entire area of the imaging area 21 can be set as an area to be read.

  Note that once the region setting period has been performed, if the next region setting period is not performed for a long time without changing the region setting, the high level signal written to the capacitor HC will decrease. May not be held properly. Therefore, even if the region setting is not changed, it is preferable to perform the region setting period within a predetermined time after the region setting period once and refresh the signal written in the capacitor HC.

  The read control is the same as in the first embodiment also in the present embodiment. Also in the present embodiment, a configuration similar to the configuration of the restricted partial region setting in the first embodiment may be adopted, or the configuration of the unconstrained partial region setting in the first embodiment may be adopted. A configuration similar to the configuration may be employed.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained. In the first embodiment, the area to be read out of the imaging area 21 is set depending on whether or not each predetermined partial area AR is included in the area to be read. In the present embodiment, the area to be read out is set. The area to be read out of the imaging area 21 is set depending on whether or not each pixel PX is included. Therefore, according to the present embodiment, the write transistor WT and the capacitor HC are required in each pixel PX, but the degree of freedom in setting the readout region in the imaging region 21 is higher than that in the first embodiment. .

  [Sixth Embodiment]

  FIG. 32 is a circuit diagram showing a schematic configuration of the solid-state imaging device 81 used in the electronic camera according to the sixth embodiment of the present invention, and corresponds to FIG. FIG. 33 is a circuit diagram showing a part of the imaging region 21 of the solid-state imaging device 81 shown in FIG. 32, and corresponds to FIG.

  32 and 33, elements that are the same as or correspond to those in FIGS. 28 and 29 are given the same reference numerals, and redundant descriptions thereof are omitted. This embodiment is different from the fifth embodiment in the following points.

  In the present embodiment, a solid-state image sensor 81 is used in place of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

  In the fifth embodiment, the selection transistor SEL is provided in each pixel PX of the imaging region 21, whereas in this embodiment, the selection transistor SEL and the connection line 26 are provided in each pixel PX of the imaging region 21. Is removed, and the drain of the selection transistor ASEL is connected to the source of the amplification transistor AMP of the pixel PX.

  In the fifth embodiment, the drains (points b in FIG. 29) of the amplification transistors AMP of all the pixels PX are connected in common by the power supply line 34, and there is amplified as the power supply voltage of the amplification transistors AMP. An effective voltage level VDD that is effective for the operation of the transistor AMP is fixedly supplied. On the other hand, in the present embodiment, the power supply line 34 is electrically separated for each row of the pixels PX, and the drain (point b in FIG. 33) of the amplification transistor AMP of each pixel PX is set for each row of the pixel PX. Are connected in common by a power supply line 34, and a power supply voltage signal φVDD is supplied from the power supply control circuit 52 as a power supply voltage of the amplification transistor AMP. When each power supply voltage signal φVDD is distinguished for each row of the pixels PX, the power supply voltage signal φVDD supplied to the drain of the amplification transistor AMP of the pixel PX in the n-th row is indicated by a symbol φVDD (n). Note that the drain of the reset transistor RST of each pixel PX is connected to the drain of the amplification transistor AMP (point b in FIG. 33) of the pixel PX by a power supply line 34.

  In the present embodiment, the power supply control circuit 52 is provided as a part of the vertical scanning circuit 22 and outputs each power supply voltage signal φVDD instead of each control signal φSEL under the control of the imaging control unit 5. Each power supply voltage signal φVDD is an effective voltage level VDD that is effective for the operation of the amplification transistor AMP, or an ineffective voltage level that is not effective for the operation of the amplification transistor AMP (here, 0V, but is not necessarily limited to 0V). The power supply control circuit 52 selectively supplies VDD or 0 V as the power supply voltage of the amplification transistor AMP of each pixel PX.

  In the present embodiment, in each pixel PX, the power supply voltage signal φVDD becomes VDD and the amplification transistor AMP operates effectively, and the power supply voltage signal φVDD becomes 0 V and the amplification transistor AMP does not operate effectively. Regarding whether or not the output signal of the pixel PX can be output to the vertical signal line 27, in the fifth embodiment, in each pixel PX, the control signal φSEL becomes high level and the selection transistor SEL is turned on and the control signal φSEL. Is substantially the same as the state in which the select transistor SEL is turned off.

  Therefore, in the present embodiment, the output signal of each pixel PX is the power supply voltage signal supplied as the power supply voltage of the amplification transistor AMP of the pixel PX while the selection transistor ASEL of the pixel PX is in the selected state (ON state). Only when φVDD is the effective voltage level VDD, the output signal of the pixel PX and the output signal of the pixel PX aligned in the column direction with respect to the pixel PX are output to the vertical signal line 27.

  In the present embodiment, the power supply control circuit 52 supplies the effective voltage level VDD as each power supply voltage signal φVDD instead of supplying the high level signal as each φSEL in the fifth embodiment, and the fifth embodiment. In this embodiment, by supplying 0V as each power supply voltage signal φVDD instead of supplying a low level signal as each φSEL, an operation similar to that of the fifth embodiment is realized.

  Also in this embodiment, the same advantages as those in the fifth embodiment can be obtained. In the present embodiment, since the selection transistor ASEL is not provided in each pixel PX, the configuration of each pixel PX is simplified.

  [Seventh Embodiment]

  FIG. 34 is a circuit diagram showing a schematic configuration of the solid-state imaging device 91 used in the electronic camera according to the seventh embodiment of the present invention, and corresponds to FIG. FIG. 35 is a circuit diagram showing a part of the imaging region 21 of the solid-state imaging device 91 shown in FIG. 34, and corresponds to FIG. 34 and 35, the same or corresponding elements as those in FIGS. 28 and 29 are denoted by the same reference numerals, and redundant description thereof is omitted.

  In the present embodiment, a solid-state image sensor 91 is used in place of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

  This embodiment is different from the fifth embodiment in that, for each of two adjacent pixels PX in the column direction, the two pixels PX are a set of a floating capacitor FD, an amplification transistor AMP, and a reset transistor RST. 27, the selection transistors SEL, ASEL, the write transistor WT, and the capacitor HC are shared, and the vertical scanning circuit 22 is replaced with the control signals φSEL, φRST, φTX as shown in FIG. The control signal φSEL, φRST, φTXA, φTXB is output.

  In FIG. 34 and FIG. 35, two pixels PX sharing one set of floating capacitor FD, amplification transistor AMP, reset transistor RST, selection transistors SEL and ASEL, write transistor WT and capacitor HC are shown as a pixel block BL. Yes. In FIGS. 34 and 35, the photodiode PD and the transfer transistor TX of the lower pixel PX in the pixel block BL are indicated by symbols PDA and TXA, respectively, and the photodiode PD of the upper pixel PX in the pixel block BL and The transfer transistors TX are indicated by symbols PDB and TXB, respectively, to distinguish them. Further, the control signal supplied to the gate of the transfer transistor TXA is φTXA, and the control signal supplied to the gate electrode of the transfer transistor TXB is φTXB to distinguish them.

  In FIGS. 28 and 29, N, n, etc. indicate pixel rows, but in FIGS. 34, 35, N, n, etc., indicate rows of the pixel block BL. One row of the pixel block BL corresponds to two rows of the pixels PX.

  The read control is the same as in the fourth embodiment also in the present embodiment. Also in this embodiment, the same configuration as the configuration of the constrained partial region in the fourth embodiment may be adopted, or the configuration of the unconstrained partial region in the fourth embodiment may be adopted. A configuration similar to the configuration may be employed.

  Also in this embodiment, the same advantages as those in the fifth embodiment can be obtained. In the present embodiment, for every two pixels PX adjacent in the column direction, the two pixels PX are a set of a floating capacitor FD, an amplification transistor AMP, a reset transistor RST, selection transistors SEL, ASEL, and a write transistor. Although the WT and the capacitor HC are shared, in the present invention, for example, for each of a predetermined number of three or more pixels PX adjacent in the column direction, the predetermined number of pixels PX includes one set of floating capacitance unit FD, amplification The transistor AMP, the reset transistor RST, the selection transistors SEL and ASEL, the write transistor WT, and the capacitor HC may be shared. In the present invention, a modification similar to the modification of the fifth embodiment to the present embodiment may be applied to the sixth embodiment.

  [Eighth Embodiment]

  FIG. 36 is a circuit diagram showing a schematic configuration of the solid-state imaging device 101 used in the electronic camera according to the eighth embodiment of the present invention, and corresponds to FIG. FIG. 37 is a circuit diagram showing one pixel PX (the pixel PX in the n-th row and the m-th column) of the solid-state imaging device 101 shown in FIG. 36, and corresponds to a part in FIG. FIG. 38 is a timing chart showing a write control signal for realizing the same setting as the setting example shown in FIG. 6 in the solid-state imaging device 101 shown in FIG. 36, and corresponds to FIG.

  36 to 38, the same or corresponding elements as those in FIG. 28, FIG. 29 and FIG. This embodiment is different from the fifth embodiment in the following points.

  In the present embodiment, a solid-state image sensor 101 is used in place of the solid-state image sensor 71 in the electronic camera according to the fifth embodiment.

  In the present embodiment, in each pixel PX, instead of the capacitor HC, an SR latch circuit 103 is used as a holding unit that holds a selection control signal for setting the selection transistor ASEL of the pixel PX to a selected state or a non-selected state. Is provided. In the present embodiment, in the solid-state imaging device 101, a reset write control circuit 102 that supplies a reset signal φWTRST that forms part of the write control signal to the reset input unit R of the SR latch circuit 103 is added. The SR latch circuit 103 can be constituted by, for example, a set of NOR gates which are not limited to this.

  The reset input portions R of the SR latch circuits 103 of all the pixels PX are commonly connected by a control line 104, and a reset signal φWTRST from the reset write control circuit 102 is supplied thereto. The set input unit S of the SR latch circuit 103 of each pixel PX is connected to the source of the write transistor WT of the pixel PX. The output part Q of the SR latch circuit 103 of each pixel PX is connected to the gate of the selection transistor ASEL of the pixel PX.

  As can be seen from comparison between FIG. 38 and FIG. 31, in this embodiment, in order to write a low level signal as a signal held in the gates of the selection transistors ASEL of all the pixels PX in the period t31 to t32, φWTR ( 1) to φWTR (9) are set to the high level, while φWTC (1) to φWTC (12) are set to the low level and only the high level is supplied to the set input portion S of the SR latch circuit 103 of all the pixels PX. Instead, the reset signal φWTRST supplied to the reset input portion R of the SR latch circuit 103 of all the pixels PX is set to the high level. In other periods, the reset signal φWTRST is maintained at a low level.

  In this embodiment, the row write control circuit 72, the column write control circuit 73, and the reset write control circuit 102 as a whole supply the write control signals φWTR, φWTC, and φWTRST to the write transistor WT as the write unit of each pixel PX. The write control unit is configured.

  In the present embodiment, the row write control circuit 72, the column write control circuit 73, the reset write control circuit 102, and the write transistor WT and the latch circuit 103 of each pixel PX are the desired one to be read out of the imaging region 21. Alternatively, an area setting unit that configures the selection transistor ASEL of the pixels PX in the plurality of partial areas to be in a selected state (ON state) is configured.

  Also in this embodiment, the same advantages as those in the fifth embodiment can be obtained. In this embodiment, the refresh operation described in the fifth embodiment is not necessary.

  In the present invention, a modification similar to the modification of the fifth embodiment to the present embodiment may be applied to the sixth and seventh embodiments. Further, instead of the capacitor HC or the SR latch circuit 103, another latch circuit or other memory may be used as the holding unit. Furthermore, a nonvolatile memory may be used as the holding unit. In this case, when the power is shut off, the entire area of the imaging area 21 is read out immediately after the power is turned on by storing the pixel in the non-volatile memory of all the pixels PX as information for the area to be read. It can be set as a state. By doing so, for example, when still image shooting is performed immediately after the power is turned on, the still image shooting can be started quickly, and the shutter chance is not missed.

  As mentioned above, although each embodiment of this invention and those modifications were demonstrated, this invention is not limited to these.

  For example, in each of the above embodiments, each of the two pixels PX adjacent in the column direction or the gates of the amplification transistors AMP of the two pixel blocks BL adjacent in the column direction are turned on and off (electrically connected and disconnected). A connection switch may be provided.

  In each of the above embodiments, the output signals of the pixels PX arranged in the same column are output to the same vertical signal line 27. However, the pixels PX arranged in the same column are divided into a plurality of groups. The pixel output signal may be output to the vertical signal line 27 that is different for each group.

  Furthermore, in the present invention, the solid-state imaging device is not limited to a single chip and may have a structure in which a plurality of chips are joined.

  In the present invention, the items of the above embodiments and their modifications may be combined as appropriate.

DESCRIPTION OF SYMBOLS 1 Electronic camera 4 Solid-state image sensor 21 Imaging area 22 Vertical scanning circuit 23 Area setting circuit 72 Row writing control circuit 73 Column writing control circuit PX Pixel PD Photodiode TX Transfer transistor AMP Amplifying transistor RST Reset transistor FD Floating capacity part SEL, ASEL selection Transistor AR Predetermined partial area BL Pixel block WT Write transistor HC capacitor

Claims (14)

A plurality of photoelectric conversion units;
A signal line for outputting a signal based on charges photoelectrically converted by the photoelectric conversion unit;
A first selection unit that is provided between the photoelectric conversion unit and the signal line and outputs the signal of the selected photoelectric conversion unit;
A second selection unit which is provided between the first selection unit and the signal line and outputs the signal of the photoelectric conversion unit output from the first selection unit to the signal line;
A solid-state imaging device.   The solid-state imaging device according to claim 1, further comprising a region setting unit that selects the first selection unit or the second selection unit of a partial region of the imaging region in which the plurality of photoelectric conversion units are arranged. The imaging area is divided into a plurality of predetermined areas,
The region setting unit supplies a selection control signal for selecting or deselecting the first selection unit or the second selection unit of the region for each of the plurality of predetermined regions. ,
The solid-state imaging device according to claim 2, wherein the partial region includes one or more of the plurality of predetermined regions.   The region setting unit includes a holding unit that holds a selection control signal for selecting or deselecting the first selection unit or the second selection unit, and the selection control signal according to a write control signal. The solid-state imaging device according to claim 2, further comprising: a writing unit that writes data, and a writing control unit that supplies the writing control signal to the writing unit. A plurality of the partial areas;
A control unit that performs read control on a row selected by the second selection unit or the first selection unit while selecting the second selection unit or the first selection unit of each row of the plurality of partial regions; The solid-state image sensor according to any one of claims 2 to 4. A plurality of photoelectric conversion units;
A signal line for outputting a signal based on charges photoelectrically converted by the photoelectric conversion unit;
A selection unit that is provided between the photoelectric conversion unit and the signal line and outputs the signal of the selected photoelectric conversion unit;
An amplification unit provided in series with the selection unit between the photoelectric conversion unit and the signal line, and outputting the signal of the photoelectric conversion unit;
A power supply control unit that selectively supplies an effective voltage level that is effective for the operation of the amplification unit or a non-effective voltage level that is not effective for the operation as a power supply voltage of the amplification unit,
A solid-state imaging device. A plurality of photoelectric conversion units;
A signal line for outputting a signal based on charges photoelectrically converted by the photoelectric conversion unit;
A first selection unit that is provided in common to two or more photoelectric conversion units of the plurality of photoelectric conversion units and outputs the signals of the selected two or more photoelectric conversion units;
A second selection unit which is provided between the first selection unit and the signal line and outputs the signal of the photoelectric conversion unit output from the first selection unit to the signal line;
A solid-state imaging device.   The solid-state imaging device according to claim 7, further comprising a region setting unit that selects the first selection unit or the second selection unit in a partial region of the imaging region in which the plurality of photoelectric conversion units are arranged. The imaging area is divided into a plurality of predetermined areas,
The region setting unit supplies a selection control signal for selecting or deselecting the first selection unit or the second selection unit of the region for each of the plurality of predetermined regions. ,
The solid-state imaging device according to claim 8, wherein the partial region includes one or more of the plurality of predetermined regions.   The region setting unit includes a holding unit that holds a selection control signal for selecting or deselecting the first selection unit or the second selection unit, and the selection control signal according to a write control signal. The solid-state imaging device according to claim 8, further comprising: a writing unit that writes data and a writing control unit that supplies the writing control signal to the writing unit. A plurality of the partial areas;
A control unit that performs read control on a row selected by the second selection unit or the first selection unit while selecting the second selection unit or the first selection unit of each row of the plurality of partial regions; The solid-state image sensor according to any one of claims 8 to 10. A plurality of photoelectric conversion units;
A signal line for outputting a signal based on charges photoelectrically converted by the photoelectric conversion unit;
A selection unit that is provided in common to two or more photoelectric conversion units of the plurality of photoelectric conversion units and outputs the signals of the selected two or more photoelectric conversion units;
An amplification unit that is provided in series with the selection unit between the two or more photoelectric conversion units and the signal line, and that outputs the signals of the two or more photoelectric conversion units;
A power supply control unit that selectively supplies an effective voltage level that is effective for the operation of the amplification unit or a non-effective voltage level that is not effective for the operation as a power supply voltage of the amplification unit,
A solid-state imaging device. A solid-state imaging device according to any one of claims 2 to 5 and 8 to 11,
A user interface for the user to command the partial area;
With
An imaging apparatus in which the partial area is set according to an instruction from the user interface. A solid-state imaging device according to any one of claims 2 to 5 and 8 to 11,
A detection unit that detects positions of a plurality of imaging targets in the imaging region based on an image signal from the solid-state imaging device;
With
An imaging apparatus in which the partial area is set according to the position detected by the detection unit.

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