JP2016092594A - Imaging device and driving method of solid state image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow for high speed acquisition of a signal required for AF operation, in a solid state image sensor having pixels for phase difference detection arranged in zigzag.SOLUTION: A solid state image sensor including a pixel region having imaging pixels and phase difference detection pixels arranged in zigzag, a column circuit to which signals from pixels arranged in the pixel region are transmitted via a vertical output line, and held in place, and an output circuit for outputting the difference signal of two signals held in the column circuit, is driven so that signals are read from two rows of phase difference detection pixels arranged in zigzag, in one horizontal scanning period.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an imaging apparatus and a method for driving a solid-state imaging element.

  There are roughly two methods as an autofocus (hereinafter abbreviated as AF) function for automatically adjusting the focal position of the taking lens. The first method is called a contrast method or the like, and a position where the contrast becomes the highest is searched based on an image captured while changing the focal position. This first method does not require a sensor for AF operation, but is not suitable for high-speed AF operation because the operation of finding a contrast peak is repeatedly performed while driving a focusing lens.

  The second method is called a phase difference detection method. For example, a digital single lens reflex camera is provided with a dedicated phase difference detection sensor, and a quick return mirror guides a part of the light flux. Although members such as dedicated sensors and mirrors occupy a large proportion in space, the amount of movement of the focal position necessary for the AF operation can be directly obtained, so that there is little need for repeated measurement and high-speed AF operation is possible.

  In recent years, instead of providing a dedicated phase difference detection sensor, a solid-state imaging device that is also used for phase difference detection is being introduced. In the solid-state imaging device also used for phase difference detection, light receiving pixels in which the photosensitive region is decentered with respect to the optical axis of the microlens are arranged at predetermined intervals in the imaging pixels. As a result, it has become possible to realize a high-speed AF operation similar to that of a conventional digital single-lens reflex camera while being low-cost and space-saving.

  Various methods have been proposed for arranging the light receiving pixels for phase difference detection in the solid-state imaging device. For example, the method described in Patent Document 1 is arranged in one horizontal line, and there is no room for correcting the influence of line deviation when obtaining a two-image correlation, and an accurate AF operation is possible. However, when information of all pixels such as a still image is used, it may be necessary to perform interpolation from surrounding pixels on the phase difference detection pixel line. Therefore, when a subject with a high-frequency component appears in the image portion, it is possible to cause image degradation such as an interpolation error.

  Further, in Patent Document 2, in a so-called Bayer arrangement, based on human image recognition characteristics, G (green) pixels with a lot of luminance information are left as imaging pixels, and R (red) pixels and B (blue) pixels A configuration is shown in which a part is replaced with a focus detection pixel. When reading a normal CMOS sensor signal with such a configuration, there is a problem that access is delayed because the signal is read from the focus detection pixels over at least two horizontal lines. In addition, there is an aspect that the horizontal two lines include G pixels unnecessary for the AF operation.

JP 2008-224801 A JP 2012-120127 A

  When signals are read from the phase difference detection pixels arranged in a staggered pattern such as R pixels and B pixels in the Bayer array, the conventional method requires a horizontal scanning period of two rows and is not necessary for the AF operation. Since signals are read up to the G pixel, high-speed AF operation is hindered. An object of the present invention is to output only signals from pixels for phase difference detection arranged in a staggered manner to the outside of a solid-state image sensor, thereby acquiring an image necessary for AF operation at high speed. Is to provide.

  The imaging apparatus according to the present invention includes imaging pixels and phase difference detection pixels in which the photosensitive region is decentered with respect to the optical axis of the microlens, and the first phase difference detection pixels are in the first pixel row. A pixel region in which a second phase difference detection pixel paired with the first phase difference detection pixel is disposed in a second pixel row adjacent to the first pixel row; The first holding means and the second holding means are provided for each column, and a signal from a pixel arranged in the pixel region is transmitted via a vertical output line, and the signal is transmitted to the first holding means and A column circuit held in the second holding means; and an output circuit for outputting a differential signal between a signal held in the first holding means of the column circuit and a signal held in the second holding means; And two adjacent solid-state image sensors in one horizontal scanning period. Arranged in behavior, and a driving circuit for driving the solid-state imaging device such that the first pixel and the signal from the second pixel for phase difference detection in the phase difference detection to be set is read.

  According to the present invention, in one horizontal scanning period, signals from two rows of phase difference detection pixels can be read and output to the outside of the solid-state imaging device, and signals necessary for AF operation can be output at high speed. It can be acquired.

It is a figure which shows the structural example of the imaging device in embodiment of this invention. It is a figure which shows the example of the imaging | photography sequence in this embodiment. It is a figure which shows the structural example of the solid-state image sensor in 1st Embodiment. It is a figure which shows the structural example of the solid-state image sensor in 1st Embodiment. 6 is a timing chart illustrating an example of driving the solid-state imaging device according to the first embodiment. It is a timing chart which shows the example of a drive of the solid-state image sensor in 2nd Embodiment. It is a figure which shows the structural example of the solid-state image sensor in 3rd Embodiment. 10 is a timing chart illustrating an example of driving a solid-state imaging device according to the third embodiment. It is a figure which shows the structural example of the solid-state image sensor in 4th Embodiment. It is a timing chart which shows the example of a drive of the solid-state image sensing device in a 4th embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, the overall configuration of an imaging apparatus according to an embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to the present embodiment. In FIG. 1, a photographic optical system 1 has a diaphragm, a mechanical shutter, a focusing lens, and the like. The solid-state imaging device 2 photoelectrically converts the subject image formed by the photographing optical system 1 and takes it out as an electrical signal. Details of the solid-state imaging device 2 will be described later.

  The A / D conversion unit (analog-digital conversion unit) 3 converts the analog image signal output from the solid-state imaging device 2 into a digital image signal. The A / D conversion unit 3 may be on-chip on the solid-state imaging device 2. The image signal digitized by the A / D conversion unit 3 is stored in the image memory 7 and subjected to various signal processing such as white balance correction and gamma correction by the signal processing circuit 6. Further, the signal processing circuit 6 performs an AF process for calculating a moving amount of the focal position based on a pixel signal from a phase difference detection pixel included in the solid-state imaging device 2.

  The image signal subjected to the signal processing by the signal processing circuit 6 is recorded on the recording medium 9 via the recording circuit 8 which is an interface circuit, for example. For example, an image signal subjected to signal processing can be directly displayed on a display device 11 such as a liquid crystal display through a display circuit 10 which is an interface circuit. Further, the display device 11 can also perform live view display for continuously displaying images to be taken in the future and playback display of recorded moving images.

  The timing generation circuit 4 drives an imaging system such as the photographing optical system 1 and the solid-state imaging device 2 through the driving circuit 5. Further, the timing generation circuit 4 drives and controls the A / D conversion unit 3 in synchronization with the driving of the imaging system and thus with the output signal of the solid-state imaging device 2. The system control unit 12 controls the entire imaging apparatus. The system control unit 12 performs various controls by, for example, reading and executing a program temporarily stored in a volatile memory (ROM: Read Only Memory) 13. A non-volatile memory (RAM: Random Access Memory) 14 stores programs and various data to be transferred when processing is performed in the imaging apparatus.

  In the present embodiment, as shown in FIG. 2, it is assumed that an imaging period for acquiring an image signal corresponding to a subject image and an AF period for performing an autofocus (AF) operation exist independently in time. ing. In the focus adjustment state of the imaging optical system 1 in the imaging period, imaging is performed with the focus adjustment result in the previous AF period being fed back. In addition, each embodiment described below defines a reading method of the solid-state imaging device 2 in the AF period, and does not limit the reading method in the imaging period.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 3 is a diagram illustrating a configuration example of the solid-state imaging device 2 according to the first embodiment. As shown in FIG. 3, the solid-state imaging device 2 has a pixel region 20 in which a subject image is formed by the photographing optical system 1. In the pixel region 20, a plurality of pixels each having a photoelectric conversion unit, a transfer unit, a reset unit, and the like are arranged two-dimensionally at equal intervals in the horizontal direction and the vertical direction.

  Further, in the solid-state imaging device 2, basically, pixels provided with red (R), green (G), and blue (B) color filters are arranged in a Bayer array. In the example shown in FIG. 3, the pixels for phase difference detection (focus detection) are arranged in a staggered manner in such a manner that R pixels and B pixels are replaced by two lines every eight lines. That is, a phase difference detection pixel is arranged at the position of the R pixel in one pixel row, and a phase difference detection pixel is arranged at the position of the G pixel in one pixel row adjacent thereto. This is repeated every 8 pixel rows. In the present embodiment, as the phase difference detection pixel, a SHA pixel in which a part of the photoelectric conversion unit is shielded from light is arranged at a position corresponding to the R pixel, and the SHA pixel is photoelectrically symmetrical with the SHA pixel at a position corresponding to the B pixel. SHB pixels in which a part of the conversion unit is shielded are arranged. An image for phase difference detection is generated based on these signals by combining the SHA pixel and the SHB pixel.

  FIG. 4A shows the pixels in the first and second rows of the solid-state imaging device 2 shown in FIG. In FIG. 4A, reference numeral 200 denotes a microlens that includes a G pixel, an R pixel, and a B pixel, and a photoelectric conversion portion of a phase difference detection pixel (SHA pixel and SHB pixel) within the diameter thereof. . Note that the SHA pixel and the SHB pixel for detecting the phase difference have their photosensitive areas eccentric to the left and right with respect to the optical axis of the microlens 200, respectively.

  The photoelectric conversion unit 201 (201a, 201b) converts an optical signal into an electric signal by photoelectric conversion. The photoelectric conversion unit 201 (201a, 201b) includes an N-type semiconductor region and also functions as a charge storage unit. The signal charge generated in the photoelectric conversion unit 201a is transferred to the charge / voltage conversion unit 202 via the transfer transistor 203a. The signal charge generated in the photoelectric conversion unit 201b is transferred to the charge / voltage conversion unit 202 via the transfer transistor 203b.

  The charge-voltage converter 202 is shared by two pixels in the vertical direction. The charge-voltage converter 202 can individually transfer the signal charges from the photoelectric converters 201a and 201b by controlling the transfer transistors 203a and 203b by the control lines Txa and Txb of the respective transfer transistors. In FIG. 3, the control lines for the transfer transistors are shown only for the first row (Txa (1)) and the second row (Txb (1)), and the other rows are not shown.

  The transfer transistor 203 (203a, 203b) is turned on when a signal supplied via the control line of the transfer transistor is at a high level, and is turned off when the signal is at a low level. A plurality of transfer transistor control lines are provided in common to the photoelectric conversion units arranged in the horizontal direction. The charge-voltage conversion unit 202 also includes an N-type semiconductor region, and also functions as a charge storage unit like the photoelectric conversion unit. The proper use of the function as the charge storage unit only corresponds to before and after the transfer of the signal charge from the photoelectric conversion unit 201 to the charge voltage conversion unit 202.

  The charge-voltage converter 202 can be reset to the power supply voltage VDD via a reset transistor 204 controlled by a signal supplied via a control line Rx. By applying a high level signal to the control line Rx, the reset transistor 204 is turned on, and the charge voltage conversion unit 202 is reset.

  Since the reset transistor 204 is turned off after the reset, the charge-voltage conversion unit 202 is in an electrically floating state. After that, when the signal charge is transferred from the photoelectric conversion unit 201, the charge-voltage conversion unit 202 drops the potential from the power supply voltage VDD by an amount corresponding to the transferred signal charge, and reads this as a signal to make analog Outputs electrical signals.

  Note that the potential corresponding to the signal charge is a potential obtained by dividing the signal charge amount by the capacitance of the charge-voltage conversion unit 202 and multiplying by a voltage amplification factor of a source follower circuit described later. In FIG. 3, the reset transistor control line Rx and the power supply voltage VDD are only shown for the charge voltage converter shared by the first row and the second row, and for the other charge voltage converters. The illustration is omitted.

  Further, the charge-voltage conversion unit 202 is connected to the gate of the amplification transistor 205. The amplification transistor 205 includes a constant current source and a source (not shown) connected to the m-th column vertical output line (column output line) Vm by the ON operation of the selection transistor 206 controlled by a signal supplied from the control line Sx. A follower circuit is configured to transmit a potential corresponding to the signal charge. In FIG. 3, the control line Sx of the selection transistor 206 is also shown only for the charge voltage conversion unit shared by the first row and the second row, and the illustration for the other charge voltage conversion unit is omitted. Yes.

  The vertical output lines Vm are commonly connected to a plurality of pixels in the vertical direction in the pixel region 20, while the charge-voltage conversion units 202 arranged in the horizontal direction exist on a one-to-one basis for each column. ing. Each element in the handling such as the conversion from the signal charge to the voltage and the signal amplification related to the reading of the pixel signal from the pixel as described above is conventionally known.

  In FIG. 3, a solid-state imaging device 2 in which pixels for 16 rows × 8 columns are arrayed at equal intervals in the vertical direction and the horizontal direction is shown as an example, which also serves as an imaging pixel and a phase difference detection pixel. The number of pixels in the pixel region 20 of 16 rows × 8 columns is set for the sake of simplicity, and practically, about several million to tens of millions of pixels are used. Here, the control lines Rx, Txa, Txb, and Sx related to the pixels are controlled in conjunction with the vertical row designation by the vertical scanning circuit 21.

  In the example shown in FIG. 3, the vertical output line Vm is commonly connected by the eight charge voltage conversion units 202 in the vertical direction, while one of the eight charge voltage conversion units 202 arranged in the horizontal direction for each column. There are a total of eight corresponding to one pair. The eight vertical output lines Vm are connected to the first signal storage section of the column circuit section 24 having the configuration shown in FIG.

  Here, when the value of m is an odd number, the first signal storage unit has capacitors C1mN and C1mS. When the value of m is an even number, the first signal storage unit has capacitors C1mM and C1mP. Have. Further, P1_N and P1_S are connected as control lines to the transistors for writing to the first signal storage portion having the capacitors C1mN and C1mS, respectively. P1_M and P1_P are connected as control lines to the transistors for writing to the first signal storage unit having the capacitors C1mM and C1mP, respectively. As described above, in the present embodiment, the potential of the vertical output line Vm is written and held in the first signal storage unit in the column circuit 24 by using different control lines separately for the case where the value of m is an odd number and the case of an even number. To do.

  A second signal storage unit is provided following the first signal storage unit of the column circuit 24. When the value of m is an odd number, the second signal storage unit has capacitors C2mN and C2mS. When the value of m is an even number, the second signal storage unit has capacitors C2mM and C2mP. The capacitors C2mN, C2mS, C2mM, and C2mP as the second signal storage unit function as a memory for one row that further transfers the potentials of the capacitors C1mN, C1mS, C1mM, and C1mP of the first signal storage unit as signals. Realize.

  The capacitor C1mN of the first signal storage unit and the capacitor C2mN of the second signal storage unit are connected via a transfer transistor, and the capacitor C1mS of the first signal storage unit and the capacitor C2mS of the second signal storage unit are connected via a transfer transistor. Connected. The capacitor C1mM of the first signal storage unit and the capacitor C2mM of the second signal storage unit are connected via a transfer transistor, and the capacitor C1mP of the first signal storage unit and the capacitor C2mP of the second signal storage unit are connected to the transfer transistor. Connected through. The transfer transistors between the capacitor of the first signal storage unit and the capacitor of the second signal storage unit are commonly connected to the control line P2.

  Note that an amplifier circuit that amplifies the signal voltage may be provided before the first signal storage unit of the column circuit 24. The amplifier circuit is widely used because it is useful as a means for reducing dark noise during shooting with high shooting sensitivity (high ISO sensitivity), but is not an essential configuration for the present invention and is therefore omitted in FIG. doing. Further, a so-called voltage follower circuit may be provided as a buffer immediately before the second signal storage unit of the column circuit 24. The voltage follower circuit has a function of driving the capacitive load of the second signal storage unit in a sufficiently early time and transmitting a potential equal to the potential stored in the first signal storage unit to the second signal storage unit.

  The vertical scanning circuit 21 performs vertical row designation so that the transfer transistor, the reset transistor, and the selection transistor included in the pixel are sequentially turned on in the vertical direction in accordance with timing described below. The horizontal scanning circuit 22 selectively and sequentially scans the potential accumulated in the capacitors C2mN, C2mS, C2mM, and C2mP as the second signal accumulation unit of the column circuit 24 in the horizontal direction so as to be output to the output circuit 23.

  The output circuit 23 outputs a difference signal between the potential when the charge-voltage conversion unit 202 is in a floating state after resetting and the S signal potential after transferring the signal charge from the photoelectric conversion unit 201. The output circuit 23 has, for example, a differential circuit configuration that subtracts and outputs a potential after signal charge transfer and a potential before signal charge transfer. Thereby, a so-called SN signal from which noise has been removed can be obtained.

  The signal line connected to the output circuit 23 may be referred to as a horizontal output line. Further, the horizontal scanning and the output of the difference signal may be collectively referred to as horizontal transfer. Further, during potential transfer from the second signal storage unit of the column circuit 24 to the horizontal output line, the capacitance between the second signal storage unit (capacitance value C2) and the capacity of the horizontal output line (capacitance CH). As a result, the signal drops to a capacity division ratio C2 / (C2 + CH) times. Therefore, the difference between the lowered potentials is output from the output circuit 23.

  FIG. 5 is a timing chart showing an example of driving the solid-state imaging device in the first embodiment. FIG. 5 shows a signal readout operation from the phase difference detection pixel in the solid-state imaging device according to the first embodiment. The driving shown in FIG. 5 is realized by the timing generation circuit 5. Hereinafter, the operation of the solid-state imaging device 2 will be described with reference to the timing chart shown in FIG.

  In FIG. 5, as indicated by the horizontal synchronization signal, the vertical scanning circuit 21 simultaneously selects the first row and the second row where the pixels for detecting the phase difference are present, and the values of the respective control lines are set to the time. Shown for each. Therefore, when the operation shown in FIG. 5 is completed, the vertical scanning circuit 21 selects the ninth row and the tenth row and repeats the same operation as in FIG. Hereinafter, such repetition is continued until there are no selectable rows where pixels for phase difference detection exist.

  At time t1 shown in FIG. 5, with the rise of the horizontal synchronization signal, the signal level of the control line Sx (1) of the selection transistor 206 in the selected pixel row (first row and second row) is set to high level. As a result, all the charge-voltage conversion units 202 of the pixels existing in the selected pixel row are connected to the vertical output line Vm.

  At time t2, the signal level of the control line Rx (1) of the reset transistor 204 becomes high level, and all the charge voltage conversion units 202 shared by the first row and the second row are reset to the power supply voltage VDD. In this way, the potential of the charge-voltage conversion unit 202 is approximately VDD. This potential state hardly changes at time t3 when the signal level of the control line Rx (0) becomes low level, the reset transistor 204 is turned off, and the reset is released. Note that the horizontal sync signal has fallen before time t2, but this is only required if the high period is maintained for a period sufficient as information of the sync signal, so the fall time is not limited. Absent.

  At time t3, the reset transistor 204 is turned off, so that the charge-voltage conversion unit 202 is in a floating state. At time t4, the signal level of the control line P1_N is set to the high level in order to transfer the potential of the charge-voltage conversion unit 202 in the odd-numbered column in such a floating state as a signal to the capacitor C1mN of the column circuit 24. . At time t5, the signal level of the control line P1_N is set to a low level.

  Next, at time t6, the signal level of the control line Txa (1) of the transfer transistor 203a becomes a high level, and all of the signal charges photoelectrically converted and accumulated in the photoelectric conversion unit 201a of the pixel existing in the first row. Is transferred to the charge-voltage converter 202. At time t7 when a sufficient period for signal charge transfer has elapsed from time t6, the signal level of the control line Txa (1) becomes low level.

  Next, at time t8, the signal level of the control line P1_S is set to a high level. As a result, the potential of the charge-voltage conversion unit 202 in the odd-numbered column is transferred as a signal and held in the capacitor C1mS as the first signal storage unit of the column circuit 24. The potential of the charge-voltage conversion unit 202 in the odd-numbered column at this time is a potential obtained by adding the potential corresponding to the signal charge of the photoelectric conversion unit 201 of the SHA pixel for phase difference detection to the above-described floating (floating) state potential. is there. At time t9, the signal level of the control line P1_S becomes low level.

  In addition, the control line P1_M is pulsed to the high level at the same timing as the control line P1_S, and the potential of the charge-voltage conversion unit 202 in the even-numbered column is transferred as a signal to the capacitor C1mM as the first signal accumulation unit of the column circuit 24. , Retained. At this time, the potential of the charge-voltage conversion unit 202 in the even-numbered column is a potential obtained by adding a potential corresponding to the signal charge of the photoelectric conversion unit 201 of the G pixel to the potential in the floating state.

  At time t10, the signal level of the control line Txb (1) of the transfer transistor 203b becomes a high level, and all the signal charges photoelectrically converted and accumulated in the photoelectric conversion unit 201b of the pixels existing in the second row are charged. It is transferred to the voltage converter 202. At time t11 when a sufficient period for signal charge transfer has elapsed from time t10, the signal level of the control line Txb (1) becomes low level.

  Next, at time t12, the signal level of the control line P1_P is set to a high level. As a result, the potential of the charge-voltage conversion unit 202 in the even column is transferred as a signal and held in the capacitor C1mP as the first signal storage unit of the column circuit 24. At this time, the electric potentials of the charge-voltage converters 202 in the even-numbered columns are set to the above-described floating (floating) potential, and the photoelectric charges of the G pixels existing in the first row and the SHB pixels for phase difference detection existing in the second row. This is a potential obtained by adding a potential corresponding to the signal charge of the conversion unit 201. At time t13, the signal level of the control line P1_P becomes low level. Further, at time t13, the signal level of the control line Sx (0) becomes a low level, and the selection of the pixels in the first row and the second row where the pixels for detecting the phase difference are present is finished.

  The above is a period corresponding to a so-called first horizontal blanking period in the driving timing of the solid-state imaging device 2 in the first embodiment. The horizontal transfer period overlaps the first horizontal blanking period in time as indicated by the horizontal scanning signal in the timing chart of FIG. This is because the signal level of the control line P <b> 2 becomes a high level in a pulse shape from time t <b> 14 to time t <b> 15, which is the second horizontal blanking period, and signals for the SHA pixel and SHB pixel for phase detection This is because it is transferred to the second signal storage unit.

  Specifically, the SHA pixels existing in the first row are transferred to the capacitors C2mS and C2mN of the second signal storage unit as the signal potential and floating state potential of the SHA pixel. Further, the SHB pixels existing in the second row are transferred to the capacitors C2mP and C2mM of the second signal storage unit as (the signal potential of the SHB pixel + the signal potential of the G pixel) and the signal potential of the G pixel.

  Therefore, if the horizontal scanning circuit 22 is driven to selectively output these difference signals, the pixel signal from the SHA pixel is obtained as a difference between the signal stored in the capacitor C2mS and the signal stored in the capacitor C2mN. be able to. Further, the pixel signal from the SHB pixel can be obtained as a difference between the signal stored in the capacitor C2mP and the signal stored in the capacitor C2mM. In other words, the signal of the SHB pixel in the even-numbered column can be differentially read with reference to the signal of the G pixel in the first row sharing the charge-voltage conversion unit 202. Meanwhile, during the first horizontal blanking period, the next row can be driven.

  As a result, even in a solid-state imaging device having phase detection SHA pixels and SHB pixels arranged in a staggered pattern, the SHA pixels and SHBs are directly connected to the horizontal output line and the output terminal 23 in one horizontal scanning period. Pixel signals can be read out. In addition, signals of G pixels that are arranged in the same pixel row as the SHA pixels and SHB pixels for phase detection and are unnecessary for the AF operation are not read out to the outside. According to the present embodiment, the signal readout time required for the AF operation can be shortened by one horizontal scanning period as compared with the conventional case, and the signal necessary for the AF operation is acquired at high speed. It becomes possible.

  Note that when signals are read out from the pixels in the row in which the imaging pixels are present, driving is performed so that only the control line Txa is set to the high level in the first horizontal scanning period without being distinguished by the value of m. As a result, if the pixel signal potential composed of the R pixel and the G pixel and the floating state potential of the charge-voltage conversion unit 202 obtained by starting up the control lines P1_N and P1_M in the same period are subtracted, SN is performed as usual. Can be obtained for each row. In the second horizontal scanning period, it is possible to drive only the control line Txb to a high level, and similarly, it is possible to read a signal from an imaging pixel row composed of SN pixels and B pixels. .

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the configuration of the solid-state imaging device 2 similar to that of the first embodiment (FIG. 3), the signals of the SHA pixel and the SHB pixel can be read out in one horizontal scanning period even if driving different from that in FIG. 5 is performed. . In the second embodiment described below, the signal readout operation from the phase difference detection pixels in the solid-state imaging device is different from the first embodiment, and the others are the same, so the description thereof is omitted.

  FIG. 6 is a timing chart illustrating a driving example of the solid-state imaging device according to the second embodiment. The operation from time t21 to time t27 is the same as the operation from time t1 to t7 in the first embodiment shown in FIG.

  At time t28, the signal level of the control line P1_S is set to a high level. As a result, the potential of the charge-voltage conversion unit 202 in the odd-numbered column is transferred as a signal to the capacitor C1mS as the first signal storage unit of the column circuit 24. The potential of the charge-voltage conversion unit 202 in the odd-numbered column at this time is a potential obtained by adding the potential corresponding to the signal charge of the photoelectric conversion unit 201 of the SHA pixel for phase difference detection to the above-described floating (floating) state potential. is there. At time t29, the signal level of the control line P1_S becomes low level. Note that, in the time t28 to the time t29, unlike the first embodiment, the second embodiment does not transfer the G pixel signals in the first row to the first signal accumulation unit through the control line P1_M.

  At time t30, the signal level of the control line Rx (1) of the reset transistor 204 becomes a high level, and all the charge voltage conversion units 202 shared by the first row and the second row are reset to the power supply voltage VDD. At time t31, since the reset transistor 204 is turned off, the charge-voltage conversion unit 202 is in a floating state. At time t32, the signal level of the control line P1_M is set to the high level in order to transfer the potential of the charge-voltage conversion unit 202 in the even-numbered column in such a floating state as a signal to the capacitor C1mM of the column circuit 24. . At time t33, the signal level of the control line P1_M is set to a low level.

  At time t34, the signal level of the control line Txb (1) of the transfer transistor 203b becomes a high level, and all the signal charges photoelectrically converted and accumulated in the photoelectric conversion unit 201b of the pixels existing in the second row are charged. It is transferred to the voltage converter 202. At time t35 when a sufficient period for signal charge transfer has elapsed from time t34, the signal level of the control line Txb (1) becomes low level.

  Next, at time t36, the signal level of the control line P1_P is set to a high level. As a result, the potential of the charge-voltage conversion unit 202 in the even column is transferred as a signal to the capacitor C1mP as the first signal storage unit of the column circuit 24. At this time, the electric potential of the charge-voltage conversion unit 202 in the even-numbered column corresponds to the signal charge of the photoelectric conversion unit 201 of the phase difference detection SHB pixel existing in the second row to the above-described floating (floating) potential. This is the potential with the potential applied. At time t37, the signal level of the control line P1_P becomes low level. Further, at time t37, the signal level of the control line Sx (0) becomes a low level, and the selection of the pixels in the first row and the second row where the pixels for detecting the phase difference are present is finished. After time t38, it is the same as after time t14 in the first embodiment shown in FIG.

  As can be seen from comparison with FIG. 4, in the second embodiment, the charge-voltage conversion unit 202 needs to be reset twice, so that the first horizontal blanking period is longer than that in the first embodiment. However, without changing the configuration of the solid-state imaging device 2, it is possible to extract only the signals of the SHA pixels and SHB pixels to the outside of the solid-state imaging device 2 in one horizontal scanning period, and signals necessary for the AF operation Can be acquired at high speed.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the first embodiment and the second embodiment, an example in which the charge-voltage conversion unit 202 is shared by two pixels in the vertical direction is shown as the configuration of the solid-state imaging device 2, but the configuration is not limited thereto. As shown in FIG. 7, each pixel may have a charge / voltage conversion unit 202.

  FIG. 7 is a diagram illustrating a configuration example of the solid-state imaging layer element according to the third embodiment. In FIG. 7, the same components as those shown in FIG. 4A are denoted by the same reference numerals, and a duplicate description is omitted. Even when configured as shown in FIG. 7, as in the first embodiment, the control lines that can control the write transistors to the first signal storage unit are provided at different timings in the even columns and the odd columns. The timing chart shown in FIG. 5 or 6 can be modified and applied.

  FIG. 8 is a timing chart showing an example of driving the solid-state imaging device in the third embodiment. FIG. 7 shows a driving example based on the same concept as in the second embodiment in the configuration of the solid-state imaging device 2 in the third embodiment. Main differences from the driving example shown in FIG. 6 shown in the second embodiment are as follows.

  First, from time t49, the control line Sx (2) of the selection transistor in the second row becomes high level, and the control line Sx (1) becomes low level, that is, the second row is selected instead of the first row. From time t50 to time t51, the signal level of the control line Rx (2) of the reset transistor in the second row becomes a high level, and the charge voltage conversion unit 202 in the second row is reset. From time t <b> 52 to time t <b> 53, the signal level of the control line P <b> 1 </ b> _M becomes high level, and the charge potential conversion unit 202 accumulates the floating potential. From time t54 to time t55, signal charge transfer of the first row transferred by the control line Tx (2) is performed. From time t56 to time t57, the potential corresponding to the SHB pixel signal is transferred to the first signal accumulation unit by the control line P1_P.

  As described above, regardless of the shared configuration of the charge-voltage conversion unit 202 of the solid-state image sensor 2, only the signals of the SHA pixel and the SHB pixel can be taken out of the solid-state image sensor 2 in one horizontal scanning period. It becomes possible to acquire signals necessary for the AF operation at high speed.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, by changing the configuration of the control line of the transfer transistor in the pixel portion, a reading method that is simpler and more effective than the above-described embodiments is realized. In the fourth embodiment, as shown in FIG. 9, the transfer transistor control line Txa in the shared column (that is, m is an even column) of the charge-voltage conversion unit 202 of the SHB pixel for phase detection and the G pixel is used. Cross Txb.

  FIG. 9 is a diagram illustrating a configuration example of the solid-state imaging layer element according to the fourth embodiment. In FIG. 9, the same components as those shown in FIG. 4A are denoted by the same reference numerals, and redundant description is omitted. In the fourth embodiment, the control line Txb controls the transfer of signal charges of the G pixel, and the control line Txa controls the transfer of signal charges of the SHA pixel and the SHB pixel. Note that such a cross structure of Tx wirings may be applied only to a row where pixels for phase difference detection exist, or may be applied to a row where pixels for imaging exist. In the latter case, the charge transfer of the imaging pixel G signal is controlled by the control line Txb, and the charge transfer of the imaging pixel R signal and the B signal is controlled by the control line Txa.

  In the fourth embodiment, a detailed timing chart is shown in FIG. 10, but in order to obtain a signal necessary for the AF operation, only the signal level of the control line Txa needs to be set to the high level. Compared with the first embodiment, since it is not necessary to read the superimposed charge of the SHB pixel and the G pixel, signals of the SHA pixel and the SHB pixel can be obtained by simple driving from time t61 to time t69. Further, since the control lines P1_N and P1_M and the control lines P1_S and P1_P need only perform the same operation regardless of the value of the column number m as shown in the figure, the drive becomes easy.

  Also in the fourth embodiment, signals necessary for the AF operation can be read out in one horizontal scanning period, and signals necessary for the AF operation can be acquired at high speed. In addition, signals of G pixels that are arranged in the same pixel row as the SHA pixels and SHB pixels for phase detection and are unnecessary for the AF operation are not read out to the outside.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

2: Solid-state imaging device 4: Timing generation circuit 5: Drive circuit 6: Signal processing circuit 7: Image memory 12: System control unit 20: Pixel area 21: Vertical scanning circuit 22 Horizontal scanning circuit 23: Output circuit 24: Column circuit 200 : Micro lens 201: Photoelectric conversion unit 202: Charge voltage conversion unit 203: Transfer transistor 204: Reset transistor 205: Amplification transistor 206: Selection transistor Vm: Vertical output line (column output line)

Claims (5)

A pixel for detecting a phase difference in which a photosensitive region is decentered with respect to an optical axis of the imaging pixel and the microlens; the first phase difference detecting pixel is disposed in a first pixel row; A pixel region in which a second phase difference detection pixel paired with a phase difference detection pixel is arranged in a second pixel row adjacent to the first pixel row; a first holding unit; 2 holding means for each column, a signal from a pixel arranged in the pixel region is transmitted via a vertical output line, and the signal is held in the first holding means and the second holding means. A solid-state imaging device, and a column circuit that outputs a differential signal between the signal held in the first holding unit and the signal held in the second holding unit of the column circuit;
In one horizontal scanning period, a signal is output from the first phase difference detection pixel and the second phase difference detection pixel that are arranged in two adjacent pixel rows of the solid-state imaging device. An image pickup apparatus comprising: a drive circuit that drives the solid-state image pickup device so as to be read out. The solid-state imaging device includes the second phase difference detection paired with a pixel in a first pixel row in which the first phase difference detection pixel is arranged and the first phase difference detection pixel. Each pixel has a charge-to-voltage converter that is shared with the pixels in the second pixel row in which the pixels for pixels are arranged and to which signal charges from the pixels are transferred,
When the drive circuit reads a signal from the first phase difference detection pixel and the second phase difference detection pixel that form a pair, the drive circuit sets the potential in a state in which the reset of the charge voltage conversion unit is released. The corresponding signal is read out and held in the first holding unit in the column in which the first phase difference detection pixels are arranged, and the signal from the pixel in the first pixel row is sent to the charge voltage conversion unit. A signal corresponding to the potential in the transferred state is read out, and the second holding means and the second phase difference detection pixel in the column in which the first phase difference detection pixel is arranged are arranged. Depending on the potential in a state where the signal from the pixel in the first pixel row and the signal from the pixel in the second pixel row are transferred to the charge-voltage conversion unit. And the second phase difference detection pixel is arranged. Imaging device according to claim 1, characterized in that held in the second holding means columns.   The drive circuit resets a charge-voltage conversion unit to which a signal charge from the pixel is transferred when reading a signal from the first phase difference detection pixel and the second phase difference detection pixel that form a pair Read out a signal corresponding to the potential in a state in which the first phase difference detection pixel is released, and holds the signal in the first holding means in the column in which the first phase difference detection pixels are arranged, and from the pixels in the first pixel row A signal corresponding to a potential in a state where the signal is transferred to the charge voltage conversion unit is read and held in the second holding unit in the column in which the first phase difference detection pixels are arranged, and the charge voltage A signal corresponding to a potential in a state in which the reset of the charge-voltage conversion unit is released after resetting the conversion unit is read into the first holding unit in the column in which the second phase difference detection pixels are arranged. Hold from the pixels of the second pixel row A signal corresponding to a potential in a state where the signal is transferred to the charge-voltage converter is read and held in the second holding unit in the column in which the second phase difference detection pixels are arranged. The imaging apparatus according to claim 1. The solid-state imaging device includes the second phase difference detection paired with a pixel in a first pixel row in which the first phase difference detection pixel is arranged and the first phase difference detection pixel. Each pixel has a charge-to-voltage converter that is shared with the pixels in the second pixel row in which the pixels for pixels are arranged and to which signal charges from the pixels are transferred,
Transfer of signal charges from the first phase difference detection pixel and the second phase difference detection pixel to the charge voltage conversion unit in the set is based on a signal supplied through the same control line. The imaging apparatus according to claim 1, wherein the imaging apparatus is performed. A pixel for detecting a phase difference in which a photosensitive region is decentered with respect to an optical axis of the imaging pixel and the microlens; the first phase difference detecting pixel is disposed in a first pixel row; A pixel region in which a second phase difference detection pixel paired with a phase difference detection pixel is arranged in a second pixel row adjacent to the first pixel row; a first holding unit; 2 holding means for each column, a signal from a pixel arranged in the pixel region is transmitted via a vertical output line, and the signal is held in the first holding means and the second holding means. For driving a solid-state imaging device, and an output circuit that outputs a difference signal between a signal held in the first holding unit and a signal held in the second holding unit of the column circuit And arranged in two adjacent pixel rows of the solid-state image sensor in one horizontal scanning period. A solid-state imaging device, wherein the solid-state imaging device is driven so that a signal is read out from the first phase-difference detection pixel and the second phase-difference detection pixel that are set. Driving method.

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