JP7497938B2 - Display device - Google Patents

Description

The present invention relates to a display device that displays images in multiple display areas.

Display devices that are installed in a specific location, such as inside a station, and display information such as train information moving in one direction on a display with many LEDs arranged on it, known as scrolling display (or sliding display), have been widely used. For example, Patent Document 1 discloses a display device that reduces the load on software by using hardware to process memory bit shifts for scrolling, so that the scrolling speed is not affected even when the amount of displayed content is large.

Japanese Patent Application Laid-Open No. 9-22269

However, for display devices capable of scrolling information such as train guides, there is a demand for so-called multi-window display, in which the display surface of an LED display is divided into multiple display areas and images including text are displayed according to a display mode (e.g., fixed display, scrolling display, etc.) set for each display area.

However, if a conventional display device such as that disclosed in Patent Document 1 is to be made compatible with multi-window display, it would be necessary to provide hardware for each of the multiple display areas in accordance with the display mode, which would inevitably complicate the device configuration and increase costs. In addition, if changes are made to the layout or display mode of the display areas, it would be necessary to modify the hardware to accommodate the changes, which makes it difficult to operate the display device flexibly.

If you try to support multi-window display by improving software instead of using hardware processing, as the number of display areas that perform scrolling increases, it becomes more difficult to complete the redrawing process of the image in that display area within the specified time, and there is a high possibility that the scrolling image will stop for a moment or that synchronization between display areas will be lost.

The present invention has been made with the above points in mind, and aims to provide a display device with a simple configuration that can display changing images in multiple display areas, and that can be operated flexibly and at low cost.

In order to achieve the above object, one aspect of the present invention provides a display device that displays an image in each display area of a display unit having a plurality of display areas, the display device including a recording unit in which an image for each display area is recorded, and a control unit that specifies a display portion of each image recorded in the recording unit based on start information and length information and displays the specified display portion in each display area, the control unit being capable of changing the start information or the length information, and the control unit changes the length information to change the width of the corresponding display area of the display unit and change the image to be displayed in the display area .

According to the display device, for each image for each display area recorded in the recording unit, the display portion to be displayed in each display area is specified based on the leading information and length information that can be changed, and the display portion of the specified image is displayed in the corresponding display area. This allows the image to be displayed in each display area while being changed using the leading information and length information, which are information with a small processing load, without providing hardware corresponding to the display mode of each display area. Such a display device has a simple configuration and can be realized at low cost. Furthermore, even if a change occurs in the layout or display mode of the display area, the leading information or length information can be changed in response to the change, so that flexible operation is possible. Furthermore, the control unit changes the length information, changing the width of the corresponding display area of the display unit and changing the image to be displayed in the display area, thereby enabling even more flexible operation of the display device.

1 is a block diagram showing a schematic configuration of a display device according to an embodiment of the present invention. 4 is a plan view showing a specific configuration example of the LED module in the above embodiment. FIG. FIG. 11 is a diagram showing an example of a train guide displayed on an LED module in the embodiment. 10 is a flowchart for explaining a display operation of train guidance in the embodiment. 11 is a conceptual diagram showing initial image data recorded in the memory of the controller board by the first writing process after the device is started up. FIG. 10A and 10B are conceptual diagrams showing the transition of image data for display areas A1 and A2 recorded in the memory of the controller board in the embodiment. FIG. 2 is a conceptual diagram for explaining processing in the FPGA of the embodiment. 5A to 5C are conceptual diagrams showing transitions of images displayed in display areas A1 and A2 of the LED module in the embodiment. 10A to 10C are conceptual diagrams showing the transition of image data for a display area A3, etc., recorded in the memory of the controller board in the embodiment. 10A to 10C are conceptual diagrams showing transitions of images displayed in the display area A3 of the LED module in the embodiment. 11A and 11B are conceptual diagrams showing changes in image data for display areas A1 and A2 recorded in the memory of the controller board in a modified example related to the above embodiment. 10A and 10B are conceptual diagrams showing transitions of images displayed in display areas A1 and A2 of the LED module in the above modified example.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a block diagram showing a schematic configuration of a display device according to an embodiment of the present invention. In Fig. 1, the display device 1 includes, for example, an LED module 10, a CPU board 30 and a controller board 50 for causing the LED module 10 to display an image, and a connector board 70 for connecting the LED module 10 and the controller board 50. The CPU board 30 includes a CPU 31, a memory 32, and a driver 33. The controller board 50 includes memories 51 and 52, and an FPGA (Field Programmable Gate Array) 53. Note that the "image" in the present invention includes images that represent letters, numbers, symbols, pictograms, etc. A pictogram is a type of graphic symbol such as an emoticon or a picture word.

2 is a plan view showing a specific example of the configuration of the LED module 10. In this example, as shown in the enlarged view of part E surrounded by a dashed line in the figure, the LED module 10 has a plurality of LEDs 11 regularly arranged vertically and horizontally, and one dot is formed by one LED 11. As each LED 11, a three-color LED, a multi-color LED (8 or 16 colors used simultaneously), or a full-color LED (16 colors used simultaneously) can be used. The light emission state of each of the LEDs 11 is controlled according to an image signal S output from the controller board 50. The controller board 50 is connected to the connector 12 of the LED module 10 via the connector board 70. The connector board 70 transmits the image signal S from the controller board 50 to each row (row) of the LED module 10.

For example, when an image representing a character is displayed on the LED module 10, one character is represented by N×N dots using N LEDs 11 in the vertical direction and N LEDs 11 in the horizontal direction. The character is displayed according to various font data expanded into dots in a pair of memories 51 and 52 of the controller board 50. A specific value of N can be, for example, 8, 16, or 24, but is not limited thereto. In the configuration example shown in FIG. 2, N×N×12×3=36N2 LEDs ¹¹ are arranged so that an image corresponding to 12 characters in the horizontal direction and 3 characters in the vertical direction can be displayed. Therefore, the LED module 10 has a display screen 13 that can display an image corresponding to 12 characters in one horizontal row (line) in three rows. Note that, although an image representing a character is given here as an example, the display screen 13 of the LED module 10 can also display images representing numbers, symbols, pictograms, and the like.

The display screen 13 is divided into a number of display areas A1, A2, A3, A4, and A5, for example, as surrounded by dashed lines in FIG. 2. Display area A1 is allocated an area for six characters from the left end of the first row, and display area A2 is allocated an area for six characters from the right end of the first row. Display area A3 is allocated an area for 12 characters from the left end of the second row, i.e., the entire second row. Display area A4 is allocated an area for six characters from the left end of the third row, and display area A5 is allocated an area for six characters from the right end of the third row.

However, the setting of each width of the display areas A1 and A2 located in the first row, in other words the setting of the boundary position of the display areas A1 and A2, can be dynamically changed by changing the length information that specifies the display portion of the image, as will be explained later with a specific example. In addition, the setting of each width (setting of the boundary position) of the display areas A4 and A5 located in the third row can also be dynamically changed in the same way as the first row.

Returning to FIG. 1, the CPU 31 of the CPU board 30 executes application programs and driver programs stored in the memory 32, and controls the operation of the driver 33 and the like in accordance with each program. This CPU board 30 can be realized, for example, by using a microcomputer board equipped with Linux (registered trademark). The application program and the driver program contain algorithms for controlling the display of the LED module 10. In addition to each of the above programs, the memory 32 of the CPU board 30 stores display data such as candidates for text and images to be displayed on the LED module 10, and character font data.

The driver 33 can set one of the pair of memories 51, 52 of the controller board 50 as an editing memory and the other as a display memory, and performs a process of switching between the editing and display memory settings at a predetermined switching period Pc. In addition, under the control of an application program executed by the CPU 31, the driver 33 writes image data (dot image data) to be displayed in each display area A1 to A5 of the LED module 10 to the memory set for editing. Here, the image data indicates, for example, a color code corresponding to each dot. The color code will be described later. Furthermore, the driver 33 writes, for the image data written in the memory set for editing, beginning information and length information for specifying the display portion to be actually displayed in each display area A1 to A5 of the LED module 10, as well as color palette setting information, to the editing memory. In addition, in parallel with the writing process to the memory set for editing, the driver 33 performs a process of changing the beginning information and length information written in the previous switching period to the memory set for display at each timing of the interrupt process for image display according to the driver program executed by the CPU 31. Image display interrupt processing is performed to periodically update the display state of the LED module 10.

The pair of memories 51, 52 on the controller board 50 can record, erase, and rewrite image data (dot image data) to be displayed in each of the display areas A1 to A5 of the LED module 10, beginning information and length information for identifying the display portion of the image data, and setting information for a color palette that defines the combination of display colors (color scheme) of the LED module 10. As described above, the driver 33 switches between using one memory for editing and the other memory for display.

The FPGA 53 identifies the display portions to be actually displayed in each of the display areas A1 to A5 of the LED module 10 based on the leading information and length information for the image data recorded in the memory set for display out of the pair of memories 51, 52, and then concatenates the image data corresponding to each of the identified display portions in a predetermined order, and outputs the concatenated image data to the LED module 10 as an image signal S. The specific operation of the FPGA 53 will be described later.

In the configuration of the embodiment described above, the LED module 10 corresponds to the display unit in the present invention. Also, the pair of memories 51, 52 on the controller board 50 correspond to the pair of recording areas of the recording unit in the present invention. Furthermore, the CPU 31 and the driver 33 of the CPU board 30, and the FPGA 53 of the controller board 50 correspond to the control unit in the present invention.

Next, the operation of the display device 1 according to the present embodiment will be described.
Here, as a specific example, the operation of each part of the device will be described in detail when the display device 1 is installed at a designated location within a station and train information as shown in Figure 3 is displayed on the display screen 13 of the LED module 10.

In the train guide example of FIG. 3, the departure time and destination of the preceding train are fixedly displayed in display area A1 on the left side of the first row of the display screen 13, and text indicating the stations where that train will stop is displayed and moved to the left in display area A2 on the right side of the first row, a so-called scrolling display (or sliding display). Furthermore, information on the approach of the train heading towards this station from the previous station is displayed as a moving picture using pictograms, a so-called animation, in display area A3 on the second row. Furthermore, the departure time and destination of the next train are fixedly displayed in display area A4 on the left side of the third row, and text indicating the stations where that train will stop is displayed and moved to the left in display area A5 on the right side of the third row.

FIG. 4 is a flow chart for explaining the operation of displaying the train guide by the display device 1. In FIG.
(Processing at device startup)
In the display device 1, when the main power supply (not shown) is turned on and the LED module 10, the CPU 31 of the CPU board 30, and the FPGA 53 of the controller board 50 are started, first, in step S101 of Fig. 4, the driver program stored in the memory 32 of the CPU board 30 is executed by the CPU 31, and the driver 33 starts operating according to the driver program. In the next step S102, the application program stored in the memory 32 is executed by the CPU 31. As a result, the CPU 31 (application), the driver 33, and the FPGA 53 operate in parallel. Immediately after the start-up, the driver 33 performs the process of step S201 described later, and the FPGA 53 performs the process of step S301 described later.

When the application program is executed in step S102, the CPU 31 outputs an instruction to the driver 33 to initialize the memories 51 and 52 of the controller board 50 in the following step S103. This causes the driver 33 to write blank data to each of the memories 51 and 52. When the initialization of the memories 51 and 52 is complete, the CPU 31 outputs a display start instruction to the driver 33 and the FPGA 53 in the next step S104. After the output of the display start instruction is finished, the process proceeds to the next step S105, where the CPU 31 goes into a standby state to wait for the reception of an interrupt signal for image editing output from the driver 33, which will be described later.

When the driver 33 completes the initialization of the internal memory in step S201, in the following step S202, the driver 33 waits for processing until it receives a display start instruction output from the CPU 31. If the driver 33 receives a display start instruction from the CPU 31 (YES), the driver 33 proceeds to the next step S203 and goes into a standby state to wait for the reception of an interrupt signal for image display output from the FPGA 53 described later.

Furthermore, when the initialization of the internal data is completed in step S301, the FPGA 53 waits in the following step S302 until it receives a display start instruction output from the CPU 31 in the above-mentioned step S104. If it receives a display start instruction from the CPU 31 (YES), it proceeds to the next step S303 and waits in the process until it reaches the timing corresponding to the update period Ps of the image signal S to be output to the LED module 10. The update period Ps of the image signal S is predetermined according to the specifications of the LED module 10, and the FPGA 53 rewrites the image signal S at each update period Ps. If it reaches the timing corresponding to the update period Ps (YES), it proceeds to the next step S304.

In step S304, the FPGA 53 uses the start information and length information to be recorded in the memory 51 (or 52) by the processing of step S107 described below to identify the display portion to be displayed in each of the display areas A1 to A5 from the image data recorded in the memory, and reads the image data corresponding to each of the identified display portions from the display memory 51 (or 52). Here, the device is in a state immediately after startup, and blank data has been written to each memory 51, 52 by the above-mentioned step S103. In addition, data corresponding to a previously specified area is set as the start information and length information. Therefore, blank (black) data corresponding to that area is read from the memory.

In the next step S305, the FPGA 53 generates an image signal S by linking each of the read image data for each stage (row) of the display screen 13 of the LED module 10, and outputs the generated image signal S to the LED module 10 via the connector board 70. Here, as described above, blank data is read out immediately after the device is started up, so an image signal S is generated that sets the display screen 13 of the LED module 10 to a blank (black) display state.

In the LED module 10 that has received the image signal S from the FPGA 53, in the next step S306, the light emission state of each of the LEDs 11 arranged in each of the display areas A1 to A5 is controlled in accordance with the image signal S. Immediately after the device is started up, the display screen 13 of the LED module 10 is in a blank (black) display state.

In the next step S307, the FPGA 53 determines whether or not the timing corresponds to the period Pi for performing interrupt processing for image display. The period Pi for interrupt processing for image display is set to a predetermined integer L times the update period Ps of the image signal S described above (Pi = Ps x L). If the timing corresponds to the period Pi for interrupt processing for image display (YES), then in the next step S308 the FPGA 53 generates an interrupt signal for image display and outputs it to the driver 33. On the other hand, if the timing does not correspond to the period Pi for interrupt processing for image display (NO), the process returns to the above-mentioned step S303.

When the driver 33 receives the interrupt signal for image display output from the FPGA 53 in step S308 (YES in step S203), the driver 33 determines in the next step S204 whether it is the timing corresponding to the memory switching period Pc. If it is not the memory switching period Pc (NO), the driver 33 changes the leading information and length information recorded in the display memory 51 (or 52) in the next step S205. Immediately after the device is started, blank data is written to each memory 51, 52, so the leading information and length information are not changed. When the processing in step S205 is completed, the process returns to the above-mentioned step S203 and waits for the reception of an interrupt signal for image display.

On the other hand, if it is determined in step S204 that the memory switching period Pc has arrived (YES), the process proceeds to step S206, where the driver 33 switches between the memories 51 and 52 for display and editing. Immediately after starting up the device, one of the memories 51 and 52, in this case memory 51, is set for editing, and the other memory 52 is set for display.

In the next step S207, the driver 33 generates an interrupt signal for image editing and outputs it to the CPU 31. This interrupt signal for image editing is a signal that indicates the timing to start processing for recording new image data, start information and length information, and color palette setting information to be displayed in each of the display areas A1 to A5 in the next switching cycle Pc, in the memory 51 (or 52) set for editing. When the output of the interrupt signal for image editing is completed, the process returns to the above-mentioned step S203 and enters a standby state for receiving an interrupt signal for image display.

(Memory write process of initial image data, etc.)
When the CPU 31 receives the interrupt signal for image editing output from the driver 33 in step S207 (YES in step S105), in the next step S106, the CPU 31 extracts sentences and/or images to be written in the memory 51 (or 52) of the controller board 50 in correspondence with each of the display areas A1 to A5 from among the sentences and image candidates recorded in the memory 32 of the CPU board 30. Then, the CPU 31 creates image data (dot image data) corresponding to each of the extracted sentences and/or images. When creating image data corresponding to a sentence, it is possible to create dot image data by expanding font data according to the letters, numbers, symbols, etc. that make up the sentence. The data value of each dot of the created image data specifies the above-mentioned color code. The color code can specify the data value of one of the data values of a plurality of colors (for example, RGB values for 16 colors) described in the color palette. The following Table 1 shows an example of the relationship between the color code, the RGB value of the color palette, and the display color. However, the relationship between the color code and the color palette is not limited to this.

When image data (dot image data) corresponding to each of the display areas A1 to A5 is created in step S106, in the next step S107, the CPU 31 calculates the position in the memory 51 (or 52) set for editing to which each piece of image data should be written, and issues an instruction to the driver 33 to write the image data from each calculated position. Upon receiving the write instruction, the driver 33 writes the image data corresponding to each of the display areas A1 to A5 created by the CPU 31 from the designated position in the memory 51 (or 52).

When the driver 33 finishes writing each image data to the memory 51 (or 52), the CPU 31 instructs the driver 33 on the start information and length information used to identify the display portion of each image data, the timing and amount of change to the start information and length information, and the color palette setting information. Upon receiving the instruction from the CPU 31, the driver 33 writes the start information, length information, and color palette setting information to the memory 51 (or 52).

In the next step S108, the CPU 31 determines whether or not writing of the image data, start information, length information, and color palette setting information corresponding to each display area A1 to A5 into memory 51 (or 52) has been completed by the processing of step S107 above. If writing has been completed (YES), the process returns to the above-mentioned step S105 and waits for reception of an interrupt signal for the next image edit. On the other hand, if writing has not been completed (NO), the processing of steps S106 and S107 above is repeated.

Figure 5 is a conceptual diagram showing the initial image data recorded in memory 51 set for editing on controller board 50 (Figure 1) by the series of processes in steps S105 to S108 above. As shown in Figure 5, memory 51 is assigned memory areas B1 to B5 as shown in the area surrounded by dashed lines in Figure 5 according to the size and display mode settings of each of display areas A1 to A5 of LED module 10 shown in Figure 3 above. Initial image data (dot image data) to be displayed in each of display areas A1 to A5 is recorded in each of memory areas B1 to B5.

The writing process of image data etc. to the editing memory 51 in steps S105 to S108 of FIG. 4 as described above is performed in parallel with the processes of steps S203 to S207 by the driver 33 and the processes of steps S303 to S308 by the FPGA 53. Then, when the driver 33 determines that the timing corresponding to the next memory switching period Pc has arrived (YES in step S204), the memory 51 (or 52) that had been set for editing is switched to display, and the memory 52 (or 51) that had been set for display is switched to editing (step S206).

As a result, in the next switching cycle Pc, the memory 51 (or 52) in which the initial image data etc. are recorded is switched to display use, and a series of image display processes are performed by the driver 33 and FPGA 53 using the display memory 51 (or 52), while the memory 52 (or 51) in which the blank data is recorded is switched to editing use, and a series of image editing processes are performed by the CPU 31 and driver 33 using the editing memory 52 (or 51).

(Image display processing)
4, the series of image display processes using the display memory 51 (or 52) are as follows: first, when the FPGA 53 determines a timing corresponding to the update period Ps of the image signal S (YES in step S303), the FPGA 53 uses the head information and length information recorded in the display memory 51 (or 52) to specify the display portions to be displayed in the display areas A1 to A5 from the image data recorded in the memory, and reads out the image data corresponding to each of the specified display portions from the display memory 51 (or 52) (step S304). Then, the FPGA 53 generates the image signal S by connecting each of the read image data for each row (stage) of the display screen 13 of the LED module 10, and outputs the generated image signal S to the LED module 10 via the connector board 70 (step S305). In the LED module 10 that has received the image signal S from the FPGA 53, the light emission state of each of the LEDs 11 arranged in each of the display areas A1 to A5 is controlled in accordance with the image signal S (step S306). As a result, train information is displayed in each of the display areas A1 to A5.

Then, when the timing corresponds to the period Pi of the interrupt process for image display (YES in step S307), an interrupt signal for image display is output from the FPGA 53 (step S308), and the interrupt signal for image display is received by the driver 33 (YES in step S203). The driver 33 changes the leading information and length information recorded in the display memory 51 (or 52) in accordance with the timing and amount of change of the leading information and length information previously instructed by the CPU 31, corresponding to the number of times the interrupt process for image display is performed (step S205). This process of changing the leading information and length information is repeated each time an interrupt signal for image display is received until the timing corresponds to the next memory switching period Pc. The method of changing the leading information and length information will be explained in detail later with a specific example. As a result, in the FPGA 53, each time the timing corresponding to the update period Ps of the image signal S occurs, the changed start information and length information recorded in the display memory 51 (or 52) is used to identify the display portion to be displayed in each of the display areas A1 to A5 from the image data recorded in the memory.

(Image editing processing)
As for a series of image editing processes using the editing memory 52 (or 51) that are carried out in parallel with a series of image display processes using the display memory 51 (or 52) as described above, similar to the case of the writing process of initial image data, etc. to the memory 51 shown in the above-mentioned steps S105 to S108, the CPU 31 and driver 33 perform a process of recording new image data, leading information and length information, as well as color palette setting information to be displayed in each display area A1 to A5 in the next switching cycle Pc.

The following describes in detail the series of operations in this embodiment as described above, firstly the operation of the display device 1 for displaying fixed and movable train information in the display areas A1 and A2 of the LED module 10, and then the operation of the display device 1 for displaying moving image information about approaching trains in the display area A3. In reality, these operations are performed in parallel. Note that the display operation of train information for the display areas A4 and A5 is the same as for the display areas A1 and A2, so a description thereof will be omitted.

(Fixed and moving display operation)
Fig. 6 is a conceptual diagram showing an excerpt of image data (dot image data) recorded for display in memory 51 (or 52) of controller board 50, which corresponds to display areas A1, A2 of LED module 10. The upper row <1> of Fig. 6 shows initial image data recorded for display in memory 51 by the first writing process after starting the device. The middle row <2> and lower row <3> of Fig. 6 show image data in memories 52 and 51 switched from editing to display in accordance with the switching period Pc.

6, the width (size in the X direction) of memory area B1 is set to be equal to or larger than the width of display area A1 where fixed display is performed, here about twice as large. The width (size in the X direction) of memory area B2 is set to be about three times as large as the width of display area A2 where moving display is performed. The height (size in the Y direction) of each memory area B1, B2 is the same as the height (N dots) of each display area A1, A2. However, the setting of each memory area B1, B2 on memory 51 is not limited to the above example, and can be set appropriately depending on the capacity of the memory to be used, etc. As the initial image data, image data that represents the characters "12:34 Shin-Osaka" starting from the left end is written in memory area B1 of memory 51, and image data that represents the characters "Stops are Shin-Yokohama, Nagoya, Kyoto" starting from the left end is written in memory area B2.

In each of the memory areas B1 and B2 of the memory 51, the initial image data as described above is recorded, and also beginning information and length information for specifying the display portion to be displayed in each of the display areas A1 and A2 of the LED module 10, as well as color palette setting information are recorded. (See step S107 in FIG. 4 above.)

Specifically, the display portion corresponding to display area A1 corresponds to six full-width characters from the beginning of the image data recorded in memory area B1 of memory 51, or 6 x N dots in terms of the number of dots in the X direction, and in this case the entire "12:34 Shin-Osaka" is the display portion. In order to identify this display portion, as shown by the arrow corresponding to time T(0) in the upper row <1> of Figure 6, a start code DP1 indicating the beginning of the display portion in memory 51 is specified as the beginning information, and a length code DS1 indicating the total length in the X direction is specified as the length information.

The display portion corresponding to display area A2 corresponds to the first six characters (6 x N dots in the X direction) of the image data recorded in memory area B2 of memory 51, and "Stops: Shin" is the display portion. To identify this display portion, as shown by the arrow line corresponding to time T(0) in the upper row <1> of Figure 6, a start code DP2 indicating the start of the display portion on memory 51 is specified as the start information, and a length code DS2 indicating the total length in the X direction is specified as the length information.

The times T(0), T(1), T(N), T(2N), ... in the figure indicate the timing at which the interrupt process for image display described above is performed, and the times in parentheses correspond to the number of times the interrupt process is performed. The period Pi at which the interrupt process for image display is performed can be set appropriately to a few milliseconds to tens of milliseconds depending on the performance of the LED module 10. The switching period Pc of the memories 51 and 52 described above is sufficiently longer than the period Pi of the interrupt process for image display, and here, for example, the memories 51 and 52 are switched between display and editing every time 3×N interrupt processes are performed (Pc=3×N×Pi).

The above start codes DP1 and DP2 can specify, for example, the address of the memory in which the data of the dot located at the beginning of the display area is stored (hereinafter referred to as the "dot address"). The above length codes DS1 and DS2 can specify, for example, the number of dots equivalent to the total length of the display area in the X direction. Note that for the total length of the display area in the Y direction (vertical width), any number of dots can be specified with N dots as the minimum unit, and here, the minimum unit of N dots (e.g., 8, 16, or 24 dots) is specified as the default value for the Y direction. However, this example does not mean that the vertical width is fixed in character units; for example, when displaying an image whose vertical width is 1.5 times larger than one character, 1.5 x N dots is specified as the default value for the Y direction.

By using the start codes DP1, DP2 and length codes DS1, DS2 as described above, the FPGA 53 of the controller board 50 identifies the display portions to be displayed in the display areas A1, A2, respectively, and reads image data corresponding to each display portion from the memory 51 (step S304 in FIG. 4). Specifically, as shown in the upper part of FIG. 7, the FPGA 53 identifies "12:34 Shin-Osaka" using the start code DP1 and length code DS1 at time T(0), and identifies "Stops: Shin" using the start code DP2 and length code DS2 at time T(0), and reads the image data corresponding to each from the memory 51.

The image data read from the memory 51 is linked by the FPGA 53 according to the order of the display areas A1 and A2 on the LED module 10, and image data such as "12:34 Shin-Osaka stop is Shin" is generated as shown in the lower part of Figure 7 <2>. The order in which the image data is linked does not necessarily have to match the order of the display areas, and it is possible to link the image data in an arbitrarily specified order. The FPGA 53 then refers to the setting information of the color palette recorded in the memory 51, converts the color code indicated by the value of each dot in the linked image data into RGB values, etc., and outputs an image signal S indicating the converted image data to the LED module 10 via the connector board 70 (step S306 in Figure 4).

In the LED module 10, the light emission state of each LED 11 arranged in the first row of display areas A1 and A2 is controlled according to the image signal S from the FPGA 53. As a result, as shown at time T(0) in the top row <1> of Figure 8, "12:34 Shin-Osaka" is displayed in the display area A1 of the LED module 10, and "Stops: Shin-Osaka" is displayed in the display area A2 (step S306 in Figure 4).

After the first train information is displayed in the display areas A1 and A2 of the LED module 10 as described above, when the period Pi of the interrupt process for image display elapses and the first interrupt time T(1) arrives, an interrupt signal for image display is output from the FPGA 53 of the controller board 50 to the driver 33 of the CPU board 30 (step S308 in FIG. 4). In the driver 33 that receives the interrupt signal for image display, a process is performed to change the leading information and length information recorded in the memory 51 to the leading information and length information at the first interrupt time T(1) according to the timing and amount of change of the leading information and length information previously instructed by the CPU 31 (step S205 in FIG. 4). In the upper row <1> of FIG. 6, the amount of change of the leading information in one interrupt process is small (+1 dot as described later), so that the amount of change is enlarged more than in reality, making it possible to illustrate the start codes DP1 and DP2 and the length codes DS1 and DS2 corresponding to the first interrupt time T(1). Also, FIG. 6 shows the state corresponding to every N interrupt processes after the first interrupt process, and FIG. 8 shows the state corresponding to every N interrupt processes, but in reality, the start codes DP1, DP2 and the length codes DS1, DS2 are changed every time an interrupt process is performed.

Specifically, as shown by the arrow line corresponding to time T(1) in the upper row <1> of FIG. 6, for the display area A1 where fixed display is performed, the timing and amount of change of the head information and length information are both specified to be unchanged, so that the same start code DP1 and length code DS1 are set at all timings of the cyclically performed interrupt processing. On the other hand, for the display area A2 where moving display is performed, for example, when the image display is moved to the left by one dot each time the interrupt processing cycle Pi elapses, +1 dot is specified as the amount of change of the head information and 0 dot (no change) is specified as the amount of change of the length information at each interrupt processing as the change timing. As a result, the address of the dot located second from the start point (left end of memory area B2) of the image data recorded in memory area B2 of memory 51 is set as the start code DP2 at the first interrupt time T(1). Also, the length code DS2 at the first interrupt time T(1) is set to the number of dots for 6 characters (6 x N dots), the same as at the time T(0) described above.

Therefore, the driver 33 rewrites the start information and length information recorded in the memory 51, i.e., the start codes DP1, DP2 and the length codes DS1, DS2 at the time T(0) described above, to the start codes DP1, DP2 and the length codes DS1, DS2 at the first interrupt time T(1) as described above. As a result, the FPGA 53 uses the start codes DP1, DP2 and the length codes DS1, DS2 at the first interrupt time T(1) recorded in the memory 51 to specify the display parts to be displayed in each display area A1, A2 from the image data recorded in the memory 51, and reads out the image data corresponding to each display part from the memory 51 (step S304 in FIG. 4). Then, the FPGA 53 connects the image data read out from the memory 51, and outputs the image signal S indicating the image data in which the color code corresponding to each dot is converted into an RGB value or the like to the LED module 10 via the connector board 70 (step S305 in FIG. 4). As a result, as mentioned above and not shown in FIG. 8, the same image as at time T(0) is fixedly displayed in display area A1, and an image shifted one dot to the left from the image at time T(0) is displayed in display area A2 (step S306 in FIG. 4).

After that, the same operation as above is repeated every time the interrupt processing period Pi elapses. The upper row <1> of the above-mentioned FIG. 6 shows the start codes DP1, DP2 and length codes DS1, DS2 of the memory 51 that are rewritten by the driver 33 when the Nth interrupt time T(N) is reached, which is the same as the number of dots for one character. At the Nth interrupt time T(N), the start code DP1 and length code DS1 of the display part corresponding to the display area A1 where fixed display is performed are the same as those before. On the other hand, the start code DP2 of the display part corresponding to the display area A2 where moving display is performed is set to the address of the dot located at the N+1th position from the start point of the image data recorded in the memory area B2 of the memory 51, that is, the start dot of the second character, and the length code DS2 is set to the number of dots for six characters (6×N). As a result, image data for "12:34 Shin-Osaka" is specified as the display portion of display area A1 at the Nth interruption time T(N), and image data for "The train station is Shin-Yoko" is specified as the display portion of display area A2.

Therefore, at the Nth interruption time T(N), the display areas A1 and A2 of the LED module 10 will display "12:34 Shin-Osaka Car Station, Shin-Yoko" as shown in the second row <2> of Figure 8. As is clear from comparing the display states at each time T(0) and T(N), the image displayed in the display area A2 moves one character's worth to the left by N interruption processes, the same number as the number of dots for one character, achieving a so-called scrolling display (or sliding display).

The upper row <1> of FIG. 6 shows the start codes DP1, DP2 and length codes DS1, DS2 of the memory 51 that are rewritten by the driver 33 when the 2×Nth interrupt time T (2N) of the interrupt process that is performed thereafter is reached, which is the same as the number of dots for two characters. As the start code DP2 that is changed over time, the address of the dot located 2×N+1th from the start point of the image data recorded in the memory area B2 of the memory 51 at the 2×Nth interrupt time T (2N), that is, the address of the dot at the beginning of the third character, is set. As a result, the display areas A1 and A2 of the LED module 10 will display "12:34 Shin-Osaka Station is Shin-Yokohama" as shown in the third row <3> of FIG. 8. If we pay attention to the transition of the display state of the display area A2, the initial image will be scrolled by moving two characters to the left while the 2×Nth interrupt process is performed.

The control of displaying train information in each display area A1, A2 of the LED module 10 using the image data recorded in memory 51 as described above continues until the switching period Pc of memories 51, 52 arrives. Here, as described above, the switching period Pc of memories 51, 52 is set to the time during which 3×N interrupt processes are performed, which is the same as the number of dots for three characters, so that the display control of display areas A1, A2 using the image data of memory 51 shown in the upper part <1> of Figure 6 continues until just before 3×N interrupt processes are performed, that is, until the 3×N-1 interrupt time T (3N-1).

While the display control of the display areas A1 and A2 is being performed using the image data in the memory 51, the driver 33 instructed by the CPU 31 creates and records new image data to be displayed in the display areas A1 and A2 in the next switching cycle Pc, and records the beginning information, length information, and color palette setting information for the memory 52 set for editing (steps S106 and S107 in FIG. 4). In other words, the CPU 31, the driver 33, and the FPGA 53 perform a process of writing new image data to be used in the next switching cycle Pc to the memory 52 (steps S105 to S108 in FIG. 4) in parallel with a process of displaying train information in the display areas A1 and A2 using the image data in the memory 51 (steps S203 to S207, S303 to S308 in FIG. 4). The process of writing image data to the memory 52 may be completed while the first to 3×N-1 interrupt processes are being performed. As a result, the load on the CPU 31 during image data writing processing is significantly reduced compared to when image data is rewritten each time an interrupt process occurs.

When the 3×Nth interrupt time T (3N) arrives, the driver 33 of the CPU board 30 switches between memories 51 and 52, setting memory 52 for display and memory 51 for editing (step S206 in FIG. 4). The middle row <2> of FIG. 6 shows the image data recorded in memory areas B1 and B2 of memory 52 that has been set for display after the switching. "12:34 Shin-Osaka" is written in memory area B1 of memory 52, starting from its left end, and "Shin-Yokohama, Nagoya, Kyoto. Stops" is written in memory area B2, starting from its left end.

The image data recorded in memory areas B1 and B2 of memory 52 as described above is used to control the display of display areas A1 and A2 in the same manner as in the case of times T(0) to T(3N-1) described above. Specifically, at the 3×Nth interrupt time T(3N), the start code DP1 and length code DS1 of the display portion corresponding to display area A1 where fixed display is performed are the same as those before. On the other hand, the start code DP2 of the display portion corresponding to display area A2 where moving display is performed is specified as the address of the dot located at the start point of the image data recorded in memory area B2 of memory 52 (the left end of memory area B2), and the length code DS2 is specified as the number of dots for six characters (6×N).

As a result, image data of "12:34 Shin-Osaka" is specified as the display portion of display area A1 during the 3×N interruption time T (3N), and image data of "is, Shin-Yokohama," is specified as the display portion of display area A2. Therefore, during the 3×N interruption time T (3N), "12:34 Shin-Osaka is, Shin-Yokohama," as shown in the fourth row <4> of FIG. 8 is displayed in display areas A1 and A2 of LED module 10. Looking at the transition in the display state of display area A2, the initial image is scrolled and moved three characters to the left while the 3×N interruption processes are being performed.

After the 3×N+1 interrupt time T(3N+1), until the next switching period Pc of the memories 51 and 52 arrives, specifically, immediately before the 6×N interrupt process is performed, that is, until the 6×N-1 interrupt time T(6N-1), the display control of the display areas A1 and A2 using the image data of the memory 52 is performed in the same manner as in the case of the interrupt times T(1) to T(3N-1) described above. In parallel with this, the CPU 31 and the driver 33 perform a process of rewriting the image data recorded in the memory areas B1 and B2 of the memory 51 set for editing to new image data to be used in the next switching period Pc. When the 6×N interrupt time T(6N) arrives, the memories 51 and 52 are switched between display and editing for the second time, which is not shown here, and thereafter, the display control and the rewriting process of the image data, etc., similar to the above-mentioned case are repeatedly performed in parallel.

The lower row <3> of FIG. 6 shows image data recorded in memory 51, which is set for display at the 12×Nth interruption time T (12N) when memories 51 and 52 are switched for the fourth time. "12:34 Shin-Osaka" is written in memory area B1 of memory 51, starting from its left end, and ", Kyoto. Stops are Shin-Yokohama and Nagoya" is written in memory area B2, starting from its left end. In display control of display areas A1 and A2 using image data of this memory 51, for example, "12:34 Shin-Osaka Kyoto." is displayed at the 13×Nth interruption time T (13N), as shown in the second row from the bottom <5> of FIG. 8, and "12:34 Shin-Osaka Kyoto. Stops" is displayed at the 14×Nth interruption time T (14N), as shown in the bottom row <6> of FIG. 8. In this way, in the moving display in display area A2, a series of instructions such as "Stopping stations are Shin-Yokohama, Nagoya, and Kyoto" is continuously and repeatedly scrolled (or displayed in a sliding screen).

(Movie display operation)
Next, the operation of the display device 1 for displaying moving image information about approaching trains (see FIG. 3) in the display area A3 of the LED module 10 will be described.

Figure 9 is a conceptual diagram showing an excerpt of the image data recorded for display in memory 51 (or 52) of controller board 50, which corresponds to display area A3 of LED module 10. The upper row <1> of Figure 9 shows the initial image data recorded in memory 51 by the first write process after the device is started. The lower row <2> of Figure 9 shows the image data recorded in memory 52 that is switched from editing to display in the next switching cycle Pc. Memory 51 (or 52) is assigned a memory area B3 corresponding to display area A3, and the width (size in the X direction) of this memory area B3 is set to be three times or more the width of display area A3. The height (size in the Y direction) of memory area B3 is the same as the height (N dots) of display area A3.

In memory area B3 of memory 51 shown in the upper row <1> of Figure 9, three patterns of image data are written as initial image data, starting from the left edge and arranged in the X direction, each pattern depicting the characters "Previous Station" and "This Station" and a pictogram showing a train running between the stations (step S107 in Figure 4). The image data of each pattern has a total length in the X direction that is the same as the width of display portion A3. The difference between the image data of each pattern is the state of ">>>" drawn in the lower left of the train pictogram.

In the following explanation, the image data located at the leftmost position in memory area B1 in the upper row <1> of Figure 9 and having a pictogram with ">" will be referred to as the first pattern. The image data located to the right of the image data of the first pattern and having a pictogram with ">>" will be referred to as the second pattern. The image data located to the right of the image data of the second pattern and having a pictogram with ">>>" will be referred to as the third pattern.

In memory area B3 of memory 51, the initial image data as described above is recorded, and also beginning information and length information for specifying the display portion to be displayed in display area A3 of LED module 10, as well as color palette setting information are recorded (step S107 in FIG. 4). The display portion to be displayed in display area A3 is one of the three patterns of image data recorded in memory area B3 of memory 51, with the image data of the first pattern being the initial display portion.

In order to specify the display portion, as shown by the arrow line corresponding to time T(0) in the upper row <1> of FIG. 9, a start code DP3 indicating the start of the display portion in memory 51 is set as the start information, and a length code DS3 indicating the total length in the X direction is specified as the length information. Specifically, the start code DP3 at time T(0) is specified as the address of a dot located at the start point (left end of memory area B3) of the image data recorded in memory area B3 of memory 51. In addition, as the length code DS3 at time T(0), since the display portion A3 has a width of 12 characters, the number of dots for 12 characters in the X direction (12 x N dots) is specified. Note that, as with the memory areas B1 and B2 described above, any number of dots can be specified with N dots as the minimum unit, and here, N dots (e.g., 8, 16, or 24 dots) of the minimum unit is specified as the default value in the Y direction.

By using the start code DP3 and length code DS3 as described above, the FPGA 53 of the controller board 50 identifies the display portion to be displayed in the display area A3, and reads image data corresponding to that display portion from the memory 51 (step S304 in FIG. 4). The FPGA 53 then refers to the color palette setting information recorded in the memory 51, converts the color code indicated by the value of each dot in the image data read from the memory 51 into RGB values, etc., and outputs an image signal S indicating the converted image data to the LED module 10 via the connector board 70 (step S305 in FIG. 4).

In the LED module 10, the light emission state of each LED 11 arranged in the display area A3 is controlled according to the image signal S from the controller board 50. As a result, as shown at time T(0) in the top row <1> of Figure 10, an image is displayed in the display area A3 of the LED module 10 in which a train pictogram with ">" is positioned between the words "Previous station" and "This station" (step S306 in Figure 4).

After the first train approach information is displayed in the display area A3 of the LED module 10 as described above, when the period Pi of the interrupt process for image display has elapsed and the first interrupt time T(1) has arrived, the driver 33 of the controller board 50 performs a process of changing the leading information and length information recorded in the memory 51 to the leading information and length information at the first interrupt time T(1) according to the timing and amount of change of the leading information and length information previously instructed by the CPU 31 (step S205 in FIG. 4). Here, the period Pi of one interrupt process is shorter than the image update period Pr for realizing a moving image display, and the image for the moving image is updated each time M interrupt processes are performed (Pr=M×Pi). In this case, the same start code DP3 and length code DS3 as those at the time T(0) described above are set in the first to M-1 interrupt processes. The image update period Pr can be set appropriately according to the frame rate of the moving image, etc.

When the M-th interrupt time T(M) arrives, the driver 33 rewrites the start code DP3 and length code DS3 at time T(0) recorded in the memory 51 to the start code DP3 and length code DS3 at the M-th interrupt time T(M) as shown in the upper row <1> of FIG. 9. Specifically, the start code DP3 at the M-th interrupt time T(M) is set to the address of the head of the image data of the second pattern, that is, the address of the 12×N+1th dot in the X direction from the left end of the memory area B3. Note that the length code DS3 at the M-th interrupt time T(M) is set to the same 12×N dots as at time T(0). As a result, the FPGA 53 uses the start code DP3 and length code DS3 at the M-th interrupt time T(M) recorded in the memory 51 to specify the image data of the second pattern as the display portion of the display area A3 at the interrupt time T(M) from the image data recorded in the memory 51 (step S304 in FIG. 4). Therefore, during the interruption time T (M), an image is displayed in the display area A3 of the LED module 10, in which a train pictogram with ">>" is positioned between the words "Previous Station" and "This Station", as shown in the second row <2> of Figure 10 (steps S305 and S306 of Figure 4).

After that, in the same manner as in the case of the Mth interrupt time T(M) described above, when it becomes the 2×Mth interrupt time T(2M) corresponding to the image update period Pr, the driver 33 rewrites the start code DP3 and length code DS3 at time T(M) recorded in the memory 51 to the start code DP3 and length code DS3 at the 2×Mth interrupt time T(2M) as shown in the upper row <1> of FIG. 9. Specifically, the start code DP3 at the 2×Mth interrupt time T(2M) is set to the address of the head of the image data of the third pattern, that is, the 24×N+1th dot in the X direction from the left end of the memory area B3. The length code DS3 is set to the same 12×N dots as at time T(0).

As a result, an image is displayed in the display area A3 of the LED module 10, in which a train pictogram with ">>>" is positioned between the words "Previous station" and "This station", as shown in the third row <3> of Fig. 10. If you pay attention to the transition of the train pictogram, you will see an animation in which the number of ">"s in the bottom left gradually increases as the interrupt process is carried out 2 x M times, showing the train traveling towards the current station.

The control of displaying approaching train information in the display area A3 of the LED module 10 using the image data recorded in the memory 51 as described above continues until the switching period Pc of the memories 51, 52 arrives. Here, for example, the video image is updated three times, that is, the memories 51, 52 are switched between display and editing at the timing when the 3×Mth interrupt process is performed. In this case, the display control of the display area A3 using the image data of the memory 51 shown in the upper row <1> of Figure 9 continues until just before the 3×Mth interrupt process is performed, that is, until the 3×M-1th interrupt time T (3M-1).

Regarding the switching period Pc between display and editing of the memories 51 and 52, the number of interrupt processes (3 x N) for switching between display and editing of the memories 51 and 52 in the display control of the display areas A1 and A2 described above and the number of interrupt processes (3 x M) for switching between display and editing of the memories 51 and 52 in the video display of the display area A3 must be matched because they use a common memory. To achieve this, the number of interrupt processes M for updating the image in the video display of the display area A3 is set to be equal to the number of dots N for one character (M = N). If the above setting is difficult due to constraints such as the frame rate of the video, the number of image updates (three times in the above example) before switching between display and editing of the memories 51 and 52 is adjusted to match the number of interrupt processes.

While the display control of the display area A3 is being performed using the image data in the memory 51, the driver 33 instructed by the CPU 31 records new image data, start information, length information, and color palette setting information to be displayed in the display area A3 in the next switching cycle Pc in the memory 52 set for editing (steps S106 and S107 in FIG. 4). In other words, the CPU 31, the driver 33, and the FPGA 53 perform a process of writing new image data, etc. to be used in the next switching cycle Pc to the memory 52 (steps S105 to S108 in FIG. 4) in parallel with a process of displaying approach information in the display area A3 using the image data, etc. in the memory 51 (steps S203 to S207, S303 to S308 in FIG. 4). The writing process to the memory 52 may be completed while the first to 3×M−1 interrupt processes are being performed.

When the 3×Mth interrupt time T (3M) arrives, the driver 33 on the CPU board 30 switches between memories 51 and 52, setting memory 52 for display and memory 51 for editing (step S206 in FIG. 4). The lower row <2> of FIG. 9 shows the image data recorded for display in memory area B3 of memory 52 after the switch. Three patterns of image data are written in memory area B3 of memory 52, aligned in the X direction starting from the left edge. The difference from the first to third patterns of image data shown in the upper row <1> of FIG. 9 is that the train pictogram is approaching the "this station" side.

Using the image data recorded in the memory area B3 of the memory 52 as described above, the display control of the display area A3 is performed in the same manner as in the case of the interruption times T(0) to T(3M-1) described above. Specifically, in the 3×Mth interruption time T(3M), the start code DP3 is set to the address of the dot located at the start point (the left end of the memory area B3) of the image data recorded in the memory area B3 of the memory 52. In addition, the length code DS3 is set to 12×N dots in the X direction. As a result, the image data of the first pattern in which the train pictogram approaches the "this station" side is specified as the display portion of the display area A3 in the 3×Mth interruption time T(3M). Therefore, in the 3×Mth interruption time T(3M), the display area A3 of the LED module 10 displays approaching train information as shown in the fourth row <4> of FIG. 10.

Then, at the 4xMth interruption time T (4M), the start code DP3 and length code DS3 as shown in the lower row <2> of Figure 9 are set, and the second pattern of image data in which the train pictogram approaches the "this station" side is specified as the display portion of the display area A3 at the 4xMth interruption time T (4M). Therefore, at the 4xMth interruption time T (4M), the display area A3 of the LED module 10 displays approaching train information as shown in the fifth row <5> of Figure 10. Thereafter, similar display control is repeated for each image update cycle.

As described above, according to the display device 1 of this embodiment, the display portion to be displayed in each display area is identified using a start code and a length code for the image data for each display area recorded in memories 51 and 52, and the start code is changed to correspond to the display mode (moving display, moving image display) of each display area. This makes it possible to move and display images containing text in each display area or to display a moving image by using information with a low processing load, namely the start code and the length code, without providing hardware corresponding to each display mode. Such a display device 1 has a simple configuration and can be realized at low cost.

The display device 1 of this embodiment can also be flexibly operated even when changes occur to the layout or display mode of the display area, since it can handle the changes by changing the start code or length code to correspond to the changes. Furthermore, the display device 1 records new image data to be used in the next memory switching cycle in the memory set for editing in parallel with the display control of each display area using image data in the memory set for display, so the load on the software can be significantly reduced compared to redrawing image data in the memory each time an interrupt process is performed. This makes it possible to perform moving display or video display while smoothly changing the image in multiple display areas.

In the above embodiment, an example has been described in which the display device 1 is installed in a predetermined location within a station and train information is displayed in each display area of the LED module 10, but the present invention is not limited to this. For example, it is also possible to display information about various facilities within a station or facilities around the station, or to install the display device in an airport, road, parking lot, commercial facility, etc. to display various types of information.

In addition, with regard to the moving display of the display area A2 described with reference to Figures 6 to 8, an example has been shown in which the image is moved one dot at a time for each periodic interrupt process, but for example, the image may be moved one dot at two interrupt processes, that is, the image may be moved one dot at every other interrupt process. In this way, the image movement (scrolling) speed can be halved. The ratio at which the image is moved one dot at a time for periodic interrupt processes can be set appropriately according to the scroll speed. Furthermore, the direction in which the image moves is not limited to the leftward direction as exemplified in the embodiment, and it is of course also possible to move the image to the rightward. In the case of a rightward movement, the change amount of the leading information may be set to the opposite sign to that in the case of a leftward movement.

In the above embodiment, an example was shown in which one horizontal row (line) of the LED module 10 was divided into two display areas A1, A2 (or A4, A5) for display (see Figures 2 and 3), but it is of course possible to divide one row into three or more display areas for display. Specifically, assuming that one row can be divided into a maximum of n (n≧3) display areas, image data (dot image data) for displaying in the n display areas A1, A2, ..., An are recorded in memory 51 (or 52), and the display portions of the image data are specified using start code and length code pairs (DP1, DS1), (DP2, DS2), ..., (DPn, DSn). At this time, for example, if you want to display nothing in the display area An, that is, to display n-1 display areas A1 to An-1, you can specify (0, 0) as (DPn, DSn). Specifying the start code and length code in this way allows you to flexibly set and change the number of divisions in a column.

Furthermore, in the above embodiment, the width of each of the display areas A1 to A5 of the LED module 10 is fixed, but it is also possible to dynamically change the width of the display area by changing the length information (length code) used to identify the display portion. Below, a corresponding modified example is described.

(Modification)
Here, a case where the widths of the display areas A1 and A2 of the LED module 10 in the above-mentioned embodiment (the positions of the boundaries between the display areas A1 and A2) are dynamically changed by changing the length code will be specifically described with reference to Figures 11 and 12. Figure 11 shows image data for the display areas A1 and A2 recorded for display in the memory 51 (or 52) of the controller board 50 in the above-mentioned modified example, and Figure 12 shows changes in the images displayed in the display areas A1 and A2 of the LED module 10.

In this modified example, the numbers displayed in the display area A1 of the LED module 10 are erased over time by the alphabet displayed in the display area A2, thereby performing a so-called wipe display.
(Wipe display operation)
Specifically, image data representing the numbers "0123456789" starting from the left end is written as initial image data into memory area B1 of memory 51 shown in the upper row <1> of Fig. 11. Image data representing the alphabets "ABCD" starting from the left end is written as initial image data into memory area B2.

In order to specify the display portion of the image data recorded in each of the memory areas B1 and B2 of the memory 51 to be displayed in each of the display areas A1 and A2 of the LED module 10, the driver 33 writes the start codes DP1 and DP2 and the length codes DS1 and DS2 as shown by the arrow lines corresponding to time T(0) in the upper row <1> of FIG. 11 into the memory 51. Specifically, the start code DP1 for specifying the display portion of the display area A1 at time T(0) is set to the address of the dot located at the start point (the left end of the memory area B1) of the image data recorded in the memory area B1 of the memory 51, and the length code DS1 is set to the number of dots for 10 characters (10 x N). This specifies the image data of "0123456789" as the display portion of the display area A1 at time T(0).

The address of the dot located at the start of the image data recorded in memory area B2 of memory 51 (the left end of memory area B2) is set as the start code DP2 for identifying the display portion of display area A2 at time T(0), and the number of dots for two characters (2 x N) is set as the length code DS2. This identifies the image data of "AB" as the display portion of display area A2 at time T(0).

The image data of the display parts of the above-specified display areas A1 and A2 are linked by the FPGA 53 of the controller board 50 according to the order of the display areas A1 and A2, the color code indicated by the value of each dot in the linked image data is converted to RGB values, etc., and an image signal S indicating the converted image data is output from the controller board 50 to the LED module 10 via the connector board 70. As a result, as shown at time T(0) in the top row <1> of FIG. 12, "0123456789" is displayed in the display area A1 of the LED module 10, and "AB" is displayed in the display area A2. At this time, the width of the display area A1 is the number of dots for 10 characters corresponding to the length code DS1 (10×N), and the width of the display area A2 is the number of dots for 2 characters corresponding to the length code DS2 (2×N). The boundary between the display areas A1 and A2 is located between the 10×Nth dot and the 10×N+1th dot from the left end of the display area A1.

Then, when the interrupt processing period Pi has elapsed, the start codes DP1, DP2 and length codes DS1, DS2 at the first interrupt time T(1) are set, as shown by the arrow line corresponding to time T(1) in the upper row <1> of Figure 11. Here, the display mode of each display area A1, A2 is set so that each time the interrupt processing period Pi has elapsed, the display of the image in display area A2 moves one dot to the left, and the total length in the X direction becomes one dot shorter in display area A1 and one dot longer in display area A2.

When setting the display mode in this way, the start code DP1 for identifying the display portion of the display area A1 at the first interrupt time T(1) is set to the same address as at the time T(0) described above, and the length code DS1 is set to a value obtained by subtracting 1 dot from the number of dots for 10 characters (10 x N-1 dots). Also, the start code DP2 for identifying the display portion of the display area A2 at the first interrupt time T(1) is set to the same address as at the time T(0) described above, and the length code DS2 is set to a value obtained by adding 1 dot to the number of dots for two characters (2 x N + 1 dots).

After that, the start codes DP1, DP2 and the length codes DS1, DS2 are repeatedly changed in the same manner as above every time the interrupt processing period Pi elapses. The upper row <1> of FIG. 11 described above shows the start codes DP1, DP2 and the length codes DS1, DS2 that are specified when the Nth interrupt time T(N), which is the same as the number of dots for one character, is reached after the first interrupt time T(1). At the Nth interrupt time T(N), the start code DP1 for specifying the display portion of the display area A1 is set to the same address as at the time T(0) described above, and the length code DS1 is set to the number of dots for nine characters (9 x N). The start code DP2 for specifying the display portion of the display area A2 is set to the same address as at the time T(0) described above, and the length code DS2 is set to the number of dots for three characters (3 x N).

As a result, the image data of "012345678" is specified as the display portion of the display area A1 at the Nth interrupt time T(N), and the image data of "ABC" is specified as the display portion of the display area A2, and the image as shown in the second row <2> of FIG. 12 is displayed in each of the display areas A1 and A2 of the LED module 10. At this time, the width of the display area A1 is the number of dots for nine characters corresponding to the length code DS1 (9×N), and the width of the display area A2 is the number of dots for three characters corresponding to the length code DS2 (3×N). The boundary between the display areas A1 and A2 is located between the 9×Nth dot and the 9×N+1th dot from the left end of the display area A1. Compared to the case of the time T(0) described above, the widths of the display areas A1 and A2 (the positions of the boundaries between the display areas A1 and A2) change dynamically while the Nth interrupt process is being performed.

The upper row <1> of FIG. 11 shows the start codes DP1, DP2 and length codes DS1, DS2 that are set when the 2×Nth interrupt time T (2N) is reached, which is the same as the number of dots for two characters, among the interrupt processes that are performed thereafter. The start code DP1 at the 2×Nth interrupt time T (2N) is set to the same address as at the time T (0) described above, and the length code DS1 is set to the number of dots for eight characters (8×N). The start code DP2 at the 2×Nth interrupt time T (2N) is set to the same address as at the time T (0) described above, and the length code DS2 is set to the number of dots for four characters (4×N). As a result, as shown in the third row <3> of FIG. 12, "01234567" is displayed in the display area A1 of the LED module 10, and "ABCD" is displayed in the display area A2.

As shown in the upper row <1> of FIG. 11, the display control of the display areas A1 and A2 using the image data recorded in the memory 51 continues, as in the above-mentioned embodiment, until the switching period Pc between the display and editing of the memories 51 and 52 arrives, that is, until the 3×N-1th interrupt time T (3N-1). Then, at the 3×Nth interrupt time T (3N), the driver 33 of the CPU board 30 switches the memories 51 and 52 between display and editing, and the memory 52 is set for display and the memory 51 is set for editing. The middle row <2> of FIG. 11 shows the image data recorded in the memory areas B1 and B2 of the memory 52 after switching. "0123456789" is written in the memory area B1 of the memory 52, starting from its left end, and "ABCDEFG" is written in the memory area B2, starting from its left end.

Using the image data recorded in the memory 52 as described above, the display control of the display areas A1 and A2 is performed in the same manner as in the case of the above-mentioned times T(0) to T(3N-1). Specifically, the address of the dot located at the start point of the image data recorded in the memory area B1 of the display memory 52 is set as the start code DP1 in the 3×Nth interrupt time T(3N), and the number of dots for 7 characters (7×N) is set as the length code DS1. Also, the address of the dot located at the start point of the image data recorded in the memory area B2 of the display memory 52 is set as the start code DP2 in the 3×Nth interrupt time T(3N), and the number of dots for 5 characters (5×N) is set as the length code DS2. As a result, as shown in the fourth row <4> of FIG. 12, "0123456" is displayed in the display area A1 of the LED module 10, and "ABCDE" is displayed in the display area A2.

After that, the display control of display areas A1 and A2 is repeated in the same manner as above. The lower row <3> of Figure 11 shows the image data recorded in memory 52 set for display after 9xN interrupt times T (9N) and the third switching between display and editing of memories 51 and 52. "0123456789" is written in memory area B1 of memory 52, starting from its left end, and "ABCDEFGHIJKL" is written in memory area B2, starting from its left end.

The address of the dot located at the start point of the image data recorded in memory area B1 of memory 52 is set as the start code DP1 in the 9xN interrupt time T (9N), and the number of dots for one character (N) is set as the length code DS1. The address of the dot located at the start point of the image data recorded in memory area B2 of memory 52 is set as the start code DP2 in the 9xN interrupt time T (9N), and the number of dots for 11 characters (11xN) is set as the length code DS2. As a result, as shown in the second row from the bottom of Figure 12 <5>, "0" is displayed in the display area A1 of the LED module 10, and "ABCDEFGHIJK" is displayed in the display area A2.

Then, when the 10xNth interrupt time T (10N) arrives, the start code DP1 is set to the same address as the 9xNth interrupt time T (9N) described above, and the length code DS1 is set to 0. The start code DP2 is set to the same address as the 9xNth interrupt time T (9N) described above, and the length code DS2 is set to the number of dots for 12 characters (12xN). As a result, as shown in the bottom row <6> of Figure 12, the images (numbers) that had been displayed in display area A1 up until that point are all erased by the images (alphabet) displayed in display area A2, completing the series of wipe displays.

The above-mentioned modified example makes it possible to easily change the boundary settings of multiple display areas, allowing for even more flexible operation. By combining various display forms as explained in the above-mentioned embodiment and modified example, a variety of multi-window displays can be realized.

In the above-mentioned embodiment and modified example, the start code and/or length code are changed in the X direction of the memories 51 and 52, and a fixed specified value is used in the Y direction. However, it is of course possible to change the start code and/or length code in the Y direction in the same manner as in the X direction. In this case, it becomes possible to perform a moving display or a wiping display in the vertical direction on the display screen of the LED module 10. Furthermore, if the start code and/or length code are changed alternately in the X direction and the Y direction, it is also possible to realize a moving display or a wiping display in a substantially diagonal direction.

1...display device, 10...LED module, 11...LED, 12...connector, 13...display screen, 30...CPU board, 31...CPU, 32...memory, 33...driver, 50...controller board, 51, 52...memory, 53...FPGA, 70...connector board, A1-A5...display area, B1-B5...memory area, DP1-DP3...start code, DS1-DS3...length code, S...image signal

Claims (6)

A display device that displays an image in each display area of a display unit having a plurality of display areas,
a recording unit for recording an image for each of the display areas;
a control unit that specifies a display portion of each image recorded in the recording unit based on start information and length information, and displays the specified display portion in each of the display areas, the control unit being capable of changing the start information or the length information;
Including,
The control unit changes the length information to thereby change a width of the corresponding display area of the display unit and change an image to be displayed in the display area . The display unit has a display screen divided into a plurality of display areas, the display areas being arranged in a row,
The control unit links the identified display parts in a predetermined order and displays them on the display screen.
The display device according to claim 1 . The display device according to claim 1 or 2, wherein the control unit changes the leading information to move the image vertically or horizontally in the corresponding display area of the display unit. The display device according to claim 1 or 2, wherein the control unit changes the leading information to display a moving image in the corresponding display area of the display unit. the recording section has a pair of recording areas,
the control unit, while specifying the display portion of each image recorded in one of the recording areas by changing the leading information or the length information and displaying the specified portion in each of the display areas, records a new image for each of the display areas in the other of the recording areas, and updates each of the images to be displayed by switching the pair of recording areas after recording of the new image is completed.
The display device according to any one of claims 1 to 4 . 6. The display device according to claim 1 , wherein the beginning information is a start code indicating the beginning of the display portion, and the length information is a length code indicating a total length of the display portion.