JP2021026182A - Display device - Google Patents

Abstract

To provide a display device which has a simple configuration in which images can be displayed while changing the images in a plurality of display regions, and can be flexibly operated at a low cost.SOLUTION: Image data to be displayed in a plurality of display regions of an LED module 10 is recorded in a pair of memories 51,52. For the image data recorded in the memory 51 (or 52) set for display, a display portion displayed in each display region is specified on the basis of head information and length information, and the specified display portion is displayed in a corresponding display region of the LED module 10. Here, the head information or length information used for specification of the display portion can be changed in accordance with the display mode of each display region.SELECTED DRAWING: Figure 1

Description

The present invention relates to a display device that displays an image in a plurality of display areas.

Conventionally, so-called scroll display (or flow display), which is installed in a predetermined place such as a station yard and displays information such as train guidance while moving in one direction on a display device in which a large number of LEDs are arranged, has been used. Possible display devices are widely used. For example, in Patent Document 1, a display in which the load of software is reduced by processing the bit shift of the memory for scroll processing by hardware so that the scroll speed is not affected even if the display content is large. The device is disclosed.

Japanese Unexamined Patent Publication No. 9-22269

By the way, for a display device capable of scrolling information such as train guidance, the display surface of the LED display is divided into a plurality of display areas, and display modes set for each display area (for example, fixed display or scroll display). It is required to support so-called multi-window display, which displays an image including characters according to (etc.).

However, in order to support multi-window display with a conventional display device as disclosed in Patent Document 1, it is necessary to provide hardware corresponding to the display mode in each of the plurality of display areas. It is inevitable that the equipment configuration will become complicated and the cost will increase. In addition, when the layout or display mode of the display area is changed, it is necessary to modify the hardware in response to the change, so that it is difficult to flexibly operate the display device. ..

When trying to support multi-window display by improving software instead of processing with hardware, the image of the display area is redrawn within a predetermined time as the number of display areas for scroll display increases. It becomes difficult to finish the processing, and there is a high possibility that the scrolled image is stopped for a moment or the display areas are out of sync.

The present invention has been made by paying attention to the above points, and provides a display device capable of low-cost and flexible operation with a simple configuration capable of displaying an image while changing it in a plurality of display areas. The purpose.

In order to achieve the above object, one aspect of the present invention provides a display device for displaying an image in each display area of a display unit having a plurality of display areas. This display device specifies a recording unit in which an image for each display area is recorded and a display portion of each image recorded in the recording unit based on head information and length information, and identifies the specified display portion. A control unit to be displayed in each display area, including the control unit capable of changing the head information or the length information.

According to the above display device, with respect to the image for each display area recorded in the recording unit, the display portion to be displayed in each display area is specified based on the changeable start information and length information, and the specified image The display part will be displayed in the corresponding display area. As a result, it is possible to display an image in each display area while changing the image by using information having a small processing load such as head information and length information without providing hardware according to the display mode of each display area. .. Such a display device has a simple configuration and can be realized at low cost. Further, even if the layout or display mode of the display area is changed, it can be dealt with by changing the head information or the length information according to the changed content, so that flexible operation is possible.

It is a block diagram which shows the schematic structure of the display device by one Embodiment of this invention. It is a top view which shows the specific structural example of the LED module in the said Embodiment. It is a figure which shows an example of the train guidance to be displayed on the LED module in the said embodiment. It is a flowchart for demonstrating the display operation of a train guide in the said embodiment. It is a conceptual diagram which shows the initial image data recorded in the memory of a controller board by the first writing process after starting a device. It is a conceptual diagram which shows the transition of the image data and the like for display areas A1 and A2 recorded in the memory of a controller board in the said embodiment. It is a conceptual diagram for demonstrating the process in FPGA of the said Embodiment. It is a conceptual diagram which shows the transition of the image displayed in the display area A1 and A2 of the LED module in the said embodiment. It is a conceptual diagram which shows the transition of the image data and the like for display area A3 recorded in the memory of a controller board in the said embodiment. It is a conceptual diagram which shows the transition of the image displayed in the display area A3 of the LED module in the said embodiment. FIG. 5 is a conceptual diagram showing changes in image data and the like for display areas A1 and A2 recorded in the memory of the controller board in a modification related to the above embodiment. It is a conceptual diagram which shows the transition of the image displayed in the display area A1 and A2 of the LED module in the said modification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing a schematic configuration of a display device according to an embodiment of the present invention. In FIG. 1, the display device 1 is, for example, a connector board 70 that connects an LED module 10, a CPU board 30 and a controller board 50 for displaying an image on the LED module 10, and the LED module 10 and the controller board 50. And, including. Further, the CPU board 30 includes a CPU 31, a memory 32, and a driver 33. Further, the controller board 50 includes memories 51 and 52 and an FPGA (Field Programmable Gate Array) 53. The "image" in the present invention includes an image representing characters, numbers, symbols, pictograms, and the like. A pictogram is a type of pictogram such as pictograms and pictograms.

FIG. 2 is a plan view showing a specific configuration example of the LED module 10. In this configuration example, in the LED module 10, as shown in the enlarged view of the portion E surrounded by the alternate long and short dash line in the figure, a plurality of LEDs 11 are regularly arranged vertically and horizontally, and one LED constitutes one dot. Has been done. As the individual LED 11, a three-color LED, a multi-color LED (8 or 16 colors for simultaneous use), a full-color LED (16 colors for simultaneous use), or the like can be used. The light emitting state of all the LEDs 11 is controlled according to the image signal S output from the controller board 50. The controller board 50 is connected to the connector 12 of the LED module 10 via the connector board 70. The connector board 70 transmits the image signal S from the controller board 50 for each stage (row) of the LED module 10.

When displaying an image representing a character on the LED module 10, for example, one character is represented by using N LEDs 11 in the vertical direction and N LEDs 11 in the horizontal direction, that is, N × N dots. Ru. Characters are displayed according to various font data dot-expanded in a pair of memories 51 and 52 of the controller board 50. The specific value of N can be, for example, 8, 16 or 24, but is not limited thereto. In the configuration example shown in FIG. 2, 12 characters in the horizontal direction, so that an image corresponding to the longitudinal direction 3 characters can be displayed, N × N × 12 × 3 = 36N 2 pieces of LED11 is provided ing. Therefore, the LED module 10 is provided with a display screen 13 capable of displaying an image corresponding to 12 characters in one horizontal row (line) in three rows. Although an image representing characters is given here as an example, the display screen 13 of the LED module 10 can also display an image representing numbers, symbols, pictograms, and the like.

The display screen 13 is divided into, for example, a plurality of display areas A1, A2, A3, A4, and A5 surrounded by a broken line in FIG. The display area A1 is allocated an area for 6 characters from the left end of the first row, and the display area A2 is allocated an area for 6 characters from the right end of the first row. Further, the display area A3 is allocated 12 characters from the left end of the second row, that is, the entire area of the second row. Further, the display area A4 is allocated an area for 6 characters from the left end of the third row, and the display area A5 is allocated an area for 6 characters from the right end of the third row.

However, the setting of each width of the display areas A1 and A2 located in the first stage, in other words, the setting of the position of the boundary between the display areas A1 and A2, is the display portion of the image as will be described later with a specific example. It is possible to change dynamically by changing the length information that specifies. Further, the setting of each width (setting of the boundary position) of the display areas A4 and A5 located in the third stage can be dynamically changed in the same manner as in the first stage.

Returning to FIG. 1, the CPU 31 of the CPU board 30 executes the application program and the driver program stored in the memory 32, and controls the operation of the driver 33 and the like according to the respective programs. The CPU board 30 can be realized by using, for example, a microcomputer board equipped with Linux (registered trademark). An algorithm for controlling the display of the LED module 10 is described in the application program and the driver program. In the memory 32 of the CPU board 30, in addition to the above programs, display data such as text and image candidate groups to be displayed on the LED module 10 and character font data are recorded.

The driver 33 can set one of the pair of memories 51 and 52 of the controller board 50 as the memory for editing and the other as the memory for display, and can set the memory settings for editing and display. The process of switching is performed at a predetermined switching cycle Pc. Further, the driver 33 displays image data (dot image data) to be displayed in the display areas A1 to A5 of the LED module 10 in the memory set for editing under the control of the application program executed by the CPU 31. Write. Here, the image data indicates, for example, a color code corresponding to each dot. The color code will be described later. Further, the driver 33 includes head information and length information for specifying a display portion to be actually displayed in the display areas A1 to A5 of the LED module 10 for the image data written in the memory set for editing, and Write the setting information of the color palette to the memory for editing. In addition, the driver 33 follows the driver program executed by the CPU 31 in parallel with the writing process to the memory set for editing, and the start information and the length written in the memory set for display in the previous switching cycle. The information is changed at each timing of interrupt processing for image display. The interrupt process for displaying an image is a process performed to periodically update the display state of the LED module 10.

The pair of memories 51 and 52 of the controller board 50 are image data (dot image data) for displaying in each display area A1 to A5 of the LED module 10, head information and length for specifying a display portion of the image data. It is possible to record, erase, and rewrite the information and the setting information of the color palette that defines the combination (color arrangement) of the display color of the LED module 10. As described above, one memory is used for editing by the driver 33. , The other memory is switched and used for display.

The FPGA 53 sets the head information and the length of the display portion to be actually displayed in the display areas A1 to A5 of the LED module 10 for the image data recorded in the memory set for display among the pair of memories 51 and 52. It is specified based on the information, the image data corresponding to each of the specified display portions is concatenated according to a predetermined arrangement order, and then the concatenated image data is output to the LED module 10 as an image signal S. The specific operation contents of the FPGA 53 will be described later.

In the configuration of the above embodiment, the LED module 10 corresponds to the display unit in the present invention. Further, the pair of memories 51 and 52 on the controller board 50 correspond to the pair of recording areas of the recording unit in the present invention. Further, the CPU 31 and the driver 33 of the CPU board 30, and the FPGA 53 of the controller board 50 correspond to the control unit in the present invention.

Next, the operation of the display device 1 according to the present embodiment will be described.
Here, as a specific example, the operation of each part of the device when the display device 1 is installed at a predetermined place in the station yard and the train guide as shown in FIG. 3 is displayed on the display screen 13 of the LED module 10 is described in detail. explain.

In the train guidance example of FIG. 3, the departure time and destination of the starting train are fixedly displayed in the display area A1 on the left side of the first stage of the display screen 13, and the stop station of the train is shown in the display area A2 on the right side of the first stage. The text is moved to the left, so-called scroll display (or flow display). Further, in the display area A3 of the second stage, the approach information from the station in front of the train to the station is displayed as a moving image by pictogram, so-called animation. Further, the departure time and destination of the next train are fixedly displayed in the display area A4 on the left side of the third row, and the text indicating the stop station of the train is moved to the left in the display area A5 on the right side of the third row. To.

FIG. 4 is a flowchart for explaining the display operation of the train guide by the display device 1.
(Processing at device startup)
In the display device 1, when the main power supply (not shown) is turned on and the LED module 10, the CPU 31 of the CPU board 30, and the FPGA 53 of the controller board 50 are started, first, in step S101 of FIG. 4, the memory 32 of the CPU board 30 The driver program stored in is executed by the CPU 31, and the driver 33 starts operating according to the driver program. In the next step S102, the application program stored in the memory 32 is executed by the CPU 31. As a result, the CPU 31 (application), the driver 33, and the FPGA 53 each operate in parallel. Immediately after the start-up, the driver 33 performs the process of step S201 described later, and the FPGA 53 performs the process of step S301 described later.

When the application program is executed in step S102, the CPU 31 outputs an instruction to initialize the memories 51 and 52 of the controller board 50 to the driver 33 in subsequent step S103. As a result, the driver 33 writes blank data to the memories 51 and 52, respectively. When the initialization of the memories 51 and 52 is completed, the CPU 31 outputs a display start instruction to the driver 33 and the FPGA 53 in the next step S104. When the output of the display start instruction is completed, the process proceeds to the next step S105, and the CPU 31 is in a standby state waiting for the reception of the interrupt signal for image editing output from the driver 33 described later.

When the initialization of the internal memory is completed in step S201, the driver 33 waits for processing in the following step S202 until a display start instruction output from the CPU 31 is obtained. Upon receiving the display start instruction from the CPU 31 (YES), the process proceeds to the next step S203, and the standby state waits for the reception of the interrupt signal for image display output from the FPGA 53, which will be described later.

Further, when the initialization of the internal data is completed in step S301, the FPGA 53 waits for processing in the following step S302 until a display start instruction output from the CPU 31 is obtained in step S104 described above. Upon receiving the display start instruction from the CPU 31 (YES), the process proceeds to the next step S303, and the process waits until the timing corresponding to the update cycle Ps of the image signal S output to the LED module 10 is reached. The update cycle Ps of the image signal S is predetermined according to the specifications of the LED module 10 and the like, and the FPGA 53 rewrites the image signal S each time the update cycle Ps is reached. When the timing corresponding to the update cycle Ps is reached (YES), the process proceeds to the next step S304.

In step S304, the FPGA 53 uses the head information and the length information to be recorded in the memory 51 (or 52) by the process of step S107 described later, and each display area from the image data recorded in the memory. Each of the display portions to be displayed on A1 to A5 is specified, and the image data corresponding to each of the specified display portions is read from the display memory 51 (or 52). Here, it is a state immediately after the device is started, and blank data is written to the respective memories 51 and 52 in step S103 described above. Further, as the start information and the length information, data corresponding to a predetermined area is set. Therefore, the blank (black) data corresponding to the area is read from the memory.

In the following step S305, the FPGA 53 connects each of the read image data for each stage (row) of the display screen 13 of the LED module 10 to generate an image signal S, and the generated image signal S is connected to the connector board 70. It is output to the LED module 10 via. Here, since the blank data is read in the state immediately after the device is started as described above, the image signal S for displaying the display screen 13 of the LED module 10 in the blank (black) state is generated.

In the LED module 10 that has received the image signal S from the FPGA 53, in the subsequent step S306, the light emitting state of each of the LEDs 11 arranged in the display areas A1 to A5 is controlled according to the image signal S. Immediately after the device is started, the display screen 13 of the LED module 10 is in a blank (black) display state.

In the next step S307, the FPGA 53 determines whether or not the timing corresponds to the cycle Pi for executing the interrupt processing for image display. The interrupt processing cycle Pi for image display is set to a predetermined integer L times the update cycle Ps of the image signal S described above (Pi = Ps × L). When the cycle Pi of the interrupt processing for image display is satisfied (YES), the FPGA 53 generates an interrupt signal for image display and outputs it to the driver 33 in the next step S308. On the other hand, if it does not correspond to the interrupt processing cycle Pi for image display (NO), the process returns to step S303 described above.

When the interrupt signal for image display output from the FPGA 53 is received by the driver 33 in step S308 (YES in step S203), the driver 33 is at the timing corresponding to the memory switching cycle Pc in the next step S204. Judge whether or not. If it does not correspond to the memory switching cycle Pc (NO), the driver 33 changes the head information and the length information recorded in the display memory 51 (or 52) in the next step S205. In the state immediately after the device is started, since the blank data is written in the memories 51 and 52, the process of changing the head information and the length information is not executed. When the process of step S205 is completed, the process returns to step S203 described above to enter the reception standby state of the interrupt signal for image display.

On the other hand, if it is determined in step S204 that the memory switching cycle Pc is applicable (YES), the process proceeds to step S206, and the driver 33 switches between display and editing of the memories 51 and 52. .. In the state immediately after the device is started, one of the memories 51 and 52, here, the memory 51 is set for editing, and the other memory 52 is set for display.

In the following step S207, the driver 33 generates an interrupt signal for image editing and outputs it to the CPU 31. The interrupt signal for image editing includes new image data, start information, and new image data for displaying in each display area A1 to A5 in the next switching cycle Pc with respect to the memory 51 (or 52) set for editing. It is a signal indicating the timing to start the process for recording the length information and the setting information of the color palette. When the output of the interrupt signal for image editing is completed, the process returns to step S203 described above to enter the reception standby state of the interrupt signal for image display.

(Memory writing process for initial image data, etc.)
When the image editing interrupt signal output from the driver 33 in step S207 is received by the CPU 31 (YES in step S105), in the next step S106, the CPU 31 is recorded in the memory 32 of the CPU board 30. And / or images to be written to the memory 51 (or 52) of the controller board 50 corresponding to each display area A1 to A5 are extracted from the candidate group of images and images. Then, the CPU 31 creates image data (dot image data) corresponding to each of the extracted sentences and / or images. When creating image data corresponding to a sentence, it is possible to create dot image data by expanding the font data according to the characters, numbers, symbols, etc. that compose the sentence. The above-mentioned color code is specified for the data value of each dot of the created image data. As the color code, it is possible to specify the data value of one of the data values of a plurality of colors (for example, RGB values for 16 colors) described in the color palette. Table 1 below shows an example of the relationship between the color code, the RGB value of the color palette, and the display color. However, the relationship between the color code and the color palette is not limited to this.

When image data (dot image data) corresponding to each display area A1 to A5 is created in step S106, the CPU 31 in the next step S107 has a memory 51 (or 52) set for editing each image data. ) The position to write on is calculated, and the driver 33 is instructed to write the image data from each of the calculated positions. The driver 33 that receives the write instruction writes the image data corresponding to the display areas A1 to A5 created by the CPU 31 from the respective designated positions on the memory 51 (or 52).

When the process of writing each image data to the memory 51 (or 52) by the driver 33 is completed, the CPU 31 determines the start information and the length information used to specify the display portion of each image data, and the start information and the length information. The driver 33 is instructed of the change timing and the change amount, and the setting information of the color palette. Upon receiving the instruction from the CPU 31, the driver 33 writes the start information, the length information, and the color palette setting information into the memory 51 (or 52).

In the following step S108, the CPU 31 writes the image data, the start information and the length information corresponding to the display areas A1 to A5, and the color palette setting information to the memory 51 (or 52) by the process of the step S107. Judges whether or not is completed. When the writing is completed (YES), the process returns to step S105 described above to enter the reception standby state of the next interrupt signal for image editing. On the other hand, if the writing is not completed (NO), the processes of steps S106 and S107 are repeated.

FIG. 5 is a conceptual diagram showing initial image data recorded in the memory 51 set for editing of the controller board 50 (FIG. 1) by the series of processes of steps S105 to S108. As shown in FIG. 5, the memory 51 is surrounded by a broken line in FIG. 5 according to the size and display mode of each of the display areas A1 to A5 of the LED module 10 shown in FIG. Memory areas B1 to B5 as shown in the portion are allocated respectively. Initial image data (dot image data) for displaying in each of the display areas A1 to A5 is recorded in each of the memory areas B1 to B5.

The process of writing the image data or the like to the memory 51 for editing in steps S105 to S108 of FIG. 4 as described above includes the processes of steps S203 to S207 by the driver 33 and the processes of steps S303 to S308 by the FPGA 53. It is done in parallel. Then, when the driver 33 determines that the timing corresponding to the next memory switching cycle Pc has been reached (YES in step S204), the memory 51 (or 52) previously set for editing is used for display. The memory 52 (or 51) that has been switched and set for display can be switched for editing (step S206).

As a result, in the next switching cycle Pc, the memory 51 (or 52) in which the initial image data and the like are recorded is switched for display, and the driver 33 and FPGA 53 using the display memory 51 (or 52) are used. A series of image display processing is performed, and the memory 52 (or 51) in which blank data is recorded is switched for editing, and a series of operations by the CPU 31 and the driver 33 using the editing memory 52 (or 51). Image editing process will be performed.

(Image display processing)
More specifically, with reference to FIG. 4, as a series of image display processes using the display memory 51 (or 52), first, the FPGA 53 determines the timing corresponding to the update cycle Ps of the image signal S. Then (YES in step S303), the FPGA 53 uses the start information and the length information recorded in the display memory 51 (or 52) to display each display area from the image data recorded in the memory. Each of the display portions to be displayed on A1 to A5 is specified, and the image data corresponding to each of the specified display portions is read from the display memory 51 (or 52) (step S304). Then, the FPGA 53 connects each of the read image data for each stage (row) of the display screen 13 of the LED module 10 to generate an image signal S, and the generated image signal S is transmitted via the connector board 70. Output to the LED module 10 (step S305). In the LED module 10 that has received the image signal S from the FPGA 53, the light emitting state of each of the LEDs 11 arranged in the display areas A1 to A5 is controlled according to the image signal S (step S306). As a result, the train guide is displayed in each of the display areas A1 to A5.

Then, at the timing corresponding to the period Pi of the interrupt processing for image display (YES in step S307), the interrupt signal for image display is output from the FPGA 53 (step S308), and the interrupt signal for image display is the driver 33. (YES in step S203), the driver 33 corresponds to the number of times the interrupt processing for image display is executed according to the change timing and change amount of the head information and the length information previously instructed by the CPU 31. , The start information and the length information recorded in the display memory 51 (or 52) are changed (step S205). The process of changing the head information and the length information is repeatedly executed each time an interrupt signal for image display is received until the timing corresponding to the next memory switching cycle Pc is reached. The method of changing the head information and the length information will be described in detail later with specific examples. As a result, in the FPGA 53, each time the timing corresponding to the update cycle Ps of the image signal S is reached, the changed head information and length information recorded in the display memory 51 (or 52) are used to perform the operation. From the image data recorded in the memory, a display portion to be displayed in each display area A1 to A5 is specified.

(Image editing process)
The series of image editing processes using the editing memory 52 (or 51), which is performed in parallel with the series of image display processing using the display memory 51 (or 52) as described above, is described above. Similar to the case of writing the initial image data and the like shown in steps S105 to S108 to the memory 51, the CPU 31 and the driver 33 newly display the initial image data in the display areas A1 to A5 in the next switching cycle Pc. A process of recording various image data, start information, length information, and color palette setting information is performed.

In the following, regarding the series of operations in the present embodiment as described above, first, the operation of the display device 1 for fixing and moving the train guide in the display areas A1 and A2 of the LED module 10 will be specifically described. Next, the operation of the display device 1 for displaying the approach information of the train in the display area A3 as a moving image will be specifically described. In reality, these operations are performed in parallel. The display operation of the train guidance for the display areas A4 and A5 is the same as that for the display areas A1 and A2, and thus the description thereof will be omitted.

(Operation of fixed and moving display)
FIG. 6 shows an excerpt of the image data (dot image data) recorded in the memory 51 (or 52) of the controller board 50 for display, which corresponds to the display areas A1 and A2 of the LED module 10. It is a conceptual diagram. The upper part <1> of FIG. 6 shows the initial image data recorded in the memory 51 for display by the first writing process after the device is started. The middle row <2> and the lower row <3> of FIG. 6 show image data of the memories 52 and 51 switched from editing to display according to the switching cycle Pc.

In the example of FIG. 6, the width of the memory area B1 (the size in the X direction) is set to be equal to or larger than the width of the display area A1 where the fixed display is performed, and here, about twice. The width of the memory area B2 (the size in the X direction) is set to about three times the width of the display area A2 where the movement display is performed. The height (size in the Y direction) of the memory areas B1 and B2 is the same as the height (N dots) of the display areas A1 and A2. However, the settings of the respective memory areas B1 and B2 on the memory 51 are not limited to the above example, and can be appropriately set according to the capacity of the memory to be used and the like. As initial image data, image data representing the characters "12:34 Shin-Osaka" is written in the memory area B1 of the memory 51 with the left end as the starting point, and the left end as the starting point in the memory area B2. Image data representing the characters "Stop stations are Shin-Yokohama, Nagoya, and Kyoto." Is written.

The initial image data as described above is recorded in the memory areas B1 and B2 of the memory 51, and the head information and the length for specifying the display portion to be displayed in the display areas A1 and A2 of the LED module 10 are recorded. The information and the setting information of the color palette are also recorded. (See step S107 in FIG. 4 described above)

Specifically, the display portion corresponding to the display area A1 is 6 characters in full-width characters from the beginning of the image data recorded in the memory area B1 of the memory 51, and 6 × N dots in the number of dots in the X direction. Here, all of "12:34 Shin-Osaka" is the display part. In order to specify this display portion, as shown by the arrow line corresponding to the time T (0) in the upper part <1> of FIG. 6, the start code DP1 indicating the beginning of the display portion on the memory 51 is used as the start information. In addition to being specified, the length code DS1 indicating the total length in the X direction is specified as the length information.

Further, the display portion corresponding to the display area A2 corresponds to 6 characters (6 × N dots in the X direction) from the beginning of the image data recorded in the memory area B2 of the memory 51, and “the stop station is , New "is the display part. In order to specify this display portion, as shown by the arrow line corresponding to the time T (0) in the upper part <1> of FIG. 6, the start code DP2 indicating the beginning of the display portion on the memory 51 is used as the start information. In addition to being designated, the length code DS2 indicating the total length in the X direction is designated as the length information.

The times T (0), T (1), T (N), T (2N), ... In the figure indicate the timing at which the above-mentioned interrupt processing for image display is executed, and the numbers in parentheses indicate the timing. It corresponds to the number of times interrupt processing is executed. The period Pi at which the interrupt processing for image display is performed can be appropriately set to about several milliseconds to several milliseconds depending on the performance of the LED module 10 and the like. The switching cycle Pc of the memories 51 and 52 described above is sufficiently longer than the interrupt processing cycle Pi for image display, and here, for example, every time 3 × N interrupt processing is performed, the memory 51 and 52 are displayed. It is assumed that switching for editing is performed (Pc = 3 × N × Pi).

As each of the start codes DP1 and DP2, for example, an address of a memory (hereinafter, referred to as “dot address”) in which dot data located at the beginning of a display portion is stored can be specified. Further, as the length codes DS1 and DS2, for example, the number of todds corresponding to the total length of the display portion in the X direction can be specified. Regarding the total length (vertical width) of the display portion in the Y direction, it is possible to specify an arbitrary number of dots with the minimum unit as N dots, and here, the minimum unit of N dots (for example, as the specified value in the Y direction). , 8, 16 or 24 dots, etc.) is specified. However, this example does not mean that the vertical width is fixed in units of one character. For example, when displaying an image whose vertical width is 1.5 times larger than that of one character, the Y direction is used. 1.5 × N dots are specified as the specified value of.

By using the start codes DP1 and DP2 and the length codes DS1 and DS2 as described above, the FPGA 53 of the controller board 50 specifies the display portion to be displayed in the display areas A1 and A2, and the image corresponding to each display portion. Data is read from the memory 51 (step S304 in FIG. 4). Specifically, as shown in the upper part <1> of FIG. 7, the FPGA 53 identifies "12:34 Shin-Osaka" by using the start code DP1 and the length code DS1 at the time T (0), and also specifies the time T. Using the start code DP2 and the length code DS2 in (0), "the stop station is new" is specified, and the image data corresponding to each is read from the memory 51.

Each image data read from the memory 51 is connected by the FPGA 53 here according to the order of the display areas A1 and A2 on the LED module 10, and is shown in the lower part <2> of FIG. 34 The image data "Shin-Osaka stop station is new" is generated. The order in which the image data is connected does not necessarily have to match the order in which the display areas are arranged, and the image data can be connected in an arbitrarily specified order. Then, the FPGA 53 refers to the setting information of the color palette recorded in the memory 51, converts the color code indicated by the value of each dot in the concatenated image data into an RGB value or the like, and indicates the image data after the conversion. The image signal S is output to the LED module 10 via the connector board 70 (step S306 in FIG. 4).

In the LED module 10, the light emitting state of each LED 11 arranged in the display areas A1 and A2 of the first stage is controlled according to the image signal S from the FPGA 53. As a result, as shown in the time T (0) at the top of FIG. 8, "12:34 Shin-Osaka" is displayed in the display area A1 of the LED module 10, and "stop station" is displayed in the display area A2. Is new ”is displayed (step S306 in FIG. 4).

After the first train guidance is displayed in the display areas A1 and A2 of the LED module 10 as described above, when the interrupt processing cycle Pi for image display elapses and the first interrupt time T (1) is reached, An interrupt signal for displaying an image is output from the FPGA 53 of the controller board 50 to the driver 33 of the CPU board 30 (step S308 in FIG. 4). In the driver 33 that has received the interrupt signal for image display, the head information and the length information recorded in the memory 51 are stored in accordance with the change timing and the change amount of the head information and the length information previously instructed by the CPU 31. The process of changing to the start information and the length information in the first interrupt time T (1) is performed (step S205 in FIG. 4). In addition, in the upper part <1> of FIG. 6, since the amount of change of the head information in one interrupt process is small (+1 dot as described later), the first time by expanding the amount of change from the actual value. The start codes DP1 and DP2 and the length codes DS1 and DS2 corresponding to the interrupt time T (1) of the above can be illustrated. Further, FIG. 6 shows a state corresponding to interrupt processing every N times after the first interrupt processing, and FIG. 8 shows a state corresponding to interrupt processing every N times. Is changed from the start code DP1 and DP2 and the length codes DS1 and DS2 each time interrupt processing is performed.

Specifically, as shown by the arrow line corresponding to the time T (1) in the upper part <1> of FIG. 6, for the display area A1 in which the fixed display is performed, the change timing and change amount of the head information and the length information. However, when both are instructed to be unchanged, the same start code DP1 and length code DS1 are set at all timings of the interrupt processing executed periodically. On the other hand, regarding the display area A2 where the movement display is performed, for example, when the image display is moved to the left by one dot each time the interrupt processing cycle Pi elapses, the interrupt processing is changed as the change timing. Each time, +1 dot is specified as the change amount of the head information, and 0 dot (no change) is specified as the change amount of the length information. As a result, as the start code DP2 in the first interrupt time T (1), the address of the dot located second from the start point (left end of the memory area B2) of the image data recorded in the memory area B2 of the memory 51 is used. Set. Further, as the length code DS2 in the first interrupt time T (1), the same number of dots (6 × N dots) for 6 characters as in the case of the time T (0) described above is set.

Therefore, the driver 33 uses the head information and the length information recorded in the memory 51, that is, the start codes DP1 and DP2 and the length codes DS1 and DS2 at the time T (0) described above for the first time as described above. The start codes DP1 and DP2 and the length codes DS1 and DS2 at the interrupt time T (1) of the above are rewritten. As a result, the FPGA 53 uses the start codes DP1 and DP2 and the length codes DS1 and DS2 at the first interrupt time T (1) recorded in the memory 51 to obtain each of the image data recorded in the memory 51. A display portion to be displayed in the display areas A1 and A2 is specified, and image data corresponding to each display portion is read from the memory 51 (step S304 in FIG. 4). Then, the FPGA 53 concatenates each image data read from the memory 51, and outputs an image signal S indicating the image data in which the color code corresponding to each dot is converted into an RGB value or the like to the LED module 10 via the connector board 70. (Step S305 in FIG. 4). As a result, although not shown in FIG. 8 as described above, the same image as at the time T (0) is fixedly displayed in the display area A1 and at the time T (0) in the display area A2. An image that has been moved by one dot to the left with respect to the image is displayed (step S306 in FIG. 4).

After that, the same operation as described above is repeated every time the interrupt processing cycle Pi elapses. In the upper part <1> of FIG. 6 described above, the start codes DP1, DP2 and the lengths of the memory 51 rewritten by the driver 33 when the Nth interrupt time T (N), which is the same as the number of dots for one character, is reached. Codes DS1 and DS2 are shown. At the Nth interrupt time T (N), the start code DP1 and the length code DS1 of the display portion corresponding to the display area A1 where the fixed display is performed are the same as those before that. On the other hand, as the start code DP2 of the display portion corresponding to the display area A2 where the movement display is performed, the dot located N + 1th from the start point of the image data recorded in the memory area B2 of the memory 51, that is, the second character. The address of the starting dot is set, and the number of dots (6 × N) for 6 characters is set as the length code DS2. As a result, the image data of "12:34 Shin-Osaka" is specified as the display part of the display area A1 in the Nth interrupt time T (N), and the display part of the display area A2 is "Car station is Shinyoko". Image data is identified.

Therefore, in the Nth interrupt time T (N), in the display areas A1 and A2 of the LED module 10, "12:34 Shin-Osaka car station is Shin-Yoko" as shown in the second stage <2> of FIG. Will be displayed. As is clear from comparing the display states of T (0) and T (N) at each time, the image displayed in the display area A2 is subjected to N times of interrupt processing, which is the same as the number of dots for one character. Then, it is moved to the left by one character, and so-called scroll display (or flow display) is realized.

The upper <1> of FIG. 6 described above is rewritten by the driver 33 when the 2 × Nth interrupt time T (2N), which is the same as the number of dots for two characters, is reached in the interrupt processing executed thereafter. The start codes DP1 and DP2 and the length codes DS1 and DS2 of the memory 51 to be generated are shown. The start code DP2, which will be changed with the passage of time, is the 2 × N + 1th from the start point of the image data recorded in the memory area B2 of the memory 51 at the 2 × Nth interrupt time T (2N). The address of the dot located at, that is, the dot at the beginning of the third character is set. As a result, "12:34 Shin-Osaka Station is Shin-Yokohama" as shown in the third row <3> of FIG. 8 is displayed in the display areas A1 and A2 of the LED module 10. Focusing on the transition of the display state of the display area A2, the initial image is scrolled and displayed by moving two characters to the left while the interrupt processing is performed 2 × N times.

The control of displaying the train guidance in the display areas A1 and A2 of the LED module 10 using the image data recorded in the memory 51 as described above is continued until the switching cycle Pc of the memories 51 and 52 arrives. .. Here, as described above, the switching cycle Pc of the memories 51 and 52 is set to the time during which interrupt processing is performed 3 × N times, which is the same as the number of dots for three characters. Therefore, the upper part <1 of FIG. The display control of the display areas A1 and A2 using the image data of the memory 51 shown in> is immediately before the interrupt processing of 3 × N times is performed, that is, the interrupt time T (3N−) of the 3 × N-1th time. It will be continued until 1).

While the display control of the display areas A1 and A2 using the image data of the memory 51 is being performed, the memory 52 set for editing is subjected to the next switching cycle by the driver 33 instructed by the CPU 31. The process of creating and recording new image data to be displayed in the display areas A1 and A2 by Pc, the process of recording the start information and the length information, and the process of recording the setting information of the color palette are performed (FIG. 4). Steps S106, S107). That is, the CPU 31, the driver 33, and the FPGA 53 use the image data of the memory 51 to display the train guidance in the display areas A1 and A2 (steps S203 to S207 and S303 to S308 in FIG. 4), and the following A process of writing new image data or the like used in the switching cycle Pc to the memory 52 (steps S105 to S108 in FIG. 4) is performed. The process of writing the image data or the like to the memory 52 may be completed during the period from the first interrupt process to the 3 × N-1th interrupt process. Therefore, the load on the CPU 31 in the image data writing process is significantly reduced as compared with the case where the image data is rewritten each time the interrupt process is performed.

When the 3 × Nth interrupt time T (3N) is reached, the driver 33 of the CPU board 30 switches between the memories 51 and 52, the memory 52 is set for display, and the memory 51 is set for editing ( Step S206 in FIG. 4). In the middle row <2> of FIG. 6, the image data recorded in the memory areas B1 and B2 of the memory 52 set for display after switching is shown. "12:34 Shin-Osaka" is written in the memory area B1 of the memory 52 starting from the left end, and "is Shin-Yokohama, Nagoya, Kyoto." Is written in the memory area B2 starting from the left end. "Is written.

Using the image data recorded in the memory areas B1 and B2 of the memory 52 as described above, the display control of the display areas A1 and A2 similar to the case of the time T (0) to T (3N-1) described above can be performed. Will be done. Specifically, in the 3 × Nth interrupt time T (3N), the start code DP1 and the length code DS1 of the display portion corresponding to the display area A1 where the fixed display is performed are the same as before. On the other hand, as the start code DP2 of the display portion corresponding to the display area A2 in which the movement display is performed, the address of the dot located at the start point (left end of the memory area B2) of the image data recorded in the memory area B2 of the memory 52 is used. As the length code DS2, the number of dots (6 × N) for 6 characters is specified.

As a result, the image data of "12:34 Shin-Osaka" is specified as the display part of the display area A1 in the 3 × Nth interrupt time T (3N), and the display part of the display area A2 is “ha, Shin-Yokohama,” Image data is identified. Therefore, in the 3 × Nth interrupt time T (3N), in the display areas A1 and A2 of the LED module 10, “12:34 Shin-Osaka is Shin-Yokohama,” as shown in the fourth stage <4> of FIG. Will be displayed. Focusing on the transition of the display state of the display area A2, the initial image is scrolled and displayed by moving to the left by 3 characters while the interrupt processing is performed 3 × N times.

After the following 3 × N + 1th interrupt time T (3N + 1), until the next switching cycle Pc of the memories 51 and 52 arrives, specifically, immediately before the interrupt processing of 6 × N times is performed, that is, 6 × N-Up to the first interrupt time T (6N-1), the display control of the display areas A1 and A2 using the image data of the memory 52 is the above-mentioned interrupt times T (1) to T (3N-1). It is carried out in the same manner as in the case of. In parallel with this, the CPU 31 performs a process of rewriting the image data or the like recorded in the memory areas B1 and B2 of the memory 51 set for editing with new image data or the like to be used in the next switching cycle Pc. And by the driver 33. When the interrupt time T (6N) of 6 × N times is reached, the memory 51 and 52 are switched between the second display and the edit, although not shown here, and the display control is the same as in the above case. And the rewriting process of image data and the like are repeatedly performed in parallel.

In the lower part <3> of FIG. 6, the 12 × Nth interrupt time T (12N) is set, and the image recorded in the memory 51 set for display after the fourth switching of the memories 51 and 52 is performed. The data is shown. "12:34 Shin-Osaka" is written in the memory area B1 of the memory 51 starting from the left end, and ", Kyoto. The stop stations are Shin-Yokohama and Nagoya" starting from the left end in the memory area B2. "Is written. In the display control of the display areas A1 and A2 using the image data of the memory 51, for example, the 13 × Nth interrupt time T (13N) is as shown in the second stage <5> from the bottom of FIG. "12:34 Shin-Osaka Kyoto." Is displayed, and at the interrupt time T (14N) of 14 x N times, "12:34 Shin-Osaka is the capital" as shown in the bottom <6> of Fig. 8. "Stop" is displayed. In this way, in the movement display in the display area A2, a series of guidances such as "Stop stations are Shin-Yokohama, Nagoya, and Kyoto" are continuously and repeatedly scrolled (or flow-displayed).

(Video display operation)
Next, the operation of the display device 1 for displaying the train approach information (see FIG. 3) as a moving image in the display area A3 of the LED module 10 will be described.

FIG. 9 is a conceptual diagram showing an excerpt of a portion of image data recorded in the memory 51 (or 52) of the controller board 50 for display, which corresponds to the display area A3 of the LED module 10. The upper part <1> of FIG. 9 shows the initial image data recorded in the memory 51 by the first writing process after the device is started. Further, in the lower part <2> of FIG. 9, the image data recorded in the memory 52 switched from the editing to the display in the next switching cycle Pc is shown. A memory area B3 corresponding to the display area A3 is allocated to the memory 51 (or 52), and the width (size in the X direction) of the memory area B3 is set to be three times or more the width of the display area A3. Has been done. The height of the memory area B3 (size in the Y direction) is the same as the height of the display area A3 (N dots).

In the memory area B3 of the memory 51 shown in the upper part <1> of FIG. 9, as initial image data, a train traveling between the characters of "mae station" and "this station" and the station, starting from the left end thereof. The image data of the three patterns depicting the pictogram representing the above is written side by side in the X direction (step S107 in FIG. 4). The image data of each pattern has the same overall length in the X direction as the width of the display portion A3. The difference in the image data of each pattern is the state of ">>>>" drawn in the lower left of the pictogram of the train.

In the following description, the image data located on the leftmost side of the memory area B1 in the upper part <1> of FIG. 9 and in which ">" is drawn in the pictogram is used as the first pattern. Further, the image data located to the right of the image data of the first pattern and having ">>" drawn on the pictogram is defined as the second pattern. Further, the image data located to the right of the image data of the second pattern and having ">>>" drawn on the pictogram is defined as the third pattern.

Initial image data as described above is recorded in the memory area B3 of the memory 51, and head information and length information for specifying a display portion to be displayed in the display area A3 of the LED module 10 and colors. Palette setting information is also recorded (step S107 in FIG. 4). The display portion to be displayed in the display area A3 is any one of the three patterns of image data recorded in the memory area B3 of the memory 51, and the image data of the first pattern is the first display portion.

In order to specify the display portion, as shown by the arrow line corresponding to the time T (0) in the upper part <1> of FIG. 9, the start code DP3 indicating the beginning of the display portion on the memory 51 is used as the start information. At the same time as being set, the length code DS3 indicating the total length in the X direction is specified as the length information. Specifically, as the start code DP3 at the time T (0), the address of the dot located at the start point (left end of the memory area B3) of the image data recorded in the memory area B3 of the memory 51 is specified. Further, as the length code DS3 at the time T (0), since the display portion A3 has a width of 12 characters here, the number of dots (12 × N dots) for 12 characters in the X direction is increased. It is specified. Regarding the total length (vertical width) of the display portion in the Y direction, it is possible to specify an arbitrary number of dots with the minimum unit as N dots, as in the case of the memory areas B1 and B2 described above. The minimum unit N dots (for example, 8, 16 or 24 dots) is specified as the specified value in the Y direction.

By using the start code DP3 and the length code DS3 as described above, the FPGA 53 of the controller board 50 identifies the display portion to be displayed in the display area A3, and reads the image data corresponding to the display portion from the memory 51 ( Step S304 in FIG. 4). Then, the FPGA 53 refers to the setting information of the color palette recorded in the memory 51, converts the color code indicated by the value of each dot in the image data read from the memory 51 into an RGB value or the like, and the converted image. An image signal S indicating data is output to the LED module 10 via the connector board 70 (step S305 in FIG. 4).

In the LED module 10, the light emitting state of each LED 11 arranged in the display area A3 is controlled according to the image signal S from the controller board 50. As a result, as shown in the time T (0) in the uppermost row <1> of FIG. 10, the pictograms of the trains on which ">" are drawn are displayed in the display area A3 of the LED module 10 as "front station" and "this time". An image located between the letters "station" is displayed (step S306 in FIG. 4).

After the approach information of the first train is displayed in the display area A3 of the LED module 10 as described above, when the interrupt processing cycle Pi for image display elapses and the first interrupt time T (1) is reached, In the driver 33 of the controller board 50, the head information and the length information recorded in the memory 51 are interrupted for the first time according to the change timing and the change amount of the head information and the length information previously instructed by the CPU 31. The process of changing to the head information and the length information in T (1) is performed (step S205 in FIG. 4). Here, the cycle Pi of one interrupt processing is shorter than the image update cycle Pr for realizing the moving image display, and the image for the moving image is updated every time the interrupt processing is performed M times. (Pr = M × Pi). In this case, in the interrupt processing from the first time to the M-1 time, the same start code DP3 and length code DS3 as at the time T (0) described above are set. The update cycle Pr of the image can be appropriately set according to the frame rate of the moving image and the like.

When the Mth interrupt time T (M) is reached, the driver 33 uses the start code DP3 and the length code DS3 at the time T (0) recorded in the memory 51 as shown in the upper part <1> of FIG. Is rewritten as the start code DP3 and the length code DS3 at the Mth interrupt time T (M). Specifically, as the start code DP3 at the Mth interrupt time T (M), the address of the beginning of the image data of the second pattern, that is, the address of the 12 × N + 1th todd in the X direction from the left end of the memory area B3 is set. Will be done. The length code DS3 at the Mth interrupt time T (M) is set to the same 12 × N dots as at the time T (0). As a result, the FPGA 53 uses the start code DP3 and the length code DS3 at the Mth interrupt time T (M) recorded in the memory 51 to select the interrupt time T (from the image data recorded in the memory 51). The image data of the second pattern is specified as the display portion of the display area A3 in M) (step S304 in FIG. 4). Therefore, in the display area A3 of the LED module 10 in the interruption time T (M), as shown in the second stage <2> of FIG. 10, the pictogram of the train on which ">>" is drawn is "mae station". Images located between the letters "this station" will be displayed (steps S305 and S306 in FIG. 4).

After that, in the same manner as in the case of the Mth interrupt time T (M), when the 2 × Mth interrupt time T (2M) corresponding to the image update cycle Pr is reached, the driver 33 moves the driver 33 to the upper part of FIG. As shown in 1>, the start code DP3 and the length code DS3 at the time T (M) recorded in the memory 51 are replaced with the start code DP3 and the length code DS3 at the 2 × Mth interrupt time T (2M). Rewrite to DS3. Specifically, as the start code DP3 of the 2 × Mth interrupt time T (2M), the address of the beginning of the image data of the third pattern, that is, the address of the 24 × N + 1th dot in the X direction from the left end of the memory area B3. Is set. As the length code DS3, the same 12 × N dots as at the time T (0) are set.

As a result, in the display area A3 of the LED module 10, as shown in the third stage <3> of FIG. 10, the pictograms of the train on which ">>>>" is drawn are the "front station" and the "this station". The image located between the characters will be displayed. Focusing on the transition of the pictogram of the train, it can be seen that the number of ">" in the lower left gradually increases and the train is running toward this station while the interrupt processing is performed 2 x M times. Displayed by animation.

The control of displaying the train approach information in the display area A3 of the LED module 10 using the image data recorded in the memory 51 as described above is continued until the switching cycle Pc of the memories 51 and 52 arrives. Here, for example, it is assumed that the image for moving image is updated three times, that is, the memory 51 and 52 are switched between display and editing at the timing when the 3 × Mth interrupt processing is executed. In this case, the display control of the display area A3 using the image data of the memory 51 shown in the upper part <1> of FIG. 9 is immediately before the interrupt processing of 3 × M times is performed, that is, the 3 × M-1 time. It is continuously performed until the interrupt time T (3M-1) of.

Regarding the switching cycle Pc between the display and editing of the memories 51 and 52, the number of interrupt processes in which the display and editing of the memories 51 and 52 are switched in the display control of the display areas A1 and A2 described above ( Since a common memory is used for 3 × N) and the number of interrupt processes (3 × M) for switching between display and editing of memories 51 and 52 in the moving image display of the display area A3. Need to match. For that purpose, in the moving image display of the display area A3, the number of interrupt processes M for updating the image is set to be equal to the number of dots N for one character (M = N). If the above settings are difficult due to restrictions such as the frame rate of the video, adjust the number of image updates (3 times in the above example) until the memory 51 and 52 are switched between display and editing. To match the number of interrupt processing.

While the display control of the display area A3 using the image data of the memory 51 is being performed, the memory 52 set for editing is subjected to the next switching cycle Pc by the driver 33 instructed by the CPU 31. A process of recording new image data to be displayed in the display area A3, start information, length information, and color palette setting information is performed (steps S106 and S107 in FIG. 4). That is, the CPU 31, the driver 33, and the FPGA 53 switch to the next in parallel with the process of displaying the approach information in the display area A3 using the image data of the memory 51 (steps S203 to S207, S303 to S308 in FIG. 4). A process of writing new image data or the like used in the period Pc to the memory 52 (steps S105 to S108 in FIG. 4) is performed. The writing process to the memory 52 may be completed while the interrupt processing from the first time to the 3 × M-1th time is executed.

When the 3 × Mth interrupt time T (3M) is reached, the driver 33 of the CPU board 30 switches between the memories 51 and 52, the memory 52 is set for display, and the memory 51 is set for editing. (Step S206 in FIG. 4). In the lower part <2> of FIG. 9, image data recorded for display in the memory area B3 of the memory 52 after switching is shown. In the memory area B3 of the memory 52, image data of three patterns are written side by side in the X direction starting from the left end thereof. The difference from the image data of the first to third patterns shown in the upper part <1> of FIG. 9 is that the pictogram of the train is approaching the "this station" side.

Using the image data recorded in the memory area B3 of the memory 52 as described above, the display control of the display area A3 is performed in the same manner as in the case of the interrupt times T (0) to T (3M-1) described above. Specifically, at the 3 × Mth interrupt time T (3M), the start code DP3 is the address of a dot located at the start point (left end of the memory area B3) of the image data recorded in the memory area B3 of the memory 52. Is set. Further, as the length code DS3, 12 × N dots in the X direction are set. As a result, as the display portion of the display area A3 in the 3 × Mth interrupt time T (3M), the image data of the first pattern in which the pictogram of the train approaches the “this station” side is specified. Therefore, in the 3 × Mth interrupt time T (3M), the train approach information as shown in the fourth stage <4> of FIG. 10 is displayed in the display area A3 of the LED module 10.

Then, when the 4 × Mth interrupt time T (4M) is reached, the start code DP3 and the length code DS3 as shown in the lower part <2> of FIG. 9 are set, and the 4 × Mth interrupt time T (4M) is set. ), The image data of the second pattern in which the pictogram of the train approaches the "this station" side is specified as the display portion of the display area A3. Therefore, in the 4 × Mth interrupt time T (4M), the train approach information as shown in the fifth stage <5> of FIG. 10 is displayed in the display area A3 of the LED module 10. After that, the same display control is repeatedly performed for each image update cycle.

As described above, according to the display device 1 of the present embodiment, with respect to the image data for each display area recorded in the memories 51 and 52, the display portion to be displayed in each display area has a start code and a length code. By using and specifying and changing the start code according to the display mode (moving display, moving image display) of each display area, it is not necessary to provide hardware according to each display mode. , The start code and the length code, which have a small processing load, can be used to move and display an image containing characters in each display area or to display a moving image. Such a display device 1 has a simple configuration and can be realized at low cost.

Further, the display device 1 of the present embodiment is flexible because even if the layout or display mode of the display area is changed, it can be dealt with by changing the start code or the length code according to the change contents. It can be operated. Further, the display device 1 newly uses the memory set for editing in the next memory switching cycle in parallel with the display control of each display area using the image data of the memory set for display. Since various image data are recorded, the load on the software can be significantly reduced as compared with the case where the image data in the memory is redrawn each time the interrupt processing is performed. This makes it possible to perform moving display and moving image display while smoothly changing images for a plurality of display areas.

In the above-described embodiment, an example in which the display device 1 is installed at a predetermined place in the station yard and the train guide is displayed in each display area of the LED module 10 has been described, but the present invention is not limited to this, for example. , It is also possible to display information on various facilities in the station yard and facilities around the station, or to install it on airports, roads, parking lots, commercial facilities, etc. to display various information.

Further, regarding the movement display of the display area A2 described with reference to FIGS. 6 to 8, an example in which the image is moved by one dot each time for the periodic interrupt processing is shown. For example, two interrupt processings are shown. The image may be moved by 1 dot, that is, the image may be moved by 1 dot by the interrupt processing of the interval. In this way, the moving (scrolling) speed of the image can be halved. The rate at which the image is moved by one dot with respect to the periodic interrupt processing can be appropriately set according to the scroll speed. Further, the moving direction of the image is not limited to the left direction illustrated in the embodiment, and of course, the moving direction of the image is also possible. In the case of moving to the right, the amount of change in the head information may be opposite to that in the case of moving to the left.

Further, in the above-described embodiment, an example is shown in which one row in the horizontal direction of the LED module 10 is divided into two display areas A1 and A2 (or A4 and A5) for display (FIG.). (2, see FIG. 3) It is of course possible to divide one column into three or more display areas for display. Specifically, assuming that one stage can be divided into a maximum of n (n ≧ 3) display areas, image data (dots) for displaying in n display areas A1, A2, ..., An. (Image data) is recorded in the memory 51 (or 52), and the display portion of the image data is a set of a start code and a length code (DP1, DS1), (DP2, DS2), ..., (DPn, DSn). Will be specified using. At this time, for example, when it is desired that the display area An is not displayed, that is, the display is divided into n-1 display areas A1 to An-1, the (DPn, DSn) is (0, It is possible to deal with it by specifying 0). By designating the start code and the length code in this way, the number of divisions in one stage can be flexibly set and changed.

Further, in the above-described embodiment, the case where the widths of the display areas A1 to A5 of the LED module 10 are fixed has been described, but by changing the length information (length code) used for specifying the display portion. It is also possible to dynamically change the width of the display area. Hereinafter, a modified example corresponding to this will be described.

(Modification example)
Here, FIGS. 11 and 12 show a case where the widths of the display areas A1 and A2 of the LED module 10 (positions of boundaries of the display areas A1 and A2) of the LED module 10 in the above-described embodiment are dynamically changed by changing the length code. It will be explained concretely with reference to it. FIG. 11 shows image data for the display areas A1 and A2 recorded in the memory 51 (or 52) of the controller board 50 for display in the above modification, and FIG. 12 shows the display area A1 of the LED module 10. , A2 shows the changes in the image displayed.

In this modification, a so-called wipe display is performed in which the numbers displayed in the display area A1 of the LED module 10 are erased by the alphabet displayed in the display area A2 with the passage of time.
(Wipe display operation)
Specifically, as initial image data, image data representing the number "0123456789" is written in the memory area B1 of the memory 51 shown in the upper part <1> of FIG. 11 starting from the left end thereof. Further, as initial image data, image data representing the alphabet of "ABCD" is written in the memory area B2 starting from the left end thereof.

With respect to the image data recorded in the memory areas B1 and B2 of the memory 51, in order to specify the display portion to be displayed in the display areas A1 and A2 of the LED module 10, the time T (1) in the upper part of FIG. The start codes DP1 and DP2 and the length codes DS1 and DS2 as shown by the arrow lines corresponding to 0) are written in the memory 51 by the driver 33. Specifically, the start code DP1 for specifying the display portion of the display area A1 at the time T (0) is located at the start point (left end of the memory area B1) of the image data recorded in the memory area B1 of the memory 51. The address of the dot to be used is set, and the number of dots (10 × N) for 10 characters is set as the length code DS1. As a result, the image data of "0123456789" is specified as the display portion of the display area A1 at the time T (0).

Further, as the start code DP2 for specifying the display portion of the display area A2 at the time T (0), a dot located at the start point (left end of the memory area B2) of the image data recorded in the memory area B2 of the memory 51. The address of is set, and the number of dots (2 × N) for two characters is set as the length code DS2. As a result, the image data of "AB" is specified as the display portion of the display area A2 at the time T (0).

The image data of the display portion of each of the specified display areas A1 and A2 is connected by the FPGA 53 of the controller board 50 according to the arrangement order of the display areas A1 and A2, and the color indicated by the value of each dot in the image data after connection. The code is converted into RGB values and the like, and an image signal S indicating the converted image data is output from the controller board 50 to the LED module 10 via the connector board 70. As a result, as shown in the time T (0) in the uppermost row <1> of FIG. 12, "0123456789" is displayed in the display area A1 of the LED module 10, and "AB" is displayed in the display area A2. Will be. The width of the display area A1 at this time is the number of dots (10 × N) for 10 characters corresponding to the length code DS1, and the width of the display area A2 is the number of dots for 2 characters corresponding to the length code DS2. It becomes (2 × N). The boundary between the display areas A1 and A2 is located between the 10 × N dot and the 10 × N + 1 dot from the left end of the display area A1.

Then, when the interrupt processing cycle Pi elapses, the start codes DP1 and DP2 in the first interrupt time T (1) and as shown by the arrow line corresponding to the time T (1) in the upper part <1> of FIG. The length codes DS1 and DS2 are set. Here, as a display mode of each display area A1 and A2, the display of the image in the display area A2 moves to the left by one dot each time the interrupt processing cycle Pi elapses, and the total length in the X direction is increased. It is assumed that the display area A1 is set to be one dot shorter and the display area A2 is set to be one dot longer.

In such a display mode setting, the same address as at the time T (0) described above is set as the start code DP1 for specifying the display portion of the display area A1 in the first interrupt time T (1). As the length code DS1, a value (10 × N-1 dots) obtained by subtracting 1 dot from the number of dots for 10 characters is set. Further, as the start code DP2 for specifying the display portion of the display area A2 in the first interrupt time T (1), the same address as in the case of the time T (0) described above is set, and the length code DS2 is set. Is set to a value (2 × N + 1 dot) obtained by adding 1 dot to the number of dots for 2 characters.

After that, every time the interrupt processing cycle Pi elapses, the start codes DP1 and DP2 and the length codes DS1 and DS2 are repeatedly changed in the same manner as described above. In the upper part <1> of FIG. 11 described above, the start code specified when the Nth interrupt time T (N), which is the same as the number of dots for one character, is reached after the first interrupt time T (1). DP1, DP2 and length codes DS1, DS2 are shown. In the Nth interrupt time T (N), the same address as in the time T (0) described above is set as the start code DP1 for specifying the display portion of the display area A1, and the length code DS1 is set. , The number of dots (9 × N) for 9 characters is set. Further, as the start code DP2 for specifying the display portion of the display area A2, the same address as at the time T (0) described above is set, and as the length code DS2, the number of dots for three characters (3). × N) is set.

As a result, the image data of "012345678" is specified as the display portion of the display area A1 in the Nth interrupt time T (N), the image data of "ABC" is specified as the display portion of the display area A2, and the LED module 10 In each of the display areas A1 and A2, an image as shown in the second row <2> of FIG. 12 is displayed. At this time, the width of the display area A1 is the number of dots (9 × N) for 9 characters corresponding to the length code DS1, and the width of the display area A2 is the number of dots for 3 characters corresponding to the length code DS2. It becomes (3 × N). The boundary between the display areas A1 and A2 is located between the 9 × N dot and the 9 × N + 1 dot from the left end of the display area A1. Compared with the case of the time T (0) described above, each width of the display areas A1 and A2 (the position of the boundary between the display areas A1 and A2) dynamically changes during the Nth interrupt processing. ing.

In the upper part <1> of FIG. 11 described above, the start set when the 2 × Nth interrupt time T (2N), which is the same as the number of dots for two characters, is reached among the interrupt processes executed thereafter. Codes DP1 and DP2 and length codes DS1 and DS2 are shown. As the start code DP1 at the 2 × Nth interrupt time T (2N), the same address as at the time T (0) described above is set, and as the length code DS1, the number of dots for 8 characters (8 ×). N) is set. Further, as the start code DP2 at the 2 × Nth interrupt time T (2N), the same address as at the time T (0) described above is set, and as the length code DS2, the number of dots for 4 characters ( 4 × N) is set. As a result, as shown in the third row <3> of FIG. 12, "01234567" is displayed in the display area A1 of the LED module 10, and "ABCD" is displayed in the display area A2.

The display control of the display areas A1 and A2 using the image data recorded in the memory 51 shown in the upper part <1> of FIG. 11 is for display and editing of the memories 51 and 52, as in the case of the above-described embodiment. It is continuously performed until the switching cycle Pc for use is reached, that is, until the 3 × N-1th interrupt time T (3N-1). Then, when the 3 × Nth interrupt time T (3N) is reached, the driver 33 of the CPU board 30 switches between the display and editing of the memories 51 and 52, and the memory 52 is set for display. 51 is set for editing. In the middle <2> of FIG. 11, the image data recorded in the memory areas B1 and B2 of the memory 52 after switching is shown. "0123456789" is written in the memory area B1 of the memory 52 starting from the left end thereof, and "ABCDEFG" is written in the memory area B2 starting from the left end thereof.

Using the image data recorded in the memory 52 as described above, the display control of the display areas A1 and A2 is performed in the same manner as in the case of the time T (0) to T (3N-1) described above. Specifically, as the start code DP1 at the 3 × Nth interrupt time T (3N), the address of the dot located at the start point of the image data recorded in the memory area B1 of the display memory 52 is set and has a length. As the code DS1, the number of dots (7 × N) for 7 characters is set. Further, as the start code DP2 at the 3 × Nth interrupt time T (3N), the address of the dot located at the start point of the image data recorded in the memory area B2 of the display memory 52 is set, and the length code DS2 The number of dots (5 × N) for 5 characters is set as. As a result, as shown in the fourth row <4> of FIG. 12, "0123456" is displayed in the display area A1 of the LED module 10, and "ABCDE" is displayed in the display area A2.

After that, the display control of the display areas A1 and A2 similar to the above case is repeatedly performed. In the lower part <3> of FIG. 11, the interrupt time T (9N) is 9 × N times, and is set for display after the third switching between the display and editing of the memories 51 and 52 is performed. The image data recorded in the memory 52 is shown. "0123456789" is written in the memory area B1 of the memory 52 starting from the left end, and "ABCDEFGHIJKL" is written in the memory area B2 starting from the left end.

As the start code DP1 at the 9 × Nth interrupt time T (9N), the address of the dot located at the start point of the image data recorded in the memory area B1 of the memory 52 is set, and the length code DS1 is 1. The number of dots (N) for characters is set. Further, as the start code DP2 at the 9 × Nth interrupt time T (9N), the address of the dot located at the start point of the image data recorded in the memory area B2 of the memory 52 is set, and the length code DS2 is set. , The number of dots (11 × N) for 11 characters is set. As a result, as shown in the second row <5> from the bottom of FIG. 12, "0" is displayed in the display area A1 of the LED module 10, and "ABCDEFGHIJK" is displayed in the display area A2. ..

Then, when the 10 × Nth interrupt time T (10N) is reached, the same address is set as the start code DP1 as in the case of the 9 × Nth interrupt time T (9N) described above, and the length code DS1 is set. 0 is set. Further, as the start code DP2, the same address as in the case of the 9 × Nth interrupt time T (9N) described above is set, and as the length code DS2, the number of dots (12 × N) for 12 characters is set. Will be done. As a result, as shown in the lowermost row <6> of FIG. 12, all the images (numbers) displayed in the display area A1 until then are erased by the images (alphabets) displayed in the display area A2, and a series of images (alphabets) are erased. Wipe display is completed.

According to the modification as described above, the boundary setting of a plurality of display areas can be easily changed, so that more flexible operation is possible. Various multi-window displays can be realized by combining various display forms as described in the above-described embodiment and modification.

In the above-described embodiment and modification, the start code and / or the length code are changed in the X direction of the memories 51 and 52, and a fixed specified value is used in the Y direction. Of course, it is also possible to change the start code and / or the length code in the Y direction in the same manner as in the case of. In this case, it becomes possible to perform vertical movement display and wipe display on the display screen of the LED module 10. Further, if the start code and / or the length code are changed alternately in the X direction and the Y direction, it is possible to substantially realize the movement display and the wipe display in the diagonal direction.

1 ... Display device, 10 ... LED module, 11 ... LED, 12 ... Connector, 13 ... Display screen, 30 ... CPU board, 31 ... CPU, 32 ... Memory, 33 ... Driver, 50 ... Controller board, 51, 52 ... Memory , 53 ... FPGA, 70 ... connector board, A1-A5 ... display area, B1-B5 ... memory area, DP1-DP3 ... start code, DS1-DS3 ... length code, S ... image signal

Claims (7)

A display device that displays an image in each display area of a display unit having a plurality of display areas.
A recording unit in which an image for each display area is recorded, and a recording unit.
A control unit that specifies a display portion of each image recorded in the recording unit based on head information and length information, and displays the specified display portion in each display area, and is the head information or the length. The control unit whose information can be changed and
Display device, including. In the display unit, the display area formed by dividing the display screen into a plurality of parts is arranged.
The control unit connects the specified display portions in a predetermined order and displays them on the display screen.
The display device according to claim 1. The display device according to claim 1 or 2, wherein the control unit moves and displays an image in a vertical direction or a horizontal direction in a corresponding display area of the display unit by changing the head information. The display device according to claim 1 or 2, wherein the control unit displays an image as a moving image in a corresponding display area of the display unit by changing the head information. Any one of claims 1 to 4, wherein the control unit changes the width of the corresponding display area of the display unit and changes the image to be displayed in the display area by changing the length information. The display device described in. The recording unit has a pair of recording areas.
While the control unit specifies and displays the display portion of each image recorded in one of the recording areas by changing the head information or the length information, the other is displayed in each display area. A new image for each display area is recorded with respect to the recording area of the above, and each image to be displayed is updated by switching a pair of the recording areas after the recording of the new image is completed.
The display device according to any one of claims 1 to 5. The display according to any one of claims 1 to 6, wherein the start information is a start code indicating the beginning of the display portion, and the length information is a length code indicating the total length of the display portion. apparatus.