JP7495646B2 - Photonics-electronics hybrid computer - Google Patents

Description

The present invention relates to an optoelectronic hybrid computer, and more particularly to an optoelectronic hybrid computer having a computing platform that combines optical pulses and electrical pulses.

Chips for digital signal processing contain electronic circuits with a large number of logic gates densely integrated. Traditionally, these electronic circuits have been realized with complementary metal-oxide semiconductor (CMOS) transistors. As CMOS transistors have become smaller, more densely integrated electronic circuits have been realized, and clock speeds have been increased, leading to continuous improvements in signal processing functions and performance. However, current CMOS transistors have been miniaturized to dimensions of a few nanometers, and further miniaturization is difficult due to various technical challenges and high costs.

To address this issue, alternative computing architectures, such as neuromorphic and quantum computing schemes, have been gaining attention. While these paradigm shifts have been successful in providing solutions to certain computational problems, there is also a demand to improve the performance of traditional von Neumann computing architectures.

Patent Publication No. 6701443

To meet such demands, the object of the present invention is to provide an optoelectronic hybrid computer equipped with a computing platform capable of high-speed operation by combining optical pulses and electrical pulses.

In order to achieve this object, one embodiment of an optoelectronic integrated computer of the present invention is characterized in that it comprises a recognition circuit which recognizes an execution instruction including an operator and an operand output from a controller, the recognition circuit including a serial-parallel converter which outputs an optical pulse which controls a corresponding decision stage for each bit of the execution instruction, and a decision circuit which selects the output of the decision stage by the optical pulse and outputs a control signal from an output port which uniquely corresponds to the execution instruction, and a memory which outputs a calculation result which has been pre-stored in response to the control signal.

FIG. 1 is a diagram showing signal processing in an ultra-high speed pattern recognition circuit according to an embodiment of the present invention; FIG. 2 is a diagram showing the configuration of an ultra-high speed pattern recognition circuit capable of processing 4-bit words according to this embodiment; FIG. 3 is a diagram illustrating how an input word represented by 4 bits is mapped to an output represented by a decimal number; FIG. 4 is a diagram showing a processing sequence in the ultra-high speed pattern recognition circuit according to the present embodiment. FIG. 5A is a diagram showing an example of an optical/electrical hybrid circuit used as a decision unit of the ultra-high speed pattern recognition circuit according to this embodiment; FIG. 5B is a diagram showing another example of an optical/electrical hybrid circuit used as a decision unit of the ultra-high speed pattern recognition circuit according to the present embodiment; FIG. 6A is a diagram showing an optical/electrical hybrid logic circuit of a determination unit according to the present embodiment; FIG. 6B is a truth table showing the relationship between the input and output of the optical/electrical hybrid logic circuit; FIG. 7 is a diagram for explaining the principle of a computing platform according to an embodiment of the present invention; FIG. 8 is a diagram showing the configuration of a computing platform according to the present embodiment. FIG. 9 is a diagram showing a schematic configuration of an optical memory of a computing platform according to the present embodiment. FIG. 10 is a diagram showing another example of the configuration of the optical memory of this embodiment.

The following describes in detail the embodiments of the present invention with reference to the drawings. Optical pulses can be generated with low jitter and can propagate long distances with low loss and low dispersion. In addition, the timing of the optical pulses can be precisely controlled by adjusting the length of the optical waveguide through which the optical pulses propagate. For example, a 20 μm optical fiber produces a delay of about 0.1 ps. Due to these characteristics, optical logic gates are suitable for high-speed digital signal processing, but unlike logic gates made of CMOS transistors, it is difficult to integrate optical logic gates on a large scale. Therefore, we will build a photonics-electronics integrated computing platform that combines optical pulses and electrical pulses.

[Ultra-high-speed pattern recognition circuit]
1 shows signal processing in an ultra-high speed pattern recognition circuit according to one embodiment of the present invention. The recognition circuit 100 has one serial port to which a high-speed bit signal is input, and 2 ^N output ports that recognize an N-bit input word and uniquely correspond to 2 ^N bit combinations. The output ports of the recognition circuit 100 are connected to 2 ^N input ports of an electric circuit 130 (see, for example, Patent Document 1).

When no signal is input to the serial port, all outputs are always at a low level. When a bit signal constituting a word is input to the serial port of the recognition circuit 100, only one output port corresponding to the bit combination of the word becomes a high level. The recognition circuit 100 operates in real time, and as soon as an N-bit word is input, the corresponding output port becomes a high level and remains at a high level for a duration sufficient to connect the output to a low-speed electrical circuit.

The recognition circuit 100 generates an output signal at a spatially separated output port corresponding to the bit combination based on the bit combination of the input word. The duration of the signal output from this output port corresponds to the duration of one word (T _word ), i.e., the duration of all bit signals, so that it is long enough to match the speed of a low-speed electric circuit. In this case, the output port to which the generated signal is output contains the collective information of all bit signals, i.e., the information of the bit combination, so that it is possible to consume less clock cycles than in the past and simplify the processing in the electric circuit.

When a number of consecutive N-bit words are input at an arbitrary time interval ( _Tnext ) as M words requiring logical operations, each word is output at a time interval ( _Tnext ) to a spatially different output port according to the bit combination. Consider a case where a logic circuit capable of processing these M consecutive low-speed signals performs the operation. The outputs corresponding to each of the M words are input consecutively to the electric circuit 130. The first input becomes the first processing result, while the next input is processed using the result of the previous input, and is updated until all operations are completed. This establishes a word-by-word processing method that can reduce the processing time of ultra-high-speed bits with a low-speed electric circuit.

Figure 2 shows the configuration of an ultra-high speed pattern recognition circuit capable of processing 4-bit words according to this embodiment. The recognition circuit 100 is composed of two main functional blocks: a serial-to-parallel converter 110 and a decision circuit 120. The output of each conversion channel of the serial-to-parallel converter 110 controls a given decision stage S of the decision circuit 120.

The most significant bit determines whether the final output is less than 8 or greater than 8, depending on whether its state is high or low. Therefore, if the value of the most significant bit is known, the number of possible values for the final output can be halved. The remaining possible values can also be halved if the state of the next most significant bit is known, meaning that the number of possible values for the final output can be narrowed down to 1/4. By repeating this procedure up to the least significant bit, it is possible to continuously eliminate the possibility of an inappropriate output and convert the word into a correct output, i.e., it is possible to make only the output from the output port corresponding to the bit combination of the word a high level state. For this reason, the decision circuit 120 is configured as follows.

The decision stage S1 corresponding to the most significant bit includes one decision unit _U1,1 , the decision stage S2 corresponding to the bit one bit lower than the most significant bit includes two decision units _U2,1 and _U2,2 , the decision stage S3 corresponding to the bit one bit lower includes four decision units _U3,1 to _U3,4 , and the decision stage S4 corresponding to the least significant bit includes eight decision units _U4,1 to _U4,8 .

The two output ports of the decision unit _U1,1 in the decision stage S1 corresponding to the most significant bit are connected to the decision unit _U2,1 of the decision stage S2 corresponding to the second most significant bit, and the other is connected to the decision unit _U2,2 . Similarly, the four output ports of the decision units _U2,1 , _U2,2 of the decision stage S2 are connected to the four decision units _U3,1 to _U3,4 of the decision stage S3 corresponding to the third most significant bit, and the eight output ports of the four decision units _U3,1 to _U3,4 of the decision stage S3 are connected to the eight decision units _U4,1 to _U4,8 of the decision stage S4 corresponding to the least significant bit.

The decision unit U _1,1 in the first decision stage S1 sets one of the two output ports to a high level based on a control signal C1 generated in a conversion channel that converts the most significant bit signal of the serial-parallel converter 110. When one of the outputs of the decision unit U _1,1 is set to a high level, only one of the two decision units U _2,1 and U _2,2 in the second decision stage S2 is activated. The activated decision unit U _2,1 or U _2,2 sets one of the two output ports to a high level based on a control signal C2 generated in a conversion channel that converts the second most significant bit signal of the serial-parallel converter 110. Through these processes, only one of the four output ports that can be selected by the second decision stage S2 becomes a high level, and signals are generated in spatially separated output ports, narrowing down the possibilities that the final output can take to 1/4. Similarly, one of the four decision units U _3,1 to U _{3,4 in the third decision stage S3 is activated by the High-level signal from the second decision stage S2. Then, one of the activated decision units U 3,1 to U 3,4 sets one} of the two output ports to High level based on the control signal C3 generated in the conversion channel that converts the third most significant bit signal of the serial-parallel converter 110. One of the eight decision units U _4,1 to U _4,8 in the fourth decision stage S4 is also activated by the High-level signal from the third decision stage S3, and sets one of the two output ports to High level based on the control signal C4 generated in the conversion channel that converts the least significant bit signal of the serial-parallel converter 110.

As shown in Figure 3, a 4-bit input word can be mapped to a decimal output, and one of the 16 output ports can be set to a high level. For example, if the 4-bit word "1101" is input to the recognition circuit 100, different binary combinations can be mapped to "11", which is one of the integers from 0 to 15 in the decimal system.

The recognition circuit 100 is not limited to processing the above 4-bit words, but can also process N-bit words having any bit combination by repeating the above procedure in the same manner to set only the output of the output port corresponding to the bit combination for each word to a High level. In this case, the serial-parallel converter 110 has N conversion channels corresponding to each bit constituting the word, and the decision circuit 120 has N decision stages S ₁ to S _N corresponding to the N conversion channels of the serial-parallel converter 110.

Of the N decision stages S ₁ to S _N , if decision stage S ₁ corresponding to the most significant bit is the first stage, then the (N-i)th decision stage S _(Ns) corresponding to the 2 ^s (s = 0, 1, 2, ..., N-1) bit contains 2 ^N-1-s decision units U, and the Nth decision stage S _N is composed of 2 ^N-1 decision units U _Ns,1 to U _Ns,t (t = 2 ^N-1 ).

Each decision unit U has two output ports, each connected one-to-one to a different decision unit U in the next lower decision stage S, and activating only one of the decision units U. In each decision stage S, only one decision unit U is activated at a time by a high-level output from the next higher decision stage S.

Decision units U belonging to the same decision stage S are connected in parallel to the same conversion channel of the serial-parallel converter 110, and the output of an activated decision unit U is controlled by a control signal C generated in the conversion channel of the serial-parallel converter corresponding to the decision stage S to which the decision unit U belongs. When the state of the control signal C is at high level, only one port of the activated decision unit U becomes high level, and when the converted bit signal is at low level, only the other port becomes high level.

In this way, only one output of one of the decision units U belonging to each decision stage S becomes a high level, and as the final output of the recognition circuit 100, one of the 2 ^N output ports of the decision units U _Ns,1 to U _Ns,t (t = 2 ^N-1 ) of the Nth decision stage S _N corresponding to the bit combination of the N-bit word can be made to be a high level.

4 shows the processing sequence in the ultra-high speed pattern recognition circuit according to this embodiment. The control signal C1 determines only the output of the unit _U1,1 , and in this example, since the most significant bit is at a high level, the signal _L1,1 is converted to a high level. Meanwhile, the signal _L1,2 remains at a steady state low level. In consideration of repeated operation, this circuit sets the duration of the signal _L1,1 to 4T (T: clock cycle time), and when a new word arrives after time 4T, the output of the unit _U1,1 can be freely determined again. The important feature for the output of each unit is a sufficiently fast rise time, which is essential for the operation of the entire circuit.

When signal _L1,1 goes high, signal _L2,2 also goes high accordingly. However, when control signal C2 is generated at high, signal _L2,2 is reset and signal _L2,1 goes high instead. Here, if the third most significant bit is low, control signal C3 goes low and signal _L3,2 remains high after being initialized by signal _L2,1 . Signal _L4,3 goes high after control signal C4 is generated, generating the final output of the circuit.

In a given stage Sn, the output start time of this stage varies with respect to the time of the clock pulse Kn. In the example, the signal _L3,2 starts before the control signal C3 occurs, but when the third most significant bit signal goes high (in this example the converted bit signal is low), the control signal _L3,1 goes high and starts a little after the start of the signal C3. Thus, the variation in the output start at each stage affects the duration of the signal at the final output of the circuit.

The signal generated at each decision stage S is used to control only one of the decision units U in the next decision stage. That is, the signal needs to operate a very small number of transistors without generating electrical loads that would impede fast operation. Also, to enable processing of high-speed electrical signals in such a configuration, the integrated circuit must be designed with dimensions that can accommodate the speed of the signals being processed.

On the other hand, each control signal C _n issued by the serial-parallel converter 110 to a particular decision stage S _n must control all decision units belonging to that decision stage. In conventional electronic circuits, the control signal must be connected to a large number of transistors with large capacitive loads, which hinders fast operation. In addition, a large capacitive load leads to a longer rise time than necessary, which extends the duration of the signal. Therefore, an optical-electrical hybrid circuit that combines optical and electrical pulses is applied, as described below.

5A shows an optical/electrical hybrid circuit used as a decision unit of the ultra-high-speed pattern recognition circuit according to this embodiment. The output of each conversion channel 111 of the serial-parallel converter 110 is connected to an optical waveguide 121 arranged adjacent to the row of decision units included in the decision stage S. The decision unit U is composed of an optical splitter 122 for drawing an optical pulse from the optical waveguide 121 to the decision unit U according to a signal L _n-1,j for activating the decision unit U from the previous decision stage S, and an optical/electrical hybrid logic circuit 123 for determining whether to output an electrical pulse from one of two output ports according to two input signals of an electrical pulse and an optical pulse.

If the converted bit signal is high, a control signal C _n , which is an optical pulse, is generated from the conversion channel 111 of the serial-to-parallel converter 110 to the decision unit U of the decision stage S, whereas if the converted bit signal is low, no optical pulse is generated.

The signal L _n-1,j is used to activate the decision unit U _n,i . Here, instead of outputting the corresponding control signal C _n individually for all decision units U _n of the decision stage S _n including the decision unit U n _,i , the signal L _{n-1,i is} used to direct the control signal C _n , which is an optical pulse, to the activated decision unit U n _,i . The signal L _n-1,i is split and the signal L _n-1,i controls the optical splitter 122 of the decision unit U _n,i to direct the control signal C _n, which is an optical pulse, to the decision unit U _n,i .

Figure 5B shows another example of an optical-electrical hybrid circuit used as a decision unit of the ultra-high-speed pattern recognition circuit of this embodiment. In order to draw the optical pulse from the optical waveguide 121 to the decision unit U, an optical resonator circuit 124 is provided instead of the optical splitter 122. As the optical resonator circuit 124, for example, an optical disk resonator, an optical ring resonator, or other high-speed modulated optical resonator having a small element size and capable of operating with low energy can be applied.

6A shows the optical-electrical hybrid logic circuit of the decision unit according to this embodiment. In the optical-electrical hybrid logic circuit 123, an electrical signal with controlled persistence is generated from the optical pulse deflected to the decision unit U _n,i . An inverting amplifier A1 and a non-inverting amplifier A2 are connected to the output of a photodiode PD, which is a light receiving element to which a control signal C _n , which is an optical pulse, is input. The output of a transistor Tr1 driven by a signal L _n-1,j from the previous decision stage S is connected to transistors Tr2 and Tr3 via buffers A3 and A4, respectively. When an optical pulse is input to the photodiode PD as the control signal C _n , the non-inverting amplifier A2 drives the transistor Tr3 to output a signal L _n,2i-1 to one of the two output ports of the decision unit U. When an optical pulse is not input to the photodiode PD, the inverting amplifier A1 drives the transistor Tr2 to output a signal L _n,2i to the other output port of the decision unit U.

Figure 6B shows a truth table that represents the input/output relationship of the optical/electrical hybrid logic circuit. The optical/electrical hybrid logic circuit 123 includes a decision circuit configured with a light receiving element and an electronic circuit. The decision circuit outputs a signal according to the truth table to one of two output ports, depending on the output of the light receiving element, based on the signal output from the previous decision stage.

[Computing Platform]
An ultra-high speed pattern recognition circuit generates a spatially differentiated output signal in response to a combination of N input bits. Ultra-high speed bit recognition with very low latency is the basis for implementing a newly proposed processor, which uses the ultra-high speed pattern recognition circuit to identify the operator and the contents of its operands that generate a particular output signal. A computational result corresponding to the combination of the operator and the operand can be obtained without performing any computational processing.

The principle of a computing platform according to one embodiment of the present invention will be described with reference to FIG. 7. The processor 200 in the computing platform of this embodiment includes a recognition circuit 202 that recognizes an execution command including an operator and an operand output from the controller 201. As described above, the recognition circuit 202 includes a serial-parallel converter that outputs an optical pulse that controls a corresponding decision stage for each bit of the execution command, and a decision circuit in which the output of the decision stage is selected by the optical pulse and a control signal is output from an output port uniquely corresponding to the execution command. The recognition circuit 202 outputs a control signal uniquely corresponding to the operator and the operand to the memory 203 as a recognition result. The memory 203 stores in advance the calculation result corresponding to the control signal. The search result corresponding to the control signal is returned to the controller 201 via the selection circuit 204.

When the processor 200 recognizes an execution command (operator + operand) during calculation processing by the recognition circuit 202, it searches the memory 203 and obtains the calculation result that has already been stored without performing the actual calculation. The above-mentioned ultra-high-speed pattern recognition circuit is applied to recognize the execution command, and by combining it with the high-speed optical memory described below, a computing platform capable of high-speed operation can be configured. Furthermore, with this configuration, the complexity of the execution command does not affect the speed at which the final calculation result is received, making it easier to speed up calculation processing.

[Photonics-electronics hybrid computer]
8 shows the configuration of the computing platform of this embodiment. A set of N parallel signals (N bits) representing an execution instruction (operator + operand) is output from the controller 201. The execution instruction is fetched from a cache memory inside the controller 201, similar to a central processing unit (CPU) of a conventional von Neumann type computing architecture. The execution instruction is converted into a serial signal by a parallel-serial conversion circuit (P/S) 251 and input to the recognition circuit 202.

The recognition circuit 202 is the ultra-high speed pattern recognition circuit described above, and an execution command is input to the serial-parallel converter 110, and N optical pulses are generated corresponding to the input N-bit input word. The optical pulses generated in each conversion channel 111 are input to the decision circuit 120 for each decision step S via the optical waveguide 121.

The duration of the electrical signal generated by the controller 201 is approximately N times the duration of the optical pulse, as described above. For example, if each optical pulse represents 10 bits with a duration of 40 ps, the controller 201 can operate at a clock of 2.5 Gb/s and operate at the speed of a typical electronic circuit. If the number of bits that the optical pulse corresponds to is increased, the clock speed of the controller 201 can be further relaxed, and if the clock speed is the same, a higher computing capacity can be obtained.

The output of the recognition circuit 202 is an electrical signal output as a control signal from one of 2 ^N output ports uniquely corresponding to a combination of N bits as a recognition result of an execution command output from the controller 201. That is, in the ultra-high speed pattern recognition circuit, an electrical signal is output from one of 2 ^N-1 decision units U _N-s,t (t=2 ^N-1 ) in the lowest N-th decision stage _S N, and is output as a final result from one of two output ports. The electrical signal output from the recognition circuit 202 drives the optical resonator 232 of the memory 203, and searches for the calculation results stored in advance in the memory 203. The memory 203 will be described in detail later. Although a high-speed optical memory will be described as an example of the memory 203, a memory made of a normal electronic circuit can also be used in the computing platform of this embodiment.

The search results from memory 203 are output as a series of serial optical pulses representing the calculation result. The serial optical pulses are sent back to controller 201 by optical switch 241 in selection circuit 204, or are routed to recognition circuit 202 to be used as new operands for the next calculation step. The optical pulses sent back to controller 201 are converted to electrical signals and output via serial-to-parallel converter (S/P) 242.

FIG. 9 shows a schematic configuration of the optical memory of the computing platform of this embodiment. The memory 203 is an all-optical memory that processes everything from input to output with optical signals. The memory 203 includes 2 ^N optical resonators 232 corresponding to the 2 ^N output ports of the recognition circuit 202 (for convenience of explanation, the case of four output ports is shown). The optical resonators 232a-d are optically coupled to an optical waveguide 237 connected to the optical pulse light source 231. When an electrical signal is output from any one of the output ports of the recognition circuit 202 and one of the corresponding optical resonators is driven, the driven optical resonator outputs the optical pulse from the optical pulse light source 231 to the division circuits 233a-d. The division circuit 233 has an optical path that divides the optical pulse into a number of optical pulses, and a delay circuit 236 set to a predetermined delay time is set in each optical path. The divided optical pulses are reflected or absorbed by the LCOS (liquid crystal on silicon) 234, which is a spatial optical phase modulator. The reflected optical pulses propagate along the original optical path and are output via circulator 235 as a series of serial optical pulses.

By setting the delay time of the delay circuit 236 of the division circuit 233 and the reflection control of the LCOS 234 in advance, a series of serial optical pulses (optical pulses representing the calculation result "10110101" in FIG. 9) that represent the desired calculation result can be derived from one input optical pulse. The execution command recognized by the recognition circuit 202 is optically processed in the memory 203, so that the response time can be shortened and power consumption can be reduced compared to memories made of conventional electronic circuits.

Fig. 10 shows another example of the configuration of the optical memory of this embodiment. This shows an example of increasing the number of processing bits of the processor in order to obtain higher computational processing power. As the number of bits increases, the output ports of the recognition circuit increase exponentially, so the configuration of the division circuit and LCOS in the optical memory also increases dramatically. Therefore, the memory 303 processes by wavelength division multiplexing using optical pulses of multiple wavelengths.

The optical pulse light source 331 is a multi-wavelength light source that transmits optical pulses of multiple wavelengths. For example, an input word is provided with an additional bit for wavelength selection in addition to an execution command. The recognition circuit 202 outputs an electrical signal OUT, which is the final result, and an additional bit WSEL for wavelength selection from one of the 2 ^N output ports as a recognition result of the execution command. The optical pulse light source 331 transmits an optical pulse by selecting one wavelength according to the additional bit WSEL, and the optical resonator 332 to which the electrical signal OUT is input outputs an optical pulse of the selected wavelength to the division circuit.

An arrayed waveguide grating (AWG) 337 is inserted as a branching circuit in front of the splitter circuit, and the optical pulse output from the optical resonator 332 is branched to splitters 333a-d according to the wavelength. In the splitter circuit, the reflection of the split optical pulse is controlled by LCOS 334, and the split optical pulse is output as a series of serial optical pulses via circulator 335.

According to this embodiment, it is possible to provide a computing platform capable of high-speed operation without relying on the high integration of conventional electronic circuits.

Claims (6)

a recognition circuit for recognizing an execution command including an operator and an operand output from a controller, the recognition circuit including a serial-parallel converter for outputting an optical pulse for controlling a corresponding decision stage for each bit of the execution command, and a decision circuit for selecting an output of the decision stage by the optical pulse and outputting a control signal from an output port uniquely corresponding to the execution command among a plurality of output ports ;
a memory that outputs a calculation result stored in advance in response to the control signal ;
The memory is an optical memory that includes a plurality of optical paths in which optical propagation delays and reflections are preset corresponding to the calculation results for each output port of the recognition circuit, and outputs, in a time series as the calculation results, optical pulses from a light source that are reflected after undergoing the propagation delay in the optical paths to which the optical pulses from the light source are introduced in response to the control signal . a recognition circuit for recognizing an execution command including an operator and an operand output from a controller, the recognition circuit including a serial-parallel converter for outputting an optical pulse for controlling a corresponding decision stage for each bit of the execution command, and a decision circuit for selecting an output of the decision stage by the optical pulse and outputting a control signal from an output port uniquely corresponding to the execution command among a plurality of output ports;
a memory that outputs a calculation result that has been stored in advance in response to the control signal;
Equipped with
The memory includes:
an optical resonator corresponding to each of the output ports of the recognition circuit, the optical resonator branching an optical pulse from a light source in response to the control signal;
a division circuit for dividing an optical pulse branched from the optical resonator, the division circuit including a delay circuit preset in the divided optical path;
a spatial light phase modulator that controls reflection of an optical pulse output from an optical path of the splitting circuit;
The calculation result is an optical pulse reflected by the spatial light phase modulator and output from the division circuit as a series of serial optical pulses. 3. The optoelectronic hybrid computer according to claim 1, further comprising a selection circuit that transmits the calculation result output from the memory to the controller or to the recognition circuit as an operand of the next execution command. The memory includes:
an optical resonator corresponding to each of the output ports of the recognition circuit, the optical resonator branching an optical pulse from the light source in response to the control signal;
a division circuit that divides an optical pulse branched from the optical resonator, the division circuit including a delay circuit in which the propagation delay is preset in the divided optical path;
a spatial light phase modulator for controlling the reflection of the optical pulse output from the optical path of the splitting circuit;
2. The optoelectronic hybrid computer according to claim 1, wherein the optical pulses output in a time series manner as the calculation result are a series of serial optical pulses output from the division circuit after the optical pulses are reflected by the spatial light phase modulator. The decision circuit of the recognition circuit comprises:
a light receiving element to which the optical pulse for controlling the decision step is input;
5. The optoelectronic hybrid computer according to claim 1, further comprising a determination circuit for outputting a signal output from a previous decision stage to one of two output ports depending on the output of the light receiving element. the light source is a multi-wavelength light source;
5. The optoelectronic hybrid computer according to claim 4 , wherein the memory further includes a branching circuit that branches the optical pulse branched from the optical resonator according to wavelength and outputs the branched optical pulse to the division circuit.

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