JP7492603B2 - A circuit for converting signals between digital and analog - Google Patents

Description

The present invention relates to a circuit for converting signals between digital and analog, a test apparatus for testing a device under test, and a method for converting signals between digital and analog.

As utilization rates of cutting-edge devices increase, the challenge of evaluating the performance of such devices in production-scale volumes becomes increasingly difficult. One of the difficulties can be attributed to traditional high-speed device test modes, which at higher frequencies tend to reflect the combined performance of the device under test (DUT) and test hardware, rather than the performance of the DUT alone.

When testing high-speed, high-performance devices in the GHz (gigahertz) frequency range, the limiting factor for performance in conventional automatic test equipment (ATE) is increasingly determined by jitter in the stimulus and conversion (sampling) clock signals of the analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) that are part of the test hardware. Jitter is the time variation of a periodic signal that is often associated with a reference clock source. Jitter can be observed in properties such as the frequency of successive pulses or the phase of a periodic signal. However, in the context of ATE performance, it is generally assumed that the limiting effect is caused by the jitter of the conversion clock alone. Therefore, high costs and advanced development efforts are generally spent on providing ultra-low jitter clocks (e.g., by developing low-jitter clock generators incorporating advanced phase-locked loop (PLL) architectures).

Nowadays, ADCs and DACs are manufactured for continuous operation at a fixed sample rate. That is, when ADCs and DACs are used in continuous mode, the converter sampling rate is locked to the data rate by a PLL. All frequencies for converting the signals are usually known, and therefore it is possible to use a digital signal processor (DSP) to convert from any user data rate to the converter rate. The same can be done in burst mode, for example as shown in Figure 8. However, it is necessary to set up the PLL before each measurement to align the clock timing as shown in Figure 9. That is, it is required to achieve accurate timing of the bursts with sub-converter rate resolution.

Conventional circuits for converting signals (such as the circuit shown in FIG. 7 as a schematic diagram) require one PLL for each channel. The simplest configuration of a PLL includes a phase comparator, a loop filter, and a voltage-controlled oscillator, but PLLs generally require specialized and expensive external components. In addition, low-jitter PLLs cannot be integrated into CMOS processes, and therefore PLLs consume a lot of board space. The time required for the PLL to stabilize before each burst is also a challenge for ATE, as tests often include many relatively short bursts.

The object of the present invention is therefore to provide an improved circuit concept for converting signals in burst mode.

The above object is achieved by a circuit for converting signals between digital and analog as set forth in claim 1, a test apparatus for testing a device under test as set forth in claim 15, and a method for converting signals between digital and analog as set forth in claim 18.

Some embodiments of the present invention also provide a computer program for performing the steps of the methods of the present invention.

A circuit according to a first aspect of the present application is a circuit for converting a signal between digital and analog (e.g., between a digital representation and an analog representation, i.e., from a digital representation to an analog representation or from an analog representation to a digital representation), in which a predetermined frequency relationship (e.g., a predetermined frequency relationship locked at a predetermined value) exists between a synchronous clock signal and a converter clock signal, and the circuit includes a processor configured to provide or use a synchronous clock signal (e.g., a synchronous clock signal that is a clock signal that indicates timing for outputting data based on input data values associated with sample times (e.g., equally spaced in time) on a time grid or time axis), and a converter clock signal (e.g., a converter clock signal that indicates timing for receiving data provided from the processor and/or that defines the time at which conversion between digital and analog is performed) configured to convert data between digital and analog. a converter coupled to the processor for receiving the synchronous clock signal; a phase comparator (e.g., coupled to the processor for receiving the synchronous clock signal and coupled to the converter for receiving the converter clock signal) configured to determine a phase relationship between the synchronous clock signal and the converter clock signal (i.e., the phase comparator is configured to perform a comparison of the timing of rising or falling edges between the synchronous clock signal and the converter clock signal, thereby performing a phase comparison between the signals); and a digital signal processor coupled to the phase comparator for receiving information regarding the phase relationship (e.g., a phase difference between the synchronous clock signal and the comparator clock signal) and configured to apply a delay to signal data (e.g., time-discrete output values associated with different sample times (e.g., not on the original time grid or time axis)) exchanged between the processor and the converter (e.g., to at least partially compensate for the phase difference between the synchronous clock signal and the converter clock signal according to the phase relationship).

In an embodiment, the circuit is configured to determine, based on information about a phase relationship between the synchronous clock signal and the converter clock signal, whether an enable signal that is time-synchronous with the synchronous clock signal and triggers conversion of data between digital and analog is sampled on a rising edge or a falling edge of the converter clock signal to obtain an enable signal that is time-synchronous with the converter clock signal.

In an embodiment, the circuit is configured to select, in response to information about the phase relationship between the synchronous clock signal and the converter clock signal, between a first mode in which an enable signal that is time-synchronous with the synchronous clock signal and triggers the conversion of data between digital and analog is sampled at an edge of a first edge type (e.g., a falling edge) of the converter clock signal to obtain an intermediate signal, and the intermediate signal is sampled at an edge of a second edge type (e.g., a rising edge) of the converter clock signal to obtain an enable signal that is time-synchronous with the converter clock signal, and a second mode in which an enable signal that is time-synchronous with the synchronous clock signal and triggers the conversion of data between digital and analog is sampled at an edge of a second edge type of the converter clock signal to obtain an enable signal that is time-synchronous with the converter clock.

In an embodiment, the circuit includes a first flip-flop circuit coupled to the processor to receive an enable signal (e.g., an enable signal that is a test signal on a different clock domain than the converter clock signal and is provided by the processor to align output timing of signal data), the first flip-flop circuit being configured to sample the enable signal at a first sampling phase to obtain a sampled signal if the phase relationship indicates that the value of the phase difference between the synchronized clock signal and the converter clock signal is within a first predetermined range (e.g., if the phase difference is less than a predetermined value that may have a risk of leading to metastability, the phase for sampling the enable signal is inverted to move the sampling time instance away from the clock edge of the synchronized clock signal), a signal selector coupled to the processor to receive the enable signal and coupled to the first flip-flop circuit to receive the sampled signal, the signal selector being configured to select one of the received signals (e.g., depending on the phase relationship) to obtain a selected signal, and a signal selector to receive the selected signal. a second flip-flop circuit coupled to the digital signal processor, the second flip-flop circuit configured to sample the enable signal at the second sampling phase when the phase relationship is within a second predetermined range (e.g., different from the first predetermined range and typically not overlapping with the first predetermined range) (which may indicate, for example, that the value of the phase difference between the synchronous clock signal and the converter clock signal is greater than a predetermined value) (in which case the edges of the sampled signal are synchronized with the converter clock signal, i.e., the output timings of the signals are aligned, and therefore it is not necessary to align the rising timings of the clock signals); and a first-in-first-out circuit coupled to the digital signal processor to receive signal data and coupled to the second flip-flop circuit via a delay circuit (e.g., calculating a delay time based on the phase difference between the enable signal and the converter clock signal) to receive a delayed version of the output signal of the second flip-flop circuit (e.g., indicative of the signal data output timing of the converter), the first-in-first-out circuit providing the converter with signal data associated with the sampled enable signal.

In an embodiment, the selector comprises a multiplexer that selects one of the input signals based on information about the phase relationship. In addition, the phase comparator comprises a phase-to-digital converter configured to measure a phase difference between the synchronized clock signal and the converter clock signal to determine the phase relationship. Furthermore, a digital signal processor (e.g., a fractional delay filter) is configured to cancel and/or at least partially compensate for the phase difference between the synchronized clock signal and the converter clock signal.

In an embodiment, the digital signal processor (e.g., a fractional delay filter) is configured to provide filtered data values associated with a conversion time in a time grid determined by the converter clock signal (e.g., a signal sample actually digital-to-analog converted by the converter at a time determined by the converter clock signal) based on one or more input data values provided synchronously with the synchronous clock signal (e.g., one or more signal samples provided by the processor that should have been digital-to-analog converted at a time determined by the synchronous clock signal, but that was not possible due to a time shift/phase shift between the synchronous clock signal and the converter clock signal), and/or the digital signal processor (e.g., a fractional delay filter) is configured to provide filtered data values aligned to a time axis determined by the synchronous clock signal based on one or more data values defined in a time grid determined by the converter clock signal (e.g., one or more signal samples actually analog-to-digital converted by the converter at a time determined by the converter clock signal, but that was not possible due to a time shift/phase shift between the synchronous clock signal and the converter clock signal).

In an embodiment, the digital signal processor or fractional delay filter uses a Farrow structure. However, any other suitable means for implementing the delay is acceptable. The circuit comprises an oscillator, where an output signal of the oscillator is used as the converter clock signal or the circuit is configured to derive the converter clock signal from an output signal of the oscillator. The circuit is configured to derive the synchronous clock signal and the converter clock signal from a common reference signal such that the frequency of the synchronous clock signal and the frequency of the converter clock signal are in a predetermined relationship. The converter is a digital-to-analog converter or an analog-to-digital converter.

A second aspect of the present application relates to a test apparatus for testing a device under test comprising a circuit according to the present application. The test apparatus is configured to execute (e.g., start) a test flow (e.g., a test flow using a multiple channel module that provides signals to the device under test and evaluates signals received from the device under test) in synchronization with a synchronous clock signal. The test apparatus is configured to provide (e.g., stimulate) the device under test with an analog signal obtained using a converter based on an input signal value (e.g., provided by a processor) and/or the apparatus is configured to obtain digital data provided by a digital signal processor based on a digitized device under test signal obtained from the converter using a delay and evaluate the digital data (e.g., to characterize the device under test).

A third aspect of the present application is a method for converting signals between digital and analog, comprising the steps of receiving a synchronous clock signal provided from or used by a processor and a converter clock signal used by a converter, determining a phase relationship between the synchronous clock signal and the converter clock signal, and applying a delay to signal data exchanged between the processor and the converter based on the phase relationship between the synchronous clock signal and the converter clock signal, wherein a predetermined frequency relationship exists between the synchronous clock signal and the converter clock signal.

The method according to the embodiment includes the steps of selecting, depending on a phase relationship between the synchronous clock signal and the converter clock signal, between a first mode in which an enable signal that is time-synchronous with the synchronous clock and triggers the conversion of data between digital and analog is sampled at an edge of a first edge type of the converter clock to obtain an intermediate signal, and the intermediate signal is sampled at an edge of a second edge type of the converter clock to obtain an enable signal that is time-synchronous with the converter clock, and a second mode in which an enable signal that is time-synchronous with the synchronous clock and triggers the conversion of data between digital and analog is sampled at an edge of a second edge type of the converter clock to obtain an enable signal that is time-synchronous with the converter clock, and providing signal data associated with the sampled enable signal to the converter.

According to a fourth aspect of the present application, there is provided a computer program configured to perform the above-mentioned method when executed on a computer or microcontroller, such that the above-mentioned method is performed by the computer program.

The following describes the embodiments of the present application in more detail with reference to the drawings.

FIG. 1 is a schematic block diagram of a circuit for converting a signal according to a first embodiment of the present invention; 2 is a schematic timing diagram of a phase comparator according to a first embodiment of the present invention; FIG. 3 is a schematic block diagram of a phase comparator according to FIG. 2 in accordance with the inventive concept; FIG. 2 is a schematic diagram illustrating the phase relationship between a synchronization clock and a converter clock according to a first embodiment of the present inventive concept. FIG. 11 is a schematic block diagram showing an example implementation of a circuit according to a second embodiment of the present invention. FIG. 4 is a schematic block diagram of a test apparatus for testing a device under test according to a third embodiment of the present inventive concept. 5 is a flow chart illustrating method steps for converting signals between digital and analog in accordance with a third embodiment of the present inventive concept. FIG. 1 is a schematic block diagram according to the prior art; FIG. 1 is a schematic timing diagram according to the prior art;

The following description sets forth specific details, such as particular embodiments, procedures, techniques, etc., for purposes of explanation and not limitation. Those skilled in the art will appreciate that other embodiments may be employed apart from these specific details. For example, the following description proceeds by using non-limiting example applications, but the techniques may be employed in any type of converter. In some cases, detailed descriptions of well-known methods, interfaces, circuits, and devices are omitted so as not to obscure the description with unnecessary detail.

Equivalent or equivalent elements having equivalent or equivalent functions are indicated in the following description with equivalent or equivalent reference symbols.

Figure 1 shows a schematic block diagram of a circuit for converting a signal according to a first embodiment of the present invention. The circuit 100 comprises a processor 2, a converter 4, a phase comparator (PDC) 6, and a digital signal processor (DSP) 8.

The processor 2 is coupled to the PDC 6 and provides a synchronous clock signal to the PDC 6. In addition, the processor 2 is coupled to the DSP 8 and provides data/signal data to the DSP 8. The processor 2 is configured to provide or use a synchronous clock signal (e.g., a synchronous clock signal that is a clock signal that indicates timing for outputting data based on input data values associated with sample times (e.g., equally spaced in time) on a time grid or time axis). In this embodiment, the synchronous clock signal is shown provided from the processor 2 to the PDC 6. However, the synchronous clock signal may be provided to the processor 2 from another data source. In this case, the processor 2 uses the provided synchronous clock signal.

The converter 4 is coupled to the PDC 6 and provides a converter clock signal to the PDC 6. In addition, the converter 4 is coupled to the DSP 8 and receives signal data provided by the processor 2 via the DSP 8. The converter 4 is configured to convert data between digital and analog using a converter clock signal (e.g., a converter clock signal that indicates the timing for receiving data provided from the processor and/or is a clock signal that defines the time at which conversion between digital and analog is performed). The converter 4 is a digital-to-analog converter or an analog-to-digital converter.

The PDC 6 is coupled to the processor 2 to receive the synchronized clock signal and to the converter 4 to receive the converter clock signal, and is configured to perform a comparison of rising or falling edge timing between the synchronized clock signal and the converter clock signal, thereby performing a phase comparison between the signals. That is, the PDC 6 detects a phase difference between the synchronized clock signal and the converter clock signal. In addition, the PDC 6 includes a phase-to-digital converter configured to measure the phase difference between the synchronized clock signal and the converter clock signal to determine the phase relationship.

The DSP 8 is coupled to the PDC 6 to receive information regarding the phase relationship (e.g., the phase difference between the synchronized clock signal and the converter clock signal), and the DSP 8 is configured to apply delays to signal data (e.g., time-discrete output values associated with different sample times (e.g., not on the original time grid or time axis)) exchanged between the processor and the converter (e.g., to at least partially compensate for the phase difference between the synchronized clock signal and the converter clock signal according to the phase relationship), and a predetermined frequency relationship (e.g., a predetermined frequency relationship locked at a predetermined value) exists between the synchronized clock signal and the converter clock signal. Furthermore, the DSP 8 is configured to cancel and/or at least partially compensate for the phase difference between the synchronized clock signal and the converter clock signal.

In circuit 100, there is a predetermined frequency relationship (e.g., a predetermined frequency relationship locked at a predetermined value) between the synchronous clock signal and the converter clock signal. The predetermined frequency relationship is defined based on a desired result or performance state of the circuit or any other criteria.

As described above, the processor 2 provides signal data to the DSP 8 and provides a synchronized clock signal to the PDC 6. The PDC 6 receives the converter clock signal from the converter 4 and determines the phase relationship between the synchronized clock signal and the converter clock signal. Information about the determined phase relationship is provided from the PDC 6 to the DSP 8. The DSP 8 then applies a delay to the signal data exchanged between the processor 2 and the converter 4 according to the phase relationship. This causes the converter 4 to compensate for the output timing difference caused by the fact that the converter clock signal is phase shifted relative to the synchronized clock signal.

2 shows a schematic timing diagram of the PDC6, and FIG. 3 shows a schematic block diagram of the PDC6. As shown in FIG. 2 and FIG. 3, the reference clock signal REFCLK/REF_CLK and the measurement clock signal MEAS_CLK are provided to the PDC6. The PDC6 then conveys the delay between the rising edge of REF_CLK (i.e., the rising edge of the reference clock signal) and the rising edge of MEAS_CLK (i.e., the rising edge of the measurement clock signal). As mentioned above, the PDC6 determines the phase difference (i.e., the delay of the signals), i.e., the accuracy of the PDC6 directly affects the timing accuracy of the circuit. Thus, the PDC6 is required to be accurate.

Figure 4 shows a schematic diagram illustrating the phase relationship between the sync clock signal and the converter clock signal. The DSP 8, or, as shown in FIG. 4, for example, the non-integer delay filtering included in the DSP 8, is configured to provide filtered data values (signal samples) associated with a conversion time in a time grid determined by the converter clock signal based on one or more input data values provided synchronously with the synchronous clock signal (e.g., one or more signal samples provided by the processor 2 that should have been digital-to-analog converted at a time determined by the synchronous clock signal but were not possible due to a time shift/phase shift between the synchronous clock signal and the converter clock signal) and that are actually digital-to-analog converted by the converter at a time determined by the converter clock signal, and/or the DSP 8 or the non-integer delay filtering is configured to provide filtered data values aligned to a time axis determined by the synchronous clock signal based on one or more data values defined in a time grid determined by the converter clock signal (e.g., one or more signal samples that should have been analog-to-digital converted at a time determined by the synchronous clock signal but were not possible due to a time shift/phase shift between the synchronous clock signal and the converter clock signal and that are actually analog-to-digital converted by the converter at a time determined by the converter clock signal).

In addition, the PDC 6 can be integrated into a standard CMOS process, thus allowing higher density compared to PLL approaches in known technology. Furthermore, one central clock generation for all converter clocks is possible, which also allows higher density. Another advantage is that usable PDC measurements are available in much less time than the typical settling times of low phase noise PLLs.

Figure 5 shows a schematic block diagram illustrating an implementation of a circuit 200 according to a second embodiment of the present invention. As shown in Figure 5, the circuit 200 further comprises a first flip-flop circuit (FF) 10, a signal selector (e.g., multiplexer) 12, a second flip-flop circuit (FF) 14, and an oscillator (VCSO) (Voltage Controlled SAW Oscillator, SAW = Surface Acoustic Wave) 16. In addition, the DSP 8 comprises a fractional delay filter, which can be implemented in a Farrow structure or any other suitable implementation can be used.

The first FF 10 is coupled to the processor 2 to receive an enable signal TEST_EN (e.g., a test signal on a different clock domain than the converter clock signal, an enable signal provided by the processor to align the output timing of the signal data), and the FF 10 is configured to sample the enable signal at a first sampling phase to obtain a sampled signal if the phase relationship indicates that the value of the phase difference between the synchronized clock signal and the converter clock signal is within a first predetermined range (e.g., if the phase difference is less than a predetermined value that may have a risk of leading to metastability, the phase for sampling the enable signal is inverted to move the sampling time instance away from the clock edge of the synchronized clock signal). The predetermined range is determined, for example, based on the required test accuracy.

A signal selector (i.e., multiplexer 12) is coupled to the processor 2 to receive the enable signal TEST_EN and to the first FF 10 to receive the sampled signals, the multiplexer 12 being configured to select one of the received signals, for example depending on the phase relationship, to obtain a selected signal EN_SYNC. The multiplexer 12 selects one of the input signals based on the information about the phase relationship.

The second FF 14 is coupled to the multiplexer 12 to receive the selected signal EN_SYNC, and the second FF 14 is configured to sample the enable signal TEST_EN at the second sampling phase when the phase relationship is within a second predetermined range (e.g., different from and typically not overlapping with the first predetermined range) (which may indicate, for example, that the value of the phase difference between the synchronous clock signal and the converter clock signal is greater than a predetermined value) (in this case, the edges of the sampled signal are synchronized with the converter clock signal, i.e., the output timing of the signals is aligned, and therefore there is no need to align the rising timing of the clock signals).

4 shows the phase difference being determined based on a rising edge, but as described above, the circuit 200 can select a falling edge. That is, the circuit 200 is configured to select between a first mode in which an enable signal that is time-synchronous with the synchronizing clock signal and triggers the conversion of data between digital and analog is sampled at an edge of a first edge type (e.g., a falling edge) of the converter clock signal to obtain an intermediate signal, and the intermediate signal is sampled at an edge of a second edge type (e.g., a rising edge) of the converter clock signal to obtain an enable signal that is time-synchronous with the converter clock signal, and a second mode in which an enable signal that is time-synchronous with the synchronizing clock signal and triggers the conversion of data between digital and analog is sampled at an edge of a second edge type of the converter clock signal to obtain an enable signal that is time-synchronous with the converter clock.

The VCSO 16 is coupled to the converter 4. The output signal of the VCSO 16 is used as the converter clock signal. The circuit 200 is configured to derive the synchronizing clock signal and the converter clock signal from a common reference signal such that the frequency of the synchronizing clock signal and the frequency of the converter clock signal are in a predetermined relationship. In addition, the circuit 200 may be configured to derive the converter clock signal from the output signal of the VCSO 16.

In addition, as shown in FIG. 5, a first-in-first-out circuit FIFO is coupled to the DSP 8 to receive the signal data, and is coupled to a second FF 14 through an additional delay circuit ("Delay N") that is used to delay the output signal of FF 14 by a programmable target number of clock signal cycles. The number of clock cycles is selected so that the FIFO enable signal READ_EN becomes active at exactly the right time when enough data is available in the FIFO and the device under test is supported to receive data via the DAC, and the FIFO provides the signal data associated with the sampled enable signal to the converter 4.

Further, as shown in FIG. 5, the circuit 200 is configured to determine whether the enable signal, which is time-synchronous with the synchronous clock signal and triggers the conversion of data between digital and analog, is sampled on a rising edge or a falling edge of the converter clock signal based on information about the phase relationship between the synchronous clock signal and the converter clock signal to obtain an enable signal that is time-synchronous with the converter clock signal.

Figure 6 shows a schematic block diagram of a test apparatus for testing a device under test according to a third embodiment of the present invention. In Figure 6, the test apparatus comprises a circuit 200 according to the second embodiment, but the test apparatus may also comprise a circuit 100 according to the first embodiment. As shown in Figure 6, the PDC 6 further comprises a processing circuit for providing information about the phase difference to the DSP 8 and the selector 12. A detailed description is omitted to avoid repeating the circuit of the present invention.

As shown in FIG. 6, in the test apparatus, the beginning of the waveform is determined by a signal (TEST_EN) (e.g., initiating a test flow (e.g., a test flow using multiple channel modules that supplies signals to a device under test and evaluates signals received from the device under test)) in synchronization with the synchronous clock signal. Therefore, the timing requirements in the data interface are relatively relaxed.

In addition, the test apparatus (i.e., circuit 200) is configured to provide to the device under test (e.g., to stimulate the device under test) an analog signal obtained using converter 4 based on an input signal value (e.g., provided by processor 2), and/or the apparatus is configured to obtain digital data provided by DSP 8 based on a digitized device under test signal obtained from converter 4 using a delay, and to evaluate the digital data (e.g., to characterize the device under test).

Figure 7 shows a flow chart illustrating steps of a method for converting signals between digital and analog according to a third embodiment of the inventive concept.

First, the synchronous clock signal and the converter clock signal are received (S10). That is, the phase comparator (i.e., for example, PDC 6 shown in FIG. 1 or FIG. 2) receives the synchronous clock signal from the processor (i.e., for example, processor 2 in FIG. 1 or FIG. 2) and the converter clock signal from the converter (i.e., for example, converter 4 in FIG. 1 or FIG. 2). The synchronous clock may be provided by the processor 2 or any other source.

Next, a phase relationship between the synchronous clock signal and the converter clock signal is determined (S12). A delay is then applied to the signal data based on the phase relationship (S14). That is, a delay is applied to the signal data exchanged between the processor and the converter based on the phase relationship between the synchronous clock signal and the converter clock signal determined in step S12. In addition, a predetermined frequency relationship exists between the synchronous clock signal and the converter clock signal.

In addition to the above steps, it is possible to select a sampling edge mode. That is, the method further includes a step of selecting a sampling edge mode (i.e., selecting between a first mode and a second mode depending on the determined phase relationship between the synchronous clock signal and the converter clock signal). In the first mode, the enable signal, which is time-synchronous with the synchronous clock, is sampled at an edge of a first edge type (e.g., a falling edge) of the converter clock signal to obtain an intermediate signal, and the intermediate signal is sampled at an edge of a second edge type (e.g., a rising edge) of the converter clock to obtain an enable signal, which is time-synchronous with the converter clock. In the second mode, the enable signal, which is time-synchronous with the synchronous clock, is sampled at an edge of a second edge type (e.g., a rising edge) to obtain an enable signal, which is time-synchronous with the converter clock. The signal data associated with the sampled enable signal is then provided to a converter (e.g., converter 4 in FIG. 1 or FIG. 2).

According to a fourth aspect of the present application, there is provided a computer program configured to perform the above-mentioned method when executed on a computer or microcontroller, such that the above-mentioned method is performed by the computer program.

Although some aspects have been described in relation to an apparatus, it will be apparent that these aspects also represent a description of a corresponding method, with blocks or devices corresponding to method steps or features of method steps. Similarly, aspects described in relation to a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus. Some or all of the method steps may be performed by (or using) a hardware apparatus, such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, one or more of the most important method steps may be performed by such an apparatus.

The data stream of the present invention can be stored on a digital storage medium or transmitted over a transmission medium, such as a wireless transmission medium or a wired transmission medium such as the Internet.

Depending on the particular implementation requirements, the embodiments of the present application may be implemented in hardware or software. Implementation may be performed using a digital storage medium (e.g., floppy disk, DVD, Blu-Ray, CD, ROM, PROM, EPROM, EEPROM, or flash memory) on which electronically readable control signals are stored, which cooperate (or can cooperate) with a programmable computer system to perform the corresponding method. Thus, the digital storage medium may be computer readable.

Some embodiments according to the invention include a data carrier having electronically readable control signals capable of cooperating with a programmable computer system to perform one of the methods described herein.

In general, embodiments of the present application may be implemented as a computer program product having program code operable to perform one of the methods when the computer program product is run on a computer. The program code may, for example, be stored on a machine readable carrier.

Other embodiments comprise the computer program stored on a machine readable carrier for performing one of the methods described herein.

Thus, in other words, an embodiment of the inventive method is a computer program having a program code for performing one of the methods described herein when the computer program runs on a computer.

Thus, a further embodiment of the method of the present invention is a data carrier (or digital storage medium, or computer readable medium) having recorded thereon a computer program for performing one of the methods described herein. The data carrier, digital storage medium, or recorded medium is typically tangible and/or non-transitory.

A further embodiment of the inventive method is therefore a data stream or a sequence of signals representing a computer program for performing one of the methods described herein. The data stream or sequence of signals may for example be configured to be transferred via a data communication connection (for example via the Internet).

A further embodiment comprises a processing means (e.g. a computer or a programmable logic device) configured or adapted to perform one of the methods described herein.

A further embodiment includes a computer having installed thereon a computer program for performing one of the methods described herein.

Further embodiments according to the invention include an apparatus or system configured to transfer (e.g., electronically or optically) a computer program for performing one of the methods described herein to a receiver. The receiver may be, for example, a computer, a mobile device, or a memory device. The apparatus or system may, for example, include a file server for transferring the computer program to the receiver.

In some embodiments, a programmable logic device (e.g., a field programmable gate array) may be used to perform some or all of the functions of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform one of the methods described herein. In general, the methods are preferably performed by any hardware apparatus.

The devices described herein may be implemented using a hardware device, or using a computer, or using a combination of a hardware device and a computer.

The devices described herein, or any components of the devices described herein, may be implemented at least in part in hardware and/or software.

The above-described embodiments are merely illustrative of the principles of the present invention. It should be understood that modifications and variations of the configurations and detailed descriptions set forth herein will be apparent to those skilled in the art. It is therefore intended to be limited only by the scope of the claims set forth below and not by the specific details presented in the description and explanation of the embodiments herein.

2 Processor 4 Converter 8 DSP
10 FF
12 Multiplexer, selector 14 FF
16 VCSO
100 Circuit 200 Circuit

Claims (20)

1. A circuit for converting signals between digital and analog, comprising:
a processor configured to provide or use a synchronous clock signal;
a converter configured to convert data between digital and analog using a converter clock signal;
a phase comparator configured to determine a phase relationship between the synchronous clock signal and the converter clock signal;
a digital signal processor coupled to the phase comparator to receive information regarding the phase relationship, the digital signal processor being configured to impart a delay to signal data exchanged between the processor and the converter in response to the phase relationship;
A circuit wherein there is a predetermined frequency relationship between the synchronous clock signal and the converter clock signal, the synchronous clock signal being a clock signal that indicates timing for the conversion between digital and analog . The circuit of claim 1, wherein the circuit is configured to determine whether an enable signal that is time-synchronous with the synchronous clock signal and triggers conversion of data between digital and analog is sampled on a rising edge or a falling edge of the converter clock signal based on information about the phase relationship between the synchronous clock signal and the converter clock signal to obtain an enable signal that is time-synchronous with the converter clock signal. the circuitry being responsive to the information regarding the phase relationship between the synchronous clock signal and the converter clock signal to:
a first mode in which the enable signal, which is time-synchronous with the synchronous clock signal and triggers the conversion of data between digital and analog, is sampled at an edge of a first edge type of the converter clock signal to obtain an intermediate signal, and the intermediate signal is sampled at an edge of a second edge type of the converter clock signal to obtain the enable signal, which is time-synchronous with the converter clock signal;
a second mode in which the enable signal, which is time-synchronous with the synchronous clock signal and triggers conversion of data between digital and analog, is sampled at an edge of the second edge type of the converter clock signal to obtain the enable signal, which is time-synchronous with the converter clock signal. a first flip-flop circuit coupled to the processor to receive an enable signal, the first flip-flop circuit configured to sample the enable signal at a first sampling phase to obtain a sampled signal when the phase relationship indicates that a value of a phase difference between the synchronous clock signal and the converter clock signal is within a first predetermined range;
a signal selector coupled to the processor to receive the enable signal and coupled to the first flip-flop circuit to receive the sampled signals, the signal selector configured to select one of the received signals to obtain a selected signal;
a second flip-flop circuit coupled to the signal selector to receive the selected signal, the second flip-flop circuit configured to sample the enable signal at a second sampling phase if the phase relationship is within a second predetermined range; and
a first-in-first-out circuit coupled to the digital signal processor to receive the signal data and coupled to the second flip-flop circuit via a delay circuit to receive a delayed version of an output signal of the second flip-flop circuit, the first-in-first-out circuit providing signal data associated with the sampled enable signal to the converter. The circuit of claim 4, wherein the selector comprises a multiplexer that selects one of the input signals based on the information about the phase relationship. The circuit of any one of claims 1 to 5, wherein the phase comparator comprises a phase-to-digital converter configured to measure a phase difference between the synchronous clock signal and the converter clock signal to determine the phase relationship. The circuit of any one of claims 1 to 6, wherein the digital signal processor is configured to cancel and/or at least partially compensate for a phase difference between the synchronous clock signal and the converter clock signal. 8. The circuit of claim 7, wherein the digital signal processor is configured to provide filtered data values associated with a conversion time in a time grid determined by the converter clock signal based on one or more input data values provided synchronously with the synchronized clock signal, and/or the digital signal processor is configured to provide filtered data values aligned to a time axis determined by the synchronized clock signal based on one or more data values defined in a time grid determined by the converter clock signal. The circuit of claim 7 or 8, wherein the digital signal processor uses a finite impulse response (FIR) filter. The circuit of claim 7 or 8, wherein the digital signal processor uses a Farrow structure. The circuit of any one of claims 1 to 10, wherein the circuit comprises an oscillator, the output signal of which is used as the converter clock signal, or the circuit is configured to derive the converter clock signal from the output signal of the oscillator. The circuit of any one of claims 1 to 11, wherein the circuit is configured to derive the synchronous clock signal and the converter clock signal from a common reference signal such that the frequency of the synchronous clock signal and the frequency of the converter clock signal are in a predetermined relationship. The circuit of any one of claims 1 to 12, wherein the converter is a digital-to-analog converter. The circuit of any one of claims 1 to 12, wherein the converter is an analog-to-digital converter. A test apparatus for testing a device under test, comprising a circuit according to any one of claims 1 to 14. The test device of claim 15, wherein the test device is configured to execute a test flow in synchronization with the synchronous clock signal. 17. The test apparatus of claim 16, wherein the apparatus is configured to supply an analog signal obtained using the converter based on an input signal value to the device under test, and/or the apparatus is configured to obtain digital data provided by the digital signal processor based on a digitized device under test signal obtained from the converter using the delay, and to evaluate the digital data. 1. A method for converting signals between digital and analog, comprising:
receiving a synchronous clock signal provided by or used by the processor and a converter clock signal used by the converter;
determining a phase relationship between the synchronous clock signal and the converter clock signal;
providing a delay to signal data exchanged between the processor and the converter based on the phase relationship between the synchronous clock signal and the converter clock signal;
A method according to claim 1, wherein a predetermined frequency relationship exists between said synchronous clock signal and said converter clock signal , said synchronous clock signal being a clock signal indicating timing for said conversion between digital and analog . The method further comprising:
In response to the phase relationship between the synchronous clock signal and the converter clock signal,
a first mode in which an enable signal , which is time-synchronous with the synchronous clock signal and triggers the conversion of data between digital and analog, is sampled at an edge of a first edge type of the converter clock signal to obtain an intermediate signal, and the intermediate signal is sampled at an edge of a second edge type of the converter clock signal to obtain the enable signal , which is time-synchronous with the converter clock signal;
a second mode in which the enable signal , which is time synchronous with the synchronous clock signal and which triggers the conversion of data between digital and analog, is sampled at an edge of the second edge type of the converter clock signal to obtain the enable signal, which is time synchronous with the converter clock signal ;
and providing the signal data associated with the sampled enable signal to the converter. A computer program for carrying out the method according to claim 18 or 19 when the computer program is run on a computer or microcontroller.