JP7476640B2 - Information processing device, interface control circuit, and method for controlling information processing device - Google Patents

Description

The present invention relates to an information processing device, an interface control circuit, and a control method for an information processing device.

For example, a bus system is known in which multiple masters and multiple slaves are connected via an interconnect. Each master takes the lead in data transfer, and each slave operates passively (see, for example, Patent Document 1).

In some cases, multiple CPUs (Central Processing Units) are connected to the interconnect as masters, and memories storing programs executed by each CPU are connected to the interconnect as slaves. For example, one of the multiple CPUs is a main CPU that controls the entire system, and another of the multiple CPUs is a sub-CPU that controls some of the system's functions. The main CPU and sub-CPU operate by fetching programs stored in the memory via the interconnect.

When the main CPU resets a sub-CPU that is fetching a program from memory and running it, the sub-CPU may be reset while it is executing a transaction with the interconnect. In this case, depending on the timing of the reset issued from the main CPU to the sub-CPU, the transaction may not be completed and the interconnect may stall.

The disclosed technology has been developed in consideration of the above-mentioned problems, and aims to inhibit a handshake between a master and an interconnect based on an external inhibition request signal without interrupting ongoing data transfer.

In order to solve the above technical problems, an information processing device of one embodiment of the present invention has a first master and a slave that transfer data based on a handshake consisting of a request and a response to the request , a second master that outputs an inhibition request signal that inhibits the handshake, an interconnect that controls transfer of data between the first master and the slave, and an interface control circuit that is provided between the first master and the interconnect and includes a mask control unit that inhibits transfer of the request issued from the first master to the interconnect while receiving the inhibition request signal that inhibits the handshake, and outputs an inhibition signal indicating that transfer of the request to the interconnect is being inhibited , and is characterized in that the second master outputs a reset signal to the first master based on receipt of the inhibition signal .

Based on an external inhibit request signal, the handshake between the master and the interconnect can be inhibited without interrupting the ongoing data transfer.

1 is a block diagram showing an example of an information processing apparatus according to a first embodiment of the present invention. 1. FIG. 4 is a timing diagram showing an example of an operation when a mask control signal is asserted while a valid signal is being negated in the information processing device of FIG. 1. FIG. 4 is a timing diagram showing an example of an operation when a mask control signal is asserted while a valid signal is asserted in the information processing device of FIG. 1. FIG. 11 is a timing diagram showing another example of the operation when the mask control signal is asserted while the valid signal is being negated in the information processing device of FIG. 1. FIG. 4 is a flow chart showing an example of an operation when a sub-CPU is reset by a main CPU in the information processing device of FIG. FIG. 11 is a block diagram showing an example of an information processing apparatus according to a second embodiment of the present invention. 7 is a timing diagram showing an example of an operation (outstanding transaction) of the information processing device of FIG. 6. 7 is a timing diagram showing an example of an operation when a mask control signal is asserted while a valid signal is being negated in the information processing device of FIG. 6; 7 is a timing diagram showing an example of an operation when a mask control signal is asserted while a valid signal is asserted in the information processing device of FIG. 6; 7 is a flow chart showing an example of an operation when a sub-CPU is reset by a main CPU in the information processing device of FIG. 6; FIG. 13 is a block diagram showing an example of an information processing apparatus according to a third embodiment of the present invention. 12 is a timing chart showing an example of an operation of the information processing device of FIG. 11 .

The following describes the embodiments with reference to the drawings. Note that in each drawing, the same components are given the same reference numerals, and duplicate descriptions may be omitted.

First Embodiment
Fig. 1 is a block diagram showing an example of an information processing apparatus according to a first embodiment of the present invention. The information processing apparatus 100 shown in Fig. 1 has CPUs 10 and 20, a memory 30, an interconnect 40, and an interface control circuit 50. Although not particularly limited, for example, the information processing apparatus 100 is an image forming apparatus such as an MFP (Multifunction Printer), and has a copy function, a facsimile function, a print function, a scanner function, etc.

The CPUs 10 and 20 act as masters with respect to the memory 30, and the memory 30 acts as a slave with respect to the CPUs 10 and 20. Note that the CPU 10 is an example of a master control device or a second master, and the CPU 20 is an example of a master or a first master. The interconnect 40 functions as a slave when communicating with the CPU 20, which is the master.

The CPUs 10, 20 and the memory 30 transfer data based on a handshake consisting of a request and a response to the request. The interconnect 40 controls the transfer of data between the CPUs 10, 20 and the memory 30. Note that data transfer based on a handshake consisting of a request and a response to the request is also performed between the CPU 20 and the interconnect 40.

For example, the CPU 10 controls the overall operation of the information processing device 100 during normal operation mode, and is powered off during low power modes such as energy saving mode. The CPU 20 operates constantly while the information processing device 100 is in operation (during normal operation mode and energy saving mode), and controls some of the functions of the information processing device 100 in place of the CPU 10 during energy saving mode. For example, the main CPU 10 and the sub-CPU 20 each fetch programs stored in the memory 30 via the interconnect 40 and operate.

The CPU 10 has a function of issuing a reset signal RESET to the CPU 20 to reset and restart the CPU 20, for example, when a program executed by the CPU 20 is rewritten (when updating the OS or firmware, etc.). Hereinafter, the CPU 10 is also referred to as the main CPU 10, and the CPU 20 is also referred to as the sub-CPU 20. The memory 30 is, for example, a Synchronous Dynamic Random Access Memory (SDRAM).

The interconnect 40 arbitrates access requests from the main CPU 10 and the sub-CPU 20 to the memory 30, and causes the memory 30 to execute a read or write operation in response to the access request (read request or write request). The interconnect 40 outputs data (programs) read from the memory 30 to the CPU (main CPU 10 or sub-CPU 20) that issued the read request.

For example, the interconnect 40 performs a handshake with the master (CPU 20 in the example of FIG. 1) based on the valid signal VALID and the ready signal READY. The valid signal VALID is asserted by the master when the data (information) output by the master is valid. The ready signal READY is asserted by the slave (interconnect 40 in the example of FIG. 1) when preparations for receiving data or control signals are complete.

Then, after a handshake is performed based on the valid signal VALID and the ready signal READY both being asserted, the data is transferred. The valid signals VALID0 and VALID are examples of requests, and the ready signal READY is an example of a response to a request.

The interconnect 40, for example, executes a transaction to transfer data DATA read from the memory 30 to the CPU 20, and outputs a completion notification signal END to the CPU 20 in synchronization with the transfer of the final data DATA to the sub-CPU 20. The completion notification signal END indicates the completion of the transaction to transfer data read from the memory 30 to the CPU 20. An example of a transaction using a valid signal VALID and a ready signal READY is described in FIG. 2 and subsequent figures.

The interface control circuit 50 includes a mask control unit 52. While the mask control signal MASKEN output from the main CPU 10 is negated, the mask control unit 52 outputs the valid signal VALID0 output from the sub CPU 20 to the interconnect 40 as the valid signal VALID. For example, the mask control unit 52 may have a function of holding the logical level of the valid signal VALID0 until it outputs the valid signal VALID. While the mask control signal MASKEN is asserted, the mask control unit 52 maintains the negated state of the valid signal VALID regardless of the logical level of the valid signal VALID0.

In this way, while the mask control signal MASKEN is asserted, the transfer of the valid signal VALID0 (i.e., VALID) to the interconnect 40 is inhibited. While the mask control signal MASKEN is asserted, the interconnect 40 does not receive the valid signal VALID and therefore does not output the ready signal READY. Therefore, the establishment of a handshake can be inhibited based on the mask control signal MASKEN that is received from the outside asynchronously with the transaction between the CPU 20 and the interconnect 40. The mask control signal MASKEN is an example of an inhibition request signal that inhibits a handshake.

When the mask control unit 52 detects that the mask control signal MASKEN is asserted, it asserts the mask signal IMASK, and when it detects that the mask control signal MASKEN is negated, it negates the mask signal IMASK. The mask signal IMASK is input to the main CPU 10.

The assertion period of the mask signal IMASK indicates that the transfer of the valid signal VALID to the interconnect 40 is being inhibited. The negation period of the mask signal IMASK indicates that the inhibition of the transfer of the valid signal VALID to the interconnect 40 is not being executed. The main CPU 10 that receives the mask signal IMASK can confirm that the assertion of the valid signal VALID is being inhibited by the mask control unit 52 according to the logic level of the mask signal IMASK. The mask signal IMASK is an example of an inhibited signal that indicates that the transfer of the valid signal VALID to the interconnect 40 is being inhibited.

In FIG. 1, the clock CLK is supplied to each of the CPUs 10 and 20, the memory 30, the interconnect 40, and the interface control circuit 50, but the type and frequency of the clock CLK may be different from each other.

Figure 2 is a timing diagram showing an example of the operation of the information processing device 100 of Figure 1 when the mask control signal MASKEN is asserted while the valid signal VALID0 is negated. That is, Figure 2 shows an example of a control method of the information processing device 100.

In the example shown in FIG. 2, the sub-CPU 20 asserts the valid signal VALID0 to a high level for, for example, two clock cycles to execute transaction A that fetches a program stored in the memory 30 (FIG. 2(a)). The valid signal VALID0 is asserted to a high level during the negation period of the mask control signal MASKEN (FIG. 2(b)).

In response to the assertion of the valid signal VALID0, the mask control unit 52 of the interface control circuit 50 asserts the valid signal VALID to a high level (FIG. 2(c)). Based on the reception of the valid signal VALID, the interconnect 40 asserts the ready signal READY to a high level, for example, for one clock cycle (FIG. 2(d)). As a result, the sub-CPU 20 and the interconnect 40 handshake regarding transaction A. The interconnect 40 starts data transfer A, which transfers the data DATA (program) read from the memory 30 to the sub-CPU 20 (FIG. 2(e)).

For example, the main CPU 10 asserts the mask control signal MASKEN to a high level to rewrite (update) a program executed by the sub CPU 20 (FIG. 2(f)). In the example shown in FIG. 2, the mask control signal MASKEN is asserted while the valid signal VALID0 is negated, but the assertion timing of the mask control signal MASKEN is arbitrary. Based on the assertion of the mask control signal MASKEN, the mask control unit 52 asserts the mask signal IMASK to a high level (FIG. 2(g)).

When the transfer of data DATA to the sub-CPU 20 by transaction A is completed, the interconnect 40 asserts the completion notification signal END to a high level for, for example, one clock cycle (Figure 2(h)). The sub-CPU 20, which has received the completion notification signal END, asserts the valid signal VALID0 to execute the next transaction (Figure 2(i)).

Because the mask control signal MASKEN is asserted, the mask control unit 52 suppresses assertion of the valid signal VALID in response to the valid signal VALID0, and maintains the negated state of the valid signal VALID (FIG. 2(j)). In other words, the mask control unit 52 suppresses the transfer of the valid signal VALID0 to the interconnect 40 while receiving the mask control signal MASKEN that suppresses the handshake.

Since the interconnect 40 does not receive the valid signal VALID, it maintains the ready signal READY in a negated state (FIG. 2(k)). This makes it possible to suppress handshakes between the sub-CPU 20 and the interconnect 40 for transactions subsequent to transaction A, and to suppress the transfer of data DATA to the sub-CPU 20.

In this way, the mask control signal MASKEN issued at any timing can prevent the execution of the next transaction between the sub CPU 20 and the interconnect 40 without interrupting the transaction currently being executed. Since the subsequent transaction is not executed, the transaction between the sub CPU 20 and the interconnect 40 is not interrupted even if the sub CPU 20 is reset. In other words, it is possible to prevent the interconnect 40 from stalling due to the interruption of the transaction.

After asserting the mask control signal MASKEN, the main CPU 10 asserts the reset signal RESET for a predetermined number of clock cycles to reset the sub-CPU 20 (FIG. 2(l)). Note that in order to prevent the interconnect 40 from stalling, the reset of the sub-CPU 20 must be performed after the execution of transaction A is completed.

Therefore, after asserting the mask control signal MASKEN, the main CPU 10 detects the assertion of the mask signal IMASK, and then waits a predetermined number of clock cycles until the execution of transaction A is completed, and then asserts the reset signal RESET. The main CPU 10 may also monitor the completion notification signal END output from the interconnect 40 to the sub-CPU 20. Then, the main CPU 10 may assert the reset signal RESET after the completion notification signal END is asserted.

For example, after the sub-CPU 20 is released from reset, it loads a boot program from a non-volatile memory (not shown) into the memory 30, and transfers the updated program from the non-volatile memory to the memory 30. The sub-CPU 20 then starts fetching the updated program stored in the memory 30. Note that the program for the sub-CPU 20 in the non-volatile memory is replaced before the sub-CPU 20 is reset.

Figure 3 is a timing diagram showing an example of the operation of the information processing device 100 of Figure 1 when the mask control signal MASKEN is asserted while the valid signal VALID0 is asserted. That is, Figure 3 shows an example of a control method of the information processing device 100. A detailed description of the same operations as those in Figure 2 will be omitted.

In FIG. 3, the mask control signal MASKEN is asserted while the valid signal VALID0 for executing transaction A is asserted (FIG. 3(a)). In this case, the mask control unit 52 suppresses the assertion of the mask signal IMASK while the valid signal VALID0 is asserted, and asserts the mask signal IMASK in the next clock cycle after the valid signal VALID0 is negated, for example (FIG. 3(b)). Because the mask signal IMASK is not asserted, it is possible to suppress the negation of valid RVALID by the assertion of the mask control signal MASKEN.

The mask control unit 52 inhibits assertion of the mask signal IMASK while asserting the valid signal VALID0, and suppresses the negation of valid RVALID. This allows the interconnect 40 to assert the ready signal READY based on the valid signal VALID, and start data transfer A (Figure 3(c)).

The assertion of the valid signal VALID in response to the next valid signal VALID0 asserted after the execution of transaction A is inhibited by the mask control signal MASKEN and is not output to the interconnect 40 (FIG. 3(d)). Therefore, similar to FIG. 2, the interconnect 40 can maintain the ready signal READY in a negated state and inhibit the handshake between the sub CPU 20 and the interconnect 40 (FIG. 3(e)). After this, the main CPU 10 asserts the reset signal RESET to reset the sub CPU 20 (FIG. 3(f)). Then, after the reset is released, the sub CPU 20 transfers the updated program from the non-volatile memory to the memory 30 and starts fetching the updated program.

Because the main CPU 10 and sub-CPU 20 operate asynchronously, the main CPU 10 cannot determine whether the sub-CPU 20 is in the middle of a transaction with the interconnect 40. However, in this embodiment, an interface control circuit 50 is placed between the sub-CPU 20 and the interconnect 40, and the mask control signal MASKEN output by the main CPU 10 controls whether or not to output the valid signal VALID to the interconnect 40. This makes it possible to prevent the sub-CPU 20 from being reset while the sub-CPU 20 is executing a transaction, and to prevent the interconnect 40 from stalling due to an inability to complete the transaction.

Figure 4 is a timing diagram showing another example of the operation when the mask control signal MASKEN is asserted while the valid signal VALID0 is negated in the information processing device 100 of Figure 1. That is, Figure 4 shows an example of a control method for the information processing device 100. Detailed explanations of operations similar to those in Figure 2 will be omitted. Figure 4 shows an example of the operation when the main CPU 10 asserts the mask control signal MASKEN and then negates the mask control signal MASKEN without asserting the reset signal RESET. The operation until the valid signal VALID0 is asserted for the second time is the same as in Figure 2.

When the mask control signal MASKEN is negated without the sub-CPU 20 being reset, the mask control unit 52 asserts the valid signal VALID according to the valid signal VALID0 (assertion level) that it holds (Figures 4(a) and (b)). For example, the second valid signal VALID corresponds to transaction B.

The interconnect 40 asserts a ready signal READY based on receiving the valid signal VALID (Figure 4(c)). This causes the sub CPU 20 and the interconnect 40 to handshake regarding transaction B. The interconnect 40 starts data transfer B, which transfers data DATA (program) read from memory 30 to the sub CPU 20 (Figure 4(d)). When the transfer of data DATA to the sub CPU 20 by transaction B is completed, the interconnect 40 asserts a completion notification signal END to a high level (Figure 4(e)). This completes data transfer B of transaction B.

In this way, when the mask control signal MASKEN from the main CPU 10 is temporarily asserted, the mask control unit 52 can continue the transaction based on the received valid signal VALID0 after negating the mask control signal MASKEN. Therefore, it is possible to prevent the occurrence of malfunctions such as an inability to execute a transaction when the mask control signal MASKEN is temporarily erroneously asserted.

Figure 5 is a flow diagram showing an example of the operation when the main CPU 10 resets the sub-CPU 20 in the information processing device 100 of Figure 1. That is, Figure 5 shows an example of a control method for the information processing device 100. The operation shown in Figure 5 is executed by the main CPU 10.

First, in step S10, the main CPU 10 asserts the mask control signal MASKEN at any timing unrelated to the operation of the sub-CPU 20. Next, in step S12, the main CPU 10 determines whether the mask signal IMASK has been asserted, and if the mask signal IMASK has been asserted, executes step S14.

In step S14, the main CPU 10 waits for a predetermined number of clock cycles to elapse, and then executes step S16. The predetermined number of clock cycles to wait in step S14 is the number of clock cycles until the ongoing transaction is completed. In step S16, the main CPU 10 outputs (asserts) a reset signal RESET to the sub CPU 20 for a predetermined period of time, resetting the sub CPU 20. The sub CPU 20 is restarted upon receiving the reset signal RESET.

Then, in step S18, the main CPU 10 negates the mask control signal MASKEN, causing the mask control unit 52 to release the inhibition of assertion of the valid signal VALID. The sub CPU 20 then starts fetching the updated program. Note that the mask control signal MASKEN may be negated while the sub CPU 20 is reset. This allows the sub CPU 20 to fetch the updated program based on the valid signal VALID0 that is output after the reset signal RESET is released.

As described above, in the first embodiment, the establishment of a handshake between the CPU 20 and the interconnect 40 can be suppressed based on the mask control signal MASKEN received from the outside asynchronously with the transaction executed between the CPU 20 and the interconnect 40. At this time, the establishment of a handshake between the CPU 20 and the interconnect 40 can be suppressed without interrupting the data transfer being executed. Therefore, when the CPU 20 is reset by the reset signal RESET output by the CPU 10 after the mask control signal MASKEN is asserted, the execution of a transaction between the CPU 20 and the interconnect 40 can be suppressed.

As a result, it is possible to prevent the interconnect 40 from stalling due to the CPU 20 being reset while a transaction is being executed, and it is possible to prevent downtime caused by a restart due to a stall. For example, if the program update executed by the CPU 20 is a remote update, a delay in noticing a stall that has occurred in the interconnect 40 may result in a long downtime. In this embodiment, it is possible to prevent the interconnect 40 from stalling, and therefore it is possible to prevent downtime even when an update is executed remotely.

For example, in a multi-CPU system (information processing device 100) in which a main CPU 10 and a sub-CPU 20 are operating, when one CPU resets the other CPU, it is possible to prevent the interconnect 40 connected to the CPU from stalling. As a result, it is possible to prevent downtime of the information processing device 100, and to prevent a decrease in performance of the information processing device 100 due to downtime.

The mask control unit 52 outputs a mask signal IMASK to the main CPU 10 based on the reception of the mask control signal MASKEN. Therefore, the main CPU 10 can confirm that the assertion of the valid signal VALID is being suppressed by the mask control unit 52 according to the level of the mask signal IMASK.

Second Embodiment
Fig. 6 is a block diagram showing an example of an information processing device according to a second embodiment of the present invention. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description will be omitted. The information processing device 102 shown in Fig. 6 has an interface control circuit 60 and an interconnect 42 instead of the interface control circuit 50 and the interconnect 40 in Fig. 1. The other configurations of the information processing device 102 are similar to those of the information processing device 100 shown in Fig. 1.

The interconnect 42 has an outstanding transaction function that allows it to issue the next transfer request during data transfer. For example, the sub-CPU 20 can issue the next valid signal VALID0 while data is being communicated between the sub-CPU 20 and the interconnect 42. Other functions of the interconnect 42 are similar to those of the interconnect 40 in FIG. 1.

The interface control circuit 60 has a mask control unit 62 and a busy monitoring unit 64. The mask control unit 62 has the same function as the mask control unit 52 of the interface control circuit 50 in FIG. 1. The busy monitoring unit 64 has a busy counter BCOUNT that is reset to "0" in the initial state.

The busy monitoring unit 64 increments the busy counter BCOUNT by "1" in response to the establishment of a handshake using the valid signal VALID and the ready signal READY, and decrements the busy counter BCOUNT by "1" in response to the completion notification signal END. The busy counter BCOUNT may be decremented by "1" when the handshake is established, and incremented by "1" when the completion notification signal END is asserted.

If the busy counter BCOUNT is other than "0", the busy monitoring unit 64 detects that a transaction is being executed between the sub CPU 20 and the interconnect 42, and asserts the busy signal BUSY. In other words, if the number of handshakes established does not match the number of assertions (outputs) of the completion notification signal END, the busy monitoring unit 64 asserts the busy signal BUSY.

When the busy counter BCOUNT is "0", the busy monitoring unit 64 detects that no transaction is being executed between the sub CPU 20 and the interconnect 42, and negates the busy signal BUSY. That is, when the number of successful handshakes matches the number of assertions of the completion notification signal END, the busy monitoring unit 64 negates the busy signal BUSY. The assertion period of the busy signal BUSY indicates the period during which data transfer is being executed after a handshake is established using a valid signal VALID and a ready signal READY. The busy monitoring unit 64 may generate the busy signal BUSY using a method other than the busy counter BCOUNT.

Figure 7 is a timing diagram showing an example of the operation (outstanding transaction) of the information processing device 102 of Figure 6. That is, Figure 7 shows an example of a control method for the information processing device 102. Detailed explanation of operations similar to those in Figure 2 will be omitted. In Figure 7, in order to explain the operation of the outstanding transaction, the mask control signal MASKEN is maintained in a negated state (low level L).

In FIG. 7, the sub-CPU 20 sequentially outputs valid signals VALID0 for executing transactions A, B, and C without waiting for the completion of data transfer (FIG. 7(a), (b), (c)). Since the mask control signal MASKEN is negated, the mask control unit 62 outputs valid signals VALID to the interconnect 42 in response to each valid signal VALID0 (FIG. 7(d), (e), (f)).

Based on receiving each valid signal VALID, the interconnect 42 outputs a ready signal READY (A, B, C) to the sub CPU 20 (FIG. 7(g), (h), (i)). The interconnect 42 reads data from the memory 30 in the order of the received valid signals VALID, and sequentially executes data transfers A, B, C in which the read data is transferred to the sub CPU 20 (FIG. 7(j), (k), (l)). Then, the interconnect 40 sequentially outputs completion notification signals END (A, B, C) to the sub CPU 20 each time data transfers A, B, C are completed (FIG. 7(m), (n), (o)).

The busy monitoring unit 64 increments the busy counter BCOUNT by "1" each time it detects the assertion of the valid signal VALID and the ready signal READY (FIG. 7 (p), (q), (r)). The busy monitoring unit 64 also decrements the busy counter BCOUNT by "1" each time it detects the assertion of the completion notification signal END (FIG. 7 (s), (t), (u)).

The busy monitoring unit 64 negates the busy signal BUSY to a low level when the busy counter BCOUNT is "0", and asserts the busy signal BUSY to a high level when the busy counter BCOUNT is other than "0" (Figures 7 (v), (w), (x)). This allows the main CPU 10 to detect the execution period of a transaction by the sub-CPU 20 based on the logical level of the busy signal BUSY.

In FIG. 7, for example, if the mask control signal MASKEN is asserted while the first valid signal VALID0 is asserted, the second and third valid signals VALID0 are not generated and only data transfer A is executed. In this case, the busy signal BUSY is negated based on the completion notification signal END shown in FIG. 7(m).

If the mask control signal MASKEN is asserted while the second valid signal VALID0 is asserted, the third valid signal VALID0 is not generated, data transfers A and B are executed, and data transfer C is not executed. In this case, the busy signal BUSY is negated based on the completion notification signal END shown in Figure 7 (n). If the mask control signal MASKEN is asserted while the third valid signal VALID0 is asserted, all data transfers A, B, and C are executed. In this case, the negation timing of the busy signal BUSY is the same as in Figure 7.

Figure 8 is a timing diagram showing an example of the operation when the mask control signal MASKEN is asserted while the valid signal VALID0 is negated in the information processing device 102 of Figure 6. That is, Figure 8 shows an example of a control method for the information processing device 102. Detailed explanations of operations similar to those in Figure 2 will be omitted. In Figure 8, the waveforms other than the busy counter BCOUNT and the busy signal BUSY are the same as those in Figure 2.

As described in FIG. 6 and FIG. 7, when the busy monitoring unit 64 detects the assertion of the valid signal VALID and the ready signal READY, it increments the busy counter BCOUNT by "1" (FIG. 8(a)). In response to the busy counter BCOUNT no longer being "0", the busy monitoring unit 64 asserts the busy signal BUSY to a high level (FIG. 8(b)).

In addition, the busy monitoring unit 64 decrements the busy counter BCOUNT by "1" in response to the assertion of the completion notification signal END (FIG. 8(c)). In response to the busy counter BCOUNT becoming "0", the busy monitoring unit 64 negates the busy signal BUSY to a low level (FIG. 8(d)). The assertion period (high level period) of the busy signal BUSY indicates that data transfer A between the CPU 20 and the interconnect 40, which is executed based on the valid signal VALID0 issued from the CPU 20 before receiving the mask control signal MASKEN, is being detected.

After receiving a high-level mask signal IMASK from the interface control circuit 60 due to the assertion of the mask control signal MASKEN, the main CPU 10 waits for the busy signal BUSY to go low. Then, based on the busy signal BUSY going low, the main CPU 10 detects that the transaction between the sub-CPU 20 and the interconnect 42 has been completed, and outputs a reset signal RESET to the sub-CPU 20 (Figure 8 (e)).

This reliably prevents the CPU 20 from being reset and the interconnect 42 from stalling during the execution of a transaction. Also, as described in FIG. 7, even if the interconnect 40 has an outstanding transaction function, it is possible to prevent the CPU 20 from being reset during the execution of any of multiple transactions.

As in the first embodiment, after the reset is released, the sub-CPU 20 transfers the updated program from the non-volatile memory to the memory 30 and starts fetching the updated program.

Figure 9 is a timing diagram showing an example of the operation when the mask control signal MASKEN is asserted while the valid signal VALID0 is asserted in the information processing device 102 of Figure 6. That is, Figure 9 shows an example of a control method for the information processing device 102. Detailed explanations of operations similar to those in Figures 2 and 3 will be omitted. In Figure 9, the waveforms other than the busy counter BCOUNT and busy signal BUSY are the same as those in Figure 3.

As in FIG. 8, when the busy monitoring unit 64 detects the assertion of the valid signal VALID and the ready signal READY, it increments the busy counter BCOUNT by "1" (FIG. 9(a)). In response to the busy counter BCOUNT no longer being "0", the busy monitoring unit 64 asserts the busy signal BUSY to a high level (FIG. 9(b)).

In addition, the busy monitoring unit 64 decrements the busy counter BCOUNT by "1" in response to the assertion of the completion notification signal END (FIG. 9(c)). In response to the busy counter BCOUNT becoming "0", the busy monitoring unit 64 negates the busy signal BUSY to a low level (FIG. 9(d)).

As in FIG. 8, after asserting the mask control signal MASKEN, the main CPU 10 waits for the busy signal BUSY to go low, and outputs a reset signal RESET to the sub CPU 20 based on the busy signal BUSY going low (FIG. 9(e)). After the reset is released, the sub CPU 20 transfers the updated program from the non-volatile memory to the memory 30 and starts fetching the updated program.

Figure 10 is a flow diagram showing an example of the operation when the main CPU 10 resets the sub-CPU 20 in the information processing device 102 of Figure 6. That is, Figure 10 shows an example of a control method for the information processing device 102. Operations similar to those in Figure 5 are given the same reference numerals, and detailed explanations are omitted. In Figure 10, the main CPU 10 executes step S15 instead of step S14 in Figure 5.

If the mask signal IMASK is asserted in step S12, the main CPU 10 executes step S15. In step S15, the main CPU 10 determines whether the busy signal BUSY is negated, and if the busy signal BUSY is negated, executes step S16 and resets the sub-CPU 20.

As described above, the second embodiment can achieve the same effect as the first embodiment. For example, the establishment of a handshake between the CPU 20 and the interconnect 42 can be suppressed based on the mask control signal MASKEN received from the outside asynchronously with the transaction executed between the CPU 20 and the interconnect 42. At this time, the establishment of a handshake between the CPU 20 and the interconnect 42 can be suppressed without interrupting the data transfer being executed. Therefore, when the CPU 20 is reset by the reset signal RESET output by the CPU 10 after assertion of the mask control signal MASKEN, the execution of a transaction between the CPU 20 and the interconnect 42 can be suppressed. As a result, it is possible to suppress the interconnect 42 from stalling due to the CPU 20 being reset during the execution of a transaction, and it is possible to suppress the occurrence of downtime due to restarting due to the stall.

Furthermore, in the second embodiment, by providing a busy monitoring unit 64 in the interface control circuit 60, the main CPU 10 can detect the execution period of a transaction by the sub-CPU 20 based on the logical level of the busy signal BUSY. The busy monitoring unit 64 can output the busy signal BUSY in accordance with the execution period of the transaction by asserting the busy signal BUSY when the number of successful handshakes and the number of assertions (outputs) of the completion notification signal END do not match.

The busy monitoring unit 64 has a busy counter BCOUNT that increments its count value by "1" in response to the establishment of a handshake and decrements its count value by "1" in response to a completion notification signal END. Therefore, when the busy counter BCOUNT is other than "0", the busy monitoring unit 64 asserts the busy signal BUSY, thereby being able to output the busy signal BUSY in accordance with the execution period of the transaction between the sub-CPU 20 and the interconnect 42.

Figure 11 is a block diagram showing an example of an information processing device according to a third embodiment of the present invention. Elements similar to those in Figures 1 and 6 are given the same reference numerals and detailed description is omitted. The information processing device 104 shown in Figure 11 has an interface control circuit 70 and an interconnect 44 instead of the interface control circuit 50 and interconnect 40 in Figure 1. The other configuration of the information processing device 104 is similar to the information processing device 100 shown in Figure 1, except that the communication protocol used for communication between the CPU 20 and the interconnect 44 is different from that of the above-mentioned embodiment. The interface control circuit 70 has a mask control unit 72 and a busy monitoring unit 74.

In this embodiment, the communication protocol used for communication between the sub-CPU 20 and the interconnect 44 is, for example, the AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) bus protocol. The AXI bus has independent address and data channels, and the data channel has separate read and write channels.

Figure 11 shows signals related to the read channel. In the read channel, there is a sequence constraint that the data handshake must be established after the address channel handshake. Therefore, the mask control unit 72 executes mask control using the control signal of the address channel.

Specifically, while the mask control signal MASKEN output from the main CPU 10 is negated, the mask control unit 72 outputs the address valid signal ARVALID0 output from the sub CPU 20 to the interconnect 44 as the address valid signal ARVALID. While the mask control signal MASKEN is asserted, the mask control unit 72 maintains the negated state of the address valid signal ARVALID regardless of the logic level of the address valid signal ARVALID0. In other words, the mask control unit 72 inhibits the transfer of the address valid signal ARVALID to the interconnect 44, thereby inhibiting the handshake of the address channel. The mask control unit 72 has the same functions as the mask control unit 52 in FIG. 1, except that the mask control unit 72 uses the address valid signals ARVALID0 and ARVALID instead of the valid signals VALID0 and VALID.

The busy monitoring unit 74 has a busy counter BCOUNT that is reset to "0" in the initial state. The busy monitoring unit 74 asserts or negates the busy signal BUSY based on the address valid signal ARVALID, the address ready signal ARREADY, the read ready signal RREADY, the read valid RVALID, and the read last signal RLAST.

Specifically, the busy monitoring unit 74 increments the busy counter BCOUNT by "1" in response to the establishment of a handshake by asserting the address valid signal ARVALID and the address ready signal ARREADY. The busy monitoring unit 74 decrements the busy counter BCOUNT by "1" in response to the assertion of the read valid signal RVALID, the read ready signal RREADY, and the read last signal RLAST. The busy monitoring unit 74 then asserts the busy signal BUSY when the busy counter BCOUNT is other than "0", and negates the busy signal BUSY when the busy counter BCOUNT is "0".

The assertion period of the busy signal BUSY indicates that the handshake has been established, but there is a transaction that has not yet been completed. Note that since the AXI bus protocol allows burst reads, in addition to the assertion of the read valid signal RVALID and the read ready signal RREADY, it is also necessary to monitor the assertion of the read last signal RLAST, which indicates the end of a burst read.

In this way, the busy monitoring unit 74 detects whether or not a transaction exists between the sub-CPU 20 and the interconnect 44 by comparing the number of successful handshakes in the address channel with the number of burst completions in the read channel. Here, the number of successful handshakes in the address channel is the number of times that the address valid signal ARVALID and the address ready signal ARREADY are asserted simultaneously. The number of burst completions in the read channel is the number of times that the read valid signal RVALID, the read ready signal RREADY, and the read last signal RLAST are asserted simultaneously.

Similar to the interconnect 42 in FIG. 6, the interconnect 44 has an outstanding transaction function that allows it to issue the next transfer request without waiting for the reception of data DATA. The other functions of the interconnect 44 are similar to those of the interconnect 40 in FIG. 1, except that it has the function of controlling communication for each address channel, read channel, and write channel.

Figure 12 is a timing diagram showing an example of the operation of the information processing device 104 of Figure 11. That is, Figure 12 shows an example of a control method for the information processing device 104. Detailed explanations of operations similar to those of Figures 2 and 7 will be omitted. In Figure 12, the mask control signal MASKEN is maintained in a negated state.

In FIG. 12, the sub-CPU 20 sequentially outputs address valid signals ARVALID0 for executing transactions A and B without waiting for the completion of data transfer (FIG. 12(a) and (b)). Because the mask control signal MASKEN is negated, the mask control unit 72 outputs address valid signals ARVALID to the interconnect 44 in response to each address valid signal ARVALID0 (FIG. 12(c) and (d)).

Based on receiving each address valid signal ARVALID, the interconnect 44 outputs an address ready signal ARREADY (A, B) to the sub-CPU 20 (Figures 12 (e) and (f)).

In response to the assertion of the first address valid signal ARVALID and the address ready signal ARREADY, the busy monitoring unit 74 increments the busy counter BCOUNT by "1" and asserts the busy signal BUSY (FIG. 12 (g) and (h)). In response to the assertion of the second address valid signal ARVALID and the address ready signal ARREADY, the busy monitoring unit 74 increments the busy monitoring unit BCOUNT by "1" and maintains the asserted state of the busy signal BUSY (FIG. 12 (i) and (j)).

The sub-CPU 20 asserts a read ready signal RREADY based on receiving the address ready signal ARREADY (FIG. 12(k)). Based on the assertion of the read ready signal RREADY, the interconnect 44 outputs a read valid RVALID to the sub-CPU 20 and starts data transfer A (FIG. 12(l)). The interconnect 44 outputs a read valid RVALID and a read last signal RLAST to the sub-CPU 20 along with the output of the final data of transaction A (FIGS. 12(m) and (n)).

In response to detecting the assertion of the read ready signal RREADY, the read valid RVALID, and the read last signal RLAST, the busy monitoring unit 74 decrements the busy counter BCOUNT by "1" (Figure 12 (o)). Because the busy counter BCOUNT is not "0", the busy monitoring unit 74 maintains the asserted state of the busy signal BUSY (Figure 12 (p)).

After this, data transfer B of transaction B is executed. The interconnect 44 outputs the read valid RVALID and the read last signal RLAST to the sub-CPU 20 along with the output of the final data of transaction B (FIG. 12 (q), (r)). In response to detecting the assertion of the read ready signal RREADY, the read valid RVALID, and the read last signal RLAST, the busy monitoring unit 74 decrements the busy counter BCOUNT by "1" (FIG. 12 (s)). Because the busy counter BCOUNT has become "0", the busy monitoring unit 74 negates the busy signal BUSY (FIG. 12 (t)).

In FIG. 12, for example, if the mask control signal MASKEN is asserted while the first address valid signal ARVALID0 is asserted, the second address valid signal ARVALID0 is not generated and only data transfer A is executed. In this case, the busy signal BUSY is negated based on the read last signal RLAST shown in FIG. 12(n).

As described above, the third embodiment can achieve the same effects as the first and second embodiments. Furthermore, in the third embodiment, even in a bus protocol in which the address channel, the read channel, and the write channel exist independently, it is possible to prevent the establishment of a handshake between the CPU 20 and the interconnect 44. Therefore, when the CPU 20 is reset by the reset signal RESET output by the CPU 10 after the mask control signal MASKEN is asserted, it is possible to prevent the execution of a transaction between the CPU 20 and the interconnect 44. As a result, it is possible to prevent the interconnect 44 from stalling due to the CPU 20 being reset during the execution of a transaction, and it is possible to prevent the occurrence of downtime due to restarting caused by the stall.

The present invention has been described above based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form.

10, 20 CPU
30 Memory 40, 42, 44 Interconnect 50, 60, 70 Interface control circuit 52, 62, 72 Mask control unit 64, 74 Busy monitoring unit 100, 102, 104 Information processing device ARREADY Address ready signal ARVALID, ARVALID0 Address valid signal BCOUNT Busy counter BUSY Busy signal CLK Clock DATA Data END Completion notification signal IMASK Mask signal MASKEN Mask control signal READY Ready signal RESET Reset signal RLAST Read last signal RREADY Read ready signal RVALID Read valid VALID, VALID0 Valid signal

Patent No. 5617429

Claims (7)

a first master and a slave for transferring data based on a handshake of a request and a response to the request;
a second master that outputs an inhibition request signal to inhibit the handshake;
an interconnect for controlling transfer of data between the first master and the slave;
an interface control circuit including a mask control unit that is provided between the first master and the interconnect and that inhibits transfer of the request issued by the first master to the interconnect while the inhibition request signal is being received, and outputs an inhibition-on-transfer signal indicating that the transfer of the request to the interconnect is being inhibited;
having
The second master outputs a reset signal to the first master based on receipt of the inhibited signal.
An information processing device comprising: a communication protocol used in communication between the first master and the interconnect includes an address channel used for communicating addresses, and a read channel and a write channel used for transferring data;
2. The information processing device according to claim 1, wherein the mask control unit inhibits the handshake of the address channel by inhibiting the transfer of an address valid signal, which is the request issued from the first master, to the interconnect while receiving the inhibition request signal. the interface control circuit further includes a busy monitor unit that outputs a busy signal while detecting a data transfer between the first master and the interconnect that is executed based on the request from the first master that was issued before receiving the inhibition request signal;
3. The information processing device according to claim 1, wherein the first master is capable of issuing a next request while data is being transferred between the first master and the interconnect based on the request. the interconnect outputs a completion notification signal to the first master upon completion of a data transfer corresponding to each of the responses;
The information processing device according to claim 3 , wherein the busy monitoring unit outputs the busy signal during a period in which the number of successful handshakes does not match the number of completion notification signals output. the second master is a main CPU that is turned off during a low power mode of the information processing device;
5. The information processing apparatus according to claim 1, wherein the first master is a sub-CPU that operates constantly during operation of the information processing apparatus and operates in place of the main CPU during the low power mode. an interconnect that controls data transfer between a first master and a slave based on a handshake between the first master and the slave consisting of a request and a response to the request; and a mask control unit that is provided between the first master and that inhibits the transfer of the request issued from the first master to the interconnect while receiving an inhibition request signal that inhibits the handshake output from a second master that outputs a reset signal to the first master based on reception of an inhibition signal, and outputs the inhibition signal indicating that the transfer of the request to the interconnect is being inhibited. A method for controlling an information processing device having a first master and a slave that transfer data based on a handshake between a request and a response to the request, an interconnect that controls data transfer between the first master and the slave, an interface control circuit provided between the first master and the interconnect, and a second master, comprising:
the second master outputs an inhibition request signal to inhibit the handshake;
a mask control unit of the interface control circuit inhibits transfer of the request issued by the first master to the interconnect while receiving the inhibition request signal, and outputs an inhibition-on-transfer signal indicating that transfer of the request to the interconnect is being inhibited;
the second master outputs a reset signal to the first master based on receipt of the inhibited signal.

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