JP2002108640A - Duplex system, single processor system and sub-board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restore a system at a state immediately before a failure is generated without lowering throughput as the system, for example, in a duplex system. SOLUTION: Control modules 15, 25 are connected with PC servers 1, 2 respectively and mutually connected by a local bus 4. Log information generated by the PC server 1 of an operating system is temporarily stored in the control module 15 and transferred to the control module 25 on the side of the PC server 2 of a standby system via the local bus 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplex system, a single processor system, and the like, which can restore a state immediately before a failure, particularly after a failure has occurred.
And sub-boards.

[0002]

2. Description of the Related Art In a database system, for example, it is very important to guarantee data. In general, in order to guarantee data, all operations on the database are logged. The information is stored in the memory and the HDD. In the unlikely event that a failure occurs in the system, it is common to recover the data based on the log information (update history of the database).

[0003] Log information is written to a memory and then written to the HDD at a certain timing. If a failure occurs in the system before writing to the HDD, the log information written to the memory between the previous writing to the HDD and the occurrence of the failure will be lost. Of the data access process will disappear. In order to reduce the amount of data that is lost, there is a method of shortening the timing (cycle) of writing to the HDD. However, increasing the write cycle to the HDD increases the load on the CPU, the system bus (internal bus), and the like. In a high-traffic system, the write time becomes a bottleneck. For this reason, there is a limit in increasing the write cycle.

[0004] As a method for solving this problem, it is conceivable to use a redundant system such as a dual system. The dual system is a system in which two identical database servers are prepared, both are always operated, and if a failure occurs on the master side, the processing is switched to the sub side to continue the processing. Therefore, synchronization control is required between the two servers, resulting in a complicated system. Also,
In some cases, a waiting state or the like occurs between the servers in order to synchronize the servers, and the performance may be degraded.

[0005] An object of the present invention is not to construct a complex system such as a dual system but to guarantee data up to immediately before a failure occurs in, for example, a database system. Provides a sub-board that can be built with a simple duplex system and can be switched to a standby system in a short time, or can be applied to a single-processor system, and provides a duplex system and a single-processor system using this sub-board. It is to be.

[0006]

A duplex system according to the present invention is a duplex system in which active and standby information processing devices are connected via a communication line, and an internal bus of the active information processing device. Connected to a local bus to temporarily store log information generated in the information processing device of the operating system, and to transfer the log information to the standby system via the local bus. A board, connected to the internal bus of the information processing apparatus in the standby system, connected to the local bus, and receives log information transferred from the sub-board in the active system via the local bus, and And a sub-board on the standby side that passes the error to the standby information processing apparatus.

In the duplex system having the above-described configuration, the log information is held and transferred to the standby side through a dedicated sub-board and a local bus. The log information can be kept. Therefore, after the occurrence of a failure, the latest log information can be used to recover from the failure just before the failure occurred.

Further, for example, the local bus has a power supply line from a standby system side to a sub board on an active system side,
Even if the internal bus of the active information processing unit stops or the power of the active system is shut down, the log information stored in the subboard of the active system is read out, and the failure is restored just before the failure occurred. can do.

Further, for example, the information processing apparatus is a database system constituting a duplex system, and the information processing apparatus in the standby system is asynchronous with the active system based on the log information received by the sub board. Update the standby database.

In the dual system, as described above, synchronous control is required between the two servers, and the system is complicated. However, in the present invention, in the duplex system, the standby system is asynchronous with the active system. Database can be updated. The update status of the database of the standby system follows the operation system slightly later than that of the active system.

According to the present invention, for example, in a single processor system, a sub-processor having a power supply backup memory connected to an internal bus of the single processor system and temporarily storing log information generated in the single processor system is provided. If a failure occurs, remove the memory with power backup or sub-board, connect to the single processor system from which the cause of the failure has been removed, and perform a failure based on the log information stored in the memory with power backup. It can be restored to the state immediately before the occurrence.

The present invention also includes the sub-board itself applied to the above-mentioned duplex system or single-processor system. The sub-board includes at least a memory with power backup, a CPU, and an interface connected to an internal bus of the information processing apparatus, and stores log information generated in the information processing apparatus in the memory with power backup via the interface. It is composed of

The sub-board is detachable from the information processing apparatus, and the memory with power backup is detachable from the sub-board.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a system configuration diagram of a duplex system which is an example of the present embodiment. An active PC server 1 and a standby PC server 2 are shown.
Are connected via LAN3.

The PC server 1 includes a CPU 11 and a memory 1
2, an HDD 13, a LAN controller 14, a control module 15 (sub board), and the like, which are connected by a system bus 16 (internal bus).

The same applies to the PC server 2, and the CPU 21
It comprises a memory 22, an HDD 23, a LAN controller 24, a control module 25 (sub-board), and the like, and these are connected by a system bus 26 (internal bus).

The control module 15 and the control module 25 are connected via the local bus 4. In this example, log information is transferred to the standby system via the local bus 4. Further, in some cases, power is supplied. Details will be described later.

The configurations of the PC servers 1 and 2 that are not directly related to the present invention are not particularly shown. In general, a personal computer-based server is called a “PC server” for a UNIX (registered trademark) server.
This is the case with personal computers equipped with Windows (registered trademark) -NT and Linux. However, the application range of the present invention is not limited to the one using such a general OS.
The system buses 16 and 26 are, for example, a PCI bus (PCI: Peripheral Component Interface), and the control modules 15 and 25 are, for example, a PC.
An I board (an extension board connected to a PCI bus).

FIG. 2 is a block diagram showing the configuration of the control module 15 on the operating system side. The control module 15 includes a microprocessor 31, a ROM 3
2, RAM 33, system bus interface 34, memory module 35, local bus interface 36
Consists of

The microprocessor 31 is a central processing unit for controlling the entire control module 15. The ROM 32 stores programs for implementing various processes / functions (described later) of the microprocessor 31.

The system bus interface 34 is a PC
1 and connected to the main body side (the configuration excluding the control module in FIG. 1 is referred to as the PC main body).
An interface for transmitting / receiving commands / data to / from the C1 body.

The memory module 35 includes an SRAM 35a
And a battery 35b for backing it up.
The memory module 35 includes the control module 15
It is detachable from the control module 15 while retaining the contents of the SRAM 35a. Of course, the control module 15 itself is also detachable from the PC 1 main body.

The local bus interface 36 is an interface for connecting to the local bus 4 and transferring log information to the standby system via the local bus 4. Further, a power supply line (not shown) is prepared for the local bus 4. As a result, the power supply of the operating PC 1 is turned off for some reason, and the control module 1 is turned off.
Even when the power is not supplied to the power supply 5 (for example, even when the system bus 16 (internal bus) is stopped), the power is supplied from the power supply on the control module 25 side of the standby system and the power supply becomes operable. At this time, the range of operation by power supply via the local bus 4 is shown by a dashed line in FIG. That is, the memory module 35 and the local bus interface 36 within the dashed line operate on the power supply of the control module 15 when the power supply of the control module 15 is ON, and are supplied from the standby system side via the local bus when the power supply of the control module 15 is OFF. Operates on electric power.

FIG. 3 is a block diagram showing the configuration of the control module 25 on the standby system side. The configuration of the control module 25 is the same as that of the control module 15. That is, the microprocessor 4
1, a ROM 42, a RAM 43, a system bus interface 44, a memory module 45, and a local bus interface 46. The memory module 45 has an SR
AM 45a and battery 45b to back it up
Consists of The difference from the control module 15 is its operation, which will be described later in detail.

Next, the operation of the active PC server 1 will be described. Generally, in order to restore a database (this may be constructed on the HDDs 13 and 23 or another storage unit (not shown) may be prepared) when a failure occurs, The contents of the operation performed for are saved as log information. Normally, log information is stored in the memory 12
It is stored on the HDD 13 and written to the HDD 13 at a certain cycle. As described above, it is desirable that this cycle be short, but there is a limit particularly in a system with high traffic.

On the other hand, in this example, the log information is stored in the memory 12 and also in the memory module 35 of the control module 15. It is desirable that the memory module 35 be formed of the SRAM 35a and the backup battery 35b as described above, rather than a nonvolatile memory such as a flash memory. This is because writing can be performed at higher speed, and log information can be stored without significantly affecting the processing time of the database. However, it does not mean that it is limited to this. For example, not only SRAM, but DR
AM or the like may be used. In any case, even if the log information in the memory 12 is lost due to a failure or the like, the log information stored in the memory module 35 is not lost, and the recovery is performed using the log information immediately before the failure occurred. Or any configuration that allows switching to the standby system.

The microprocessor 31 of the control module 15 transmits the log information stored in the memory module 35 to the local memory at a certain cycle (or arbitrarily or when the amount of data to be stored exceeds a predetermined threshold). The data is transferred to the memory module 45 of the standby control module 25 via the bus interface 36 and the local bus 4. The transfer of log information from the active system to the standby system may be performed frequently. This is because the load on the CPU 11 on the main body side does not increase.

When the microprocessor 41 confirms the writing to the memory module 45, it notifies the CPU 21. The CPU 21 reads log information from the memory module 25, writes the log information into the HDD 23, and updates its own database based on the log information. In this way, the standby database can follow the data update of the active database with a slight delay. As a result, switching to the standby system when a failure occurs in the active system can be performed in a short time.

The operation of the active PC server 1 will be described in more detail below. First, an operation of transferring log information generated on the PC server 1 side to the control module 15 will be described with reference to FIG.

As shown in FIG. 4, usually, a log information storage area is prepared on the memory 12, and when new log information is generated due to an operation performed on the database or the like,
This log information is stored in a free area in the log information storage area. Further, the newly generated log information is also stored in the SRAM 35a in the control module 15 via the device driver 17 for the control module.

In addition, in the writing cycle to the HDD, the memory 1
Log information stored in the log information storage area 2
A process for writing to the HDD is performed. This is a general write process, and no special process is performed. However, this will be described below with reference to FIG.

FIG. 5 is a diagram for explaining the writing process to the HDD. First, two log information storage areas in the memory 12 are prepared. For example, a log information storage area A and a log information storage area B shown in the drawing are prepared, threshold values are set, and
Write log information to either storage area,
If the threshold is exceeded, switch to the other and repeat. In the figure, the log information is written to the log information storage area A, and when the newly generated log information is written, the log information storage area A exceeds the threshold. The state of switching is shown.

Thereafter, the newly generated log information is stored in the log information storage area B, and the log information stored in the log information storage area A is transferred to the HDD 13 via the HDD device driver 18. Perform the process of writing to. When the writing process to the HDD 13 is completed, the log information storage area A is left empty to prepare for the next switching. The reason why two storage areas are provided and switched alternately in this way is that writing processing to the HDD generally takes a relatively long time.

Next, the process of storing the newly generated log information in the SRAM 35a in the control module 15 via the device driver 17 for the control module will be described in detail below with reference to specific examples. I do.

For example, the PC server 1 issues a log information write command to the control module 15 in which the storage address of the newly generated log information on the memory 12 and the number of bytes thereof are set. Upon receiving this command, the control module 15 reads information of the set number of bytes from the set address from the memory 12 and transfers it to its own memory module 35 (SRAM 35a).

More specifically, the control module 1
The system bus interface 34 of FIG. 5 has a register area 50 as shown in FIG. 6, for example. The register area 50 is used for exchanging commands / responses between the PC server 1 and the control module 15.

In the example shown in FIG. 6, the register area 50 is
It comprises a command register 51, an address setting register 52, a transfer byte number register 53, and a status register 54.

For example, the log information write command is temporarily stored in the command register 51, the storage address of the log information in the memory 12 is temporarily stored in the address setting register 52, and the number of bytes thereof is temporarily stored in the transfer byte number register 53. The microprocessor 31 reads out the command / data held in each register, recognizes the contents of the instruction, and executes a process according to the instruction.

Then, the microprocessor 31 stores status information indicating whether the command has been normally completed in the status register 54,
A response is returned to the C server 1 body.

The commands basically include a log information read command in addition to the log information write command. The log information read command includes a log information read command on the active side and a log information read command on the standby side.

When a log information read command on the operating side is transmitted, the control module 15
The log information stored in a log information storage area 60 described later in the RAM 35a is stored in the memory 1 of the PC server 1 main body.
Transfer to 2. At that time, information of a write pointer 61 described later is also transferred. This command is used in a single processor system as described later.

FIG. 7 shows an example of the log information storage area 60 in the SRAM 35a of the control module 15. The control module 15 stores the log information read from the memory 12 in response to the log information write command,
The log information is stored in the area specified by the write pointer 61 in the log information storage area 60. Then, the write pointer 61 is updated. The log information storage area 60 forms a ring buffer. When the update of the write pointer 61 completes, the write pointer 61 returns to the head position of the log information storage area 60.

The control module 15 then
Notifies the device driver of the end of the command.
That is, as described above, the status information indicating whether the command has been normally completed is stored in the status register 54.

The control module 15 transfers the log information to the control module 25 on the standby system side via the local bus 4. Although there is no particular limitation on the transfer cycle, even if the transfer cycle is shortened (frequent transfer is performed), the CPU 11 or the system bus 16
(Internal bus) does not increase the load.

Here, the size of the log information storage area 60 shown in the figure is not particularly limited, but is desirably at least as large as the above “log information storage area A + log information storage area B”. Good. Because, for example, as shown in FIG.
If a failure occurs during writing to the log 13 and the log information in the log information storage area A is lost, it is preferable that the log information in the log information storage area A has been completely transferred to the standby system. However, if not, or in a single processor system described later, the SRAM 35a
It is necessary that the log information of the log information storage area A be stored in the log information storage area 60 in the file. And the HD
During the writing to D13, the log information storage areas B and S
Since new log information is stored in the RAM 35a,
Considering a margin, it is desirable that the size be equal to or more than “log information storage area A + log information storage area B”. From this, the fact that the log information is transferred to the standby system does not mean that the log information is immediately deleted from the SRAM 35a.

The above is merely an example, and the present invention is not limited to this. Although the device driver is not shown in FIG. 2, it is not shown because the device driver does not have a special function. As described above, a general driver function is provided.

Next, the operation of the standby system will be described.
The command on the standby side is one, which is the log information read command on the standby side (different from the log information read command on the active side).

The CPU 21 of the PC server 2 on the standby system side
When the system starts up, the control module 25
In response to this, the log information read command on the standby side is transmitted. At that time, the memory 22 to which the log information should be transferred
Specify the above address and number of bytes. The address is the start address of the log information storage area of the memory 22 when the system starts up. Since the number of bytes is not known at this time, for example, an arbitrary larger number of bytes is specified. The system bus interface 44 of the standby-side control module 25 also has a register area substantially similar to the system bus interface 34, and the command, address, and number of bytes are stored in this register area.

The control module 25 stores the log information transferred from the operating system via the local bus 4 as described above into the memory module 45 (SRAM 45).
The write pointer is stored in the log information storage area in a) and the write pointer is updated. The log information storage area and the write pointer of the SRAM 45a have the same configuration as the SRAM 35a.

Then, the control module 25
The log information is transferred to the specified address in the memory 22 as a response to the log information read command on the standby side. At this time, by storing the number of bytes of the log information in the register area of the system bus interface 44 (corresponding to the transfer byte number register 53),
Since the C server 2 main body can know the number of bytes of the log information to be transferred, it calculates the address of the memory 22 where the log information is to be stored next, and, together with this address information, reads the next log information read command. Outgoing.

The memory 22 has two log information storage areas, similarly to the memory 12 on the active side, and when one exceeds a threshold, switches to the other and executes a write process to the HDD 23.

The standby system also updates its own database based on the log information sent from the operating system. Next, an operation when a failure occurs in the active PC server 1 will be described.

In this case, the latest log information stored in the memory module 35 is stored in the standby memory module 4.
5, the standby system can be updated to the latest database, so that the standby system can be switched to the active system and processing can be continued.

Considering the worst case, the latest log information cannot be transferred to the standby system and the operating system falls due to a system failure. The power may be turned off.
In any of these cases, the latest log information remains in the active memory module 35, and the standby system cannot update to the latest database.

In such a case, usually, the CPU 21 of the standby control module 25 can recognize that the operating system has gone down via the LAN 3 or the like, and notifies the microprocessor 41 of the control module 25 of the fact. I do. The microprocessor 41 reads the log information stored in the active memory module 35 via the local bus interface 46 and transfers it to its own memory module 45. At this time, even if the standby system is turned off, the memory module 3
5 and the local bus interface 36 are operable because power is supplied through the local bus 4.

As described above, with a configuration in which a dedicated control module is added to a relatively simple duplex system, if a failure occurs in a database system or the like, for example, immediately before the failure occurs, the throughput of the system is not reduced. Failure recovery can be performed using the latest log information, and switching to the standby system can be performed in a short time.

The scope of application of the present invention is not limited to the above-described multiprocessor system (duplex system), but can be applied to, for example, a configuration in which a database is constructed by a single processor system. In this case, an inexpensive system can be constructed.

When a failure occurs in the single processor system, the portion where the updated contents of the database are not reflected on the HDD in the past will naturally disappear. HD
If the write cycle to D is made earlier, the proportion of the portion that disappears decreases, but this does not mean that the possibility of the disappearance disappears. Further, shortening the writing cycle increases the load on the CPU due to the writing process to the HDD, and lowers the throughput of the system.

In this example, as described above, the sub-board (control module) itself is detachable from the system, or a memory module (memory with battery backup (SRAM) storing log information) from the sub-board. If a failure occurs in the system, remove the sub-board or memory module (the latest log information is stored in the memory) and prepare a system in which the cause of the failure has been removed. Then, the HDD is restored to the state before the start of log information acquisition. If it is possible to restore the log information before starting to collect it, it is possible to recover the database to a state almost immediately before the failure occurs based on the log information. The log information is read from the memory module of the sub board by transmitting a log information read command on the operating side.

As described above, even in a single processor system, by using the sub-board of this example, H
Even if the writing cycle to the DD is not particularly shortened (that is, without increasing the load on the CPU), there is no possibility that the log information disappears, or the ratio thereof can be made very small, and the occurrence of a failure can be prevented. The database can be recovered to a state almost immediately before.

[0061]

As described in detail above, according to the duplex system, the single processor system, and the sub-board of the present invention, log information is stored in the memory (with battery backup) of the sub-board. Since the active sub-board itself transfers the log information to the standby sub-board via the local bus of the board, the load on the active-system CPU for transferring the log information is eliminated. Need not be particularly short), using the latest log information without reducing system throughput,
It is possible to restore the standby database to a state immediately before the failure occurs.

The memory for storing log information in the sub board is provided with a battery backup so that the latest log information can be stored even if the log information cannot be transferred from the operating system or the power is turned off. Is stored in memory. By supplying power from the local bus, it is possible to read the latest log information from the standby sub-board via the local bus even in the above state,
It is possible to restore the standby database to a state immediately before the failure occurs.

The memory of the sub board can be removed while the battery backup is valid, so that even if the memory is applied to a single processor system instead of a duplex system, log information is stored in the event of a failure during operation. By removing the failed memory and returning to the system from which the cause of the failure has been removed, it is possible to restore the log information to the state immediately before the occurrence of the failure.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a duplex system.

FIG. 2 is a block diagram illustrating a configuration example of a control module on an operating system side.

FIG. 3 is a block diagram illustrating a configuration example of a control module on a standby system side;

FIG. 4 is a diagram for explaining a process of storing newly generated log information.

FIG. 5 is a diagram for explaining a writing process to an HDD.

FIG. 6 is a diagram illustrating an example of a register area of a system bus interface.

FIG. 7 shows an example of a log information storage area in the SRAM of the control module.

[Explanation of symbols]

 1 PC Server 2 PC Server 3 LAN 4 Local Bus 11 CPU 12 Memory 13 HDD 14 LAN Controller 15 Control Module 16 System Bus 21 CPU 22 Memory 23 HDD 24 LAN Controller 25 Control Module 26 System Bus 31 Microprocessor 32 ROM 33 RAM 34 System Bus interface 35 Memory module 35a SRAM 35b Battery 36 Local bus interface 41 Microprocessor 42 ROM 43 RAM 44 System bus interface 45 Memory module 45a SRAM 45b Battery 46 Local bus interface 50 Register area 51 Command register 52 Address setting register 53 Transfer byte number register 54 Stay Status register 60 Log information storage area 61 Write pointer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04L 12/40 H04L 11/00 320 5K032 29/14 13/00 311 5K035 (72) Inventor Taketo Sakamaki Chiba 3-5-3-1210 Takasu, Mihama-ku, Chiba-shi Inside Shinjo Institute of Management Co., Ltd. (72) Inventor Yasushi Karatsu 1-1-1, Tanabe Shinda, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Masatoshi Kinoshita 1-1-1, Tanabe-Shinda, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture F-term in Fuji Electric Co., Ltd. KC59 ME02 ME09 5K032 BA04 DA11 DB31 EB06 5K035 DD01 KK01 LL15

Claims (6)

[Claims] 1. A duplex system comprising an active information processing apparatus and a standby information processing apparatus connected via a communication line, wherein the duplex system is connected to an internal bus of the active information processing apparatus and to a local bus. A sub-board on the active side which temporarily stores log information generated in the active information processing apparatus and transfers the log information to the standby side via the local bus; A standby device connected to the bus and connected to the local bus, receiving log information transferred from the sub board on the operating system side via the local bus, and passing the log information to the information processing device in the standby system A duplex system comprising: a system-side sub-board; and recovering from a failure immediately before the failure occurs after the failure has occurred. 2. The local bus has a power supply line from a standby system side to a sub board on an active system side, and when an internal bus of an information processing device of the active system is stopped or the power supply of the active system is turned off. 2. The duplex system according to claim 1, wherein even in such a case, the log information stored in the sub-board on the operating system side is read, and the failure is recovered in a state immediately before the occurrence of the failure. 3. The information processing apparatus is a database system configuring a duplex system, and the standby information processing apparatus is configured to be in a standby state asynchronously with an active system based on log information received by the sub board. 2. The system according to claim 1, wherein the system database is updated.
Or the duplex system according to 2. 4. A single-processor system, comprising: a sub-board connected to an internal bus of the single-processor system and having a memory with a power supply backup for temporarily storing log information generated in the single-processor system; After removing the memory with power backup or the sub-board, connect to the single processor system from which the cause of the failure has been removed, and restore the state immediately before the failure based on the log information stored in the memory with power backup. A single processor system. 5. An information processing apparatus comprising: at least a memory with a power backup, a CPU, and an interface connected to an internal bus of the information processing apparatus, and storing log information generated in the information processing apparatus in the memory with the power backup via the interface. A sub-board characterized by the following. 6. The sub-board is detachable from the information processing apparatus, and the memory with power backup is detachable from the sub-board.
Sub board described.