JP7456501B2 - 情報処理回路および情報処理回路の設計方法 - Google Patents

情報処理回路および情報処理回路の設計方法 Download PDF

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JP7456501B2
JP7456501B2 JP2022527306A JP2022527306A JP7456501B2 JP 7456501 B2 JP7456501 B2 JP 7456501B2 JP 2022527306 A JP2022527306 A JP 2022527306A JP 2022527306 A JP2022527306 A JP 2022527306A JP 7456501 B2 JP7456501 B2 JP 7456501B2
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circuit
parameter
parameter value
value output
output circuit
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崇 竹中
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NEC Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]

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JP2022527306A 2020-05-26 2020-05-26 情報処理回路および情報処理回路の設計方法 Active JP7456501B2 (ja)

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JPWO2021240633A1 JPWO2021240633A1 (https=) 2021-12-02
JPWO2021240633A5 JPWO2021240633A5 (https=) 2023-01-30
JP7456501B2 true JP7456501B2 (ja) 2024-03-27

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TW (1) TWI841838B (https=)
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002117389A (ja) 1990-01-24 2002-04-19 Hitachi Ltd 情報処理装置
JP2018133016A (ja) 2017-02-17 2018-08-23 株式会社半導体エネルギー研究所 ニューラルネットワークシステム
US20190318232A1 (en) 2013-10-11 2019-10-17 Hrl Laboratories, Llc Scalable Integrated Circuit with Synaptic Electronics and CMOS integrated Memristors

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6864224B2 (ja) * 2017-01-27 2021-04-28 富士通株式会社 プロセッサ、情報処理装置及びプロセッサの動作方法
CN110036384B (zh) * 2017-09-29 2021-01-05 索尼公司 信息处理设备和信息处理方法
TWI659324B (zh) * 2018-02-14 2019-05-11 倍加科技股份有限公司 電路規劃結果產生方法與系統
US11586907B2 (en) * 2018-02-27 2023-02-21 Stmicroelectronics S.R.L. Arithmetic unit for deep learning acceleration
US11886980B2 (en) * 2019-08-23 2024-01-30 Nvidia Corporation Neural network accelerator using logarithmic-based arithmetic
WO2021084717A1 (ja) * 2019-10-31 2021-05-06 日本電気株式会社 情報処理回路および情報処理回路の設計方法
JP7364026B2 (ja) * 2020-02-14 2023-10-18 日本電気株式会社 情報処理回路
US20230376769A1 (en) * 2022-05-18 2023-11-23 Seyed Alireza GHAFFARI Method and system for training machine learning models using dynamic fixed-point data representations

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002117389A (ja) 1990-01-24 2002-04-19 Hitachi Ltd 情報処理装置
US20190318232A1 (en) 2013-10-11 2019-10-17 Hrl Laboratories, Llc Scalable Integrated Circuit with Synaptic Electronics and CMOS integrated Memristors
JP2018133016A (ja) 2017-02-17 2018-08-23 株式会社半導体エネルギー研究所 ニューラルネットワークシステム

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TWI841838B (zh) 2024-05-11
US20230205957A1 (en) 2023-06-29
JPWO2021240633A1 (https=) 2021-12-02
WO2021240633A1 (ja) 2021-12-02
TW202147162A (zh) 2021-12-16

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