JP7440014B2 - トポロジカル量子コンピューティングコンポーネント、システム、および方法 - Google Patents
トポロジカル量子コンピューティングコンポーネント、システム、および方法 Download PDFInfo
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- JP7440014B2 JP7440014B2 JP2022523120A JP2022523120A JP7440014B2 JP 7440014 B2 JP7440014 B2 JP 7440014B2 JP 2022523120 A JP2022523120 A JP 2022523120A JP 2022523120 A JP2022523120 A JP 2022523120A JP 7440014 B2 JP7440014 B2 JP 7440014B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
- G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66977—Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Description
本発明は、米国空軍によって授与された契約第FA9550-16-1-0328号および同第FA8649-19-PA-435号、ならびにNASAによって授与された契約第NNX16CJ30P号および同第80NSSC18C0003号に基づき、政府の支援を受けてなされた。政府は、本発明において一定の権利を有する。
本出願は、2019年10月21日に出願されたUS62/924,150に対する優先権を主張する。
本発明は、概して、量子ビットおよび量子コンピューティングシステムおよび方法に関する。より具体的には、本発明は、トポロジカル量子ビット(キュービット)、キュービットおよび計算システムを含む量子レジスタ、ならびにトポロジカルキュービットを含む方法に関する。
Claims (7)
- キュービットデバイスであって、
基材上に固定化されたナノ結晶と、
前記ナノ結晶の下面と接触しているか、またはそれと並置されたバック電極と、
前記ナノ結晶中の電子電流を測定するように構成された電子電流検知手段と、を含み、
前記ナノ結晶が、前記ナノ結晶と関連付けられた電子電流の重ね合わせ状態または基底状態を有し、
前記ナノ結晶が、電荷対対称性を含み、前記電子電流が、前記ナノ結晶の上面と下面とを分離する晶癖面内で、時計回りの、反時計回りの、またはその両方の方向に移動し、
前記電子電流が前記電子電流検知手段によって測定されるまで前記電子電流が未知であるように、前記ナノ結晶中の前記電流を、前記バック電極を使用して重ね合わせの状態にすることができ、
前記ナノ結晶中の前記電子電流の前記方向を、前記電子電流検知手段によって検知して、論理ゼロまたは論理1に対応するバイナリ出力を産生することができる、キュービットデバイス。 - 前記電子電流検知手段が、
前記ナノ結晶の上面上の第1の場所と接触しているか、またはそれと並置された第1の電極と、
前記ナノ結晶の上面上の第2の場所と接触しているか、またはそれと並置された第2の電極と、を含み、
前記第1および第2の電極が、前記電子電流の方向を検知するように構成されている、請求項1に記載のキュービットデバイス。 - 前記ナノ結晶が、遷移金属ジカルコゲニド(TMD)を含む、請求項1に記載のキュービットデバイス。
- 前記ナノ結晶の中央の外縁部に沿って形成された金属ドーパントナノ粒子をさらに含み、前記金属が、銅、銀、金、およびそれらの組み合わせからなる群から選択される、請求項3に記載のキュービットデバイス。
- 前記重ね合わせ状態が、-80℃~25℃の温度で前記基底状態から生成される、請求項1に記載のキュービットデバイス。
- 前記ナノ結晶と接触しているか、またはそれと並置されて、コントローラおよび/または検知素子との機能的接続を提供する、2つ以上の追加の電気リードをさらに含む、請求項1に記載のキュービットデバイス。
- 請求項1に記載の複数のキュービットデバイスを含む量子レジスタであって、前記キュービットデバイスが、前記キュービットの電荷量子間の結合を介して量子エンタングルし、前記キュービットデバイスが、直接物理的には接続されていない、量子レジスタ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962924150P | 2019-10-21 | 2019-10-21 | |
US62/924,150 | 2019-10-21 | ||
PCT/US2020/056725 WO2021158269A1 (en) | 2019-10-21 | 2020-10-21 | Topological quantum computing components, systems and methods |
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JP2022553014A JP2022553014A (ja) | 2022-12-21 |
JPWO2021158269A5 JPWO2021158269A5 (ja) | 2023-10-27 |
JP7440014B2 true JP7440014B2 (ja) | 2024-02-28 |
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US (2) | US11580437B2 (ja) |
EP (1) | EP4048629A4 (ja) |
JP (1) | JP7440014B2 (ja) |
KR (1) | KR20230009351A (ja) |
CN (1) | CN114788011A (ja) |
BR (1) | BR112022007368A2 (ja) |
WO (1) | WO2021158269A1 (ja) |
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WO2023224659A2 (en) * | 2021-12-08 | 2023-11-23 | Quoherent Inc. | Controllable topological qubit entanglement |
CN115862788B (zh) * | 2022-12-29 | 2023-08-29 | 中国科学院福建物质结构研究所 | 一种电子结构拓扑分析的方法 |
Citations (1)
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WO2011036214A1 (en) | 2009-09-23 | 2011-03-31 | Université Catholique de Louvain | A memory device and a method of manufacturing the memory device |
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US7749922B2 (en) * | 2005-05-05 | 2010-07-06 | The Board Of Trustees Of The University Of Illinois | Nanowire structures and electrical devices |
US9842921B2 (en) * | 2013-03-14 | 2017-12-12 | Wisconsin Alumni Research Foundation | Direct tunnel barrier control gates in a two-dimensional electronic system |
US10657456B1 (en) * | 2018-06-15 | 2020-05-19 | Brookhaven Science Associates, Llc | Quantum computing using chiral qubits |
AU2019304104B2 (en) * | 2018-07-20 | 2023-03-09 | Silicon Quantum Computing Pty Limited | A quantum processing system |
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WO2011036214A1 (en) | 2009-09-23 | 2011-03-31 | Université Catholique de Louvain | A memory device and a method of manufacturing the memory device |
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JP2022553014A (ja) | 2022-12-21 |
US20220269969A1 (en) | 2022-08-25 |
WO2021158269A1 (en) | 2021-08-12 |
KR20230009351A (ko) | 2023-01-17 |
EP4048629A4 (en) | 2023-11-29 |
US11880744B2 (en) | 2024-01-23 |
US11580437B2 (en) | 2023-02-14 |
US20230206107A1 (en) | 2023-06-29 |
CN114788011A (zh) | 2022-07-22 |
BR112022007368A2 (pt) | 2022-07-05 |
EP4048629A1 (en) | 2022-08-31 |
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