WO2024049496A2

WO2024049496A2 - Topological quantum computing systems and methods

Info

Publication number: WO2024049496A2
Application number: PCT/US2023/012011
Authority: WO
Inventors: Alton J. REICH; Roberto Di Salvo
Original assignee: Streamline Automation Llc
Priority date: 2022-01-31
Filing date: 2023-01-31
Publication date: 2024-03-07
Also published as: WO2024049496A3

Abstract

A topological quantum processor includes a topological quantum register comprising a plurality of entangled topological qubits on a silicon oxide layer of a silicon substrate. Measuring means determine the direction of spin current for each of the entangled topological qubits simultaneously. A digital processor provides interface with a digital computer and controls the operation of a power supply to place the entangled topological qubits into a state of superposition and to control the operation of the measuring means.

Description

TITLE OF THE INVENTION:

Topological Quantum Computing Systems and Methods

RELATED APPLICATIONS:

This application claims priority to US 63/305,146 filed January 31, 2022.

FIELD OF THE INVENTION:

The field of this invention relates topological quantum computing involving topological quantum bits, topological material qubits, arranged into arrays on substrates. The topological qubits may comprise pnictogen trichalcogenide, PTC, nanoplates that communicate with and are controlled by conventional computing hardware and software.

In quantum computing, quantum-mechanical phenomena such as superposition and entanglement are used to perform certain types of computations. Topological quantum computer circuits are based on topological material qubits, which function as the fundamental units of information storge, processing, or representation in a quantum computer. Any 2-state quantum object, including a topological material qubit, is capable of existing in a state of superposition composed of two basis states, 0 or 1. Multiple topological material qubits, or topological qubits, are functionally coupled to make a quantum register, which is a quantum computing analog of a classical processor register. Topological material quantum logic gates, or topological quantum gates, are basic quantum circuits comprising a small number of topological qubits that can be combined to make larger topological material quantum computing circuits. Topological material quantum logic gates enable logical operations to be performed using topological qubits to control the flow of information and processing of it within a topological quantum material computer, or topological quantum computer.

Topological qubits are functional at temperatures up to room temperature, e.g. about 300K, which may provide an enormous advantage over qubits based on quantum objects such as Cooper pairs, ions, and neutral atoms that function at cryogenic temperatures approaching absolute zero. The implementation of existing quantum computers is also limited by short coherence times, or the length of time a prepared quantum state can be maintained before it interacts with its environment to disturb the quantum state. This is, at least in part, because current quantum computing technology is based on manipulating small numbers of electrons, photons, or ions, which cannot be directly coupled to electric contacts. While topological material qubit technology provides for room temperature operation, the full development of operational topological material quantum processors requires architectures providing functional connections and/or communications between topological qubits and conventional processors so that the operation of topological quantum registers can be controlled and state information of the topological qubits can be converted to conventional data for processing.

BRIEF SUMMARY OF THE INVENTION:

Embodiments of the present invention preferably seek to mitigate, alleviate or eliminate one or more of the challenges, such as the above-identified, singly or in any combination by providing a quantum processor comprising components and functional connections between a plurality of topological qubits and a conventional processor so that the operation of topological qubits is controlled by the conventional processor and state information of the topological qubits is converted to conventional data for processing by a conventional processor.

BRIEF DESCRIPTION OF THE DRAWINGS:

Fig. 1 is a top view transmission electron micrograph of a bipyramidal pnictogen trichalcogenide, PTC nanoplatelet;

Fig. 2 is a top view of a pyramidal PTC nanoplatelet;

Fig. 3 is a top view of a pyramidal PTC nanoplatelet decorated with silver nanoparticles;

Fig. 4 is a side cross-sectional view of a topological qubit comprising a TQN on a silicon substrate;

Fig. 5 is a side cross-sectional view of a topological qubit comprising a TQN on a silicon substrate;

Fig. 6 is a top view of a topological qubit comprising a TQN on a silicon substrate;

Fig. 7 is an example of a current measurement result;

Fig. 8 is a top view of a topological qubit configured for capacitance measurement;

Fig. 9 is a top view of an alternate topological qubit configured for capacitance measurement;

Fig. 10 is a top view of an alternate topological qubit configuration for capacitance measurement;

Fig. 11 is an example of a capacitance measurement result;

Fig. 12 is a top view of an alternate topological qubit configuration for magnetic measurement;

Fig. 13 is a side view illustrating proximity entanglement between TQNs in a topological qubit register;

Fig. 14 is a side cross-section view illustrating top to top electrical entanglement;

Fig. 15 is a side cross-section view illustrating top to bottom electrical entanglement;

Fig. 16 is a side cross-section view illustrating bottom to bottom electrical entanglement; Fig. 17 is a top view illustration of a six topological qubit register of proximity entangled TQNs;

Fig. 18 is a top view illustration of a four topological qubit register of electrically entangled TQNs;

Fig. 19 is a top view illustration of a two topological qubit register of electrically entangled TQNs configured for capacitance measurement;

Fig. 20 is a top view illustration of one embodiment of a topological qubit register comprising six qubits and seven switches for selectively entangling topological qubits;

Fig. 21 is a top view illustration of one embodiment of a topological qubit register comprising eight qubits and fourteen electrical connections with switches for selectively entangling topological qubits;

Fig. 22 is a diagram showing functional connections for components of a quantum processor comprising 5 or more qubits;

Fig. 23 is a diagram showing functional connections for components of a quantum processor comprising a quantum co-processor comprising n qubits; and

Fig. 24 is a diagram showing functional connections for components of a quantum processor comprising an integrated quantum processor comprising n qubits.

DETAILED DESCRIPTION OF THE INVENTION:

Specific embodiments of the invention are described with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, like numbers refer to like elements.

All art specific terms are intended to have their art accepted meaning unless otherwise specified. All non-art specific words are intended to have their plain language meanings in the context with which they are used, unless otherwise specified.

As used herein, a nanoparticle is a particle having at least one dimension that is less than 1,000 nanometers, or 1 micrometer, in length. The terms "nanoplatelet" and "nanoplate" are used herein to refer to a nanoparticle having a diameter of from about 1 micrometer to about 20 micrometers and a height of less than about 200 nanometers.

As used herein, a "topological quantum nanoparticle" is a nanoparticle comprising a quantum material object having a topology that creates at least two degenerate charge parity protected quantum states and separates the occupation of the states by reducing tunneling/hopping transitions between the states. As used herein, a "topological quantum nanocrystal" is a crystalline nanoparticle having a topology that creates at least two degenerate charge parity protected quantum states and separates the occupation of the states by reducing tunneling/hopping transitions between the states. Examples of a "topological quantum nanocrystal" include chiral, self-assembled, bipyramidal pnictogen trichalcogenide, PTC, nanoplatelets and transition metal dichalcogenide, TMD, nanoplatelets comprising Sb₂Te₃, BisTea, or MoS₂, optionally decorated with nanoparticles of elements from Group IVA-VI 11 A and Group IB of the periodic table of elements and especially nickel, silver, gold, platinum, and/or copper. Examples of other topological insulators include Bi_xSbi._x, Bi₂Se₃, Bi₂Te₂Se, Bi₄Br₄, beta-Ag₂Te, GeBi₂Te₄, and WC. In the past, nanoplatelets comprising Sb₂Te₃ or Bi₂Te₃ may have been mistakenly described as transition metal dichalcogenides rather than pnictogen trichalcogenides.

Examples of non-crystalline topological quantum nanoparticles include topological insulators having washer, bipyramidal, biconic, or bispiral conic shapes that exhibit a chiral spin current flow.

As used herein, an "electrical connection" to a qubit may be a direct contact via a conducting lead or an indirect connection via a conducting lead positioned in close proximity to the qubit such that a functional electromagnetic connection is formed in which a current or a potential can be conducted between the qubit and the conducting lead. Examples of non-contacting connections include capacitive and inductive connections.

As used herein, a "magnetic connection" between qubits is a physical connection that carries spin-polarised electrons between the qubits. The spin polarization of the electrons may be maintained or reversed by the magnetic connection.

As used herein, "controlling a magnetic connection" means changing the strength of the magnetic connection between qubits connected by the magnetic connector or switching the magnetic connection on and off to allow or interrupt the magnetic connection between qubits.

As used herein, a "topological quantum computer" or a "topological quantum processor" is a device that utilizes one or more topological quantum nanoparticles that are configured to enable the superposition and measurement of quantum states of the topological quantum nanoparticles where the quantum states are prepared and measured.

Topological Quantum Nanoparticles:

Topological quantum nanoparticles, TQNs, (11) may have different three-dimensional shapes and topologies. One type of TQN (11) comprises a pnictogen trichalcogenide, PTC, having a bipyramidal shape. Fig. 1 is a top view electron micrograph of a chiral, self-assembled, topological Sb₂Te₃ PTC nanoplatelet (12) in which a triangular spiral structure is visible on the top face (13) of the PTC nanoplatelet (12). Edges (14) of the bottom face (15) are visible around the edges (15) of the top face (13).

Fig. 2 is a top view drawing of a PTC nanoplatelet (12) of the type shown in Fig. 1. The crystal lattice formed around a central axis forms sequential layers (22) (Fig. 1). The diameter (24), or maximum width of the nanoplatelet, is normally at least five times greater than the height of the nanoplatelet in the direction along the central axis of the spirals. Axially, at or near the center of the PTC nanoplatelet (12), a habit plane (26) (Fig. 4) separates the top and bottom halves of the PTC nanoplatelet (12). A persistent spin current runs along the spiral of the top face (13) of the top side above the habit plane (26) and along a central dislocation, the top of which (43) is labeled in Fig. 1. This spin current does not cross the habit plane (26) onto the bottom face (15) and a mirror spin current is present in the bottom half in the central dislocation and on the bottom face (15). One spin current direction dominates for any given measurement, so that any measurement of spin current along the outside edges (14) will give a clockwise or counterclockwise spin current following the spiral. The spin current can be enhanced by doping, or decorating, the habit plane edges (14) with metal nanoparticles (27) as shown in Fig. 3. Additionally or alternatively, the energy difference between bistable points may be adjusted with doping by filling the topological states with an abundance of one type of electron carrier or another to optimize decoherence times at different temperatures.

Topological Quantum Nanoparticle Qubit and Qubit Registers:

Fig. 4 is a side cross-sectional view of components of one embodiment of a TQN-based topological material qubit, or topological qubit, (49). The TQN (11), in this case a PTC nanoplatelet (12), is oriented on a silicon wafer substrate (40) having a surface electrically insulating layer (41) having a thickness of at least 3A to 7 A so that the habit plane (26) is mainly parallel the insulating layer (41). Examples of suitable electrical insulators include silicon dioxide, sapphire, and alumina. The TQN (11) may be, for example, an Sb2Tea or a Bi2Tes PTC nanoplatelet doped with copper or silver and having a diameter of from about 1 mm to about 20 mm and with a height of less than about 200 nm. The TQN (11) may be positioned above a back gate, or bottom gate, lead (42) electrically connected to a power source (P), which can be used to pulse the TQN (11) with an electrical potential of between 0.2 V and 1.0 V for a period of 0.1 msec to 1 msec as a means for placing the TQN (11) into a state of superposition in which the spin current direction around the edge (14) of the habit plane (26) may be considered to be both clockwise and counterclockwise. The power supply may be a precision variable voltage supply. The back gate lead (42) may physically contact the bottom face (15) of the TQN (11) or be close enough to transmit a potential or a current across a small gap or thin section of silicon dioxide between the lead (42) and the TQN (11).

Fig. 4 shows an embodiment in which the back gate lead (42) is not in direct contact with the bottom face (15) of the TQN (11). The back gate lead (42) may be positioned as shown or in direct contact with the bottom face (15) of the TQN (11). A first top lead (44) is in contact with, or in close proximity to, the top face (13) of the TQN (11) near the edge (14) of the habit plane (26). In this example, a second top lead (45) is in contact with, or in close proximity to, the top face (13) of the TQN (11) at a location that is on an opposite side of the top face (13) from the first top lead (44). The second top lead (45) need not be positioned on the opposite side of the top face (13) from the first top lead (44) and may be positioned at a distance from the first top lead (44) sufficient for a current or voltage to be detected between the two leads (44,45), such as at an angle of 120° with respect to the top end (23) of the TQN (11) (Fig. 6). The measured potential difference between the first and second leads (44,45) indicates the direction and magnitude of the spin current. One of the top leads (44,45) may also serve as a ground lead or an additional top lead (not shown) may be used as a ground lead when pulsing the TQN (11) with a potential from the back gate lead (42). The direction of the pulse may be reversed with the back gate lead (42) acting as a ground.

While positioning the back gate lead (42) in or on the substrate (40) is convenient for making the topological qubit (49), the back gate lead (42) is not strictly necessary. The TQN (11) may be pulsed by an additional top gate lead (not shown) in contact with or in close proximity to the top end of the TQN (11) or a lead in contact with or in close proximity to the top face (13) or bottom face (15) of the TQN with a lead with a lead on an opposite side of the TQN (11) acting as a ground.

Fig. 5 is a side cross-sectional view showing a layout of components of another embodiment of a TQN-based topological qubit (49). In this embodiment, the TQN (11) is oriented as in Fig. 4. The back gate lead (42) in this embodiment is shown as in physical contact with the bottom face (15) of the TQN (11) but the back gate lead (42) may alternatively be close enough to transmit a current and potential across a small gap or thin section of silicon dioxide between the lead and the TQN (11). A first top lead (44) is in contact with, or in close proximity to, the top face (13) of the TQN (11) near the edge (14) of the habit plane (26). In this example, a second top lead (45) is in contact with the top end (23), or in close proximity to, the top end (23) of the TQN (11). The measured potential difference between the first and second leads (44,45) indicates the direction and magnitude of the spin current. The state measuring means (46) may be based on voltage measuring means, current measuring means, capacitance measuring means, and magnetic field measuring means. One advantage of topological qubits (49) over other quantum computing technologies is a longer coherence time, or the length of time that a qubit can maintain a state of superposition. Coherence measurements of individual topological qubits (49) comprising PTC nanoplatelets (12) indicate that topological qubits have coherence time of from 10 ms to at least 10 s. These coherence times allow ample time for the quantum states of topological qubits (49) to be determined simultaneously after they have been placed into a quantum state of superposition.

Voltage Measuring Means for Qubit State:

Referring to Fig. 4, the first lead (44) and the second lead (45) are electrically connected to the TQN (11) on the same side of the habit plane (26), which may be the top face (13) as shown, but may alternatively be the bottom face (15). The first and second leads (44,45) are positioned such that they are separated on the nanoplatelet by at least a quarter of the diameter (24) of the TQN (11) and are connected to a means for measuring voltage. The measured potential difference between the first and second leads (44,45) indicates the direction and magnitude of the spin current. For PTC nanoplatelet topological qubits (49), the measured voltage is on the order of microvolts, which is readily measured using existing volt meters. The voltage measurement may be a direct measurement of the potential between the first and second leads (44,45). Alternatively, an alternating potential may be applied a to the leads and a change in phase of the applied potential may be used to detect the direction of current in the qubit (49). For the embodiment shown in Fig. 5, as with the embodiment shown in Fig. 4, the measured potential difference between the first and second leads (44,45) indicates the direction and magnitude of the spin current flowing on the TQN (11).

Current Measuring Means for Qubit State:

Referring to Fig. 4, the first lead (44) and the second lead (45) are electrically connected to the PTC nanoplatelet (12) on the same side of the habit plane (26), which may be the top face (13) as shown, but may alternatively be the bottom face (15), in which case the leads are bottom face leads. The first and second top face leads (44,45) are positioned such that they are separated on the nanoplatelet by at least half of the diameter (24) of the nanoplatelet (12) and are connected to a means for measuring current such as a complementary metal-oxide-semiconductor (CMOS). The current measured between the first and second top face leads (44,45) indicates the direction and magnitude of the spin current for the PTC nanoplatelet (12). The current may be measured directly or a very low input alternating current on the order of nano amps and millivolts may be delivered through the first top face lead (44) with the current coming from the second top face lead (45) measured. A change in slope for amperage vs. voltage is used to detect the direction of current in the topological qubit (49). Fig. 7 illustrates an amperage vs. voltage graph in which the current measurement is made across a top face (13) of the PCT nanoplatelet (12), for example as shown in Fig. 6. The direction of spin current, e.g. clockwise or counterclockwise, is distinguished by the differences between the two curves, one for spin current in the opposite direction of the delivered current (left) and one for spin current in the same direction as the delivered current.

The minimum current required to measure voltage depends on the sensitivity of the measuring device. The presence of silver nanoparticles or other nanoparticle dopants such as gold, platinum, copper, nickel and other Group IVA-VI II A and Group IB metals may be used to form metallic nanoparticles bonded to the edges of the habit plane of PTC nanoplates and establish a metal semiconductor junction that may be used to increase electron density as needed to provide reliable measurable voltages. For any given topological qubit design, one may make a Hall measurement to determine detectable levels of current using a picoammeter and adjust the presence or absence or type or amount of dopant as needed to achieve detectable levels of current.

Capacitance Measuring Means for Qubit State:

A first embodiment of a topological qubit (49) comprising capacitance state measuring means (46) is illustrated in Fig. 8. A first end (81) of a capacitor (80) is positioned on the substrate (40) or insulating layer (41) on one lateral side of the bottom face (15) of the PTC nanoplatelet (12). A second, opposite end (82) of the capacitor (80) is positioned on the substrate (40) or insulating layer (41) on the opposite side of the bottom face (15) of the PTC nanoplatelet (12). A time varying voltage is applied into the first end (81) of the capacitor (80) and a time varying voltage is measured out from the second end (82) of the capacitor (80). The electric field caused by the spin electron current of the topological qubit (49) will cause a phase shift between the applied and measured voltages with the magnitude of the phase shift indicating which direction the current is flowing in the PTC nanoplatelet (12). The first and second ends (81,82) of the capacitor (80) are preferably positioned off center with respect to the PTC nanoplatelet (12) as shown in Fig. 8 but they may alternatively be positioned centrally with respect to the PTC nanoplatelet (12) as shown in Fig. 9. For embodiments as shown in Figs. 8 and 9, the first and second ends (81,82) of the capacitor (80) may be positioned on opposite sides of the top face (13) of the PTC nanoplatelet (12) instead of the bottom face (15) of the PTC nanoplatelet (12).

An electrolyte (83) may be placed between the first and second ends (81,82) of the capacitor (80) and in contact with the PTC nanoplatelet (12) so that voltage and current may be measured at the second end (82) of the capacitor (80) (Fig. 12) with the phase shift of the current and/or voltage identifying the state of the PTC nanoplatelet (12).

Another capacitance measuring configuration for a qubit (49) is illustrated in Fig. 10. A first end (81) of a capacitor (80) is positioned on the substrate (40) or an insulator layer (41) on the substrate below the PTC nanoplatelet (12). An insulator (dielectric) layer is placed on the first end (81) of a capacitor, preferably before the PTC nanoplatelet (12) is placed on the substrate (40). An insulator layer is applied to the top side of the PTC nanoplatelet (12) above the first end (81) of a capacitor. A second end (82) of the capacitor (80) is positioned above the insulator on the top half of the PTC nanoplatelet (12). A time varying voltage is applied into the first end (81) of the capacitor and a time varying voltage is measured out from the second end (82) of the capacitor. The electric field of the qubit causes a phase shift between the applied and measured voltages with the magnitude of the phase shift indicating which direction the current is flowing in the PTC nanoplatelet (12).

Fig. 11 illustrates a capacitance measurement output that may be used to determine a state of a PTC -based qubit, depending on the direction of the applied time varying voltage ad the direction of the spin current. If the directions of the applied voltage and spin current are opposite one another, the phase shift will be to the left as for State 0. If the directions of the applied voltage and spin current are aligned with one another, the phase shift will be to the right as for State 1.

A SQUID measuring means for determining the state (46) of the PTC nanoplatelet (12) is illustrated in Fig. 12. The SQUID loop (121) is positioned in close proximity to the PTC nanoplatelet (12) to measure the magnetic field in and near the SQUID loop (121), which indicates the direction of current flow in the PTC nanoplatelet (12). A disadvantage of this means for determining the state (46) of the PTC nanoplatelet (12) is that cryogenic temperatures are required for the measurement, while the qubit is operational at room temperature. Cryogenic temperatures, however, may greatly extend the coherence times of the qubit for certain applications.

Entanglement of Qubits:

TQN-based qubits can be entangled by proximity, electrical connection, and selectable electrical connection. Fig. 13 illustrates one example of entangling two topological qubits (49) by proximity. A first PTC -based qubit (QB1) having a diameter (dl) may be entangled with a second qubit (QB2) having a dimeter (d2) with the first and second qubits being separated by a distance S. The distance S is small enough for the electric or magnetic fields associated with the spin currents to influence one another. For an average diameter (AD) of the first and second qubits (dl+d2)/2, S is preferably in a range of from 0.01AD to 1.0AD, or from 0.01 mm to 5.0 mm for AD ranging from 1 mm to 5 mm. The optimal spacing may vary depending on the composition and size of the topological qubits (49). Entangled topological qubits (49) oriented side by side in the same plane have opposite directions of spin current. Topological qubits (49) oriented top to bottom to be vertically entangled by proximity have the same directions of spin current.

TQN-based qubits can also be entangled by electrical connection using connecting leads (140) to electrically connect topological qubits (49) to one another. The interconnecting leads (140) are impedance matched. Figs. 14-16 are side cross-sectional views of two qubits connected by a lead (140) comprising an optional solid-state switch (99), such as a microtransistor, for selectively entangling or disentangling the two topological qubits (49). The qubits may be electrically connected top to top through a connecting lead (140), bottom to bottom through their back gate leads (42), or top to bottom or bottom to bottom through their back gate leads (42) and/or a connecting lead (140), optionally comprising a transistor or other solid state switch (99).

Connecting PTC nanoplatelet (12) topological qubits (49) top to top (Fig. 14) or bottom to bottom (Fig. 16) entangles them to have opposite directions of spin current and connecting qubits top to bottom (Fig. 15) or bottom to top entangles them to have the same directions of spin current. The connecting leads (140) are shown as being above the substrate (40) and insulating layer (41) but a connecting lead (140) may be on or in the substrate (40) or insulating layer (41) for a portion of all of its length. Back gate electrodes (42) may be connected by a conducting lead in, on, or under the substrate (40).

Solid state switches (99) may be incorporated into the connecting leads (140) to allow topological qubits (49) to be selectively entangled or disconnected. The connecting leads may extend to a location remote from the substrate (40), for example to a conventional computer or microprocessor for controlling the switches (99). It is also possible to arrange an array of qubits with some of the qubits entangled by proximity, some entangled by electrical connection, and some qubits entangled with a plurality of qubits by proximity and/or electrical connections. Solid state switches (99) suitable for use with electrical connecting leads (140), including micro transistors, are commercially available. Topological Quantum Nanoparticle Registers:

A topological qubit register (171) comprises at least two entangleable topological qubits (49) arranged on a substrate (40) with each topological qubit electrically connected to a bottom, or back gate (42), comprising an electrical conductor. Alternatively, the topological qubits may be electrically connected a top, or front, gate instead of a back gate (42). The back gate (42) may be configured as an discrete structure or it may be an exposed portion of a larger electrode that forms a plurality of back gates (42). Fig. 17 is a schematic top view of one embodiment of a TQN-based register (171) comprising an array of six topological qubits (49, QB-QB6) entangled by proximity. QB 1 is entangled with QB2 and QB4, QB2 is entangled with QB1, QB3, and QB5. QB3 is entangled with QB2 and QB6. QB4 is entangled with QB1 and QB5. QB5 is entangled with QB2, QB4, and QB6. QB 6 is entangled with QB3 and QB5. Since all of the qubits (49) are arranged side-by-side, their entanglement is such that each topological qubit (49) has an opposite direction of spin current from each neighboring qubit. Specific types of logic gates can be generated by the placement of qubits in different relative spatial positions (e.g. side to side and/or top to bottom) to provide any desired entanglement patterns.

Fig. 18 is a top view schematic of a TQN-based register (171) comprising a series array of four PTC -based topological qubits (49) electrically entangled top to bottom. The topological qubits (49) are electrically connected in series by conducting leads (140), which may run along the top of the substrate, inside the substrate, below the substrate, and/or combinations of these. In alternative embodiments, any number of topological qubits (49) may all be connected top to top or in any combination of top to top, top to bottom, and bottom to top. Additionally or alternatively, any one of the qubits may be electrically connected to and entangled with more than one of the other qubits. Any number or combination of conducting leads may comprise a solid state switch (99).

Fig. 19 is a top view schematic of a register (171) comprising two PTC -based topological qubits (49) and capacitance measuring means (46) to illustrate one example configuration for simultaneously determining the quantum current states of both topological qubits (49). The topological qubits (49) may be connected top to top or top to bottom. Additionally or alternatively, the two qubits may be electrically connected to separate back gate leads or a common back gate lead. Having the qubits electrically connected to a common back gate lead simplifies the process of pulsing both qubits at the same time to set them into superposition states. This applies to arrays of qubits as well as portions of arrays of qubits (49). More than two topological qubits (49) may share a common back gate or common front gate. Fig. 20 is a top view schematic of an array (172) comprising six topological qubits (49) entangled with seven selectively switchable connecting leads. Q.B1 can be selectively entangled with QB2 and/or QB4, QB2 can be selectively entangled with QB1, QB3, and/or QB5. QB3 can be selectively entangled with QB2 and/or QB6. QB4 can be selectively entangled with QB1 and/or QB5. QB5 can be selectively entangled with QB2, QB4, and/or QB6. QB6 can be selectively entangled with Q.B3 and/or QB5. The switch containing connecting leads (140) may be configured to connect any pair of qubits top to top or top to bottom to allow the configuration of different types of logic gates using the same array of topological qubits (49). Solid state switches (99) may be incorporated into any array of qubits to allow the gating to be reconfigured by opening or closing them to change connection patterns to form differently configured registers and/or gates.

Fig. 21 is top view schematic of an embodiment of an array of eight topological qubits (49) connected by fourteen connecting leads (140) comprising selectively switchable solid state switches (99). Arrays of topological qubits may have any number of spatial arrangements or configurations, including square, rectangular, triangular, and diamond arrays making it possible to create a wide variety and number of gates and registers using the same array (172). Using switchable more than one switchable connecting lead (140) between pairs of topological qubits (49), or a combination of a switchable connecting lead (140) and a switchable back gate electrode (42), it is possible to change the entanglement between pairs of topological qubits (49) between top to top, top to bottom, bottom to top, and/or bottom to bottom.

Topological Quantum Circuits:

A topological quantum circuit may be constructed by forming a sequence of topological quantum gates. One advantage of constructing an array (172) of topological qubits (49) connected by connecting leads (140) comprising selectively switchable solid state switches (99) is that the solid state switches may be used to generate different topological quantum circuits from the same array of static topological qubits.

Topological Quantum Nanoparticle Processor:

A TQN processor, or topological quantum processor (241) may comprise a digital processor (240) interfacing with at least one TQB-based register (171). The computing device provides sets of instructions executed by convention circuitry to communicate with, control, and receive information from the quantum register (171). The computing device (240) sets TQN-based topological qubits (49) to desired states, for example by setting a superposition state or a state with one direction of current flow or another by controlling a potential applied to the back gate electrodes (42). The computing device (240) communicates with means for measuring quantum states (46) of the topological qubits (49). The computing means may comprise means for measuring quantum states (46) that are electrically connected to contacts on the topological quantum register (171).

Advantages of TQN-based quantum registers (171) include their ability to operate at temperatures compatible with standard digital computers and that they can be manufactured using methods and materials compatible with those for making digital computers. This means that it is possible integrate one or more TQN-based quantum registers (171) into a conventional digital computer or processor (240) in which the one or more quantum registers (171) is incorporated into the circuitry of the digital computer or processor.

Operation of a topological quantum processor (241) may comprise the following operations: using the digital processor (240), addressing each topological qubit (49); using the digital processor (240), performing one or more functional tests to identify which topological qubits (49) are functioning properly and which are not; using the digital processor (240), receiving input data through a user interface or from a program to determine which interconnections are made between topological qubits by controlling solid state switches; using the digital processor (240), controlling solid state switches connecting topological qubits to form one or more topological quantum registers (171); using the digital processor (240), controlling solid state switches connecting topological qubits to form one or more topological quantum gates; using the digital processor (240), controlling solid state switches connecting topological qubits to form one or more topological quantum circuits; using the digital processor (240), providing a timing circuit for sequential and simultaneous actions including setting topological qubits into superposition (254) and measuring states of collections of entangled topological qubits; and using the topological quantum register(s), performing a quantum Fourier transform.

Some or all of the operations may be performed in a variety of sequences and many other operations are possible. Some of the operations are performed iteratively. For example, once the solid state switches have been set under the control of the digital processor or computer, the qubits may be repeatedly set to superposition and measured. Topological Quantum Processor Architecture:

Each topological qubit (49) in a topological quantum register (171) comprises a TQN (11) electrically connected to two leads used to place the qubit into a state of superposition. The state of each qubit is later determined using a measuring means (46) that may be based on measuring a current, a voltage, or a capacitance to determine the direction of the spin current. This may involve one or two additional leads electrically connected to the TQN (11). The process of pulsing a power supply P to set each qubit into a superposition state is controlled by a digital processor (240). For embodiments in which the measuring means (46) requires application of a voltage or current through a lead in electrical contact with the TQN (11), the process of applying a voltage or a current from the power supply P to the lead is controlled by a digital processor (240). The operation of measuring means is controlled by a digital processor (240) and analog signals from the measuring means (46) are digitized for processing by a digital processor (240). If the qubits (49) are entangled via controllable switches (99), the operation of the switches is controlled by a digital processor (240). The digital processor (240) may additionally provide an interface with a central processing unit, SPU, of a digital computer having a user interface and display. While it is possible for these processes to be controlled by different digital processors, it may be preferable for all of these processes to be controlled by a single digital processor (240).

Fig. 22 illustrates one embodiment of a topological quantum processor (241) comprising a topological quantum register (171), in electrical communication with a field programmable gate array, FPGA, (242). An analog to digital converter, ADC, (244) may be electrically connected directly to the measuring means (46) of the topological qubits or indirectly through the FPGA as shown. A power supply (P), a precision variable voltage supply, PWS, (246) in this example, may be connected directly to the back gates (42) of the topological qubits (49) or through the FPGA as shown. The power supply may additionally be connected directly to measuring means (46) that apply a voltage or current to a TQN (11) during measurements or through the FPGA (242) as shown. For example, the PWS (246) may be controlled to configure the generation of input wave forms. Application of a voltage or current through the measuring means (46) is also controlled by the FPGA (242). The FPGA receives digital data from the ADC (244) generated from analog data from the measuring means (46) and transmits the digital data to a digital processor (240) via wired or wireless transmission, which provides an interface with a digital computer. The FPGA may also transmit analog data from the measuring means (46) to the ADC (244) when the ADC (244) is connected to the measuring means (46) of the topological qubits (49) through the FPGA. All of the components are preferably positioned on a single circuit board but may be located on different circuit boards in any combination. The digital processor (240) may communicates with the ADC and said PVVS via said FPGA. In some embodiments, the silicon substrate (40) is secured in a chip carrier and wire bonding is used to connect electrically conductive traces in the silicon substrate (40) to the pins of a chip carrier. The chip carrier is placed on a circuit board and the pins are connected to conductive traces of the circuit board. An external circuit may be configured to produce input wave forms to the on-chip circuit and to measure the output of the on-chip circuit.

Fig. 23 illustrates another embodiment of a topological quantum processor (241) comprising a topological quantum register (171). In this embodiment, the ADC (244) and PVVS (246) are on the same silicon substrate (40) as the topological quantum register (171). In a preferred embodiment, the topological qubits are connected to the ADC (244) and PVVS (246) through conducting traces in the silicon substrate (40). The digital processor (240) is preferably positioned on the same circuit board as the silicon substrate (indicated by the dashed line) containing the topological quantum register (171), ADC (244), and PVVS (246). In this embodiment, the digital processor (240) comprises executable software casing the digital processor to control the PVVS (246), to receive digital data from the ADC (244), and to interface with a digital computer to transmit digital data to the computer and to receive instructions for controlling the operation of the topological quantum processor (241). In some embodiments, the silicon substrate (40) is secured in a chip carrier and wire bonding is used to connect electrically conductive traces in the silicon substrate (40) to the pins of a chip carrier. The chip carrier is placed on a circuit board and the pins are connected to conductive traces of the circuit board. An external circuit may be configured to produce input wave forms to the on-chip circuit and to measure the output of the on-chip circuit.

Fig. 24 illustrates an embodiment of a topological quantum processor (241) in which the components (171, 240, 244, 246) are integrated into a single silicon chip, as indicated by the dashed line. In this embodiment, the digital processor (240) is preferably configured to execute algorithms for controlling the setting and reading of quantum states, via the PVVS (246) and ADC (24).

The qubits (49) in any of the embodiments in Figs. 22-24 may be selectively entangled qubits and/or qubits that are statically entangled by their electrical connectivity or proximity, for example, in any combination. The digital processor (240) provides executes algorithms for controlling the PVVS (246) or other power supply (P) and for controlling the ADC (244). The digital computer is preferably remote to, but may be integrated with, the topological quantum processor (241).

Claims

CLAIMS:

1. A topological quantum processor (241) comprising: a topological quantum register (171) comprising a plurality of entangled topological qubits (49) positioned on a silicon oxide layer of a silicon substrate (40); measuring means (46) configured for determining a direction of spin current for each of said plurality of entangled topological qubits (49) simultaneously; a digital processor (240); a power supply (P); and an analog to digital converter, ADC (244), configured to receive analog signals from said topological quantum register (171) and convert said analog signals into digital data wherein said digital processor (240) comprises executable code configured to interface with a digital computer and to implement algorithms to control the operation of said power supply (P) to place said plurality of entangled topological qubits (49) into states of superposition and to control the operation of said measuring means (46).

2. The topological quantum processor of claim 1, further comprising a Field Programmable Gate Array, FPGA (242), controlled by said digital processor (240) and electrically connected to said plurality of entangled topological qubits (49) and measuring means (46) and wherein said digital processor (240) communicates with said ADC and said power supply via said FPGA.

3. The topological quantum processor of claim 2, wherein said FPGA is programmed to control a flow of data to and from said topological quantum register (171) and to control the application of voltage to said plurality of entangled topological qubits.

4. The topological quantum processor of claim 1, wherein said ADC and said power supply are positioned on said silicon substrate (40).

5. The topological quantum processor of claim 1 or claim 4, wherein said microprocessor is positioned on said silicon substrate (40).

6. The topological quantum processor of any of claims 1-5, wherein said plurality of topological qubits are connected via switchable connections for selectively entangling said plurality of topological qubits.

7. The topological quantum processor of claim 6, wherein said digital processor (240) isprogrammed to control said switchable connections.

8. The topological quantum processor of any of claims 1-5, wherein said plurality of topological qubits are entangled via static electrical connections.

9. The topological quantum processor of any of claims 1-5, wherein said plurality of topological qubits are entangled via positional proximity.

10. The topological quantum processor of any of claims 1-9, wherein said power supply ( P) is a precision variable voltage supply (246) and wherein said precision variable voltage supply (246) is controlled by said digital processor (240) to configure the generation of input wave forms.

11. The topological quantum processor of any of claims 1-10, wherein said plurality of topological qubits each comprise a bipyramidal pnictogen trichalcogenide, PTC, nanoplatelet.

12. The topological quantum processor of claim 11, wherein said bipyramidal pnictogen trichalcogenide, PTC, nanoplatelet is decorated with nickel, silver, gold, platinum, and/or copper nanoparticles.

13. The topological quantum processor of any of claims 1-12, wherein said measuring means (46) is a current measuring means.

14. The topological quantum processor of any of claims 1-12, wherein said measuring means (46) is a voltage measuring means.

15. The topological quantum processor of any of claims 1-12, wherein said measuring means (46) is a capacitance measuring means.