JP7439196B2 - semiconductor equipment - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device. One aspect of the present invention relates to a storage device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical fields of one embodiment of the present invention disclosed in this specification etc. include semiconductor devices, display devices, light emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices, input/output devices, and driving methods thereof. , or their manufacturing method.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Transistors, semiconductor circuits, arithmetic devices, storage devices, and the like are examples of semiconductor devices. Furthermore, imaging devices, electro-optical devices, power generation devices (including thin film solar cells, organic thin film solar cells, etc.), and electronic devices may include semiconductor devices.

2. Description of the Related Art In recent years, as the amount of data handled has increased, semiconductor devices with larger storage capacities have been required. In order to increase the storage capacity per unit area, it is effective to form memory cells by stacking them (see Patent Document 1 and Patent Document 2). By stacking the memory cells, the storage capacity per unit area can be increased in accordance with the number of stacked memory cells.

Further, Patent Document 3 discloses a nonvolatile memory device using an oxide semiconductor.

US Patent Publication No. 2011/0065270 US Patent No. 9634097 US Patent Publication No. 2016/0079268

In addition to a memory cell array for storing data, a memory device has a control circuit for controlling write and read operations. Generally, the drive voltage of the memory cell array is higher than that of the control circuit, so the drive circuit that drives the memory cell array based on the signal generated by the control circuit has
A high-voltage element is required. However, these high-voltage transistors and other elements are larger in size than the elements that make up the control circuit, so as the number of memory cells (that is, storage capacity) increases, the peripheral circuits including the drive circuit There was a problem in that the area occupied by the device also increased.

An object of one embodiment of the present invention is to reduce the area occupied by a peripheral circuit. Another object of the present invention is to provide a semiconductor device with a large storage capacity per unit area. or
One of our challenges is to provide semiconductor devices with high productivity. Or a new semiconductor device,
Alternatively, one of the challenges is to provide a storage device.

Note that the description of these issues does not preclude the existence of other issues. Note that one embodiment of the present invention does not need to solve all of these problems. Note that problems other than these can be extracted from descriptions such as the specification, drawings, and claims.

One embodiment of the present invention is a semiconductor device including a memory transistor and a transistor. The memory transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first semiconductor layer. The transistor has a fourth conductive layer, a fifth conductive layer, a fourth insulating layer, and a second semiconductor layer. The first conductive layer has an opening, the first insulating layer is provided in contact with the inside of the opening, the second insulating layer is provided in contact with the inside of the first insulating layer, and the third insulating layer is provided in contact with the inside of the first insulating layer. The layer is provided in contact with the inside of the second insulating layer, and the first semiconductor layer is provided in contact with the inside of the third insulating layer, and protrudes in the vertical direction from the opening of the first conductive layer. provided. Further, the second conductive layer is provided in contact with the bottom of the first semiconductor layer, and the third conductive layer is provided in contact with the top of the first semiconductor layer. The fourth conductive layer and the fifth conductive layer are provided in contact with the second semiconductor layer, respectively. The fourth insulating layer is provided in contact with the second semiconductor layer. The fifth conductive layer has a portion that overlaps with the second semiconductor layer via the fourth insulating layer. Furthermore, the first insulating layer, the third insulating layer, and the fourth insulating layer each contain an oxide. Furthermore, the second insulating layer contains nitride. Further, the first semiconductor layer and the second semiconductor layer contain the same metal oxide.

Moreover, in the above, it is preferable that the third conductive layer, the fourth conductive layer, and the fifth conductive layer contain the same metal element.

Moreover, in the above, it is preferable that the first semiconductor layer and the second semiconductor layer are formed by processing the same metal oxide film.

Moreover, in the above, it is preferable that the third conductive layer, the fourth conductive layer, and the fifth conductive layer are formed by processing the same conductive film.

Moreover, in the above, it is preferable that the first conductive layer and the fourth conductive layer are electrically connected.

Moreover, in the above, it is preferable to have a substrate. At this time, it is preferable that a plurality of memory transistors be provided on the substrate. Furthermore, it is preferable that the plurality of memory transistors be stacked in a vertical direction with respect to one surface of the substrate.

Further, in the above, the first semiconductor layer and the second semiconductor layer are the first semiconductor film and the second semiconductor layer.
It is preferable to have a laminated structure of semiconductor films. At this time, it is preferable that the first semiconductor film and the second semiconductor film have different crystallinity. Alternatively, the first semiconductor film and the second semiconductor film preferably have different compositions.

According to one aspect of the present invention, the area occupied by peripheral circuits can be reduced. Alternatively, a semiconductor device with a large storage capacity per unit area can be provided. Alternatively, a highly productive semiconductor device can be provided. Alternatively, a new semiconductor device or storage device can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily need to have all of these effects. Note that effects other than these can be extracted from descriptions such as the specification, drawings, and claims.

A top view and a cross-sectional view of a semiconductor device. FIG. 2 is a perspective view of a semiconductor device. FIG. 2 is a top view of a semiconductor device. A cross-sectional view of a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 3 is a diagram illustrating an example of a method for manufacturing a semiconductor device. A block diagram and a circuit diagram of a storage device. FIG. 3 is a diagram showing an example of a three-dimensional structure of a storage device. FIG. 3 is a diagram showing an example of a three-dimensional structure of a storage device. FIG. 3 is a diagram showing an example of a three-dimensional structure of a storage device. A circuit diagram of a storage device. FIG. 3 is a circuit diagram illustrating an example of the operation of a storage device. Example of storage device configuration. Block diagram of the AI system. Block diagram of the AI system. Example of IC configuration. Configuration example of electronic equipment. Configuration example of electronic equipment.

Embodiments will be described in detail using the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that the form and details thereof can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

In the configuration of the invention described below, the same parts or parts having similar functions are designated by the same reference numerals in different drawings, and repeated explanation thereof will be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

In each figure described in this specification, the size of each structure, layer thickness, or area is as follows.
May be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

Note that ordinal numbers such as "first" and "second" in this specification and the like are added to avoid confusion of constituent elements, and are not limited numerically.

A transistor is a type of semiconductor element, and can perform current and voltage amplification, switching operations that control conduction or non-conduction, and the like. The transistor in this specification is an IGFET (Insulated Gate Field Effect Transistor).
istor) and thin film transistor (TFT)
)including.

Furthermore, the functions of "source" and "drain" may be interchanged when transistors with different polarities are used, or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be used interchangeably.

Further, in this specification and the like, either the source or the drain of a transistor may be referred to as a "first electrode", and the other of the source or drain may also be referred to as a "second electrode". Note that the gate is also referred to as a "gate" or "gate electrode."

In this specification and the like, metal oxide refers to a metal oxide in a broad sense. Metal oxides include oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OS).
It is classified as such. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. That is, when it is described as an OS FET, it can be referred to as a transistor including a metal oxide or an oxide semiconductor.

(Embodiment 1)
In this embodiment, a structure example, a manufacturing method example, a circuit structure, and an operation method example of a semiconductor device of one embodiment of the present invention will be described.

One embodiment of the present invention has a structure in which a memory cell array and a circuit portion including a high-voltage transistor are provided over the same substrate. The memory cell array has a structure in which a plurality of memory transistors are stacked in the thickness direction (vertical direction). Therefore, it is possible to arrange a high voltage transistor near the memory cell array, and the area occupied by the semiconductor device can be reduced.

Here, the semiconductor layer included in the memory transistor and the semiconductor layer included in the high voltage transistor are formed by processing the same semiconductor film. This can also serve as the formation process for each semiconductor layer, so the manufacturing process can be simplified and the manufacturing cost of the semiconductor device can be reduced. Furthermore, it is preferable that the wiring connected to the memory cell array and the source electrode, drain electrode, gate electrode, etc. of the high voltage transistor be formed by processing the same conductive film.

In addition, in the semiconductor layers of the memory transistor and the high-voltage transistor,
It is preferable to use an oxide semiconductor. A transistor using an oxide semiconductor can have a higher source-drain breakdown voltage than a transistor using silicon, and therefore can be suitably used as a transistor forming a circuit portion. In addition, compared to silicon, transistors using oxide semiconductors have the characteristic that their drive performance does not deteriorate easily even when the gate insulating layer is thickened, so it is possible to improve the gate breakdown voltage. Reliability can be improved by using transistors in the circuit portion and the memory transistor.

Here, it is preferable to provide a circuit section including the memory cell array and high voltage transistors so as to be superimposed on a control circuit that controls the memory cell array. For example, this can be realized by forming the control circuit with a CMOS circuit formed on a single crystal silicon substrate, and forming a memory cell array and a circuit section on top of the CMOS circuit. As a result, the area occupied by the semiconductor device can be further reduced, so the number of chips per single crystal silicon substrate can be increased, and manufacturing costs can be reduced.

A more specific example will be described below with reference to the drawings.

[Configuration example]
Below, the configurations of the memory transistors of the semiconductor device 700, the memory cell array 700M, and the transistors included in the circuit portion 700D will be described with reference to the drawings.

[Memory cell array]
1(A) is a top view of the semiconductor device 700, and FIG. 1(B) is a top view of the semiconductor device 700.
It is a sectional view of a part shown by a dashed-dotted line of A2. In addition, FIG. 1(C) shows A3-A in FIG. 1(A).
FIG. 4 is a cross-sectional view of a portion indicated by a dashed line at No. 4, and is a cross-sectional view for explaining a memory string.

Further, FIG. 1(D) is an enlarged cross-sectional view or perspective view of a portion surrounded by a dashed line in FIG. 1(B), and is a diagram illustrating a memory transistor functioning as a memory cell. Note that, in the following description, an orthogonal coordinate system consisting of an x-axis, a y-axis, and a z-axis is set as shown in FIG. 1 for convenience. Here, the x-axis and the y-axis represent the substrate 7 on which the semiconductor device 700 is provided.
The z-axis is parallel to the top surface of the substrate 720, and the z-axis is perpendicular to the top surface of the substrate 720.

The semiconductor device 700 includes a memory cell array 700M and a circuit section 700D on a substrate 720.
and has. FIG. 1 shows a transistor 750 included in the circuit portion 700D.

The memory cell array 700M includes a plurality of conductive layers 701 (conductive layers 701_
1 to conductive layer 701_m: m is a natural number of 2 or more), conductive layer 702, plural insulating layers 703
(insulating layers 703_1 to 703_3), a plurality of oxide layers 704 (oxide layers 704_
1 to oxide layer 704_3), a plurality of conductive layers 705 (conductive layer 705_1 to conductive layer 705
_3), multiple conductive layers 706 (conductive layers 706_1 to 706_3), multiple connection layers 707 (connection layers 707_1 to connection layers 707_m), multiple conductive layers 708 (conductive layers 708
_1 to conductive layers 708_m), a plurality of insulating layers 722, an insulating layer 724, and the like.

The conductive layers 701 or 702 and the insulating layers 722 are alternately laminated to form a laminate including an insulating layer 724 provided to cover them. An insulating layer 703 is provided inside an opening formed to penetrate the stack. The oxide layer 704 is the insulating layer 70
It is provided inside 3. A conductive layer 705 is provided to be electrically connected to the upper end of the oxide layer 704. A conductive layer 706 is provided to be electrically connected to the lower end of the oxide layer 704. The connection layer 707 is electrically connected to the conductive layer 701. The conductive layer 708 is electrically connected to the connection layer 707.

Note that in FIG. 1B, the conductive layers 701 are shown in three or more stages to represent the plurality of conductive layers 701; however, this embodiment is not limited to FIG. layer 701
It is sufficient if it has two or more stages. Further, in FIG. 1B and the like, an insulating layer 703 and an oxide layer 704, and a conductive layer 706 and a conductive layer 7 are provided in a plurality of columnar openings arranged in the x direction.
Although three of these are shown to represent 05, etc., the number is not limited to this, and it is sufficient to have at least two or more.

Here, as shown in FIGS. 1A and 1B, the conductive layer 701 is provided extending in the x-axis direction. Further, as shown in FIGS. 1B and 1C, the insulating layer 703 and the oxide layer 704 are provided extending in the z-axis direction. The insulating layer 703 is a columnar oxide layer 704
It is set up so as to surround the side of the building. That is, it is preferable that the conductive layer 701, the insulating layer 703, and the oxide layer 704 are provided to intersect perpendicularly to each other. Also, Figure 1(B)
As shown in , the connection layer 707 is formed in a columnar shape and is provided extending in the z-axis direction.
Further, the conductive layer 708 may be provided extending in the y-axis direction. Further, a conductive layer functioning as a wiring BL connected to the conductive layer 705 may be provided extending in the y-axis direction. Note that the conductive layer 70
5 may function as the wiring BL, and the conductive layer may be provided extending in the y-axis direction.

The columnar oxide layer 704 is electrically connected to the conductive layer 706 at the lower end in the z-axis direction,
It is electrically connected to the conductive layer 705 at the upper end. Further, as shown in FIG. 1C, the conductive layer 706 is electrically connected to the lower ends of two adjacent columnar oxide layers 704, and the upper ends of the two columnar oxide layers 704 are connected to each other. It is electrically connected to an electrically isolated conductive layer 705.

Here, the vicinity of a region where the conductive layer 701 intersects with the insulating layer 703 and the oxide layer 704 functions as a memory transistor (memory transistor 710). In addition, the conductive layer 70
The selection transistor (
It functions as a bit line side selection transistor (SDT) or a source line side selection transistor (SST). The channel length directions of these memory transistors and selection transistors are parallel to the z-axis. Memory transistors or selection transistors are electrically connected in series and constitute a memory string.

Note that the structure of the semiconductor device shown in this embodiment is an example, and the present invention is not limited to the number and arrangement of circuit elements, wiring, etc. shown in the drawings etc. related to this embodiment. . The number and arrangement of circuit elements, wiring, etc. included in the semiconductor device according to this embodiment can be appropriately set according to the circuit configuration and driving method.

It is preferable that the substrate 720 on which the memory cell array 700M and the circuit section 700D are provided has an insulating surface. As the substrate having an insulating surface, a semiconductor substrate having an insulating film formed on its surface, an insulating substrate, a conductive substrate having an insulating film formed on its surface, etc. may be used. As the semiconductor substrate, for example, a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. Further, as the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), a resin substrate, etc. may be used. Further, a semiconductor substrate having an insulating region inside the semiconductor substrate described above, such as an SOI (Silicon On Insulator) substrate, may be used. Further, as the conductive substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. may be used.

The conductive layer 701 functions as a gate of the memory transistor 710 and is electrically connected to the word line. That is, the conductive layer 701, the connection layer 707, and the conductive layer 708 also function as part of the word line. Here, the conductive layer 701 is preferably provided in a stepped shape, with the lower conductive layer 701 extending toward the A2 side than the upper conductive layer 701, as shown in FIG. 1B. In this way, by providing the conductive layer 701, a part of the upper surface of the lower conductive layer 701 does not overlap with the upper conductive layer 701, so that the corresponding area of each layer of the conductive layer 701 and each connection layer 707 are separated. can be connected.

As the conductive layer 701, a conductive material such as silicon or metal can be used. When using silicon as the conductive layer 701, amorphous silicon or polysilicon can be used. Further, in order to impart conductivity to silicon, a p-type impurity or an n-type impurity may be added. Further, as a conductive material containing silicon, silicide containing titanium, cobalt, or nickel can be used for the conductive layer 701. Further, when a metal material is used for the conductive layer 701, aluminum, chromium, copper, silver, gold, platinum, tantalum,
A material containing one or more metal elements selected from nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used.

A conductive layer 702 is provided over the conductive layer 701 with an insulating layer 722 interposed therebetween. Conductive layer 702
functions as a gate of a selection transistor (a bit line side selection transistor: SDT and a source line side selection transistor: SST). Further, the same material as the conductive layer 701 can be used for the conductive layer 702. Further, the conductive layer 702 may be made of the same material as the conductive layer 701, or may be made of a different material. The conductive layer 701 and the conductive layer 702 may be determined depending on the purpose, taking into consideration the work function and the like.

As the insulating layer 722 provided above or below the conductive layer 701 and the conductive layer 702, an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide can be used. You can use objects, etc. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide, or silicon oxide or resin with vacancies have dielectric properties. It is suitable for use in the insulating layer 722 because of its low rate.

On the other hand, as the insulating layer 722, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium, oxynitride containing aluminum and hafnium, oxide containing silicon and hafnium, oxide containing silicon and hafnium It is also possible to use a nitride or a nitride containing silicon and hafnium, but since these have a high dielectric constant, a parasitic capacitance is generated between the two conductive layers 701 or between the conductive layer 701 and the conductive layer 702. may occur. Therefore, the material used for the insulating layer 722 can be determined depending on the design and application of the device.

Further, as the insulating layer 724 that covers the conductive layer 701, the conductive layer 702, and the like, the same material as the insulating layer 722 can be used.

The oxide layer 704, the insulating layer 703, and the conductive layer 701 (conductive layer 701_1 to conductive layer 7
01_m), the memory transistor 710 is configured. Figure 1(B),
(C) shows an example in which memory transistors 710 are stacked in m stages (m is a natural number of 2 or more).

The conductive layer 705 is electrically connected to the oxide layer 704 and connected to the source line SL or the bit line B.
It functions as part of L. It is preferable to use a conductive material containing a metal element as the conductive layer 705. Further, a metal compound layer containing a metal element of the conductive layer 705 and a component of the oxide layer 704 is preferably formed at the interface between the conductive layer 705 and the oxide layer 704. Formation of the metal compound is preferable because the contact resistance between the conductive layer 705 and the oxide layer 704 is reduced. Alternatively, the conductive layer 705 absorbs oxygen contained in the oxide layer 704 and reduces the resistance of the oxide layer 704 near the interface between the conductive layer 705 and the oxide layer 704. Contact resistance with the physical layer 704 can be reduced.

As the conductive layer 705, it is preferable to use a conductive material containing one or more metal elements selected from aluminum, ruthenium, titanium, tantalum, chromium, tungsten, and copper.

As shown in FIG. 1C, the conductive layer 706 includes an oxide layer 704 that is electrically connected to the conductive layer 705 that functions as part of the bit line BL, and a conductive layer that functions as part of the source line SL. By electrically connecting the oxide layer 704 to the oxide layer 705, a memory string is formed. An area surrounded by a dashed line in FIG. 1A represents one memory string. Although three memory strings are clearly shown in FIG. 1A, in reality, it is preferable that one memory cell array has an even number of memory strings;
It is more preferable that ⁿ (n is a natural number of 1 or more).

The same material as the conductive layer 705 can be used for the conductive layer 706. In addition, the conductive layer 70
6 may be made of the same material as the conductive layer 705 or may be made of a different material.

Further, at the interface between the conductive layer 706 and the oxide layer 704, a metal element included in the conductive layer 706 and
A metal compound layer containing the components of the oxide layer 704 is preferably formed. Formation of the metal compound is preferable because the contact resistance between the conductive layer 706 and the oxide layer 704 is reduced. Alternatively, the conductive layer 706 absorbs oxygen contained in the oxide layer 704 and reduces the resistance of the oxide layer 704 near the interface between the conductive layer 706 and the oxide layer 704. Contact resistance with the physical layer 704 can be reduced.

FIG. 1D shows an enlarged view of one memory transistor 710 and its vicinity.
As shown in FIG. 1D, the insulating layer 703 includes an insulating layer 703a, an insulating layer 703b, and an insulating layer 703c. The insulating layer 703a is provided on the conductive layer 701 side, and the insulating layer 703c is provided on the conductive layer 701 side.
is provided on the oxide layer 704 side, and the insulating layer 703b is provided on the insulating layer 703a and the insulating layer 703c.
provided between. The insulating layer 703a functions as a gate insulating layer, the insulating layer 703b functions as a charge storage layer, and the insulating layer 703c functions as a tunnel insulating layer.

Here, FIG. 2A shows a perspective view of one memory transistor 710 and its vicinity.

It is preferable to use silicon oxide or silicon oxynitride as the insulating layer 703a.
Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, these may be stacked to form the insulating layer 703a.

For the insulating layer 703b, a material that functions as a charge storage layer is preferably used, and silicon nitride or silicon nitride oxide is preferably used. Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used.

It is preferable to use silicon oxide or silicon oxynitride as the insulating layer 703c.
Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, these may be stacked to form the insulating layer 703c. Also,
The insulating layer 703c is preferably thinner than the insulating layer 703a. As will be described in detail later, when data is written to or erased from the memory transistor, charges are transferred between the oxide layer 704 and the insulating layer 702b through the insulating layer 703c. That is, the insulating layer 703
c functions as a tunnel insulating layer.

In particular, when forming the insulating layer 703 in an opening provided in a stacked body including a conductive layer 701, a conductive layer 702, and an insulating film, the insulating layer 703 formed at the bottom of the opening may be removed using dry etching or the like. It is necessary to remove it by directional etching. During anisotropic etching, the side surfaces of the insulating layer 703c are also exposed to plasma, radicals, gas, chemicals, and the like. When the side surfaces of the insulating layer 703c are damaged by these, trap centers are generated in the insulating layer 703c, which may affect the electrical characteristics of the transistor. In order to suppress the generation of trap centers, the side surfaces of the insulating layer 703c are required to have high resistance to damage caused by etching. In this case, it is preferable to use aluminum oxide, a stack of silicon oxide and aluminum oxide, or a stack of silicon oxynitride and aluminum oxide as the insulating layer 703c.

The insulating layer 703a, the insulating layer 703b, and the insulating layer 703c can be formed using an ALD method or a CVD method. In addition, the insulating layer 703a, the insulating layer 703b, and the insulating layer 70
In order to prevent contamination of the interface 3c, it is preferable to form the film continuously in the same chamber or using a multi-chamber type film forming apparatus having a plurality of chambers without being exposed to the atmosphere.

The oxide layer 704 is preferably formed using a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). An oxide semiconductor is preferable because it provides a transistor with better on-characteristics and higher mobility than a semiconductor made of silicon or the like.

For example, as the oxide layer 704, In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel,
one or more selected from germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium)
It is preferable to use metal oxides such as In addition, as the oxide layer 704, In-Ga oxide, In
-Zn oxide may also be used.

FIGS. 2B and 2C show an example in which the oxide layer 704 has a stacked structure.

As shown in FIG. 2B, the memory transistor 710 preferably includes an oxide layer 704a provided on the insulating layer 703c side and an oxide layer 704b provided inside the oxide layer 704a. At this time, it is preferable to use an oxide with a relatively wide energy gap as the oxide layer 704a with respect to the oxide layer 704b. Here, an oxide with a wide energy gap is sometimes called a wide gap, and an oxide with a narrow energy gap is sometimes called a narrow gap.

When the oxide layer 704a has a narrow gap and the oxide layer 704b has a wide gap, the energy at the bottom of the conduction band of the oxide layer 704a is preferably higher than the energy at the bottom of the conduction band of the oxide layer 704b. In other words, it is preferable that the electron affinity of the oxide layer 704a is smaller than the electron affinity of the oxide layer 704b.

Further, it is preferable that the oxide layer 704a and the oxide layer 704b have different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide layer 704a, the atomic ratio of the element M among the constituent elements is lower than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide layer 704b. , preferably larger. Further, in the metal oxide used for the oxide layer 704a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide layer 704b. Also,
In the metal oxide used for the oxide layer 704b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide layer 704a.

In the oxide layer 704a, for example, In:Ga:Zn=1:3:4, In:Ga:Zn=1
:3:2, or a metal oxide having a composition of In:Ga:Zn=1:1:1 or a composition in the vicinity thereof can be used. Further, the oxide layer 704b includes, for example, In:Ga:Zn
=4:2:3 to 4.1, In:Ga:Zn=1:1:1, or In:Ga:Zn=5
Metal oxides having a composition of :1:6 or a composition in the vicinity thereof can be used. It is preferable that the oxide layer 704a and the oxide layer 704b are combined so as to satisfy the above atomic ratio relationship. For example, the oxide layer 704a is made of a metal oxide having a composition of In:Ga:Zn=1:3:4 or a composition in the vicinity thereof, and the oxide layer 704b is made of a metal oxide having a composition of In:Ga:Zn=1:3:4.
Preferably, the metal oxide has a composition of 4:2:3 to 4.1 or a composition in the vicinity thereof. Note that the above composition indicates the atomic ratio in the oxide formed on the substrate or the atomic ratio in the sputtering target.

Further, as the oxide layer 704a, CAAC-OS, which will be described later, is used, and the oxide layer 704b is
It is preferable to use CAC-OS. As the oxide layer 704a, CAAC-O
When S is used, the c-axis is preferably oriented parallel to the xy plane shown in FIG.

Here, at the junction between the oxide layer 704a and the oxide layer 704b, the lower end of the conduction band changes gently. In other words, it can be said that the lower end of the conduction band at the junction between the oxide layer 704a and the oxide layer 704b changes continuously or is connected continuously. In order to do this, it is preferable to lower the defect level density of the mixed layer formed at the interface between the oxide layer 704a and the oxide layer 704b.

Specifically, when the oxide layer 704a and the oxide layer 704b have a common element other than oxygen (as a main component), a mixed layer with a low defect level density can be formed. For example, if the oxide layer 704b is made of In-Ga-Zn oxide, the oxide layer 704a is made of In-
It is preferable to use Ga--Zn oxide, Ga--Zn oxide, gallium oxide, or the like. This results in
The density of defect levels at the interface between the oxide layer 704a and the oxide layer 704b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the memory transistor 710 can obtain a high on-current.

As shown in FIG. 2B, the oxide layer 704b is provided so as to be surrounded by the oxide layer 704a. In such a structure, the conductive layers 705 to 70 are connected to the oxide layer 704.
6 or in the direction from the conductive layer 706 to the conductive layer 705 (ie, the z-axis direction), carriers mainly flow in the component having a narrow gap. Therefore, when the above configuration is used, a high current driving force, that is, a large on-state current, and a high field-effect mobility can be obtained in the on-state of the transistor.

Furthermore, by providing the oxide layer 704a between the oxide layer 704b and the insulating layer 703c, the oxide layer 704b, which serves as a carrier path, and the insulating layer 703c do not come into direct contact with each other.
Formation of trap centers can be suppressed. The trap center formed at the interface between the semiconductor (oxide semiconductor) and the insulating layer captures electrons and changes the threshold voltage of the transistor in a positive direction, which affects the reliability and on/off characteristics of the transistor. may have an adverse effect on. Therefore, a transistor using the oxide is not affected by the electrical characteristics of the trap center, and thus can obtain higher current driving force in the on state, that is, a large on-state current, and high field-effect mobility. In addition, the transistor,
A semiconductor device using the transistor can have high reliability.

In the memory transistor 710 illustrated in FIG. 2D, an oxide layer 704a is provided inside an insulating layer 703a, an insulating layer 703b, and an insulating layer 703c, and an oxide layer 704b is provided inside the oxide layer 704a. , an oxide layer 704c is provided inside the oxide layer 704b. Further, an insulating layer 711 may be provided so as to be embedded inside the oxide layer 704c. Note that the insulating layer 711 is not necessarily provided, and a cavity may be provided inside the oxide layer 704c.

The oxide layer 704b is provided so as to be sandwiched between the oxide layer 704a and the oxide layer 704c. At this time, the oxide layer 704c preferably has a wide gap similarly to the oxide layer 704a. By providing the oxide layer 704c with a wide gap, carriers flowing through the oxide layer 704 can be confined in the oxide layer 704b, resulting in a high current driving force in the on state of the transistor, that is, a large on-state current, and a high field effect. mobility can be obtained.

Further, in the case where the insulating layer 711 is provided inside the oxide layer 704c, the insulating layer 711 is preferably made of a material that can supply oxygen to the oxide layer 704. By using an oxide containing as little hydrogen or nitrogen as the insulating layer 711, oxygen can be supplied to the oxide layer 704 in some cases. By supplying oxygen to the oxide layer 704, impurities such as hydrogen and water contained in the oxide layer 704 can be removed, and the oxide layer 704 becomes highly purified. By using an oxide with minimal impurities as the oxide layer 704, a memory transistor and a semiconductor device using the transistor can have high reliability.

Further, as the insulating layer 711, a material that can supply impurities such as hydrogen and nitrogen can also be used. By using an oxide containing hydrogen or nitrogen for the insulating layer 711, hydrogen or nitrogen can be supplied to the oxide layer 704 in some cases. By supplying hydrogen or nitrogen to the oxide layer 704, the resistance value of the oxide layer 704 may be reduced. By lowering the resistance value of the oxide layer 704 to an extent that does not adversely affect circuit operation, the memory transistor can be operated with a lower driving voltage. Furthermore, it is possible to obtain a high current driving force, that is, a large on-state current, and a high field-effect mobility in the on-state of the memory transistor.

FIG. 2D shows a perspective view of a selection transistor (bit line side transistor: SDT, or source line side transistor: SST) and its vicinity.

As shown in FIG. 2D, the selection transistor does not need to be provided with a charge storage layer. Therefore, in the bit line side transistor: SDT and the source line side transistor: SST, a structure may be adopted in which the insulating layer 703b and the insulating layer 703c are not provided as the insulating layer 703, and only the insulating layer 703a is provided.

Note that although the oxide layer 704 is shown as a single layer in FIG. 2D, the oxide layer 704 is not limited to this.
The oxide layer 704 may have a two-layer structure or a three-layer structure, as exemplified above, or a stacked structure of four or more layers. Further, an insulating layer 711 may be provided inside the oxide layer 704.

Note that the opening formed in the stacked body in which the memory transistor 710 is provided is shown in FIG.
) and in each of the figures in FIG. 2, the upper surface is circular, but the upper surface is not limited to this. For example, the upper surface may be elliptical, or polygonal such as a triangle or a quadrangle. Moreover, when setting it as a polygonal shape, it is good also as a shape with rounded corners. Further, the top surface shape and cross-sectional shape of the insulating layer 703 and the oxide layer 704 may also change depending on the top surface shape and cross-sectional shape of the opening. Further, the opening may have a shape such that the cross-sectional area of the lower opening (on the conductive layer 706 side) is narrower than the cross-sectional area of the upper opening (on the conductive layer 705 side).

[Connection configuration example]
FIG. 3 is a top view illustrating a memory device 700A in which a plurality of memory cell arrays 700M each having six stages of memory transistors are combined. In addition, in FIG. 3, for ease of explanation,
Some components are omitted. For example, selection transistors (a bit line side transistor: SDT and a source line side transistor: SST) provided on the conductive layer 701 and the conductive layer 702 that are their constituent elements are omitted. In addition, bit line BL and source line SL
conductive layer 705 functioning as part of the word line WL, and conductive layer 7 functioning as part of the word line WL.
08 is shown by a solid line.

In the memory device 700A, each memory cell array 700M has four memory strings each having six stages of memory transistors.

The ends of the memory strings on the bit line side are connected to different bit lines BL (BL_1 to B
L_4). On the other hand, the end of the memory string on the source line side is connected to the source line S
It is electrically connected to L and is given a common potential. The source line SL may be grounded or may be given a constant potential. Further, the potential may be varied in accordance with the operation of the circuit.

The conductive layers 701_1 to 701_6 are electrically connected to different word lines WL, respectively. The conductive layers 701_1 to 701_6 on the bit line side are electrically connected to WLa_1 to WLa_6, respectively, and the conductive layers 701_1 to 701_6 on the source line side are electrically connected to WLb_1 to WLb_6, respectively.

Bit lines BL (BL_1 to BL_4) and word lines (WLa_1 to WLa_6)
, and WLb_1 to WLb_6), the memory cell array 700M
Any memory transistor within can be selected. Further, writing, reading, erasing, etc. can be performed on the selected memory transistor.

Furthermore, since each memory string is provided with a selection transistor (not shown), any memory cell array 700M in the storage device 700A is selected, and any memory transistor in the selected memory cell array 700M is selected. , writing, reading, erasing, etc.

[Circuit section]
The circuit portion 700D is provided with at least one transistor 750. 1A and 1B illustrate a transistor 750 as an example of the circuit portion 700D.
The transistor 750 is a transistor in which a metal oxide is applied to a semiconductor layer in which a channel is formed, and has extremely high breakdown voltage.

The transistor 750 includes an oxide layer 751, a conductive layer 752, a conductive layer 753a, and a conductive layer 75.
3b, and an insulating layer 754. Oxide layer 751 is provided on insulating layer 724. An insulating layer 754 is provided over the oxide layer 751, and a portion thereof functions as a gate insulating layer. A conductive layer 752 is provided over the insulating layer 754, and a portion of the conductive layer 752 functions as a gate electrode. The conductive layer 753a and the conductive layer 753b are provided in contact with the oxide layer 751, respectively, and function as a source electrode or a drain electrode.

Here, the oxide layer 751 is preferably formed by processing the same oxide film as the oxide layer 704 included in the memory transistor 710. Further, the conductive layer 753a and the conductive layer 753b are preferably formed by processing the same conductive film as the conductive layer 705 and the conductive layer 708 of the memory cell array 700M.

As a result, part of the manufacturing process of the transistor 750 can be used as the manufacturing process of the memory cell array 700M, so that the memory cell array 700M and the circuit section 700M can be manufactured at low cost.
D can be formed on the same substrate.

For the insulating layer 754, the same material as the insulating layer 703a can be used.

For the conductive layer 752, the same material as the conductive layer 701 and the like can be used.

Next, a connection example between the transistor 750 and the memory cell array 700M will be described.

FIG. 4A shows an enlarged view of the transistor 750. Furthermore, in FIG. 4(A),
A cross-sectional schematic diagram of one word line electrically connected to a transistor 750 and one memory string is shown.

In FIG. 4A, an insulating layer 761 having a plurality of openings is provided to cover the transistor 750. In addition, a plurality of connection layers (connection layer 762, connection layer 7
63, a connection layer 764a, a connection layer 764b, etc.) are provided. Further, on the insulating layer 761, there are a plurality of conductive layers (conductive layer 765, conductive layer 766a, conductive layer 766b) that function as wiring.
etc.) are provided.

The conductive layer 753b of the transistor 750 is electrically connected to the conductive layer 766b via the connection layer 764b. Further, the conductive layer 753a of the transistor 750 and the conductive layer 701 are the connection layer 707, the conductive layer 708, the connection layer 763, the conductive layer 766a, and the connection layer 764a.
electrically connected via. Further, the conductive layer 705 is electrically connected to the conductive layer 765 via the connection layer 762.

With such a structure, the transistor 750 and the conductive layer 7 functioning as a word line can be connected to each other.
01 can be electrically connected.

Here, the transistor 750 illustrated in FIG. 4A has an oxide layer 7 that functions as a semiconductor layer.
A conductive layer 753a and a conductive layer 753b are provided in contact with a part of the upper surface and the side surface of 51. Further, the insulating layer 754 and the conductive layer 752 are the conductive layer 753a and the conductive layer 753, respectively.
It has a part that overlaps with b. The structure of the transistor 750 shown in FIG. 4A is TGTC.
It can be said to be a (Top-Gate-Bottom-Contact) type transistor.

FIG. 4(B) shows an example of a cross-sectional configuration that partially differs from FIG. 4(A).

In the transistor 750 illustrated in FIG. 4B, the end of the oxide layer 751 and the end of the conductive layer 753a or the conductive layer 753b are aligned with each other. Further, an oxide layer 751 exists under the conductive layer 753a and the conductive layer 753b, and is formed so that the conductive layer 753a and the conductive layer 753b do not contact the insulating layer 724. With such a configuration, the conductive layer 7
Oxygen in the insulating layer 724 can be prevented from diffusing into the conductive layer 53a, the conductive layer 753b, etc.
A decrease in the amount of oxygen that can be supplied from the insulating layer 724 to the oxide layer 751 can be prevented, and a decrease in conductivity due to oxidation of the conductive layers 753a and 753b can be suppressed.

The structure shown in FIG. 4B includes, for example, an oxide film serving as an oxide layer 751 and a conductive layer 75.
3a and a conductive film that will become the conductive layer 753b, the laminated film is processed so as to leave a region that will become the oxide layer 751, and then a channel formation region on the oxide layer 751 is formed. It can be formed by removing a portion of the overlapping conductive film by etching.

Here, an oxide layer 751a containing the same oxide as the oxide layer 751 may be formed between the conductive layer 708 and the connection layer 707. The oxide layer 751a is the conductive layer 708 and the connection layer 7.
07, oxygen in the film is extracted by the heat applied during the process, hydrogen is supplied, etc., and the carrier density is sufficiently high, that is, the resistance is sufficiently low. It has become. Therefore, it can be said that the provision of the oxide layer 751a has almost no effect on the increase in electrical resistance.

The above is a description of the configuration example.

[Metal oxide]
In the following, metal oxides applicable to the oxide layer 704, the oxide layer 751, and the like illustrated in the above configuration example will be described.

Preferably, the metal oxide contains at least indium or zinc. In particular, it is preferable to include indium and zinc. In addition to these, aluminum, gallium,
It is preferable that yttrium or tin is included. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements that can be used as the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as element M,
A plurality of the above-mentioned elements can also be combined.

Note that in this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide (metal oxide).
ide). In addition, metal oxides containing nitrogen can be replaced with metal oxynitrides (me
tal oxynitride).

[Composition of metal oxide]
Below, CAC (C
The configuration of the loud-Aligned Composite)-OS will be explained.

In addition, in this specification etc., CAAC (c-axis aligned crystal
1), and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material configuration.

CAC-OS or CAC-metal oxide has a part of the material having a conductive function, a part of the material having an insulating function, and the entire material having a semiconductor function. Note that when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is to flow electrons (or holes) that serve as carriers, and the insulating function is to flow electrons (or holes) that serve as carriers. This function does not allow electrons to flow. Switching function (On/Off
function) can be added to CAC-OS or CAC-metal oxide. By separating the functions of CAC-OS or CAC-metal oxide, the functions of both can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in a material, a conductive region and an insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. Further, the conductive regions may be observed to be connected in a cloud-like manner with the periphery blurred.

In addition, in CAC-OS or CAC-metal oxide, a conductive region and
The insulating regions each have a thickness of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or more.
It may be dispersed in the material with a size of less than m.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal ox
ide is composed of a component having a wide gap caused by the insulating region and a component having a narrow gap caused by the conductive region. In the case of this configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. Furthermore, the component having a narrow gap acts complementary to the component having a wide gap, and carriers also flow into the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current, and high field effect mobility can be obtained in the on state of the transistor.

That is, CAC-OS or CAC-metal oxide is a matrix composite or a metal matrix composite.
It can also be called a matrix composite.

[Structure of metal oxide]
Oxide semiconductors (metal oxides) are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-
axis aligned crystalline oxide semiconductor
ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox
ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS
: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.

CAAC-OS has c-axis orientation and a plurality of nanocrystals connected in the a-b plane direction, resulting in a distorted crystal structure. Note that distortion refers to a location where the orientation of the lattice arrangement changes between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in a region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have irregular hexagonal shapes. In addition, the distortion may have a pentagonal or heptagonal lattice arrangement. Note that in CAAC-OS, it is difficult to confirm clear grain boundaries (also referred to as grain boundaries) even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, and the bond distance between atoms changes due to substitution of metal elements. It's for a reason.

In addition, CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an "In layer") and a layer containing element M, zinc, and oxygen (hereinafter referred to as a (M,Zn) layer) are laminated. They tend to have a structure (also called a layered structure). Note that indium and element M can be substituted with each other, and when element M of the (M, Zn) layer is substituted with indium, (In, M, Zn
) layer. Furthermore, when indium in the In layer is replaced with element M, (In,
M) It can also be expressed as a layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, in CAAC-OS, it is difficult to confirm clear grain boundaries, so it can be said that reduction in electron mobility due to grain boundaries is less likely to occur. In addition, since the crystallinity of metal oxides may deteriorate due to the incorporation of impurities or the formation of defects, CAAC- _OS
It can also be said to be a metal oxide with low acancy (also called acancy). Therefore, CAAC-
Metal oxides with OS have stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and have high reliability.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, in nc-OS, no regularity is observed in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductor.

The a-like OS is a metal oxide with a structure between that of an nc-OS and an amorphous oxide semiconductor. A-like OS has holes or low density areas. That is, a-li
ke OS has lower crystallinity compared to nc-OS and CAAC-OS.

Oxide semiconductors (metal oxides) have a variety of structures, each with different properties.
The oxide semiconductor of one embodiment of the present invention includes an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li
The computer may have two or more of ke OS, nc-OS, and CAAC-OS.

[Transistor with metal oxide]
Next, a case where the above metal oxide is used in a channel formation region of a transistor will be described.

Note that by using the above metal oxide in a channel formation region of a transistor, a transistor with high field-effect mobility can be realized. Further, a highly reliable transistor can be realized.

Further, it is preferable to use a metal oxide with low carrier density for the transistor. In order to lower the carrier density of the metal oxide film, the impurity concentration in the metal oxide film may be lowered to lower the defect level density. In this specification and the like, the term "high purity intrinsic" or "substantially high purity intrinsic" means that the impurity concentration is low and the defect level density is low. For example, the metal oxide has a carrier density of less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and 1×10 ⁻⁹ /cm 3 . cm ³ or more.

Further, since a metal oxide film that is highly pure or substantially pure has a low defect level density, the trap level density may also be low.

Furthermore, charges captured in the trap levels of metal oxides take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor including a metal oxide with a high trap level density in a channel formation region may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the metal oxide. In addition, in order to reduce the impurity concentration in metal oxides,
Preferably, the impurity concentration in adjacent films is also reduced. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

〔impurities〕
Here, the influence of each impurity in the metal oxide will be explained.

When a metal oxide contains silicon or carbon, which is one of the Group 14 elements, a defect level is formed in the metal oxide. For this reason, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon near the interface with the metal oxide (secondary ion mass spectrometry (SIM)
S: Secondary Ion Mass Spectrometry) of 2×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁷ atoms
/ ^cm3 or less.

Further, when the metal oxide contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in a channel formation region tends to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

Further, when nitrogen is contained in a metal oxide, electrons as carriers are generated, the carrier density increases, and the metal oxide tends to become n-type. As a result, a transistor in which a metal oxide containing nitrogen is used in a channel formation region tends to have normally-on characteristics. Therefore, in the metal oxide, it is preferable that nitrogen in the channel forming region be reduced as much as possible.
For example, the nitrogen concentration in a metal oxide is 5×10 ¹⁹ atoms/cm in SIMS.
less than ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸
atoms/cm ³ or less, more preferably 5×10 ¹⁷ atoms/cm ³ or less.

Furthermore, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using a metal oxide containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the metal oxide be reduced as much as possible. Specifically, in metal oxides, the hydrogen concentration obtained by SIMS is lower than 1×10 ²⁰ atoms/cm ³ , preferably 1×10 ¹⁹
atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , even more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using a metal oxide with sufficiently reduced impurities in a channel formation region of a transistor, off-state current of the transistor can be reduced and stable electrical characteristics can be provided.

[Example of manufacturing method]
Below, an example of a method for manufacturing the semiconductor device 700 illustrated in FIG. 1 will be described with reference to FIGS.
This will be explained with reference to 7. In addition, in each figure of FIG. 5 to FIG. 17, (A) is a top view seen from the z-axis direction, and (B) is a cross-sectional view of the part indicated by the dashed line A1-A2 in (A), (
C) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in (A).

First, a conductive layer 706 is formed on a substrate 720 having an insulating surface, and an insulating film 721 is formed to cover the conductive layer 706 (see FIG. 5).

The conductive layer 706 can be formed by first forming a conductive film to become the conductive layer 706 and processing it using a lithography method. However, the conductive layer 706 and the insulating film 7
The method of forming 21 is not limited to this. An insulating film 721 is formed on a substrate 720, and the insulating film 721
A groove or an opening may be formed by removing unnecessary portions of the conductive layer 706, and the conductive layer 706 may be embedded in the groove or the opening. This method of forming a conductive layer is sometimes called a damascene method (single damascene method, dual damascene method). Conductive layer 706 formed by damascene method
, and by further forming an insulating film over the insulating film 721, the structure shown in FIG. 5 can be obtained.

The conductive layer 706 and the insulating film 721 are formed by sputtering or chemical vapor deposition (CVD).
chemical vapor deposition) method, molecular beam epitaxy (MB
E: Molecular Beam Epitaxy) method, pulsed laser deposition (PLD:
Pulsed Laser Deposition) method or ALD (Atomic L
This can be done using the ayer deposition method or the like.

Note that the CVD method is plasma CVD (PECVD) that uses plasma.
Enhanced CVD) method, Thermal CVD (TCVD: Thermal C
It can be classified into the photo CVD method, which uses light, and the photo CVD method, which uses light. Furthermore, depending on the raw material gas used, metal CVD (MCVD) method, organometallic CVD method, etc.
(MOCVD: Metal Organic CVD) method.

The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method that can reduce plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.

Further, the ALD method is also a film forming method that can reduce plasma damage to the object to be processed. Furthermore, since plasma damage does not occur during film formation in the ALD method, a film with fewer defects can be obtained.

The CVD method and the ALD method are film-forming methods in which a film is formed by a reaction on the surface of an object, unlike film-forming methods in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed by changing the flow rate ratio of source gases. Further, for example, in the CVD method and the ALD method, by changing the flow rate ratio of the raw material gas while forming the film, it is possible to form a film in which the composition changes continuously. When forming a film while changing the flow rate ratio of source gases, compared to forming a film using multiple film forming chambers, the time required for film forming can be reduced by the amount of time required for transportation and pressure adjustment. In some cases, it is possible to improve the productivity of semiconductor devices.

Note that in the lithography method, the resist is first exposed to light through a photomask. Next, a resist mask is formed by removing or leaving the exposed area using a developer.
Next, by performing an etching process through the resist mask, a conductive film, a semiconductor film, an insulating film, or the like can be processed into a desired shape. For example, KrF excimer laser light, Ar
A resist mask may be formed by exposing a resist to light using F excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when using an electron beam or an ion beam, a mask is not required. Note that the resist mask can be removed by performing a dry etching process such as ashing, by performing a wet etching process, by performing a wet etching process after a dry etching process, or by performing a dry etching process after a wet etching process.

Further, a hard mask made of an insulating film or a conductive film may be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, a resist mask is formed on top of that, and the hard mask material is etched to form a hard mask in the desired shape. be able to.

A dry etching method or a wet etching method can be used for this processing. Processing by dry etching is suitable for microfabrication.

As a dry etching device, a capacitively coupled plasma (CCP) with parallel plate electrodes is used.
:Capacitively Coupled Plasma) etching apparatus can be used. A capacitively coupled plasma etching apparatus having parallel plate type electrodes may have a configuration in which a high frequency power source is applied to one electrode of the parallel plate type electrodes. Alternatively, a configuration may be adopted in which a plurality of different high frequency power sources are applied to one electrode of a parallel plate type electrode. Alternatively, a configuration may be adopted in which a high frequency power source having the same frequency is applied to each of the parallel plate type electrodes. Alternatively, a configuration may be adopted in which high frequency power sources having different frequencies are applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source is, for example, an inductively coupled plasma (ICP).
A plasma etching device or the like can be used.

When a hard mask is used for etching the conductive film, the etching process may be performed after removing the resist mask used to form the hard mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the conductive film. on the other hand,
If the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask.

The conductive film to be the conductive layer 706 is preferably formed by using a sputtering method to form a conductive film containing a metal element. Alternatively, it can also be formed using a CVD method.

The surface of the insulating film 721 is preferably subjected to planarization treatment, if necessary. A chemical mechanical polishing (CMP) method or a reflow method can be used for the planarization process.

Subsequently, conductive films 701A and insulating films 722A are alternately stacked on the insulating film 721.
Although this embodiment shows an example in which the conductive film 701A is formed over the insulating film 721 and the insulating film 722A is formed over the conductive film 701A, the order of formation is not limited to this. An insulating film 722A may be formed over the insulating film 721, and a conductive film 701A may be formed over the insulating film 722A. A CVD method can be used to form the conductive film 701A and the insulating film 722A. Also,
A sputtering method may also be used.

Further, in this embodiment, the number of laminated conductive films 701A and insulating films 722A is not limited. Two or more layers can be formed depending on the required performance of the semiconductor device. For example, the conductive film 701A and the insulating film 722A may each have 16 layers, 32 layers, 64 layers, or 128 layers, or may have 200 or more layers.

Subsequently, a conductive film 702A is formed on the uppermost insulating film 722A. after that,
A mask 723 is formed on the conductive film 702A (see FIG. 6). The conductive film 702A can be formed using the same method and the same material as the conductive film 701A. Note that the conductive film 702A may be formed by the same method as the conductive film 701A, or may be formed by a different method. Further, the conductive film 702A may be made of the same material as the conductive film 701A, or may be made of a different material.

Next, the conductive film 702A, the conductive film 701A, and the insulating film 722A are processed, and as shown in FIG.
A step-shaped conductive film 701B, a conductive film 702B, and an insulating film 722B are formed as shown in FIG. In processing the conductive film 702A, the conductive film 701A, and the insulating film 722A, the conductive film 7
02A, the conductive film 701A, and the insulating film 722A, and the slimming of the mask 723 are performed alternately, thereby forming the step-shaped conductive film 701B, the conductive film 702B, and the insulating film 72.
2B can be formed. Conductive film 702A, conductive film 701A, and insulating film 722A
By this processing, the mask 723 is reduced in both width and thickness, becoming a mask 723A (see FIG. 7).

Next, the mask 723A is removed and an insulating layer 724 is formed. The insulating layer 724 can be formed using a CVD method. The insulating layer 724 is preferably planarized using a CMP method or a reflow method. Subsequently, a mask 725 is formed on the insulating layer 724 (see FIG. 8). It is preferable to form the mask 725 over the planarized insulating layer 724 because the accuracy of lithography improves.

Next, the insulating layer 724, the conductive film 702B, the conductive film 701B, the insulating film 722B, and the insulating film 721 are processed using the mask 725 (see FIG. 9). Through this processing, a conductive layer 701 that functions as a gate of a memory transistor and is electrically connected to a word line, and a conductive layer 702 that functions as a gate of a selection transistor are formed. Furthermore, the insulating film 722B becomes an insulating layer 722 through this processing.

Thereafter, mask 725 is removed. Next, an insulating layer 726 is formed to bury the portion removed by the above processing. The insulating layer 726 can be formed using a CVD method or an ALD method. In particular, it is preferable to use the ALD method because it is possible to form a film with a uniform thickness even in grooves and openings with a large aspect ratio. Or ALD method and CV
The insulating layer 726 may be formed by combining method D. The insulating layer 726 is preferably planarized using a CMP method or a reflow method. When planarization treatment is performed using a CMP method, the insulating layer 726 may be polished until the surface of the insulating layer 724 is exposed. Further, the insulating layer 724 and the insulating layer 726 may be polished together to an extent that the insulating layer 724 is not lost.

Next, the insulating layer 724 is processed using a lithography method to form a first opening so that the conductive layer 701 is exposed (see FIG. 10). The first opening is a conductive layer 7 formed in a stepwise manner.
01 respectively. Although not shown, it is preferable that an opening through which the conductive layer 702 is exposed is also formed at the same time.

Next, a connection layer 707 is formed to fill the first opening. The connection layer 707 is C
It can be formed using a VD method or an ALD method. In particular, it is preferable to use the thermal CVD method or the ALD method because it is possible to form a film with a uniform thickness even in grooves and openings with a large aspect ratio. Alternatively, the connection layer 707 may be formed by combining CVD and ALD methods. Further, the connection layer 707 may have a laminated structure consisting of a plurality of layers. The connection layer 707 can be formed by forming a conductive film to become the connection layer 707 over the insulating layer 724 and inside the first opening, and removing unnecessary conductive film using CMP or the like.

Next, the insulating layer 724, the conductive layer 702, the conductive layer 701, the insulating layer 722, and the insulating film 72
1 is processed using a lithography method to form a second opening so that the conductive layer 706 is exposed (see FIG. 11).

Next, an insulating layer 703 is formed on the insulating layer 724 and the connection layer 707 and inside the second opening.
An insulating film 703A is formed (see FIG. 12). Although not shown, the insulating film 703A
may be formed by sequentially stacking an insulating film to serve as the insulating layer 703a, an insulating film to serve as the insulating layer 703b, and an insulating film to serve as the insulating layer 703c. The insulating film 703A can be formed using a CVD method or an ALD method. In particular, it is preferable to use the ALD method because it is possible to form a film with a uniform thickness even in grooves and openings with a large aspect ratio. Or A
The insulating film 703A may be formed by combining the LD method and the CVD method. The insulating film serving as the insulating layer 703a, the insulating film serving as the insulating layer 703b, and the insulating film serving as the insulating layer 703c may be formed using the same film forming apparatus or different film forming apparatuses. Note that the insulating layer 70
The insulating film that becomes the insulating layer 703c is thinner than the insulating layer 703a.
It is preferable to form the insulating film thinner than the insulating film 03a.

Next, the insulating film 703A formed at the bottom of the second opening is removed to obtain the insulating layer 703 (see FIG. 13). It is preferable to use anisotropic etching to remove the insulating film 703A. At this time, the insulating layer 724 and the insulating film 703A on the connection layer 707 are also removed, so the insulating layer 703 is provided only on the sidewall of the second opening. By removing the insulating film 703A at the bottom of the second opening, the conductive layer 706 is exposed again.

Here, as shown in FIG. 13(D), in the insulating layer 703 located above the second opening,
It is preferable to remove the insulating layer 703b and the insulating layer 703c. FIG. 13(D) is an enlarged view of a portion surrounded by a dashed line in FIG. 13(B). First, a sacrificial layer 727 that can be easily removed in a later step is formed so as to be buried inside the second opening, and is removed by etching or the like to a desired depth inside the second opening. Due to this etching, the exposed insulating layer 703
By sequentially removing the insulating layer 703b and the insulating layer 703b, the insulating layer 703 located in the horizontal direction (xy direction) of the conductive layer 702 can be left only as the insulating layer 703a. In this case, the gate insulating films of the selection transistors SST and SDT are constituted by the insulating layer 703a. After removing the insulating layer 703c and the insulating layer 703b, the sacrificial layer 727 is removed.

Next, an oxide film 704A is formed inside the second opening and on the insulating layer 724 (FIG.
reference). The oxide film 704A is a film that will become the oxide layer 704 and the oxide layer 751 later.
Here, in the case where the oxide film 704A is a stacked film, two or three layers of oxide films may be sequentially formed. At this time, the oxide layer 751 applied to the transistor 750 can also have a similar stacked structure.

The oxide film 704A can be formed using a CVD method, an ALD method, or a sputtering method. In particular, it is preferable to use the ALD method because it is possible to form a film with a uniform thickness even in grooves and openings with a large aspect ratio. Alternatively, the oxide film 704A may be formed by combining two or more of ALD, sputtering, and CVD. When the oxide film 704A is a laminated film, an oxide film that becomes the oxide layer 704a and an oxide film that becomes the oxide layer 704b, or an oxide film that becomes the oxide layer 704a, and an oxide film that becomes the oxide layer 7
An oxide film to become the oxide layer 704b and an oxide film to become the oxide layer 704c are sequentially formed. Here, the different oxide films may be formed using the same film forming apparatus or may be formed using different film forming apparatuses.

Further, an insulating layer 711 may be formed inside the oxide film 704A. The insulating layer 711 is
It can be formed by a CVD method, an ALD method, or the like. The insulating layer 711 is made of an oxide layer 7 in accordance with the characteristics required for the memory transistor and the semiconductor device including the memory transistor.
A material that supplies oxygen or a material that supplies hydrogen to 04 can be used.

Here, the oxide film 704A is formed so as to be in contact with the conductive layer 706. Oxide film 704
When A and the conductive layer 706 are in contact with each other, a metal compound layer containing the metal element of the conductive layer 706 and the component of the oxide film 704A is formed at the interface between the conductive layer 706 and the oxide film 704A. There is. By forming the metal compound, the conductive layer 706 and the subsequent oxide layer 704 are formed.
This is preferable because it reduces the contact resistance. Further, the conductive layer 706 may absorb oxygen contained near the bottom of the oxide film 704A. At this time, the resistance of the oxide film 704A near the interface with the conductive layer 706 is reduced, and the contact resistance between the conductive layer 706 and the subsequent oxide layer 704 is reduced, which is preferable. With the oxide film 704A and the conductive layer 706 in contact with each other,
By performing the heat treatment, the resistance of a part of the oxide film 704A is further reduced, and the contact resistance between the conductive layer 706 and the oxide layer 704 to be formed is further reduced. The heat treatment is performed in an atmosphere containing nitrogen.
It is preferable to carry out at a temperature of 00°C or more and 500°C or less, more preferably 300°C or more and 400°C or less.

Subsequently, a mask 731 is formed on the oxide film 704A, and unnecessary portions of the oxide film 704A are etched using the mask 731 (see FIG. 15). Thereby, the columnar oxide layer 704 and the thin film oxide layer 751 can be formed at the same time. After that, mask 731 is removed.

Here, in the case where the insulating layer 711 is formed, it is preferable to remove the insulating layer 711 over the oxide layer 751 and the oxide layer 704 by etching after removing the mask 731.

Subsequently, a conductive film is formed and processed using a lithography method to form the conductive layer 70.
5. Form a conductive layer 708, a conductive layer 753a, and a conductive layer 753b (see FIG. 16).

Note that although not shown, depending on the etching conditions of the conductive film, the upper part of the oxide layer 751 may become thinner. Further, depending on the etching conditions of the conductive film, the portions of the insulating layer 724 that are not covered by the conductive layer 705, the conductive layer 708, the conductive layer 753a, and the conductive layer 753b may become thinner.

Subsequently, an insulating film to become an insulating layer 754 and a conductive film to become a conductive layer 752 are sequentially formed and processed using a lithography method to form an insulating layer 754 and a conductive layer 752 (FIG. 17). reference). Through the above steps, the transistor 750 can be formed.

Note that only the conductive film that will become the conductive layer 752 may be etched without etching the insulating film that will become the insulating layer 754. At this time, the insulating layer 754 is provided to cover the conductive layer 705, the conductive layer 708, and the like.

Note that when forming the transistor shown in FIG. 4B, first an oxide film 704A,
A laminated film is formed by stacking conductive films such as the conductive layer 753a, and the laminated film is processed so as to leave a region that will become the oxide layer 751 and the like. After that, a portion of the conductive film overlapping the channel formation region on the oxide layer 751 is removed by etching, thereby forming the channel formation region. As a result, a finer transistor 750 can be manufactured.

In the subsequent steps, the insulating layer 761 and the connection layer 762 illustrated in FIG.
, the connection layer 763, the connection layer 764a, the connection layer 764b, the conductive layer 765, the conductive layer 766a, the conductive layer 766b, etc. may be formed. Moreover, an insulating layer, a connection layer, and a conductive layer functioning as a wiring may be further laminated and formed above this.

By manufacturing a memory cell array as described above, memory transistors in a plurality of layers can be manufactured at once without performing pattern formation for manufacturing memory transistors in each layer. Furthermore, when manufacturing a memory cell array using the above method, even if the number of layers of memory transistors is increased, the number of steps for patterning and etching the memory transistors does not increase. In this way, the process for manufacturing the memory cell array can be shortened, so a semiconductor device with high productivity can be provided.

Furthermore, by simultaneously forming the oxide layer that functions as the semiconductor layer of the memory cell array and the oxide layer that functions as the semiconductor layer of the transistor, the transistor can be placed near the memory cell array while minimizing the increase in process steps. can be formed. Furthermore, by forming the wiring connected to the memory cell array and the source electrode and drain electrode of the transistor at the same time, the process can be further simplified.

The above is an explanation of the method for manufacturing a semiconductor device.

[Example of storage device configuration]
FIG. 18A shows a configuration example of a three-dimensional NAND type nonvolatile storage device (3D NAND). The memory device 100 shown in FIG. 18(A) includes a control circuit 105, a memory cell array 1
10, and peripheral circuits.

The control circuit 105 has a function of controlling the entire storage device 100 and writing data and reading data. The control circuit 105 processes command signals from the outside and generates control signals for peripheral circuits. FIG. 18A shows a row decoder 12 as a peripheral circuit.
1. Row driver 122, sense amplifier 123, source line driver 124, input/output circuit 12
5, a buffer 126, etc. are provided.

Memory cell array 110 has a plurality of memory strings 112. FIG. 18B shows an example of the circuit configuration of the memory string 112. In the memory string 112, a selection transistor SST and memory transistors MT1 to M are connected between the bit line BL and the source line SL.
T2k (k is an integer of 1 or more) and a selection transistor SDT are electrically connected in series.

Note that when the memory transistors MT1 to MT2k are not distinguished from each other, they are referred to as memory transistors MT. The same applies to other elements.

The selection transistors SST and SDT and the memory transistors MT1 to MT2k are each transistors whose channels are formed of metal oxide, as described above. The memory transistor MT includes a charge storage layer and constitutes a nonvolatile memory cell.

The gates of the selection transistors SST and SDT are connected to the selection gate lines SGL and DGL, respectively.
electrically connected to. The gates of memory transistors MT1 to MT2k are electrically connected to word lines WL1 to WL2k, respectively. The bit line BL extends in the column direction, and the selection gate lines SGL, DGL, and word line WL extend in the row direction.

The input/output circuit 125 temporarily holds data written to the memory cell array 110, temporarily holds data read from the memory cell array 110, and the like.

Source line driver 124 drives source line SL.

Bit line BL is electrically connected to sense amplifier 123. The sense amplifier 123 detects and amplifies the voltage read from the memory string 112 to the bit line BL when reading data. Furthermore, when writing data, a voltage corresponding to the written data is input to the bit line BL.

Row decoder 121 decodes address data input from the outside and selects a row to be accessed. The row driver 122 inputs voltages necessary for writing, reading, and erasing data to the selection signal lines DGL, SGL, and word line WL according to the decoding result of the row decoder 121.

Buffer 126 is located between row decoder 121 and word line WL, and has a function of stabilizing the voltage applied to word line WL. Further, it may include a switching element and function as a selector.

FIG. 18C shows an inverter circuit 126a that can be used for the buffer 126. The inverter circuit 126a has a configuration in which a transistor M1 and a transistor M2 are connected in series. Further, the gate of the transistor M1 is connected to an input terminal IN to which an input signal is input, and the gate of the transistor M2 is connected to an input signal INB to which a signal obtained by inverting the input signal is input. For example, the word line W is connected to the output terminal OUT of the inverter circuit 126a.
L is connected.

FIG. 18(D) shows a switch circuit 126b that can be used for the buffer 126.
Switch circuit 126b includes a transistor M3. The gate of the transistor M3 is connected to the input terminal SW, one of the source and drain is connected to the input terminal IN, and the other is connected to the output terminal OUT. A selection signal input to the input terminal SW controls conduction or non-conduction between the input terminal IN and the output terminal OUT.

The high voltage transistor 750 illustrated above can be applied to, for example, a transistor included in the buffer 126, the row driver 122, the sense amplifier 123, the source line driver 124, and the like. Further, when the transistor 750 is applied to the buffer 126, it can be applied to at least one of the transistor M1 and the transistor M2 of the inverter circuit 126a, or the transistor M3 of the switch circuit 126b.

19 to 21 show examples of three-dimensional stacked structures of the memory cell array 110. Figure 19 shows
FIG. 2 is a diagram schematically showing an example of a three-dimensional structure of a memory cell array 110 using a circuit diagram. Figure 20 shows
1 is a perspective view showing an example of a three-dimensional structure of a memory cell array 110. FIG. FIG. 21 is a perspective view showing an example of the three-dimensional structure of the connection portion between the word line WL and the conductive layer 701.

As shown in FIG. 19, the memory cell array 110 is provided in a stacked manner in a region where the sense amplifiers 123 are formed. Thereby, the layout area of the storage device 100 can be reduced. Each word line WL is electrically connected to a buffer 126 having a high voltage transistor, and the buffer 126 is electrically connected to a row driver 122 provided below. Note that although FIG. 19 shows an example in which the row driver 122 is provided below the buffer 126, part or all of the row driver 122 may be formed of a high voltage transistor and placed side by side with the buffer 126.

Further, as shown in FIGS. 20 and 21, in the conductive layers 701 on the same level, the conductive layer 701a on the bit line BL side is connected to the word line WLa, and the conductive layer 701b on the source line SL side is connected to the word line WLb. Ru. Note that FIGS. 19 to 21 show examples in which eight memory transistors MT1 to MT8 are provided per one memory string 112.

Here, in the above example, the memory cell array 110 includes the memory string 112 to which a memory transistor including a charge storage layer is applied. Examples of such a memory transistor include a transistor having a MONOS structure, a transistor having a SONOS structure, a transistor having a floating gate structure, and the like.

Note that the memory cells that can be applied to the memory cell array 110 are not limited to these. Figure 22 (
A) and (B) show examples of circuit diagrams of memory cells having different configurations.

Two memory cells 131 are shown in FIG. 22(A). The memory cell 131 includes a transistor M and a capacitor C. Further, the memory cell 131 is connected to a word line WL1 or WL2, a bit line BL, and a wiring PL to which a predetermined potential is applied.

The transistor M has a gate connected to the word line WL1 or word line WL2, one of the source or drain connected to the bit line BL, and the other source or drain connected to the capacitive element C.
Connect to one electrode of The other electrode of the capacitive element C is connected to the wiring PL.

The memory cell 131 can hold data by accumulating charge in the capacitive element C.

By using a transistor that uses an oxide semiconductor and has an extremely small off-state current as the transistor M, the data retention period can be made extremely long compared to the case where a transistor that uses silicon is used. Therefore, since the frequency of refresh operations can be reduced, a memory cell with extremely low power consumption can be realized.

Two memory cells 132 are shown in FIG. 22(B). The memory cell 132 includes a transistor M1, a transistor M2, and a capacitor C. The memory cell 132 also includes a word line WL1 or WL2, a bit line BL, a wiring SL1 or wiring SL2 that functions as a selection signal line, and a wiring RL1 or wiring R that functions as a read signal line.
L2 is connected to a wiring PL to which a predetermined signal is applied.

The transistor M1 has a gate connected to the word line WL1 or word line WL2, one of the source or drain connected to the bit line BL, and the other source or drain connected to one electrode of the capacitive element C and the gate of the transistor M2. Connecting. In the transistor M2, one of the source and the drain is connected to the wiring SL1 and the wiring SL2, and the other of the source and the drain is connected to the wiring RL1 and the wiring RL2. The other electrode of the capacitive element C is connected to the wiring PL.
Connect with.

The memory cell 132 can hold data by holding the potential of the node connected to the gate of the transistor M2. In addition, since the conduction state of transistor M2 changes depending on the potential applied to transistor M2, it is possible to use a non-destructive method by detecting the current flowing between wiring SL1 (or wiring SL2) and wiring RL1 (or wiring RL2). You can read the data with .

By using a transistor that uses an oxide semiconductor and has extremely low off-state current as the transistor M1, the data retention period can be made extremely long compared to the case where a transistor that uses silicon is used. Further, it is preferable to use a transistor using single crystal silicon as the transistor M2.

[About circuit operation of storage device]
Next, FIG. 23 shows the operation of writing and reading data to the memory string 112.
This will be explained using (A) to (C). Note that hereinafter, a group of memory transistors MT that share word lines WL1 to WL2k will be referred to as a page.

Although FIGS. 23A to 23C show an example in which the memory string 112 includes memory transistors MT1 to MT8, the number of memory transistors MT is not limited thereto.

[Erase operation]
When writing data to the memory transistor MT, it is preferable to erase the data before the write operation. Note that the operation of erasing data may also be referred to as a reset operation. The erase operation is performed for each memory string 112 (also called block). For example, select a block from which you want to erase data, and erase the word lines WL1 to WL1 as shown in FIG.
L8 has a low potential (a potential at which the memory transistors MT1 to MT8 are non-conductive, for example 0V).
), apply the erase potential VE to the source line SL and the bit line BL, and make the selection transistor SDT and the selection transistor SST conductive. By the reset operation, electrons accumulated in the charge storage layers of each of memory transistors MT1 to MT8 can be extracted. As a result, memory transistors MT1 to MT8 enter a state where they hold data "1".

Note that it is preferable that the data of the memory transistor MT, which is not rewritten, be stored in another memory area before the block erase operation.

[Write operation]
First, the data write operation will be explained using FIG. 23(B).

The data write operation can be performed for each page as described above. First, a write potential (for example, 15 V) is applied to the word line of the page to which writing is to be performed, and a positive potential (a potential at which the transistor is turned on, for example, 3 V) is applied to the word line of the page to which no writing is to be performed. Here, as shown in FIG. 23B, a write potential is first applied to the word line WL1, and a positive potential is applied to the word lines WL2 to WL8. Then, the selection transistor SST is brought into a non-conductive state, and the selection transistor SDT is brought into a conductive state. By doing so, data corresponding to the potential of the bit line BL is written into the memory transistor MT1. Specifically, the bit line BL
When the potential is low (for example, 0V), electrons are injected into the charge storage layer of the memory transistor MT1 due to a large potential difference with the write potential applied to the word line WL1. Further, when the potential of the bit line BL is a positive potential, the potential difference with the write potential applied to the word line WL1 becomes small, so that electrons are not injected into the charge storage layer of the memory transistor MT1. That is, when a low potential is applied to the bit line BL, data "0" is written to the memory transistor MT1, and when a positive potential is applied, the data in the memory transistor MT1 cell remains "1". .

Here, by applying a different potential to the bit line BL for each memory string 112,
Data can be written page by page.

Note that multi-value data can also be written into the memory transistor MT. For example, the amount of charge injected into the charge storage layer of the memory transistor may be controlled by the potential of the bit line BL or the like or the time for applying the potential.

[Reading operation]
Next, a data read operation will be explained using FIG. 23(C).

Data read operations can also be performed page by page. First, a low potential (for example, 0V) is applied to the word line of the page to be read, and a positive potential (a potential at which the transistor is turned on, for example, 3V) is applied to the word line of the page not to be read. Here, Figure 23 (
As shown in C), a low potential is first applied to the word line WL1, and the word lines WL2 to WL8
Apply a positive potential to Then, selection transistor SST and selection transistor SST are rendered conductive. Further, a read potential (for example, 1V) is applied to the bit line BL, and a low potential (for example, 0V) is applied to the source line SL. At this time, the memory transistor
If the data stored in the memory transistor MT1 is "0", current will not flow through the memory string 112 and the potential of the bit line BL will drop. The potential does not change.The sense amplifier 123 connects the bit line BL
detects and amplifies the potential of Through the above steps, data in the memory string 112 can be read.

Here, by reading the data of each memory string 112 to the bit line BL, data can be read in page units.

The above is an explanation of the circuit operation of the memory device.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 2)
In this embodiment, an application example of a memory device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device described in the above embodiments can be used, for example, as a storage device of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/playback devices, navigation systems, etc.). Applicable to In addition,
Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment may be used as a memory card (for example, an S
It is applied to various removable storage devices such as D card), USB memory, and SSD (solid state drive). FIG. 24 schematically shows several configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

FIG. 24(A) is a schematic diagram of a USB memory. The USB memory 1100 is housed in a housing 1101
, a cap 1102, a USB connector 1103, and a board 1104. Substrate 110
4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110.
5. Controller chip 1106 is attached. Memory chip 1 on board 1104
The semiconductor device described in the previous embodiment can be incorporated into 105 or the like.

FIG. 24(B) is a schematic diagram of the external appearance of the SD card, and FIG. 24(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The board 1113 is housed in the housing 1111. For example, the substrate 11
13, a memory chip 1114 and a controller chip 1115 are attached.
By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data can be read from and written to the memory chip 1114 through wireless communication between the host device and the SD card 1110. The semiconductor device described in the previous embodiment can be incorporated into the memory chip 1114 of the substrate 1113 or the like.

FIG. 24(D) is a schematic diagram of the external appearance of the SSD, and FIG. 24(E) is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in a housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156,
For example, a DRAM chip may be used. A memory chip 1154 is also provided on the back side of the substrate 1153.
By providing this, the capacity of the SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into the memory chip 1154 of the substrate 1153 or the like.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 3)
In this embodiment, using FIG. 25, A
I will explain about the I system.

FIG. 25 is a block diagram showing a configuration example of the AI system 4041. AI system 404
1 includes a calculation section 4010, a control section 4020, and an input/output section 4030.

The calculation unit 4010 includes an analog calculation circuit 4011, a DOSRAM 4012, and a NOSR.
It has AM4013, FPGA4014, and 3D-NAND4015.

Here, DOSRAM (registered trademark) is a “Dynamic Oxide Semiconductor”.
It is an abbreviation for "onductor RAM" and refers to a RAM having 1T (transistor) and 1C (capacitance) type memory cells.

Also, NOSRAM (registered trademark) is a nonvolatile oxide semiconductor.
It is an abbreviation for "Iconductor RAM" and refers to a RAM that has gain cell type (2T type, 3T type) memory cells. DOSRAM and NOSRAM are memories that take advantage of the low off-state current of a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor). Note that in the following, a memory device using an OS transistor, such as a NOSRAM, may be referred to as an OS memory.

The control unit 4020 includes a CPU (Central Processing Unit) 40
21, GPU (Graphics Processing Unit) 4022, and P
LL (Phase Locked Loop) 4023 and SRAM (Static R
andom Access Memory) 4024 and PROM (Programma
ble Read Only Memory) 4025 and memory controller 4026
, a power supply circuit 4027 , and a PMU (Power Management Unit) 40
28.

The input/output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input/output module 4034, a communication module 4035,
has.

The calculation unit 4010 can perform learning or inference using a neural network.

The analog calculation circuit 4011 includes an A/D (analog/digital) conversion circuit, a D/A (digital/analog) conversion circuit, and a product-sum calculation circuit.

It is preferable that the analog arithmetic circuit 4011 be formed using an OS transistor. OS
The analog arithmetic circuit 4011 using transistors has an analog memory and can perform sum-of-products operations necessary for learning or inference with low power consumption.

DOSRAM4012 is a DRAM formed using OS transistors, and
The SRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021. DOSRAM4012 includes memory cells including OS transistors and Si
It has a readout circuit section including a transistor. Since the memory cell and the readout circuit section can be provided in different stacked layers, the DOSRAM 4012 can reduce the overall circuit area.

Calculations using neural networks may require more than 1000 pieces of input data.
When storing the above input data in an SRAM, the SRAM has a limited circuit area and a small storage capacity, so the above input data must be stored in small pieces. DOSRAM401
2, it is possible to arrange memory cells in a highly integrated manner even with a limited circuit area, and SRA
It has a larger storage capacity than M. Therefore, the DOSRAM 4012 can efficiently store the input data.

NOSRAM 4013 is a nonvolatile memory using OS transistors. NOSRA
M4013 can be used for flash memory or ReRAM (Resistive Random).
Access Memory), MRAM (Magnetoresistive Random)
Compared to other non-volatile memories such as dom access memory, it consumes less power when writing data. Furthermore, unlike flash memory and ReRAM, the elements do not deteriorate when data is written, and there is no limit to the number of times data can be written.

Further, the NOSRAM 4013 can store multi-value data of 2 bits or more in addition to 1-bit binary data. NOSRAM4013 stores multivalued data,
The memory cell area per bit can be reduced.

Further, the NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as is, no D/A conversion circuit or A/D conversion circuit is required. Therefore, NOS
The RAM 4013 can reduce the area of peripheral circuits. Note that in this specification, analog data refers to data having a resolution of 3 bits (8 values) or more. The above-mentioned multivalued data may be included in the analog data.

The data and parameters used for neural network calculations must be submitted to NOSRA.
It can be stored in M4013. The above-mentioned data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021, but the above-mentioned data and parameters can be stored in the internal NOSRAM 4013 at higher speed and with lower power consumption. can be stored. Further, since the NOSRAM 4013 can have longer bit lines than the DOSRAM 4012, the storage capacity can be increased.

The FPGA 4014 is an FPGA using OS transistors. AI system 404
1 uses the FPGA4014 to implement deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep layers, which will be described later in hardware. Neural network connections can be constructed, such as belief networks (DBNs). By configuring the neural network connections described above using hardware, faster execution can be achieved.

FPGA 4014 is an FPGA with an OS transistor. OS-FPGA is S
The memory area can be smaller than that of an FPGA made up of RAM. Therefore,
Even if a context switching function is added, there is little increase in area. Furthermore, the OS-FPGA can transmit data and parameters at high speed by boosting.

3D-NAND4015 is a nonvolatile memory using an oxide semiconductor. 3D-NAN
The D4015 is a highly integrated memory and has a large storage capacity per unit area.

Furthermore, the 3D-NAND 4015 can store multi-value data of 2 bits or more in addition to 1-bit binary data. By storing multilevel data, the 3D-NAND 4015 can further reduce the memory cell area per bit.

Further, as the 3D-NAND 4015, for example, the semiconductor device described in the above embodiment mode can be used. As a result, the area occupied by the memory cell can be reduced, so that the 3D-NAND 4015 can be further highly integrated. Therefore, 3D-NA
The storage capacity per unit area of the ND4015 can be increased.

The AI system 4041 includes an analog calculation circuit 4011, DOSRAM 4012, NOS
RAM 4013 and FPGA 4014 can be provided on one die (chip). Therefore, the AI system 4041 can perform neural network calculations at high speed and with low power consumption. In addition, analog calculation circuit 4011, DOSRAM4
012, NOSRAM4013, and FPGA4014 can be manufactured using the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.

Note that the calculation unit 4010 includes a DOSRAM 4012, a NOSRAM 4013, and an FP
It is not necessary to have all GA4014s. Depending on the problem that the AI system 4041 wants to solve, one or more of the DOSRAM 4012, NOSRAM 4013, and FPGA 4014 may be selected and provided.

The AI system 4041 uses a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network ( DBN), etc. can be performed. PROM 4025 can store programs for executing these operations. Further, part or all of these programs may be stored in the NOSRAM 4013 or 3D-NAND 4015. 3D-
The NAND 4015 is a highly integrated memory and has a large storage capacity per unit area, so it can store large-capacity programs.

Many existing programs that exist as libraries assume GPU processing. Therefore, it is preferable that the AI system 4041 includes the GPU 4022. AI
In the system 4041, among the product-sum calculations used in learning and inference, the calculation unit 4010 executes the rate-determining product-sum calculation, and the other product-sum calculations can be executed by the GPU 4022.
This allows for faster learning and inference.

The power supply circuit 4027 not only generates a low voltage potential for the logic circuit, but also generates a potential for analog calculation. The power supply circuit 4027 may use an OS memory. Power supply circuit 40
No. 27 can reduce power consumption by storing the reference potential in the OS memory.

The PMU 4028 has a function of temporarily turning off the power supply to the AI system 4041.

It is preferable that the CPU 4021 and the GPU 4022 have an OS memory as a register. By having the OS memory, the CPU 4021 and the GPU 4022 can continue to hold data (logical values) in the OS memory even when power supply is turned off. As a result, AI system 4041 can save power.

The PLL 4023 has a function of generating a clock. AI system 4041 is PL
Operations are performed based on the clock generated by L4023. Preferably, PLL 4023 has OS memory. By having an OS memory, the PLL 4023 can hold an analog potential that controls the oscillation cycle of the clock.

AI system 4041 may store data in external memory such as DRAM. Therefore, the AI system 4041 preferably includes a memory controller 4026 that functions as an interface with an external DRAM. In addition, the memory controller 4026
is preferably placed near the CPU 4021 or GPU 4022. By doing so, data can be exchanged quickly.

A part or all of the circuit shown in the control section 4020 can be formed on the same die as the calculation section 4010. By doing so, the AI system 4041 can achieve high speed and low power consumption.
Can perform neural network calculations.

The data used for neural network calculations is stored on an external storage device (HDD (Hard Drive).
(Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably includes an external storage control circuit 4031 that functions as an interface with an external storage device.

Learning and inference using neural networks often deal with audio and video, so A
I system 4041 has an audio codec 4032 and a video codec 4033.
The audio codec 4032 encodes and decodes audio data.
The video codec 4033 encodes and decodes video data.

AI system 4041 can perform learning or inference using data obtained from external sensors. Therefore, the AI system 4041 includes a general-purpose input/output module 4034. The general-purpose input/output module 4034 is, for example, a USB
ial Bus) and I2C (Inter-Integrated Circuit).

The AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 uses the communication module 403
It is preferable to have 5.

The analog arithmetic circuit 4011 may use a multi-level flash memory as the analog memory. However, flash memory has a limit on the number of times it can be rewritten. Furthermore, it is extremely difficult to form a multilevel flash memory in an embedded manner (forming an arithmetic circuit and memory on the same die).

Further, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limit on the number of times it can be rewritten and also has problems in terms of storage accuracy.
Furthermore, since the device is composed of two terminals, the circuit design for separating data writing and data reading becomes complicated.

Furthermore, the analog arithmetic circuit 4011 may use MRAM as an analog memory.
However, MRAM has a low resistance change rate and has a problem in storage accuracy.

In view of the above, it is preferable that the analog arithmetic circuit 4011 uses the OS memory as the analog memory.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 4)
[Application example of AI system]
In this embodiment, an application example of the AI system shown in the above embodiment will be described using FIG. 26.

FIG. 26A shows an AI system 4041A in which the AI systems 4041 described in FIG. 25 are arranged in parallel, and signals can be transmitted and received between the systems via a bus line.

The AI system 4041A illustrated in FIG. 26(A) includes a plurality of AI systems 4041_1
to AI systems 4041_n (n is a natural number). The AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098.

Furthermore, FIG. 26(B) shows an AI system 4041B in which the AI systems 4041 described in FIG. 25 are arranged in parallel as in FIG. 26(A), and signals can be sent and received between the systems via a network. be.

The AI system 4041B illustrated in FIG. 26(B) includes a plurality of AI systems 4041_1
to AI system 4041_n. AI system 4041_1 to AI system 4
041_n are connected to each other via a network 4099.

The network 4099 may have a configuration in which a communication module is provided in each of the AI systems 4041_1 to 4041_n to perform wireless or wired communication.
The communication module can perform communication via the antenna. For example, World Wi
The Internet, intranet, extranet, PAN (Personal Area Network), and LAN (Local A
rea Network), CAN (Campus Area Network), MA
N (Metropolitan Area Network), WAN (Wide Ar
Each electronic device can be connected to a computer network such as GAN (Global Area Network) or GAN (Global Area Network) to perform communication. When performing wireless communication, LTE (Long Term Evolution) is used as a communication protocol or communication technology.
tion), GSM (Global System for Mobile Commu)
nication: registered trademark), EDGE (Enhanced Data Rates)
for GSM Evolution), CDMA2000 (Code Divisio
n Multiple Access 2000), communication standards such as W-CDMA (registered trademark), or Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBe
It is possible to use specifications standardized by IEEE for communication, such as e (registered trademark).

With the configurations shown in FIGS. 26A and 26B, analog signals obtained by external sensors or the like can be processed by separate AI systems. For example, biological information such as brain waves, pulse,
Information such as blood pressure and body temperature can be acquired by various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor, and the analog signals can be processed by separate AI systems. By processing signals or performing learning in each separate AI system, the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculations. As a result, recognition accuracy can be improved. It is expected that from the information obtained by each AI system, it will be possible to instantly and comprehensively grasp complex changes in biological information.

The structure shown in this embodiment can be used in combination with the structures shown in other embodiments as appropriate.

(Embodiment 5)
This embodiment shows an example of an IC incorporating the AI system shown in the above embodiments.

The AI system shown in the above embodiment includes a digital processing circuit made of Si transistors such as a CPU, an analog calculation circuit using OS transistors, 3D-NAND, OS-FPG, etc.
A and OS memories such as DOSRAM and NOSRAM can be integrated into one die.

FIG. 27 shows an example of an IC incorporating an AI system. AI system I shown in Figure 27
C7000 has a lead 7001 and a circuit section 7003. AI system IC7000
is mounted on a printed circuit board 7002, for example. A plurality of such IC chips are combined and electrically connected to each other on a printed circuit board 7002 to complete a board (mounted board 7004) on which electronic components are mounted. In the circuit portion 7003, the various circuits described in the above embodiment modes are provided on one die. As shown in the previous embodiment, the circuit portion 7003 has a stacked structure and is roughly divided into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. The OS transistor layer 7033 is replaced by the Si transistor layer 7031.
Since the AI system IC 7000 can be provided in a stacked manner, it is easy to downsize the AI system IC 7000.

In Figure 27, the AI system IC7000 package includes a QFP (Quad Flat
However, the form of the package is not limited to this.

Digital processing circuits such as CPUs and analog calculation circuits using OS transistors, 3D-
All OS memories such as NAND, OS-FPGA, DOSRAM, and NOSRAM are
It can be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. That is, the elements constituting the AI system can be formed in the same manufacturing process. Therefore, in the IC shown in this embodiment, even if the number of constituent elements increases, there is no need to increase the manufacturing process, and the above AI system can be incorporated at low cost.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 6)
[Electronics]
A semiconductor device according to one embodiment of the present invention can be used in various electronic devices. 28 and 29 show specific examples of electronic devices using the semiconductor device according to one embodiment of the present invention.

A robot 2000 shown in FIG. 28(A) includes a calculation device 2001, a sensor 2002, a light 2003, a lift 2004, a drive unit 2005, and a movement mechanism 2011, and can take still images and videos while moving. Such a robot can be used as a security system or a monitoring system.

The robot 2000 may further include a communication means 2006, a speaker 2007, a microphone 2008, a display section 2009, a light emitting section 2010, and the like.

A semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 2001. Furthermore, for the calculation device 2001, an IC incorporating an AI system according to one embodiment of the present invention can be used. The sensor 2002 has a function as a camera that photographs the surroundings of the robot 2000. The light 2003 can be used as a light when the sensor 2002 photographs the surroundings of the robot 2000. Note that when the sensor 2002 takes a still image, the light 2003 preferably functions as a flashlight. sensor 20
02 is connected to the robot body via a lift 2004. The height of sensor 2002 can be adjusted by lift 2004. Lift 2004 is preferably telescoping. Further, the lift 2004 may be a folding type lift made up of a plurality of booms. Further, since the robot 2000 is provided with a drive unit 2005 and a movement mechanism 2011 connected to the drive unit 2005, the imaging range by the sensor 2002, that is, the monitoring range is expanded, which is preferable.

The communication means 2006 can transmit information captured by the sensor 2002 to an administrator or a server owned by the administrator. In addition, the information captured by the sensor 2002 is analyzed by the computing device 2001, and if it is determined that there is an emergency such as a crime, accident, or fire, the information is sent to a security company, police, fire department, medical institution, or the owner of the land or building. You can contact us. speaker 2
007 can transmit information to those around the robot, such as warning criminals, asking questions to injured or suddenly ill people, and guiding evacuations. Microphone 2008 can be used to acquire sounds around robot 2000. Also, a communication means 2006 and a speaker 2007
By using this together, the robot 2000 can have the function of a telephone.
People around the robot 2000 can talk to the administrator or any other person. Display section 2
009 can display any information. In the event of an emergency, disaster information and evacuation routes can be displayed. Further, by using the communication means 2006, the speaker 2007, and the microphone 2008, the robot 2000 can function as a videophone. The people around the robot 2000 are the administrator, any other person, and the display section 200.
You can have a conversation while looking at 9.

The light emitting unit 2010 can indicate the direction of movement and the stopped state of the robot 2000 using text or light. It may also indicate an emergency situation.

FIG. 28(B) is a block diagram showing the configuration of the robot 2000. Arithmetic device 2001
turns on or off the light 2003 based on information such as images obtained by the sensor 2002.
Adjust the brightness. It also adjusts the height of the lift 2004 or controls the drive unit 2005 to align the robot 2000 and the sensor 2002. In addition, the drive unit 2
The operating status of 005 can be shown using the light emitting unit 2010. In addition, the communication means 200
6 can be used to transmit information about the surroundings of the robot 2000 obtained from the sensor 2002 and the microphone 2008 to the administrator or a server owned by the administrator. In addition, depending on the computing device 2001 and the administrator's judgment, the speaker 2007 and the display unit 2009 may be used to
Information can be transmitted around the robot 2000.

If a sensor that can capture an image even when the surroundings are dark is used as the sensor 2002, the light 2003 may not be provided. As such a sensor, selenium (
An image sensor using Se) can be used.

Such a robot 2000 can be used for security of commercial facilities and offices.
Information obtained from the sensor 2002 and the microphone 2008 is stored in the computing device 2001 and the server. The stored information will be analyzed by an AI system and will be used to prevent loss or damage of items.
Determine whether there is an abnormality such as intrusion by a suspicious person or disaster such as fire. Deep learning may be used to analyze the information. If it is determined that an abnormality has occurred, the robot 2000 contacts the administrator, transmits information to the surrounding area, and records the surrounding situation.

Further, the robot 2000 may be used to monitor the growth status of agricultural products. A robot 2000 installed in a rice field or field uses a sensor 2002 to monitor the shape, size, and color of leaves or fruits of agricultural crops, and determines whether they are sick or have pests attached to them. robot 2
Since 000 is provided with a moving mechanism 2011, it is possible to monitor the growth status of agricultural products over a wide range. Further, since the robot 2000 is provided with a lift 2004, leaves and fruits at any height can be monitored regardless of the type of agricultural products or growth conditions. The monitoring results are sent to the producer using the communication means 2006, and the producer can determine the type, amount, and timing of application of fertilizers and pesticides necessary for the crops. Furthermore, using the arithmetic device 2001,
The monitoring results may be analyzed by an AI system to determine the type, amount, and timing of application of fertilizers and pesticides required for agricultural crops, and notify producers of the results. Deep learning may be used to analyze the monitoring results.

FIG. 29(A) shows a sorting system 3000 using a robot 3001. The robot 3001 includes a computing device 3002, a boom 3003, and an arm 3004. Further, the robot 3001 may include a wired or wireless communication means 3011.
The sorting system 3000 also includes a housing 3008 having a sensor 3009.
The housing 3008 has a communication means 3010. The housing 3008 is the sorting system 30
00, or on the ceiling, wall, or beam (none of which are shown) of the sorting work area. Furthermore, the housing 3008 may be provided in the robot 3001. For example, boom 3003
, or may be provided on the arm 3004. When the housing 3008 is provided in the robot 3001, the information obtained by the sensor 3009 may be sent to the arithmetic unit 3002 and processed without going through the communication means 3010 and 3011.

The boom 3003 is movable, and the arm 3004 can be placed at a desired position. Further, the arm 3004 may be telescopic. After extending the arm placed on the desired article 3007, grabbing the desired article 3007, and retracting the arm 3004, the boom 3
003 may be used to move the arm 3004.

Sorting system 3000 can move items 3007 in container 3005 to container 3006. Container 3005 and container 3006 may have the same shape or different shapes. In addition, a plurality of articles 3007 contained in one container 3005 can be stored in a plurality of containers 3006.
You may move by dividing it into .

As the containers 3005 and 3006, containers, cardboard boxes, boxes for packaging products, cases, films, or bags, food storage vats, lunch boxes, and the like are used. Also,
At least one of container 3005 and container 3006 may be a cooking utensil such as a pot or a frying pan.

A semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 3002. Furthermore, for the calculation device 3002, an IC incorporating an AI system according to one embodiment of the present invention can be used.

The sensor 3009 reads the position of the container 3005, the position of the container 3006, the inside of the container 3005, and the state of the article 3007 inside the container 3005, and transmits the information to the computing device 3002 using the communication means 3010. Information is transmitted wirelessly or by wire. In addition, the communication means 30
Information may be transmitted by wire without using 10. Arithmetic device 3002 analyzes the transmitted information. Here, the state of the articles 3007 refers to the shape, number, overlapping of the articles 3007, and the like. The calculation device 3002 performs analysis based on the information from the sensor 3009,
Detailed information about the article 3007 is derived. The three-dimensional shape and hardness (softness) of the article 3007 are derived by comparing it with data stored in the computing device 3002 or a server that can communicate with the robot 3001. Also, from the three-dimensional shape and hardness (softness) of the article 3007, the arm 30
The shape of 04 can be changed.

To derive detailed information about the article 3007, analysis using an AI system can be used. Deep learning may be used to analyze the information.

FIG. 29(B) shows an arm in which a pair of plates 3021 move in the horizontal direction and can sandwich an article 3007. By horizontally moving the pair of plates 3021 toward the center, the article 3007 can be sandwiched. Such an arm can grasp the article 3007 with a surface, and is suitable for grasping the article 3007 having a columnar shape such as a cube or a rectangular parallelepiped. Figure 29
(C) is an arm in which a plurality of bars 3022 move horizontally and can sandwich an article 3007. By horizontally moving the plurality of bars 3022 toward the center, the article 30
07 can be inserted. Such an arm can capture the article 3007 at a point,
It is suitable for gripping an article 3007 that has a spherical shape, or when the shape of the article 3007 is not constant, that is, an irregularly shaped article 3007. Note that in FIG. 29C, the number of bars 3022 is four, but the present embodiment is not limited to this. The number of bars 3022 may be three or five or more. FIG. 29(D) shows an arm that can sandwich an article 3007 by rotating a pair of plates 3023 around a common axis so that they approach each other. Such an arm can grasp the article 3007 with a surface, and is suitable for grasping the article 3007 having a thin film shape such as paper or film. FIG. 29E shows an arm that can hold an article 3007 by rotating a pair of hook-shaped plates 3024 around a common axis so that their tips approach each other. Such an arm can grasp an article 3007 as a point or a line, and is suitable for grasping an article 3007 that has a thin film shape, such as paper or film, or an article 3007 that has a smaller granular shape. . Alternatively, as shown in FIG. 29(F), a spatula 3025 may be attached to the tip of the arm to scoop up an article 3007 having a smaller granular shape.

The arms shown in FIGS. 29(A) to 29(F) are examples, and one embodiment of the present invention is not limited to these shapes. Further, the description of the use of each arm is also an example, and one embodiment of the present invention is not limited to these descriptions.

The robot 3001 moves the boom 3003 and moves the arm 3004 over a desired article 3007 in the container 3005 based on a signal from the computing device 3002. In the case of a telescoping arm 3004, the arm 3004 is extended and the tip of the arm 3004 is lowered to the level of the article 3007. Move the tip of the arm to grab the desired article 3007. Retract the arm while holding the item 3007. Move the boom 3003 again and move the arm 3004 to the container 300.
6 to the desired position. At this time, the arm 3004 may be rotated to adjust the angle of the article 3007 with respect to the container 3006. Arm 3004 is extended and article 3007 is placed in container 3006, and arm 3004 releases article 3007. By repeating the above operations, the robot 3001 can move the article 3007 from the container 3005 to the container 3006.

Since the position information of the containers 3005 and 3006 and the condition of the article 3007 are analyzed using an AI system, the article 3007 can be reliably stored regardless of the shape or hardness of the article 3007.
7 can be moved. Examples of the article 3007 include not only articles packed in cubic or rectangular boxes, or boxes or cases of arbitrary shapes, but also shaped processed foods such as eggs, hamburgers and croquettes, and non-conforming foods such as potatoes and tomatoes. Examples include foods such as regular-shaped vegetables, mechanical parts such as screws and nuts, and thin films such as paper and film. The sorting system 3000 shown in this embodiment can change the shape of the arm in consideration of the shape and hardness of the article 3007. 3005
can be moved from the container 3006 to the container 3006.

For example, a storage device using the semiconductor device of one embodiment of the present invention can retain control information, control programs, and the like for the electronic device described above for a long period of time. By using a semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be achieved.

Further, for example, an IC in which the above-mentioned AI system is incorporated can be used in the arithmetic unit of the above-mentioned electronic equipment. As a result, the electronic device shown in this embodiment can perform accurate operations according to the situation with low power consumption using the AI system.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

100 Storage device 105 Control circuit 110 Memory cell array 112 Memory string 121 Row decoder 122 Row driver 123 Sense amplifier 124 Source line driver 125 Input/output circuit 126 Buffer 126a Inverter circuit 126b Switch circuit 131 Memory cell 132 Memory cell 700 Semiconductor device 700A Storage device 700D Circuit portion 700M Memory cell array 701 Conductive layer 701_m Conductive layer 701_1 Conductive layer 701_6 Conductive layer 701a Conductive layer 701A Conductive film 701b Conductive layer 701B Conductive film 702 Conductive layer 702A Conductive film 702b Insulating layer 702B Conductive film 703 Insulating layer 703_1 Insulating layer 703 ＿３ Insulating layer 703a Insulating layer 703A Insulating film 703b Insulating layer 703c Insulating layer 704 Oxide layer 704_1 Oxide layer 704_3 Oxide layer 704a Oxide layer 704A Oxide film 704b Oxide layer 704c Oxide layer 705 Conductive layer 705_1 Conductive layer 705_3 Conductive layer 706 Conductive layer 706_1 Conductive layer 706_3 Conductive layer 707 Connection layer 707_m Connection layer 707_1 Connection layer 708 Conductive layer 708_m Conductive layer 708_1 Conductive layer 710 Memory transistor 711 Insulating layer 720 Substrate 721 Insulating film 722 Insulating layer 722A Insulating film 722B Insulating film 723 Mask 723A Mask 724 Insulating layer 725 Mask 726 Insulating layer 727 Sacrificial layer 731 Mask 750 Transistor 751 Oxide layer 751a Oxide layer 752 Conductive layer 753a Conductive layer 753b Conductive layer 754 Insulating layer 761 Insulating layer 762 Connection layer 763 Connection layer 764a Connection layer 764b Connection layer 765 Conductive layer 766a Conductive layer 766b Conductive layer 1100 USB memory 1101 Housing 1102 Cap 1103 USB connector 1104 Board 1105 Memory chip 1106 Controller chip 1110 SD card 1111 Housing 1112 Connector 1113 Board 1114 Memory chip 1115 Controller chip 1150 SSD
1151 Housing 1152 Connector 1153 Board 1154 Memory chip 1155 Memory chip 1156 Controller chip 2000 Robot 2001 Arithmetic device 2002 Sensor 2003 Light 2004 Lift 2005 Drive section 2006 Communication means 2007 Speaker 2008 Microphone 2009 Display section 2010 Light emitting section 2011 Movement mechanism 30 00 System 3001 Robot 3002 Arithmetic device 3003 Boom 3004 Arm 3005 Container 3006 Container 3007 Article 3008 Housing 3009 Sensor 3010 Communication means 3011 Communication means 3021 Plate 3022 Bar 3023 Plate 3024 Plate 3025 Spatula 4010 Arithmetic unit 4011 Analog arithmetic circuit 4012 DOSRAM
4013 NOSRAM
4014 FPGA
4020 Control unit 4021 CPU
4022 GPU
4023PLL
4025 PROM
4026 Memory controller 4027 Power supply circuit 4028 PMU
4030 Input/output unit 4031 External storage control circuit 4032 Audio codec 4033 Video codec 4034 General-purpose input/output module 4035 Communication module 4041 AI system 4041_n AI system 4041_1 AI system 4041A AI system 4041B AI system 4098 Bus line 4099 Network 7000 AI system IC
7001 Lead 7002 Printed board 7003 Circuit portion 7004 Mounting board 7031 Si transistor layer 7032 Wiring layer 7033 OS transistor layer

Claims (1)

A semiconductor device including a memory transistor, a transistor, and an oxide layer,
The memory transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. a semiconductor layer;
The transistor includes a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a fourth insulating layer, and a second semiconductor layer,
the first conductive layer has an opening;
The first insulating layer has a region in contact with an inner side surface of the opening,
The second insulating layer has a region in contact with an inner side surface of the first insulating layer,
The third insulating layer has a region in contact with an inner side surface of the second insulating layer,
The first semiconductor layer has a region in contact with an inner side surface of the third insulating layer, and is provided to protrude in the vertical direction from the opening of the first conductive layer,
The second conductive layer has a region in contact with the bottom of the first semiconductor layer,
The third conductive layer has a region in contact with an upper part of the first semiconductor layer,
The fourth conductive layer and the fifth conductive layer have regions in contact with the upper surface of the second semiconductor layer,
The fourth insulating layer has a region in contact with the top surface of the fourth conductive layer, a region in contact with the top surface of the fifth conductive layer, and a region in contact with the top surface of the second semiconductor layer. ,
The sixth conductive layer has a region overlapping with the second semiconductor layer via the fourth insulating layer,
The first conductive layer is always electrically connected to the fourth conductive layer or the fifth conductive layer via the oxide layer,
A semiconductor device in which the oxide layer, the first semiconductor layer, and the second semiconductor layer include the same metal oxide.

Images