JP2022171745A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an occupied area of a peripheral circuit of a storage device and provide a storage device having a large storage capacity per unit area.

SOLUTION: A memory cell array and a circuit unit including a high breakdown voltage transistor are configured to be provided on a same substrate. The memory cell array includes a configuration in which a plurality of memory transistors are laminated vertically. A semiconductor layer of the memory transistor and a semiconductor layer of the high breakdown voltage transistor are formed by processing the same semiconductor film. An oxide semiconductor is applied to a semiconductor layer of each of the memory transistor and the high breakdown voltage transistor.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2023,JPO&INPIT

Description

One embodiment of the present invention relates to a semiconductor device. One aspect of the present invention relates to a storage device.

Note that one embodiment of the present invention is not limited to the above technical field. Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input/output devices, and driving methods thereof. , or methods for producing them, can be mentioned as an example.

Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one mode of a semiconductor device. Imaging devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices may include semiconductor devices.

2. Description of the Related Art In recent years, as the amount of data to be handled increases, semiconductor devices with larger storage capacity are required. In order to increase the storage capacity per unit area, it is effective to stack memory cells (see Patent Documents 1 and 2). By stacking the memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells.

Further, Patent Document 3 discloses a nonvolatile memory device using an oxide semiconductor.

U.S. Patent Publication No. 2011/0065270 U.S. Pat. No. 9,634,097 U.S. Patent Publication No. 2016/0079268

A memory device has a memory cell array for storing data and a control circuit for controlling write and read operations. Since the drive voltage of the memory cell array is generally higher than that of the control circuit, the drive circuit that drives the memory cell array based on the signal generated by the control circuit includes:
An element with high withstand voltage is required. However, since such high-voltage transistors and other elements are larger in size than the elements that constitute the control circuit, the increase in the number of memory cells (that is, the storage capacity) leads to an increase in the number of peripheral circuits including the drive circuit. However, there is a problem that the occupied area is increased.

An object of one embodiment of the present invention is to reduce the area occupied by a peripheral circuit. Another object is to provide a semiconductor device with a large memory capacity per unit area. or,
An object is to provide a semiconductor device with high productivity. Or a new semiconductor device,
Another object is to provide a storage device.

The description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from descriptions in the specification, drawings, claims, and the like.

One embodiment of the present invention is a semiconductor device including a memory transistor and a transistor. The memory transistor has a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer and a first semiconductor layer. The transistor has a fourth conductive layer, a fifth conductive layer, a fourth insulating layer, and a second semiconductor layer. The first conductive layer has an opening, the first insulating layer is provided in contact with the inner side of the opening, the second insulating layer is provided in contact with the inner side of the first insulating layer, and the third insulating layer is provided in contact with the inner side of the first insulating layer. The first semiconductor layer is provided in contact with the inner side of the second insulating layer, and the first semiconductor layer is provided in contact with the inner side of the third insulating layer and protrudes vertically beyond the opening of the first conductive layer. be provided. The second conductive layer is provided in contact with the bottom of the first semiconductor layer, and the third conductive layer is provided in contact with the top of the first semiconductor layer. A fourth conductive layer and a fifth conductive layer are provided in contact with the second semiconductor layer, respectively. A fourth insulating layer is provided in contact with the second semiconductor layer. The fifth conductive layer has a portion overlapping with the second semiconductor layer with the fourth insulating layer interposed therebetween. Additionally, the first insulating layer, the third insulating layer, and the fourth insulating layer each include an oxide. Furthermore, the second insulating layer includes nitride. Further, the first semiconductor layer and the second semiconductor layer contain the same metal oxide.

Further, in the above, the third conductive layer, the fourth conductive layer, and the fifth conductive layer preferably contain the same metal element.

Further, in the above, the first semiconductor layer and the second semiconductor layer are preferably formed by processing the same metal oxide film.

Further, in the above, the third conductive layer, the fourth conductive layer, and the fifth conductive layer are preferably formed by processing the same conductive film.

Further, in the above, the first conductive layer and the fourth conductive layer are preferably electrically connected.

Moreover, in the above, it is preferable to have a substrate. At this time, it is preferable that a plurality of memory transistors be provided over the substrate. Furthermore, it is preferable that the plurality of memory transistors be stacked vertically with respect to one surface of the substrate.

Further, in the above, the first semiconductor layer and the second semiconductor layer are the first semiconductor film and the second semiconductor film.
It is preferable to have a laminated structure of semiconductor films. At this time, it is preferable that the first semiconductor film and the second semiconductor film have different crystallinities. Alternatively, it is preferable that the first semiconductor film and the second semiconductor film have different compositions.

According to one embodiment of the present invention, the area occupied by peripheral circuits can be reduced. Alternatively, a semiconductor device with a large memory capacity per unit area can be provided. Alternatively, a semiconductor device with high productivity can be provided. Alternatively, a novel semiconductor device or memory device can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from descriptions in the specification, drawings, claims, and the like.

1A and 1B are a top view and a cross-sectional view of a semiconductor device; 1 is a perspective view of a semiconductor device; FIG. 1 is a top view of a semiconductor device; FIG. Sectional drawing of a semiconductor device. 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B illustrate an example of a method for manufacturing a semiconductor device; 4A and 4B are a block diagram and a circuit diagram of a memory device; FIG. 4 is a diagram showing an example of a three-dimensional structure of a storage device; FIG. 4 is a diagram showing an example of a three-dimensional structure of a storage device; FIG. 4 is a diagram showing an example of a three-dimensional structure of a storage device; A circuit diagram of a memory device. 4A and 4B are circuit diagrams each illustrating an operation example of a memory device; A configuration example of a storage device. Block diagram of AI system. Block diagram of AI system. Configuration example of IC. A configuration example of an electronic device. A configuration example of an electronic device.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the descriptions of the embodiments shown below.

In the configuration of the invention to be described below, the same reference numerals are used in common for the same parts or parts having similar functions in different drawings, and repeated description thereof will be omitted. Moreover, when referring to similar functions, the hatch patterns may be the same and no particular reference numerals may be attached.

In each drawing described in this specification, the size, layer thickness, or region of each configuration is
May be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

Note that ordinal numbers such as “first” and “second” in this specification and the like are used to avoid confusion of constituent elements, and are not numerically limited.

A transistor is a type of semiconductor element, and can achieve current or voltage amplification, switching operation for controlling conduction or non-conduction, and the like. A transistor in this specification is an IGFET (Insulated Gate Field Effect Trans
Itor) and thin film transistors (TFT: Thin Film Transistor
)including.

Also, the functions of "source" and "drain" may be interchanged when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification, the terms "source" and "drain" can be used interchangeably.

In this specification and the like, either the source or the drain of a transistor may be called a "first electrode", and the other of the source and the drain may be called a "second electrode". Note that a gate is also called a “gate” or a “gate electrode”.

In this specification and the like, a metal oxide is a metal oxide in broad terms. Metal oxides include oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OSs).
etc. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. In other words, an OS FET can be referred to as a transistor including a metal oxide or an oxide semiconductor.

(Embodiment 1)
In this embodiment, a structure example, a manufacturing method example, a circuit structure, and an operation method example of a semiconductor device of one embodiment of the present invention will be described.

One embodiment of the present invention has a structure in which a memory cell array and a circuit portion including high-voltage transistors are provided over the same substrate. The memory cell array has a structure in which a plurality of memory transistors are stacked in the thickness direction (vertical direction). Therefore, it is possible to arrange a high-voltage transistor in the vicinity of the memory cell array, so that the area occupied by the semiconductor device can be reduced.

Here, the semiconductor layer included in the memory transistor and the semiconductor layer included in the high-voltage transistor are formed by processing the same semiconductor film. As a result, the manufacturing process can be simplified and the manufacturing cost of the semiconductor device can be reduced because the process for forming each semiconductor layer can also be performed. Furthermore, it is preferable that the wirings and the like connected to the memory cell array and the source electrode, the drain electrode, the gate electrode, and the like of the high-voltage transistor are formed by processing the same conductive film.

In addition, in the semiconductor layers respectively included in the memory transistor and the high-voltage transistor,
Application of an oxide semiconductor is preferable. A transistor including an oxide semiconductor can have higher withstand voltage between a source and a drain than a transistor including silicon or the like, and thus can be suitably used as a transistor included in a circuit portion. In addition, since a transistor using an oxide semiconductor has a feature that driving capability is less likely to decrease even if the thickness of the gate insulating layer is increased compared to a transistor using silicon, it is possible to improve the gate breakdown voltage. Reliability can be improved by using a transistor for a circuit portion and a memory transistor.

Here, it is preferable to provide a circuit portion including the memory cell array and the high-voltage transistor so as to overlap the control circuit for controlling the memory cell array. For example, it can be realized by configuring the control circuit with a CMOS circuit or the like formed on a single crystal silicon substrate, and forming a memory cell array and a circuit section thereon. Accordingly, the area occupied by the semiconductor device can be further reduced, so that the number of chips per single crystal silicon substrate can be increased and the manufacturing cost can be reduced.

A more specific example will be described below with reference to the drawings.

[Configuration example]
The configurations of the memory transistors of the semiconductor device 700, the memory cell array 700M, and the transistors included in the circuit portion 700D are described below with reference to the drawings.

[Memory cell array]
FIG. 1A is a top view of a semiconductor device 700, and FIG. 1B is A1-1 in FIG. 1A.
It is a cross-sectional view of the portion indicated by the dashed-dotted line of A2. In addition, FIG. 1(C) is A3-A in FIG. 1(A).
4 is a cross-sectional view of a portion indicated by a dashed-dotted line 4, and is a cross-sectional view for explaining a memory string.

FIG. 1D is an enlarged cross-sectional view or perspective view of a portion surrounded by a dashed line in FIG. 1B, and is a diagram for explaining a memory transistor functioning as a memory cell. In the following, as shown in FIG. 1, an orthogonal coordinate system consisting of x-axis, y-axis, and z-axis is set for the sake of convenience. Here, the x-axis and the y-axis are the substrate 7 on which the semiconductor device 700 is provided.
The z-axis is taken parallel to the top surface of substrate 720 and perpendicular to the top surface of substrate 720 .

A semiconductor device 700 includes a memory cell array 700M and a circuit section 700D on a substrate 720.
and FIG. 1 shows a transistor 750 included in the circuit portion 700D.

The memory cell array 700M includes a plurality of conductive layers 701 (conductive layers 701_
1 to conductive layers 701_m (m is a natural number of 2 or more), a conductive layer 702, and a plurality of insulating layers 703
(insulating layers 703_1 to 703_3), a plurality of oxide layers 704 (oxide layers 704_
1 to oxide layers 704_3), a plurality of conductive layers 705 (conductive layers 705_1 to 705
_3), a plurality of conductive layers 706 (conductive layers 706_1 to 706_3), a plurality of connection layers 707 (connection layers 707_1 to 707_m), and a plurality of conductive layers 708 (conductive layer 708
_1 to conductive layers 708_m), a plurality of insulating layers 722, an insulating layer 724, and the like.

The conductive layer 701 or the conductive layer 702 and the insulating layer 722 are alternately stacked to form a stacked body including an insulating layer 724 provided to cover them. An insulating layer 703 is provided inside an opening formed to penetrate the stack. Oxide layer 704 is insulating layer 70
3 is provided inside. A conductive layer 705 is provided to be electrically connected to the top end of the oxide layer 704 . A conductive layer 706 is provided to be electrically connected to the bottom edge of the oxide layer 704 . The connection layer 707 is electrically connected to the conductive layer 701 . A conductive layer 708 is electrically connected to the connection layer 707 .

Note that three or more stages of the conductive layers 701 are shown in FIG. 1B in order to show the plurality of conductive layers 701; layer 701
should be provided in two or more stages. In addition, in FIG. 1B and the like, an insulating layer 703 and an oxide layer 704, and a conductive layer 706 and a conductive layer 706 are provided in a plurality of columnar openings arranged in the x direction.
05 and the like, three of these are shown, but the number is not limited to this, and at least two or more may be provided.

Here, as shown in FIGS. 1A and 1B, the conductive layer 701 is provided extending in the x-axis direction. In addition, as shown in FIGS. 1B and 1C, the insulating layer 703 and the oxide layer 704 are provided extending in the z-axis direction. The insulating layer 703 is a columnar oxide layer 704
It is provided so as to surround the side of the In other words, the conductive layer 701, the insulating layer 703, and the oxide layer 704 are preferably provided so as to perpendicularly cross each other. Also, FIG.
, the connection layer 707 is formed in a columnar shape and provided extending in the z-axis direction.
Alternatively, the conductive layer 708 may be extended in the y-axis direction. Further, a conductive layer functioning as a wiring BL connected to the conductive layer 705 may be provided extending in the y-axis direction. Note that the conductive layer 70
5 may function as the wiring BL, and the conductive layer may be provided extending in the y-axis direction.

The columnar oxide layer 704 is electrically connected to the conductive layer 706 at the lower end in the z-axis direction,
It is electrically connected to the conductive layer 705 at its upper end. In addition, as shown in FIG. 1C, the conductive layer 706 is electrically connected to the lower ends of two adjacent columnar oxide layers 704, and the upper ends of the two columnar oxide layers 704 are respectively It is electrically connected to the electrically isolated conductive layer 705 .

Here, the vicinity of a region where the conductive layer 701, the insulating layer 703, and the oxide layer 704 intersect functions as a memory transistor (memory transistor 710). Also, the conductive layer 70
2, the insulating layer 703 and the oxide layer 704 intersect with the selection transistor (
bit line side select transistor: SDT or source line side select transistor: SST). The channel length directions of these memory transistors and select transistors are parallel to the z-axis. Memory transistors or select transistors are electrically connected in series and constitute a memory string.

Note that the configuration of the semiconductor device shown in this embodiment is an example, and the present invention is not limited to the number, arrangement, etc. of circuit elements, wiring, etc. shown in the drawings and the like according to this embodiment. . The number, arrangement, and the like of circuit elements, wirings, and the like included in the semiconductor device according to this embodiment can be appropriately set according to the circuit configuration and the driving method.

The substrate 720 provided with the memory cell array 700M and the circuit portion 700D preferably has an insulating surface. As the substrate having an insulating surface, a semiconductor substrate having an insulating film formed thereon, an insulating substrate, a conductive substrate having an insulating film formed thereon, or the like may be used. As the semiconductor substrate, for example, a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like may be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, or the like may be used. A semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, may also be used. As the conductive substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like may be used.

Conductive layer 701 functions as a gate of memory transistor 710 and is electrically connected to a word line. That is, the conductive layer 701, the connection layer 707, and the conductive layer 708 also function as part of the word line. Here, as shown in FIG. 1B, the conductive layer 701 is preferably provided in a stepped manner in which the lower conductive layer 701 extends from the upper conductive layer 701 toward the A2 side. By providing the conductive layer 701 in this way, a part of the upper surface of the lower conductive layer 701 does not overlap with the upper conductive layer 701, so that the regions of the conductive layer 701 and the connection layers 707 are separated from each other. can be connected.

As the conductive layer 701, a conductive material such as silicon or metal can be used. When silicon is used for the conductive layer 701, amorphous silicon or polysilicon can be used. In addition, a p-type impurity or an n-type impurity may be added in order to impart conductivity to silicon. As a conductive material containing silicon, silicide containing titanium, cobalt, or nickel can be used for the conductive layer 701 . When a metal material is used for the conductive layer 701, aluminum, chromium, copper, silver, gold, platinum, tantalum,
A material containing one or more metal elements selected from nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used.

The conductive layer 702 is provided over the conductive layer 701 with the insulating layer 722 interposed therebetween. Conductive layer 702
functions as the gate of the select transistor (bit line side select transistor: SDT and source line side select transistor: SST). A material similar to that of the conductive layer 701 can be used for the conductive layer 702 . For the conductive layer 702, the same material as that of the conductive layer 701 may be used, or a different material may be used. The conductive layer 701 and the conductive layer 702 may be determined in consideration of the work function and the like depending on the application.

As the insulating layer 722 provided in an upper layer or a lower layer of the conductive layers 701 and 702, an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, or metal oxynitride is used. Objects can be used. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon- and nitrogen-added silicon oxide, or vacant silicon oxide or resin has a relative dielectric It is preferred for use in the insulating layer 722 due to its low modulus.

On the other hand, as the insulating layer 722, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, and an oxide containing silicon and hafnium Nitride or nitride containing silicon and hafnium can also be used, but these have high dielectric constants, so parasitic capacitance is generated between the two conductive layers 701 or between the conductive layers 701 and 702 . may occur. Therefore, the material used for the insulating layer 722 can be determined according to the device design and application.

For the insulating layer 724 that covers the conductive layers 701, 702, and the like, a material similar to that of the insulating layer 722 can be used.

An oxide layer 704, an insulating layer 703, and a conductive layer 701 (conductive layers 701_1 to 701
01_m) constitute the memory transistor 710 . FIG. 1(B),
(C) shows an example in which memory transistors 710 are stacked in m stages (m is a natural number of 2 or more).

Conductive layer 705 is electrically connected to oxide layer 704 and is connected to source line SL or bit line B
Acts as part of L. A conductive material containing a metal element is preferably used for the conductive layer 705 . A metal compound layer containing the metal element of the conductive layer 705 and the components of the oxide layer 704 is preferably formed at the interface between the conductive layer 705 and the oxide layer 704 . Formation of the metal compound is preferable because the contact resistance between the conductive layer 705 and the oxide layer 704 is reduced. Alternatively, the conductive layer 705 absorbs oxygen contained in the oxide layer 704 to reduce the resistance of the oxide layer 704 in the vicinity of the interface between the conductive layer 705 and the oxide layer 704 . contact resistance with the material layer 704 can be reduced.

A conductive material containing one or more metal elements selected from aluminum, ruthenium, titanium, tantalum, chromium, tungsten, and copper is preferably used for the conductive layer 705 .

As shown in FIG. 1C, the conductive layer 706 includes an oxide layer 704 electrically connected to the conductive layer 705 functioning as part of the bit line BL, and a conductive layer functioning as part of the source line SL. A memory string is configured by electrically connecting to an oxide layer 704 that is electrically connected to 705 . A region surrounded by a dashed line in FIG. 1A represents one memory string. Although three memory strings are clearly shown in FIG. 1A, it is preferable that the number of memory strings included in one memory cell array is an even number.
ⁿ (n is a natural number of 1 or more) is more preferable.

A material similar to that of the conductive layer 705 can be used for the conductive layer 706 . Also, the conductive layer 70
6 may use the same material as the conductive layer 705, or may use a different material.

At the interface between the conductive layer 706 and the oxide layer 704, a metal element included in the conductive layer 706 and
It is preferable that a metal compound layer containing the components of the oxide layer 704 is formed. Formation of the metal compound is preferable because the contact resistance between the conductive layer 706 and the oxide layer 704 is reduced. Alternatively, the conductive layer 706 absorbs oxygen contained in the oxide layer 704 to reduce the resistance of the oxide layer 704 in the vicinity of the interface between the conductive layer 706 and the oxide layer 704 . contact resistance with the material layer 704 can be reduced.

FIG. 1D shows an enlarged view of one memory transistor 710 and its vicinity.
As shown in FIG. 1D, the insulating layer 703 has an insulating layer 703a, an insulating layer 703b, and an insulating layer 703c. The insulating layer 703a is provided on the conductive layer 701 side, and the insulating layer 703c
is provided on the oxide layer 704 side, and the insulating layer 703b is provided on the insulating layer 703a and the insulating layer 703c.
provided between The insulating layer 703a functions as a gate insulating layer, the insulating layer 703b functions as a charge storage layer, and the insulating layer 703c functions as a tunnel insulating layer.

Here, FIG. 2A shows a perspective view of one memory transistor 710 and its vicinity.

Silicon oxide or silicon oxynitride is preferably used for the insulating layer 703a.
Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, these may be laminated to form the insulating layer 703a.

The insulating layer 703b is preferably formed using a material that functions as a charge storage layer, such as silicon nitride or silicon nitride oxide. Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used.

Silicon oxide or silicon oxynitride is preferably used for the insulating layer 703c.
Alternatively, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium may be used. Alternatively, these layers may be stacked to form the insulating layer 703c. again,
The insulating layer 703c is preferably thinner than the insulating layer 703a. Although the details will be described later, electric charges are transferred between the oxide layer 704 and the insulating layer 702b through the insulating layer 703c when data is written to or erased from the memory transistor. That is, the insulating layer 703
c functions as a tunnel insulating layer.

In particular, when the insulating layer 703 is formed in the opening provided in the stacked body including the conductive layer 701, the conductive layer 702, and the insulating film, the insulating layer 703 formed at the bottom of the opening is changed by dry etching or the like. It must be removed by anisotropic etching. During the anisotropic etching, the insulating layer 703c is exposed to plasma, radicals, gases, chemicals, and the like even on its side surfaces. If the side surface of the insulating layer 703c is damaged by these, a trap center is generated in the insulating layer 703c, which may affect the electrical characteristics of the transistor. In order to suppress the generation of trap centers, the side surfaces of the insulating layer 703c are required to have high resistance to damage due to etching. In this case, the insulating layer 703c is preferably formed using aluminum oxide, a stack of silicon oxide and aluminum oxide, or a stack of silicon oxynitride and aluminum oxide.

The insulating layers 703a, 703b, and 703c can be formed by an ALD method or a CVD method. In addition, the insulating layer 703a, the insulating layer 703b, and the insulating layer 70
In order to prevent contamination of the interface of 3c, it is preferable to continuously form films in the same chamber or by using a multi-chamber film-forming apparatus having a plurality of chambers without exposure to the atmosphere.

A metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide layer 704 . An oxide semiconductor is preferable to a semiconductor made of silicon or the like because the transistor has better on-state characteristics and high mobility.

For example, the oxide layer 704 may be an In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel,
one or more selected from germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.)
It is preferable to use a metal oxide such as Further, as the oxide layer 704, In—Ga oxide, In
-Zn oxide may be used.

2B and 2C show an example in which the oxide layer 704 has a stacked structure.

As shown in FIG. 2B, the memory transistor 710 preferably has an oxide layer 704a provided on the insulating layer 703c side and an oxide layer 704b provided inside the oxide layer 704a. At this time, the oxide layer 704a preferably uses an oxide having a relatively wide energy gap with respect to the oxide layer 704b. Here, an oxide with a wide energy gap is sometimes called a wide gap, and an oxide with a narrow energy gap is sometimes called a narrow gap.

When the oxide layer 704a has a narrow gap and the oxide layer 704b has a wide gap, the energy of the conduction band bottom of the oxide layer 704a is preferably higher than the energy of the conduction band bottom of the oxide layer 704b. Also, in other words, the electron affinity of the oxide layer 704a is preferably smaller than the electron affinity of the oxide layer 704b.

In addition, it is preferable that the oxide layer 704a and the oxide layer 704b are combined with different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide layer 704a, the atomic ratio of the element M among the constituent elements is higher than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide layer 704b. , preferably large. In the metal oxide used for the oxide layer 704a, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide layer 704b. again,
The atomic ratio of In to the element M in the metal oxide used for the oxide layer 704b is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide layer 704a.

In the oxide layer 704a, for example, In:Ga:Zn=1:3:4, In:Ga:Zn=1
:3:2, or In:Ga:Zn=1:1:1 and compositions in the vicinity thereof. In addition, the oxide layer 704b includes, for example, In:Ga:Zn
= 4:2:3 to 4.1, In:Ga:Zn = 1:1:1, or In:Ga:Zn = 5
Metal oxides having a composition of :1:6 and nearby compositions can be used. It is preferable to combine these oxide layers 704a and 704b while satisfying the above atomic ratio relationship. For example, the oxide layer 704a is a metal oxide having a composition of In:Ga:Zn=1:3:4 and its vicinity, and the oxide layer 704b is a metal oxide having a composition of In:Ga:Zn=1:3:4.
Metal oxides having a composition of 4:2:3 to 4.1 and nearby compositions are preferred. The above composition indicates the atomic ratio in the oxide formed on the substrate or the atomic ratio in the sputtering target.

CAAC-OS, which will be described later, is used as the oxide layer 704a, and the oxide layer 704b is used.
It is preferable to use CAC-OS as the CAAC-O as the oxide layer 704a
When using S, the c-axis is preferably oriented parallel to the xy plane, such as that shown in FIG.

Here, the bottom of the conduction band changes smoothly at the junction between the oxide layers 704a and 704b. In other words, it can be said that the bottom of the conduction band at the junction between the oxide layers 704a and 704b continuously changes or continuously joins. In order to achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide layers 704a and 704b.

Specifically, when the oxide layer 704a and the oxide layer 704b contain a common element (main component) other than oxygen, a mixed layer with a low defect level density can be formed. For example, when the oxide layer 704b is an In--Ga--Zn oxide, the oxide layer 704a may be In--
Ga--Zn oxide, Ga--Zn oxide, gallium oxide, or the like may be used. This will
The defect level density at the interface between the oxide layers 704a and 704b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the memory transistor 710 can obtain a high on-current.

As shown in FIG. 2B, the oxide layer 704b is provided so as to be surrounded by the oxide layer 704a. In such a configuration, oxide layer 704 has conductive layers 705 through 70 .
6 or the direction from the conductive layer 706 to the conductive layer 705 (that is, the z-axis direction), the carriers mainly flow in the component having a narrow gap. Therefore, when the above structure is used, high current drivability, that is, large on-current and high field-effect mobility can be obtained in the on state of the transistor.

Further, by providing the oxide layer 704a between the oxide layer 704b and the insulating layer 703c, the oxide layer 704b serving as a carrier path and the insulating layer 703c are not in direct contact with each other.
Formation of trap centers can be suppressed. A trap center formed at the interface between a semiconductor (oxide semiconductor) and an insulating layer traps electrons and shifts the threshold voltage of a transistor in the positive direction. may adversely affect Therefore, a transistor using the oxide is not affected by trap centers in terms of electrical characteristics, and thus can have higher current drivability, that is, a large on-state current and a high field-effect mobility in the on state. Also, the transistor,
And a semiconductor device using the transistor can have high reliability.

In the memory transistor 710 illustrated in FIG. 2D, the oxide layer 704a is provided inside the insulating layers 703a, 703b, and 703c, and the oxide layer 704b is provided inside the oxide layer 704a. , an oxide layer 704c is provided inside the oxide layer 704b. Further, an insulating layer 711 may be embedded inside the oxide layer 704c. Note that the insulating layer 711 is not necessarily provided, and the inside of the oxide layer 704c may be hollow.

The oxide layer 704b is provided so as to be sandwiched between the oxide layer 704a and the oxide layer 704c. At this time, the oxide layer 704c preferably has a wide gap like the oxide layer 704a. By providing the wide-gap oxide layer 704c, carriers flowing through the oxide layer 704 can be confined in the oxide layer 704b, and high current drivability, that is, a large on-state current and a high field effect can be achieved in the on state of the transistor. Mobility can be obtained.

In the case where the insulating layer 711 is provided inside the oxide layer 704 c , the insulating layer 711 is preferably made of a material that can supply oxygen to the oxide layer 704 . By using an oxide containing as little hydrogen or nitrogen as possible for the insulating layer 711 , oxygen can be supplied to the oxide layer 704 in some cases. By supplying oxygen to the oxide layer 704, impurities such as hydrogen and water contained in the oxide layer 704 can be removed, and the oxide layer 704 is highly purified. By using an oxide in which impurities are reduced as much as possible for the oxide layer 704, the memory transistor and the semiconductor device including the transistor can have high reliability.

Alternatively, a material capable of supplying impurities such as hydrogen or nitrogen can be used for the insulating layer 711 . By using an oxide containing hydrogen or nitrogen for the insulating layer 711 , hydrogen or nitrogen can be supplied to the oxide layer 704 in some cases. Supplying hydrogen or nitrogen to the oxide layer 704 may reduce the resistance value of the oxide layer 704 . By lowering the resistance value of the oxide layer 704 to the extent that it does not adversely affect the circuit operation, the memory transistor can be operated with a lower driving voltage. In addition, high current drivability, that is, large on-current and high field effect mobility can be obtained in the ON state of the memory transistor.

FIG. 2D shows a perspective view of a selection transistor (bit line side transistor: SDT or source line side transistor: SST) and its vicinity.

As shown in FIG. 2D, the selection transistor need not be provided with a charge storage layer. Therefore, in the bit line side transistor: SDT and the source line side transistor: SST, only the insulating layer 703a may be provided as the insulating layer 703 without providing the insulating layer 703b and the insulating layer 703c.

Note that although the oxide layer 704 is shown as a single layer in FIG. 2D, it is not limited to this.
The oxide layer 704 may have a two-layer structure, a three-layer structure, or a laminated structure of four or more layers, as exemplified above. An insulating layer 711 may be provided inside the oxide layer 704 .

Note that the opening formed in the laminate in which the memory transistor 710 is provided is the same as in FIG.
) and each figure in FIG. 2, the upper surface is circular, but the shape is not limited to this. In the case of a polygonal shape, the corners may be rounded. In addition, the top surface shape and cross-sectional shape of the insulating layer 703 and the oxide layer 704 change in accordance with the top surface shape and cross-sectional shape of the opening in some cases. Further, the opening may have a shape such that the cross-sectional area of the lower opening (on the conductive layer 706 side) is narrower than the cross-sectional area of the upper opening (on the conductive layer 705 side).

[Connection configuration example]
FIG. 3 is a top view for explaining a memory device 700A in which a plurality of memory cell arrays 700M each having six stages of memory transistors are combined. In addition, in FIG. 3, in order to facilitate the explanation,
Some components are omitted. For example, the selection transistors (bit line side transistor: SDT and source line side transistor: SST) provided on the conductive layer 701 and the conductive layer 702 as their component are omitted. Also, the bit line BL and the source line SL
conductive layer 705 functioning as part of the word line WL and conductive layer 7 functioning as part of the word line WL
08 is indicated by a solid line.

In the memory device 700A, each memory cell array 700M has four memory strings each having six stages of memory transistors.

Different bit lines BL (BL_1 to BL_1 to B
L_4). On the other hand, the end of the memory string on the source line side is connected to the source line S
L and are given a common potential. The source line SL may be grounded or given a constant potential. Further, the potential may be varied according to the operation of the circuit.

The conductive layers 701_1 to 701_6 are electrically connected to different word lines WL. The conductive layers 701_1 to 701_6 on the bit line side are electrically connected to WLa_1 to WLa_6, respectively, and the conductive layers 701_1 to 701_6 on the source line side are electrically connected to WLb_1 to WLb_6, respectively.

Bit lines BL (BL_1 to BL_4) and word lines (WLa_1 to WLa_6
, and WLb_1 to WLb_6), the memory cell array 700M
Any memory transistor in can be selected. Also, writing, reading, erasing, etc. can be performed on the selected memory transistor.

In addition, since each memory string is provided with a selection transistor (not shown), an arbitrary memory cell array 700M within the memory device 700A is selected, and an arbitrary memory transistor within the selected memory cell array 700M is selected. , can be written, read, and erased.

[Circuit part]
At least one or more transistors 750 are provided in the circuit portion 700D. FIGS. 1A and 1B show a transistor 750 as an example of the circuit portion 700D.
The transistor 750 is a transistor in which metal oxide is applied to a semiconductor layer in which a channel is formed and has extremely high withstand voltage.

The transistor 750 includes an oxide layer 751, a conductive layer 752, a conductive layer 753a, and a conductive layer 75.
3b, and an insulating layer 754. FIG. An oxide layer 751 is provided over the insulating layer 724 . An insulating layer 754 is provided over the oxide layer 751 and part of it functions as a gate insulating layer. A conductive layer 752 is provided over the insulating layer 754 and part of it functions as a gate electrode. The conductive layers 753a and 753b are provided in contact with the oxide layer 751, respectively, and function as source and drain electrodes.

Here, the oxide layer 751 is preferably formed by processing the same oxide film as the oxide layer 704 included in the memory transistor 710 . Furthermore, the conductive layers 753a and 753b are preferably formed by processing the same conductive film as the conductive layers 705 and 708 of the memory cell array 700M.

Thus, part of the manufacturing process of the transistor 750 can be combined with the manufacturing process of the memory cell array 700M, so that the memory cell array 700M and the circuit portion 700 can be manufactured at low cost.
D can be formed on the same substrate.

For the insulating layer 754, a material similar to that of the insulating layer 703a can be used.

A material similar to that of the conductive layer 701 or the like can be used for the conductive layer 752 .

Next, an example of connection between the transistor 750 and the memory cell array 700M will be described.

FIG. 4A shows an enlarged view of the transistor 750. FIG. Furthermore, in FIG. 4(A),
A cross-sectional schematic diagram of one word line and one memory string electrically connected to transistor 750 is shown.

In FIG. 4A, an insulating layer 761 having a plurality of openings is provided to cover the transistor 750 . In addition, a plurality of connection layers (connection layer 762, connection layer 7
63, connection layers 764a, connection layers 764b, etc.) are provided. In addition, over the insulating layer 761, a plurality of conductive layers (a conductive layer 765, a conductive layer 766a, and a conductive layer 766b) functioning as wirings are provided.
etc.) are provided.

The conductive layer 753b of the transistor 750 is electrically connected to the conductive layer 766b through the connection layer 764b. In addition, the conductive layer 753a of the transistor 750 and the conductive layer 701 are the connection layer 707, the conductive layer 708, the connection layer 763, the conductive layer 766a, and the connection layer 764a.
are electrically connected via In addition, the conductive layer 705 is electrically connected to the conductive layer 765 through the connection layer 762 .

With such a structure, the transistor 750 and the conductive layer 7 functioning as a word line
01 can be electrically connected.

Here, the transistor 750 illustrated in FIG. 4A includes the oxide layer 7 functioning as a semiconductor layer.
A conductive layer 753a and a conductive layer 753b are provided in contact with part of the top surface and the side surface of 51 . In addition, the insulating layer 754 and the conductive layer 752 correspond to the conductive layer 753a and the conductive layer 753, respectively.
It has a portion overlapping with b. The transistor 750 shown in FIG. 4A has a structure of TGTC
It can be said to be a (Top-Gate-Bottom-Contact) type transistor.

FIG. 4B shows a cross-sectional configuration example that is partly different from that of FIG. 4A.

In the transistor 750 illustrated in FIG. 4B, the edge of the oxide layer 751 is aligned with the edge of the conductive layer 753a or the conductive layer 753b. Further, the oxide layer 751 exists under the conductive layers 753a and 753b, and is formed so that the conductive layers 753a and 753b and the insulating layer 724 are not in contact with each other. With such a configuration, the conductive layer 7
oxygen in the insulating layer 724 can be prevented from diffusing into 53a, the conductive layer 753b, and the like;
A decrease in the amount of oxygen that can be supplied from the insulating layer 724 to the oxide layer 751 can be prevented, and a decrease in conductivity due to oxidation of the conductive layers 753a and 753b can be suppressed.

A structure as shown in FIG.
A stacked film is formed by stacking conductive films to be 3a and a conductive layer 753b, and the stacked film is processed so as to leave a region to be the oxide layer 751. Subsequently, a channel formation region over the oxide layer 751 and a channel formation region are formed. It can be formed by removing part of the overlapping conductive film by etching.

Here, an oxide layer 751 a containing the same oxide as the oxide layer 751 is formed between the conductive layer 708 and the connection layer 707 in some cases. The oxide layer 751 a is the conductive layer 708 and the connection layer 7 .
07, oxygen is extracted from the film by heat applied during the process, and hydrogen is supplied. It's becoming Therefore, it can be said that the provision of the oxide layer 751a has almost no effect of an increase in electrical resistance.

The above is the description of the configuration example.

[Metal oxide]
Metal oxides that can be applied to the oxide layer 704, the oxide layer 751, and the like described in the above structural examples are described below.

The metal oxide preferably contains at least indium or zinc. Indium and zinc are particularly preferred. Also, in addition to them, aluminum, gallium,
It preferably contains yttrium, tin, or the like. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

Consider here the case where the metal oxide is an In-M-Zn oxide with indium, the element M and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M,
A plurality of the aforementioned elements can also be combined.

In this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide (metal ox
ide) in some cases. In addition, a metal oxide containing nitrogen is a metal oxynitride (me
tal oxynitride).

[Structure of Metal Oxide]
CAC (C
Loud-Aligned Composite)-OS configuration will be described.

In this specification and the like, CAAC (c-axis aligned crystal
l), and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in a part of the material, and a semiconductor function in the whole material. Note that when CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the conductive function is to flow electrons (or holes) that serve as carriers, and the insulating function is to serve as carriers. It is a function that does not flow electrons. A switching function (On/Off
function) can be given to CAC-OS or CAC-metal oxide. By separating each function in CAC-OS or CAC-metal oxide, both functions can be maximized.

CAC-OS or CAC-metal oxide also has a conductive region and an insulating region. The conductive regions have the above-described conductive function, and the insulating regions have the above-described insulating function. In some materials, the conductive region and the insulating region are separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected like a cloud with its periphery blurred.

Further, in CAC-OS or CAC-metal oxide, the conductive region and
The insulating region is 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.
It may be dispersed in the material with a size of m or less.

Also, CAC-OS or CAC-metal oxide is composed of components having different bandgaps. For example, CAC-OS or CAC-metal ox
The ide is composed of a component having a wide gap resulting from an insulating region and a component having a narrow gap resulting from a conductive region. In the case of this configuration, when the carriers flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having a narrow gap acts complementarily on the component having a wide gap, and carriers also flow into the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, high current drivability, that is, large on-current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide is a matrix composite or a metal matrix composite.
It can also be called a matrix composite).

[Structure of Metal Oxide]
Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS (c-
axis aligned crystal oxide semiconductor
ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox
ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS
: amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

CAAC-OS has a c-axis orientation and a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction. The strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagons and may have non-regular hexagons. Also, the distortion may have a lattice arrangement of pentagons, heptagons, and the like. In CAAC-OS, it is difficult to confirm clear crystal grain boundaries (also called grain boundaries) even in the vicinity of strain. That is, it can be seen that the distortion of the lattice arrangement suppresses the formation of grain boundaries. This is because the CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. It's for.

CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as a (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is substituted with indium, (In, M, Zn
) layer. Further, when indium in the In layer is replaced with the element M, (In,
M) can also be expressed as a layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, in CAAC-OS, since it is difficult to confirm a clear crystal grain boundary, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. In addition, since the crystallinity of metal oxides may be degraded by contamination of impurities and generation of defects, CAAC-OS is capable of preventing impurities and defects ( _oxygen v
It can also be said that it is a metal oxide with little acancy). Therefore, CAAC-
A metal oxide having an OS has stable physical properties. Therefore, a metal oxide containing CAAC-OS is heat resistant and highly reliable.

The nc-OS has periodic atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Also, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, an nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

An a-like OS is a metal oxide having a structure between an nc-OS and an amorphous oxide semiconductor. An a-like OS has void or low density regions. That is, a-li
ke OS is less crystalline compared to nc-OS and CAAC-OS.

Oxide semiconductors (metal oxides) have various structures, each of which has different characteristics.
An oxide semiconductor of one embodiment of the present invention includes an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, and an a-li semiconductor.
It may have two or more of ke OS, nc-OS, and CAAC-OS.

[Transistor Containing Metal Oxide]
Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described.

Note that by using the above metal oxide for a channel formation region of a transistor, a transistor with high field-effect mobility can be realized. Further, a highly reliable transistor can be realized.

A metal oxide with low carrier density is preferably used for a transistor. In order to lower the carrier density of the metal oxide film, the impurity concentration in the metal oxide film should be lowered to lower the defect level density. In this specification and the like, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the metal oxide has a carrier density of less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and a carrier density of 1×10 ⁻⁹ /cm 3 . cm ³ or more.

In addition, since a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low defect level density, the trap level density may also be low.

In addition, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave like a fixed charge. Therefore, a transistor including a metal oxide with a high trap level density in a channel formation region may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. Also, in order to reduce the impurity concentration in the metal oxide,
It is preferable to reduce the impurity concentration in adjacent films as well. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

〔impurities〕
Here, the effect of each impurity in the metal oxide will be described.

If the metal oxide contains silicon or carbon, which is one of the Group 14 elements, a defect level is formed in the metal oxide. For this reason, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide (secondary ion mass spectrometry (SIM)
S: concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms/cm ³ or less, preferably 2 × 10 ¹⁷ atoms
/cm ³ or less.

Further, if the metal oxide contains an alkali metal or an alkaline earth metal, it may form a defect level and generate carriers. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region tends to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

In addition, when nitrogen is contained in the metal oxide, electrons as carriers are generated, the carrier density increases, and the metal oxide tends to be n-type. As a result, a transistor using a metal oxide containing nitrogen for a channel formation region tends to have normally-on characteristics. Therefore, nitrogen in the channel formation region in the metal oxide is preferably reduced as much as possible.
For example, the nitrogen concentration in the metal oxide is 5×10 ¹⁹ atoms/cm in SIMS.
Less than ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸
atoms/cm ³ or less, more preferably 5×10 ¹⁷ atoms/cm ³ or less.

In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor using a metal oxide containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably 1×10 ¹⁹
It is less than atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , still more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, off-state current of the transistor can be reduced and stable electrical characteristics can be imparted to the transistor.

[Example of manufacturing method]
An example of a method for manufacturing the semiconductor device 700 illustrated in FIGS.
7 for explanation. 5 to 17, (A) is a top view seen from the z-axis direction, (B) is a cross-sectional view of the part indicated by the dashed line A1-A2 in (A), (
C) is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in (A).

First, a conductive layer 706 is formed over a substrate 720 having an insulating surface, and an insulating film 721 is formed to cover the conductive layer 706 (see FIG. 5).

The conductive layer 706 can be formed by first forming a conductive film to be the conductive layer 706 and then processing the conductive layer 706 by a lithography method. However, the conductive layer 706 and the insulating film 7
The formation method of 21 is not limited to this. An insulating film 721 is formed over a substrate 720 and the insulating film 721 is
A groove or opening may be formed by removing an unnecessary portion of , and the conductive layer 706 may be embedded in the groove or the opening. Such a method of forming a conductive layer is sometimes called a damascene method (single damascene method, dual damascene method). A conductive layer 706 formed by the damascene method
, and another insulating film over the insulating film 721, the structure shown in FIG. 5 can be obtained.

The conductive layer 706 and the insulating film 721 are formed by sputtering, chemical vapor deposition (CVD:
Chemical Vapor Deposition) method, molecular beam epitaxy (MB
E: Molecular Beam Epitaxy) method, pulsed laser deposition (PLD:
Pulsed Laser Deposition) method or ALD (Atomic L
Ayer Deposition) method or the like can be used.

The CVD method is a plasma CVD (PECVD: Plasma
Enhanced CVD) method, thermal CVD using heat (TCVD: Thermal C
VD) method, photo CVD (Photo CVD) method using light, and the like. Furthermore, depending on the raw material gas used, metal CVD (MCVD: Metal CVD) method, organic metal CVD
(MOCVD: Metal Organic CVD) method.

The plasma CVD method can obtain high quality films at relatively low temperatures. Moreover, since the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, a thermal CVD method that does not use plasma does not cause such plasma damage, so that the yield of semiconductor devices can be increased. Moreover, since the thermal CVD method does not cause plasma damage during film formation, a film with few defects can be obtained.

The ALD method is also a film forming method capable of reducing plasma damage to the object to be processed. Also, the ALD method does not cause plasma damage during film formation, so that a film with few defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of the object to be processed, unlike film forming methods in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method which is not easily affected by the shape of the object to be processed and which has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method, such as the CVD method, which has a high film formation rate.

In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, it is possible to form a film of any composition depending on the flow rate ratio of source gases. Further, for example, in the CVD method and the ALD method, it is possible to form a film whose composition is continuously changed by changing the flow rate ratio of the source gases while forming the film. When film formation is performed while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened by the time required for transportation and pressure adjustment, compared to the case where film formation is performed using a plurality of film formation chambers. In some cases, the productivity of semiconductor devices can be improved.

Note that in the lithography method, first, the resist is exposed through a photomask. The exposed regions are then removed or left behind using a developer to form a resist mask.
Next, the conductive film, the semiconductor film, the insulating film, or the like can be processed into a desired shape by etching treatment through the resist mask. For example, KrF excimer laser light, Ar
A resist mask may be formed by exposing the resist using F excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Also, an electron beam or an ion beam may be used instead of the light described above. A mask is not necessary when using an electron beam or an ion beam. Note that the resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.

Alternatively, a hard mask made of an insulating film or a conductive film may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film as a hard mask material is formed on the conductive film, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. be able to.

A dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing.

As a dry etching device, a capacitively coupled plasma (CCP) having parallel plate electrodes is used.
: Capacitively Coupled Plasma) etching equipment can be used. A capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, a plurality of different high-frequency power sources may be applied to one of the parallel plate electrodes. Alternatively, a high-frequency power source of the same frequency may be applied to each parallel plate type electrode. Alternatively, a configuration in which high-frequency power sources with different frequencies are applied to the parallel plate electrodes may be used. Alternatively, a dry etching apparatus having a high density plasma source can be used. A dry etching apparatus having a high-density plasma source is, for example, an inductively coupled plasma (ICP).
ed Plasma) etc. can be used.

In the case of using a hard mask for etching the conductive film, the etching treatment may be performed after removing the resist mask used for forming the hard mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. After etching the conductive film, the hard mask may be removed by etching. on the other hand,
If the hard mask material does not affect the post-process or can be used in the post-process, it is not necessary to remove the hard mask.

A conductive film to be the conductive layer 706 is preferably formed using a sputtering method using a conductive film containing a metal element. It can also be formed using a CVD method.

The surface of the insulating film 721 is preferably subjected to planarization treatment as necessary. A chemical mechanical polishing (CMP) method or a reflow method can be used for the planarization treatment.

Subsequently, a conductive film 701 A and an insulating film 722 A are alternately stacked over the insulating film 721 .
Although an example in which the conductive film 701A is formed over the insulating film 721 and the insulating film 722A is formed over the conductive film 701A in this embodiment mode, the order of formation is not limited to this. An insulating film 722A may be formed over the insulating film 721, and a conductive film 701A may be formed over the insulating film 722A. A CVD method can be used for forming the conductive film 701A and the insulating film 722A. again,
A sputtering method may also be used.

Further, in this embodiment mode, the number of layers of the conductive film 701A and the insulating film 722A is not limited. Two or more layers can be formed for each layer depending on the required performance of the semiconductor device. For example, the conductive film 701A and the insulating film 722A may each have 16 layers, 32 layers, 64 layers, or 128 layers, or 200 layers or more.

Subsequently, a conductive film 702A is formed over the insulating film 722A located on the uppermost side. after that,
A mask 723 is formed over the conductive film 702A (see FIG. 6). The conductive film 702A can be formed using a method and a material similar to those of the conductive film 701A. Note that the conductive film 702A may be formed by the same method as the conductive film 701A, or may be formed by a different method. Further, the conductive film 702A may be made of the same material as the conductive film 701A, or may be made of a different material.

Next, the conductive film 702A, the conductive film 701A, and the insulating film 722A are processed, and FIG.
A stepped conductive film 701B, a conductive film 702B, and an insulating film 722B are formed as shown in FIG. In processing the conductive film 702A, the conductive film 701A, and the insulating film 722A, the conductive film 7
02A, the conductive film 701A, and the insulating film 722A are alternately etched and the mask 723 is slimmed, so that the stepped conductive film 701B, the conductive film 702B, and the insulating film 72 are formed.
2B can be formed. Conductive film 702A, conductive film 701A, and insulating film 722A
7, the width and thickness of the mask 723 are reduced to form a mask 723A (see FIG. 7).

Next, the mask 723A is removed and an insulating layer 724 is formed. The insulating layer 724 can be formed using a CVD method. The insulating layer 724 is preferably planarized by a CMP method or a reflow method. Subsequently, a mask 725 is formed over the insulating layer 724 (see FIG. 8). Forming a mask 725 over the planarized insulating layer 724 is preferable because it improves lithography accuracy.

Next, the insulating layer 724, the conductive film 702B, the conductive film 701B, the insulating film 722B, and the insulating film 721 are processed using the mask 725 (see FIG. 9). By this processing, a conductive layer 701 functioning as the gate of the memory transistor and electrically connected to the word line, and a conductive layer 702 functioning as the gate of the selection transistor are formed. Also, the insulating film 722B becomes the insulating layer 722 by the processing.

After that, the mask 725 is removed. Next, an insulating layer 726 is formed so as to bury the portion removed by the above processing. The insulating layer 726 can be formed using a CVD method or an ALD method. In particular, the use of the ALD method is preferable because a film having a uniform thickness can be formed even in trenches and openings with a large aspect ratio. Or, ALD method and CV
The insulating layer 726 may be formed by combining the D methods. The insulating layer 726 is preferably planarized by a CMP method or a reflow method. In the case of performing planarization treatment using a CMP method, the insulating layer 726 may be polished until the surface of the insulating layer 724 is exposed. Alternatively, the insulating layer 724 and the insulating layer 726 may be polished together to the extent that the insulating layer 724 does not disappear.

Next, the insulating layer 724 is processed by a lithography method to form a first opening so that the conductive layer 701 is exposed (see FIG. 10). The first opening is the conductive layer 7 formed stepwise.
01 for each. Although not shown, it is preferable to form an opening through which the conductive layer 702 is exposed at the same time.

Next, a connection layer 707 is formed so as to fill the first opening. The connection layer 707 is C
It can be formed using a VD method or an ALD method. In particular, the thermal CVD method or the ALD method is preferable because a film having a uniform thickness can be formed even in a trench or an opening having a large aspect ratio. Alternatively, the connection layer 707 may be formed by combining CVD and ALD methods. Moreover, the connection layer 707 may have a laminated structure including a plurality of layers. The connection layer 707 can be formed by forming a conductive film to be the connection layer 707 over the insulating layer 724 and inside the first opening, and removing unnecessary conductive films by CMP or the like.

Next, an insulating layer 724, a conductive layer 702, a conductive layer 701, an insulating layer 722, and an insulating film 72 are formed.
1 is processed by lithography to form a second opening to expose the conductive layer 706 (see FIG. 11).

Next, the insulating layer 703 is formed on the insulating layer 724 and the connection layer 707 and inside the second opening.
An insulating film 703A is formed (see FIG. 12). Although not shown, the insulating film 703A
can be formed by sequentially stacking an insulating film to be the insulating layer 703a, an insulating film to be the insulating layer 703b, and an insulating film to be the insulating layer 703c. The insulating film 703A can be formed using the CVD method or the ALD method. In particular, the use of the ALD method is preferable because a film having a uniform thickness can be formed even in trenches and openings with a large aspect ratio. or A
The insulating film 703A may be formed by combining the LD method and the CVD method. An insulating film to be the insulating layer 703a, an insulating film to be the insulating layer 703b, and an insulating film to be the insulating layer 703c may be formed by the same film forming apparatus or by different film forming apparatuses. Note that the insulating layer 70
The insulating film to be the insulating layer 703c is thinner than the insulating layer 703c so that the insulating layer 703c is thinner than the insulating layer 703a.
It is preferable to form it thinner than the insulating film which becomes 03a.

Next, the insulating film 703A formed on the bottom of the second opening is removed to obtain the insulating layer 703 (see FIG. 13). Anisotropic etching is preferably used to remove the insulating film 703A. At this time, the insulating layer 724 and the insulating film 703A on the connection layer 707 are also removed, so that the insulating layer 703 is provided only on the side walls of the second opening. By removing the insulating film 703A at the bottom of the second opening, the conductive layer 706 is exposed again.

Here, as shown in FIG. 13D, of the insulating layer 703 located above the second opening,
It is preferable to remove the insulating layer 703b and the insulating layer 703c. FIG. 13(D) is an enlarged view of a portion surrounded by a dashed line in FIG. 13(B). First, a sacrificial layer 727 that can be easily removed in a post-process is formed so as to be embedded in the inside of the second opening, and is removed by etching or the like to a desired depth inside the second opening. The insulating layer 703 exposed by the etching
By sequentially removing the insulating layer 703c and the insulating layer 703b, the insulating layer 703 located in the horizontal direction (xy direction) of the conductive layer 702 can be only the insulating layer 703a. In this case, the gate insulating films of the select transistors SST and SDT are composed of the insulating layer 703a. After removing the insulating layer 703c and the insulating layer 703b, the sacrificial layer 727 is removed.

Next, an oxide film 704A is formed inside the second opening and on the insulating layer 724 (see FIG. 14).
reference). The oxide film 704A is a film that becomes the oxide layer 704 and the oxide layer 751 later.
Here, when the oxide film 704A is a laminated film, two or three layers of oxide films may be sequentially formed. At this time, an oxide layer 751 applied to the transistor 750 can also have a similar stacked structure.

The oxide film 704A can be formed using a CVD method, an ALD method, or a sputtering method. In particular, the use of the ALD method is preferable because a film having a uniform thickness can be formed even in trenches and openings with a large aspect ratio. Alternatively, the oxide film 704A may be formed by combining two or more of the ALD method, the sputtering method, and the CVD method. When the oxide film 704A is a stacked film, the oxide film to be the oxide layer 704a and the oxide film to be the oxide layer 704b, or the oxide film to be the oxide layer 704a and the oxide layer 704b are used.
An oxide film to be 04b and an oxide film to be the oxide layer 704c are sequentially formed. Here, different oxide films may be formed by the same film forming apparatus, or may be formed by different film forming apparatuses.

Further, an insulating layer 711 may be formed inside the oxide film 704A. The insulating layer 711 is
It can be formed by a CVD method, an ALD method, or the like. The insulating layer 711 is the oxide layer 7 in accordance with the characteristics required for the memory transistor and the semiconductor device having the memory transistor.
A material that supplies oxygen to 04 or a material that supplies hydrogen can be used.

Here, the oxide film 704 A is formed so as to be in contact with the conductive layer 706 . Oxide film 704
When A is in contact with the conductive layer 706, a metal compound layer containing the metal element of the conductive layer 706 and the component of the oxide film 704A is formed at the interface between the conductive layer 706 and the oxide film 704A. There is The formation of the metal compound causes the conductive layer 706 and subsequent oxide layer 704 to
It is preferable because the contact resistance with is reduced. Further, the conductive layer 706 may absorb oxygen contained near the bottom of the oxide film 704A. At this time, the resistance of the oxide film 704A near the interface with the conductive layer 706 is reduced, and the contact resistance between the conductive layer 706 and the subsequent oxide layer 704 is reduced, which is preferable. With the oxide film 704A and the conductive layer 706 in contact,
By performing the heat treatment, the resistance of part of the oxide film 704A is reduced, and the contact resistance between the conductive layer 706 and the oxide layer 704 later is reduced. The heat treatment is performed in an atmosphere containing nitrogen.
It is preferable to carry out at 00° C. or higher and 500° C. or lower, preferably 300° C. or higher and 400° C. or lower.

Subsequently, a mask 731 is formed over the oxide film 704A, and unnecessary portions of the oxide film 704A are etched using the mask 731 (see FIG. 15). Thus, the columnar oxide layer 704 and the thin oxide layer 751 can be formed at the same time. After that, the mask 731 is removed.

Here, when the insulating layer 711 is formed, it is preferable to remove the insulating layer 711 over the oxide layer 751 and the oxide layer 704 by etching after removing the mask 731 .

Subsequently, a conductive film is formed and processed using a lithography method to form a conductive layer 70.
5. A conductive layer 708, a conductive layer 753a, and a conductive layer 753b are formed (see FIG. 16).

Although not shown, the upper portion of the oxide layer 751 may be thinned depending on the etching conditions of the conductive film. Depending on the etching conditions of the conductive film, a portion of the insulating layer 724 which is not covered with the conductive layers 705, 708, 753a, and 753b may be thin.

Subsequently, an insulating film to be the insulating layer 754 and a conductive film to be the conductive layer 752 are sequentially formed and processed by a lithography method to form the insulating layer 754 and the conductive layer 752 (FIG. 17). reference). Through the above steps, the transistor 750 can be formed.

Note that only the conductive film to be the conductive layer 752 may be etched without etching the insulating film to be the insulating layer 754 . At this time, the insulating layer 754 is provided so as to cover the conductive layers 705, 708, and the like.

Note that in the case of forming the transistor illustrated in FIG. 4B, first, the oxide film 704A and
A stacked film is formed by stacking a conductive film to be the conductive layer 753a and the like, and the stacked film is processed so that a region to be the oxide layer 751 and the like are left. After that, part of the conductive film overlapping with the channel formation region over the oxide layer 751 is removed by etching, so that the channel formation region can be formed. Thus, a finer transistor 750 can be manufactured.

In subsequent steps, the insulating layer 761 and the connection layer 762 illustrated in FIG. 4A are formed according to the circuit configuration.
, a connection layer 763, a connection layer 764a, a connection layer 764b, a conductive layer 765, a conductive layer 766a, a conductive layer 766b, and the like are formed. Moreover, an insulating layer, a connection layer, and a conductive layer functioning as a wiring may be further stacked above this.

By fabricating the memory cell array as described above, memory transistors of a plurality of layers can be fabricated collectively without performing pattern formation for fabricating memory transistors for each layer. Furthermore, when fabricating a memory cell array by the above method, even if the number of layers of memory transistors is increased, the number of steps for patterning and etching the memory transistors does not increase. As described above, the number of steps for manufacturing a memory cell array can be shortened, so that a semiconductor device with high productivity can be provided.

Further, by simultaneously forming an oxide layer functioning as a semiconductor layer of a memory cell array and an oxide layer functioning as a semiconductor layer of a transistor, transistors can be placed near the memory cell array while minimizing an increase in the number of steps. can be formed. Further, the process can be further simplified by simultaneously forming the wirings connected to the memory cell array and the source and drain electrodes of the transistors.

The above is the description of the method for manufacturing the semiconductor device.

[Configuration example of storage device]
FIG. 18A shows a configuration example of a NAND-type nonvolatile memory device (3D NAND) with a three-dimensional structure. The memory device 100 shown in FIG. 18A includes a control circuit 105, a memory cell array 1
10, and peripheral circuits.

The control circuit 105 has a function of controlling the entire storage device 100 and performing data writing and data reading. The control circuit 105 processes command signals from the outside and generates control signals for peripheral circuits. FIG. 18A shows a row decoder 12 as a peripheral circuit.
1, row driver 122, sense amplifier 123, source line driver 124, input/output circuit 12
5, a buffer 126 and the like are provided.

The memory cell array 110 has multiple memory strings 112 . FIG. 18B shows a circuit configuration example of the memory string 112 . In the memory string 112, a selection transistor SST and memory transistors MT1 to M are provided between the bit line BL and the source line SL.
T2k (k is an integer equal to or greater than 1) and selection transistor SDT are electrically connected in series.

Note that the memory transistors MT1 to MT2k are referred to as memory transistors MT when they are not distinguished from each other. The same applies to other elements.

The selection transistors SST and SDT and the memory transistors MT1 to MT2k are, as described above, transistors whose channels are formed of metal oxide. The memory transistor MT has a charge storage layer and constitutes a nonvolatile memory cell.

Gates of the select transistors SST and SDT are connected to select gate lines SGL and DGL, respectively.
is electrically connected to Gates of the memory transistors MT1 to MT2k are electrically connected to word lines WL1 to WL2k, respectively. Bit lines BL extend in the column direction, and select gate lines SGL, DGL and word lines WL extend in the row direction.

The input/output circuit 125 temporarily holds data written to the memory cell array 110, temporarily holds data read from the memory cell array 110, and the like.

The source line driver 124 drives the source line SL.

Bit line BL is electrically connected to sense amplifier 123 . The sense amplifier 123 detects and amplifies the voltage read from the memory string 112 to the bit line BL when reading data. Also, when writing data, a voltage corresponding to write data is input to the bit line BL.

Row decoder 121 decodes externally input address data and selects a row to be accessed. The row driver 122 inputs voltages necessary for writing, reading, and erasing data to select signal lines DGL, SGL, and word lines WL according to the decoding result of the row decoder 121 .

Buffer 126 is located between row decoder 121 and word line WL and has a function of stabilizing the voltage applied to word line WL. Moreover, it may have a switching element and have a function as a selector.

An inverter circuit 126a that can be used for the buffer 126 is shown in FIG. The inverter circuit 126a has a configuration in which a transistor M1 and a transistor M2 are connected in series. An input terminal IN to which an input signal is input is connected to the gate of the transistor M1, and an input signal INB to which a signal obtained by inverting the above input signal is input is connected to the gate of the transistor M2. For example, the word line W
L is connected.

A switch circuit 126b that can be used for the buffer 126 is shown in FIG.
The switch circuit 126b has a transistor M3. The gate of the transistor M3 is connected to the input terminal SW, one of its source and drain is connected to the input terminal IN, and the other is connected to the output terminal OUT. A selection signal input to the input terminal SW controls conduction or non-conduction between the input terminal IN and the output terminal OUT.

The high withstand voltage transistor 750 illustrated above can be applied to transistors included in the buffer 126, the row driver 122, the sense amplifier 123, the source line driver 124, and the like, for example. When the transistor 750 is applied to the buffer 126, it can be applied to at least one of the transistor M1 and the transistor M2 of the inverter circuit 126a or the transistor M3 of the switch circuit 126b, for example.

19 to 21 show examples of a three-dimensional stacked structure of the memory cell array 110. FIG. Figure 19 shows
FIG. 3 is a diagram schematically showing an example of a three-dimensional structure of the memory cell array 110 as a circuit diagram; FIG. 20 shows
3 is a perspective view showing an example of a three-dimensional structure of the memory cell array 110; FIG. FIG. 21 is a perspective view showing an example of the three-dimensional structure of the connecting portion between the word line WL and the conductive layer 701. FIG.

As shown in FIG. 19, the memory cell array 110 is stacked in a region where the sense amplifiers 123 are formed. Thereby, the layout area of the memory device 100 can be reduced. Each word line WL is electrically connected to a buffer 126 having a high withstand voltage transistor, and the buffer 126 is electrically connected to a row driver 122 provided therebelow. Although FIG. 19 shows an example in which the row driver 122 is provided below the buffer 126 , part or all of the row driver 122 may be configured with high-voltage transistors and arranged side by side with the buffer 126 .

20 and 21, among the conductive layers 701 on the same level, the conductive layer 701a on the bit line BL side is connected to the word line WLa, and the conductive layer 701b on the source line SL side is connected to the word line WLb. be. 19 to 21 show an example in which eight memory transistors MT1 to MT8 are provided for one memory string 112. FIG.

Here, an example in which the memory cell array 110 has the memory string 112 to which the memory transistor having the charge storage layer is applied has been described above. Examples of such memory transistors include transistors having a MONOS structure, transistors having a SONOS structure, and transistors having a floating gate structure.

Note that memory cells that can be applied to the memory cell array 110 are not limited to this. Figure 22 (
A) and (B) show examples of circuit diagrams of memory cells having different configurations.

Two memory cells 131 are shown in FIG. The memory cell 131 has a transistor M and a capacitor C. A word line WL1 or a word line WL2, a bit line BL, and a wiring PL to which a predetermined potential is applied are connected to the memory cell 131 .

The transistor M has a gate connected to the word line WL1 or the word line WL2, one of the source and the drain connected to the bit line BL, and the other of the source and the drain connected to the capacitive element C.
to one electrode of the The other electrode of the capacitive element C is connected to the wiring PL.

By accumulating charge in the capacitor C, the memory cell 131 can hold data.

When a transistor including an oxide semiconductor and having extremely low off-state current is used as the transistor M, the data retention period can be significantly longer than in the case of using a transistor including silicon. Therefore, the frequency of refresh operations can be reduced, so that a memory cell with extremely low power consumption can be realized.

Two memory cells 132 are shown in FIG. The memory cell 132 includes a transistor M1, a transistor M2, and a capacitor C. The memory cell 132 includes a word line WL1 or a word line WL2, a bit line BL, a wiring SL1 or a wiring SL2 functioning as a selection signal line, and a wiring RL1 or a wiring R functioning as a read signal line.
A wiring PL to which a predetermined signal is applied is connected to L2.

The transistor M1 has a gate connected to the word line WL1 or the word line WL2, one of the source and the drain connected to the bit line BL, and the other of the source and the drain connected to one electrode of the capacitor C and the gate of the transistor M2. Connecting. One of the source and the drain of the transistor M2 is connected to the wiring SL1 or the wiring SL2, and the other of the source and the drain is connected to the wiring RL1 or the wiring RL2. The other electrode of the capacitive element C is the wiring PL
Connect with

The memory cell 132 can hold data by holding the potential of the node to which the gate of the transistor M2 is connected. In addition, since the conduction state of the transistor M2 changes depending on the potential applied to the transistor M2, the current flowing between the wiring SL1 (or the wiring SL2) and the wiring RL1 (or the wiring RL2) can be detected to prevent destruction. You can read the data with

When a transistor including an oxide semiconductor and having extremely low off-state current is used as the transistor M1, the data retention period can be significantly longer than in the case of using a transistor including silicon. A transistor using single crystal silicon is preferably used as the transistor M2.

[Regarding the circuit operation of the storage device]
Next, the data write and read operations to the memory string 112 will be described with reference to FIG.
Description will be made using (A) to (C). A group of memory transistors MT sharing the word lines WL1 to WL2k is hereinafter referred to as a page.

Although FIGS. 23A to 23C show an example in which the memory string 112 has memory transistors MT1 to MT8, the number of memory transistors MT is not limited to this.

[Erase operation]
When writing data to the memory transistor MT, it is preferable to erase the data before the write operation. Note that the operation of erasing data may also be referred to as a reset operation. The erase operation is performed for each memory string 112 (also called block). For example, a block whose data is to be erased is selected, and word lines WL1 to W are erased as shown in FIG.
A low potential (a potential at which the memory transistors MT1 to MT8 are non-conductive, for example 0V) is applied to L8.
), the erase potential VE is applied to the source line SL and the bit line BL, and the selection transistor SDT and the selection transistor SST are turned on. The reset operation can extract electrons accumulated in the respective charge accumulation layers of the memory transistors MT1 to MT8. As a result, the memory transistors MT1 to MT8 are in a state of holding data "1".

It is preferable to store the data of the memory transistors MT, which are not to be rewritten, in another memory area before the block erase operation.

[Write operation]
First, a data write operation is described with reference to FIG.

The data write operation can be performed for each page as described above. First, a write potential (eg, 15 V) is applied to the word line of the page to be written, and a positive potential (the potential at which the transistor becomes conductive, eg, 3 V) is applied to the word line of the page not to be written. Here, as shown in FIG. 23B, first, a write potential is applied to the word line WL1, and a positive potential is applied to the word lines WL2 to WL8. Then, the select transistor SST is rendered non-conductive, and the select transistor SDT is rendered conductive. By doing so, data corresponding to the potential of the bit line BL is written to the memory transistor MT1. Specifically, the bit line BL
is a low potential (for example, 0 V), electrons are injected into the charge storage layer of the memory transistor MT1 due to an increase in potential difference from the write potential applied to the word line WL1. Also, when the potential of the bit line BL is positive, the potential difference from the write potential applied to the word line WL1 becomes small, so electrons are not injected into the charge storage layer of the memory transistor MT1. That is, when a low potential is applied to the bit line BL, data "0" is written in the memory transistor MT1, and when a positive potential is applied, the data in the memory transistor MT1 cell remains "1". .

Here, by applying a different potential to each memory string 112 to the bit line BL,
Data can be written page by page.

Note that multi-valued data can also be written to the memory transistor MT. For example, the amount of charge injected into the charge storage layer of the memory transistor may be controlled by the potential of the bit line BL or the like and the time for applying the potential.

[Read operation]
Next, a data reading operation is described with reference to FIG.

Data read operations can also be performed page by page. First, a low potential (for example, 0 V) is applied to the word line of the page to be read, and a positive potential (the potential at which the transistor becomes conductive, for example, 3 V) is applied to the word line of the page not to be read. Here, FIG. 23 (
As shown in C), first, a low potential is applied to word line WL1, and word lines WL2 to WL8 are applied.
apply a positive potential to Then, the select transistor SST and the select transistor SST are turned on. Also, a read potential (eg, 1 V) is applied to the bit line BL, and a low potential (eg, 0 V) is applied to the source line SL. At this time, the memory transistor
If the data is 1", a current flows through the memory string 112 and the potential of the bit line BL drops. If the data stored in the memory transistor MT1 is "0", no current flows through the memory string 112 and the bit line BL becomes The potential does not change, and the sense amplifier 123 connects the bit line BL
, and amplifies it. As described above, the data in the memory string 112 can be read.

Here, by reading the data of each memory string 112 to the bit line BL, the data can be read in page units.

The above is the description of the circuit operation of the storage device.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 2)
In this embodiment, an application example of a memory device using the semiconductor device described in any of the above embodiments will be described. The semiconductor devices described in the above embodiments are, for example, storage devices of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/reproducing devices, navigation systems, etc.). can be applied to note that,
Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in any of the above embodiments may be a memory card (for example, S
D card), USB memory, SSD (Solid State Drive), and various other removable storage devices. FIG. 24 schematically shows some configuration examples of the removable storage device. For example, the semiconductor devices described in the previous embodiments are processed into packaged memory chips and used for various storage devices and removable memories.

FIG. 24A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101
, cap 1102 , USB connector 1103 and substrate 1104 . substrate 110
4 is housed in a housing 1101 . For example, substrate 1104 includes memory chip 110
5. The controller chip 1106 is installed. Memory chip 1 on substrate 1104
105 or the like can incorporate the semiconductor device described in the above embodiment.

FIG. 24B is a schematic diagram of the appearance of the SD card, and FIG. 24C is a schematic diagram of the internal structure of the SD card. SD card 1110 has housing 1111 , connector 1112 and substrate 1113 . A substrate 1113 is housed in a housing 1111 . For example, substrate 11
13, a memory chip 1114 and a controller chip 1115 are attached.
By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Alternatively, a wireless chip having a wireless communication function may be provided on the substrate 1113 . As a result, data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110 . The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 of the substrate 1113 or the like.

FIG. 24D is a schematic diagram of the appearance of the SSD, and FIG. 24E is a schematic diagram of the internal structure of the SSD. SSD 1150 has housing 1151 , connector 1152 and substrate 1153 . A substrate 1153 is housed in a housing 1151 . For example, substrate 1153 has memory chip 1154 , memory chip 1155 and controller chip 1156 attached thereto. A memory chip 1155 is a work memory for the controller chip 1156,
For example, a DRAM chip may be used. A memory chip 1154 is also provided on the back side of the substrate 1153 .
By providing the , the capacity of the SSD 1150 can be increased. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 of the substrate 1153 or the like.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 3)
In this embodiment, FIG. 25 is used to describe an A
The I system will be explained.

FIG. 25 is a block diagram showing a configuration example of the AI system 4041. As shown in FIG. AI system 404
1 has a calculation unit 4010 , a control unit 4020 and an input/output unit 4030 .

The arithmetic unit 4010 includes an analog arithmetic circuit 4011, a DOSRAM 4012, a NOSR
It has AM4013, FPGA4014 and 3D-NAND4015.

Here, DOSRAM (registered trademark) means "Dynamic Oxide Semi
It is an abbreviation for "conductor RAM" and refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells.

NOSRAM (registered trademark) is a nonvolatile oxide sem
It is an abbreviation for “iconductor RAM” and refers to a RAM having gain cell type (2T type, 3T type) memory cells. DOSRAMs and NOSRAMs are memories that take advantage of low off-state current of a transistor using an oxide as a semiconductor (hereinafter referred to as an OS transistor). Note that, hereinafter, a memory device using an OS transistor, such as a NOSRAM, may be referred to as an OS memory.

The control unit 4020 is a CPU (Central Processing Unit) 40
21, GPU (Graphics Processing Unit) 4022, P
LL (Phase Locked Loop) 4023 and SRAM (Static R
Android Access Memory) 4024 and PROM (Programma
ble Read Only Memory) 4025 and a memory controller 4026
, a power supply circuit 4027 , and a PMU (Power Management Unit) 40
28 and .

The input/output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, a video codec 4033, a general-purpose input/output module 4034, a communication module 4035,
have

The computing unit 4010 can perform learning or inference by a neural network.

The analog arithmetic circuit 4011 has an A/D (analog/digital) conversion circuit, a D/A (digital/analog) conversion circuit, and a sum-of-products arithmetic circuit.

The analog arithmetic circuit 4011 is preferably formed using an OS transistor. OS
The analog arithmetic circuit 4011 using transistors has an analog memory and can perform sum-of-products calculation required for learning or inference with low power consumption.

A DOSRAM 4012 is a DRAM formed using an OS transistor, and a DO
The SRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021 . The DOSRAM 4012 includes memory cells including OS transistors and Si
It has a read circuit section including a transistor. Since the memory cells and the readout circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the overall circuit area.

Calculations using neural networks may have more than 1000 input data.
When the input data is stored in the SRAM, the SRAM has a limited circuit area and a small storage capacity, so the input data must be divided and stored. DOSRAM401
2 is capable of arranging memory cells in a highly integrated manner even in a limited circuit area;
Larger storage capacity than M. Therefore, the DOSRAM 4012 can efficiently store the input data.

A NOSRAM 4013 is a nonvolatile memory using an OS transistor. NOSRA
M4013 is a flash memory or ReRAM (Resistive Random
Access Memory), MRAM (Magnetoresistive Ran
It consumes less power when writing data than other non-volatile memories such as dom access memory. In addition, unlike flash memory and ReRAM, the device does not deteriorate when data is written, and there is no limit to the number of times data can be written.

The NOSRAM 4013 can store not only 1-bit binary data but also multi-value data of 2 bits or more. The NOSRAM 4013 stores multivalued data so that 1
The memory cell area per bit can be reduced.

Also, the NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, it does not require a D/A conversion circuit or an A/D conversion circuit. Therefore, NOS
The RAM 4013 can reduce the area of peripheral circuits. In this specification, analog data refers to data having a resolution of 3 bits (8 values) or more. Analog data may include the multivalued data described above.

The data and parameters used for neural network calculations are temporarily stored in NOSRA
It can be stored in M4013. Although the above data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021, the NOSRAM 4013 provided inside can store the above data and parameters at a higher speed and with lower power consumption. can be stored. Also, since the NOSRAM 4013 can have a longer bit line than the DOSRAM 4012, the memory capacity can be increased.

The FPGA 4014 is an FPGA using OS transistors. AI system 404
1 uses FPGA 4014 to implement deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), deep A neural network connection can be constructed, such as a belief network (DBN). By constructing the connection of the above neural network with hardware, it can be executed at a higher speed.

FPGA 4014 is an FPGA having an OS transistor. OS-FPGA is S
The area of the memory can be made smaller than that of FPGA configured with RAM. for that reason,
Even if the context switching function is added, the increase in area is small. Also, the OS-FPGA can transmit data and parameters at high speed by boosting.

A 3D-NAND 4015 is a nonvolatile memory using an oxide semiconductor. 3D-NAN
The D4015 is a highly integrated memory with a large storage capacity per unit area.

Also, the 3D-NAND 4015 can store not only 1-bit binary data but also multi-value data of 2 bits or more. By storing multilevel data, the 3D-NAND 4015 can further reduce the memory cell area per bit.

Further, as the 3D-NAND 4015, for example, the semiconductor device described in any of the above embodiments can be used. As a result, the area occupied by the memory cell can be reduced, so that the 3D-NAND 4015 can be further highly integrated. Therefore, 3D-NA
The storage capacity per unit area of ND4015 can be increased.

AI system 4041 includes analog arithmetic circuit 4011, DOSRAM 4012, NOS
RAM 4013 and FPGA 4014 can be provided on one die (chip). Therefore, the AI system 4041 can perform neural network calculations at high speed and with low power consumption. Also, the analog arithmetic circuit 4011, the DOSRAM 4
012, NOSRAM 4013, and FPGA 4014 can be made in the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.

Note that the calculation unit 4010 includes a DOSRAM 4012, a NOSRAM 4013, and an FP
It is not necessary to have all GA4014. One or more of the DOSRAM 4012, NOSRAM 4013, and FPGA 4014 may be selected and provided according to the problem that the AI system 4041 wants to solve.

The AI system 4041 is a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network ( DBN) can be performed. PROM 4025 can store programs for performing these operations. Also, part or all of these programs may be stored in the NOSRAM 4013 or 3D-NAND 4015 . 3D-
The NAND 4015 is a highly integrated memory and has a large storage capacity per unit area, so it can store large-capacity programs.

Many existing programs that exist as libraries assume GPU processing. Therefore, AI system 4041 preferably has GPU 4022 . AI
The system 4041 can execute rate-determining sum-of-products operations in the computing unit 4010 among sum-of-products operations used in learning and inference, and can perform other sum-of-products operations using the GPU 4022 .
By doing so, learning and inference can be executed at high speed.

The power supply circuit 4027 not only generates low voltage potentials for logic circuits, but also generates potentials for analog operations. The power supply circuit 4027 may use an OS memory. power supply circuit 40
27 can reduce power consumption by storing the reference potential in the OS memory.

The PMU 4028 has the function of temporarily turning off the power supply of the AI system 4041 .

The CPU 4021 and GPU 4022 preferably have OS memories as registers. Since the CPU 4021 and the GPU 4022 have OS memories, they can continue to hold data (logical values) in the OS memories even when the power supply is turned off. As a result, the AI system 4041 can save power.

The PLL 4023 has a function of generating clocks. AI system 4041 is PL
It operates based on the clock generated by the L4023. PLL 4023 preferably has an OS memory. Since the PLL 4023 has an OS memory, it can hold an analog potential that controls the clock oscillation cycle.

The AI system 4041 may store data in external memory such as DRAM. Therefore, the AI system 4041 preferably has a memory controller 4026 that functions as an interface with an external DRAM. Also, the memory controller 4026
is preferably placed near the CPU 4021 or GPU 4022 . By doing so, data can be exchanged at high speed.

Part or all of the circuitry shown in control unit 4020 can be formed on the same die as arithmetic unit 4010 . By doing so, the AI system 4041 can achieve high speed and low power consumption,
Neural network computations can be performed.

Data used for computation of the neural network is stored in an external storage device (HDD (Hard
Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably has an external storage control circuit 4031 that functions as an interface with the external storage device.

Learning and inference using neural networks often deal with audio and video, so A
I-system 4041 has audio codec 4032 and video codec 4033 .
The audio codec 4032 encodes (encodes) and decodes (decodes) audio data.
and the video codec 4033 encodes and decodes video data.

AI system 4041 can learn or make inferences using data obtained from external sensors. Therefore, the AI system 4041 has a general purpose input/output module 4034 . The general-purpose input/output module 4034 is, for example, a USB (Universal Ser
(Inter-Integrated Circuit) and I2C (Inter-Integrated Circuit).

AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, the AI system 4041 uses the communication module 403
5 is preferred.

The analog arithmetic circuit 4011 may use a multilevel flash memory as an analog memory. However, flash memory has a limited number of times it can be rewritten. Moreover, it is very difficult to form a multilevel flash memory by embedding (forming an arithmetic circuit and a memory on the same die).

Further, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limited number of rewritable times, and has a problem in terms of storage accuracy.
Furthermore, since the device has two terminals, the circuit design for separating data writing and reading becomes complicated.

Also, the analog arithmetic circuit 4011 may use an MRAM as an analog memory.
However, the MRAM has a low rate of resistance change and has a problem in terms of storage accuracy.

In view of the above, the analog arithmetic circuit 4011 preferably uses an OS memory as an analog memory.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 4)
[Application example of AI system]
In this embodiment, an application example of the AI system described in the above embodiment will be described with reference to FIG.

FIG. 26(A) shows an AI system 4041A in which the AI systems 4041 described in FIG. 25 are arranged in parallel, and signals can be transmitted and received between the systems via a bus line.

The AI system 4041A illustrated in FIG. 26A includes a plurality of AI systems 4041_1
to AI system 4041_n (n is a natural number). The AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098 .

FIG. 26B shows an AI system 4041B in which the AI systems 4041 described in FIG. 25 are arranged in parallel in the same manner as in FIG. be.

The AI system 4041B illustrated in FIG. 26B includes a plurality of AI systems 4041_1
to AI system 4041_n. AI system 4041_1 to AI system 4
041_n are connected to each other via a network 4099 .

The network 4099 may have a configuration in which a communication module is provided in each of the AI systems 4041_1 to 4041_n to perform wireless or wired communication.
The communication module can communicate via the antenna. For example, World Wi
Internet, intranet, extranet, PAN (Personal Area Network), LAN (Local A
area network), CAN (Campus Area Network), MA
N (Metropolitan Area Network), WAN (Wide AR
Each electronic device can be connected to a computer network such as a GAN (Global Area Network) and a GAN (Global Area Network) to perform communication. When performing wireless communication, as a communication protocol or communication technology, LTE (Long Term Evolu
tion), GSM (Global System for Mobile Communications)
nication: registered trademark), EDGE (Enhanced Data Rates
for GSM Evolution), CDMA2000 (Code Division
n Multiple Access 2000), W-CDMA (registered trademark), or a communication standard such as Wi-Fi (registered trademark), Bluetooth (registered trademark), ZigBe
Specifications standardized by IEEE for communication such as e (registered trademark) can be used.

With the configurations of FIGS. 26A and 26B, analog signals obtained by external sensors or the like can be processed by separate AI systems. For example, like biological information, brain waves, pulse,
Information such as blood pressure, body temperature, etc. can be acquired by various sensors such as an electroencephalogram sensor, a pulse wave sensor, a blood pressure sensor, and a temperature sensor, and analog signals can be processed by separate AI systems. By performing signal processing or learning in each of the separate AI systems, the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be improved. From the information obtained by each AI system, it can be expected that changes in complexly changing biological information can be instantly and comprehensively grasped.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments.

(Embodiment 5)
This embodiment shows an example of an IC incorporating the AI system shown in the above embodiment.

The AI system shown in the above embodiment includes a digital processing circuit made of Si transistors such as a CPU, an analog arithmetic circuit using OS transistors, 3D-NAND, OS-FPG
A and OS memory such as DOSRAM, NOSRAM can be integrated on one die.

FIG. 27 shows an example of an IC incorporating an AI system. AI system I shown in FIG.
The C7000 has leads 7001 and a circuit portion 7003 . AI system IC7000
are mounted on the printed circuit board 7002, for example. A plurality of such IC chips are combined and electrically connected to each other on the printed board 7002 to complete a board (mounting board 7004) on which electronic components are mounted. In the circuit portion 7003, various circuits described in the above embodiment modes are provided on one die. The circuit portion 7003 has a laminated structure as shown in the previous embodiment, and is roughly divided into a Si transistor layer 7031 , a wiring layer 7032 and an OS transistor layer 7033 . The OS transistor layer 7033 is replaced by the Si transistor layer 7031
, the AI system IC 7000 can be easily miniaturized.

In FIG. 27, a QFP (Quad Flat
Package) is applied, but the form of the package is not limited to this.

Digital processing circuits such as CPU, analog arithmetic circuits using OS transistors, 3D-
NAND, OS-FPGA and OS memories such as DOSRAM and NOSRAM are all
It can be formed in the Si transistor layer 7031 , the wiring layer 7032 and the OS transistor layer 7033 . That is, the elements constituting the AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment mode does not require an increase in the number of manufacturing processes even if the number of constituent elements increases, and the AI system can be incorporated at a low cost.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 6)
[Electronics]
A semiconductor device according to one embodiment of the present invention can be used for various electronic devices. 28 and 29 illustrate specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention.

A robot 2000 shown in FIG. 28A includes an arithmetic device 2001, a sensor 2002, a light 2003, a lift 2004, a drive unit 2005, and a moving mechanism 2011, and can take still images and moving images while moving. Such robots can be used as security systems and surveillance systems.

The robot 2000 may further include communication means 2006, a speaker 2007, a microphone 2008, a display section 2009, a light emitting section 2010, and the like.

A semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 2001 . An IC in which the AI system according to one embodiment of the present invention is incorporated can be used for the arithmetic device 2001 . The sensor 2002 has a function as a camera that photographs the surroundings of the robot 2000 . The light 2003 can be used as a light when the sensor 2002 captures an image around the robot 2000 . Note that when the sensor 2002 captures a still image, the light 2003 preferably functions as a flashlight. sensor 20
02 is connected to the robot body via a lift 2004 . The height of sensor 2002 can be adjusted by lift 2004 . Lift 2004 is preferably telescoping. Also, the lift 2004 may be of a foldable type composed of a plurality of booms. Further, since the robot 2000 is provided with the drive unit 2005 and the movement mechanism 2011 connected to the drive unit 2005, the range of imaging by the sensor 2002, that is, the range of monitoring is increased, which is preferable.

A communication unit 2006 can transmit information captured by the sensor 2002 to an administrator or a server owned by the administrator. Information picked up by the sensor 2002 is analyzed by the arithmetic unit 2001, and if it is determined that there is an emergency such as a crime, accident, or fire, the information is sent to security companies, police, fire departments, medical institutions, land and building owners. can be contacted. speaker 2
007 can transmit information to the surroundings of the robot, such as a warning to criminals, inquiries to injured or sick people, guidance for evacuation, and the like. A microphone 2008 can be used to capture sounds around the robot 2000 . Also, communication means 2006 and speaker 2007
, the robot 2000 can function as a telephone.
People around the robot 2000 can converse with the administrator or any person. Display part 2
009 can display arbitrary information. In the event of an emergency, disaster information and evacuation routes can be displayed. Also, by using the communication means 2006, the speaker 2007, and the microphone 2008 together, the robot 2000 can function as a videophone. The people around the robot 2000 can be the administrator or arbitrary people and the display unit 200
You can talk while looking at 9.

The light emitting unit 2010 can indicate the traveling direction and the stop state of the robot 2000 with characters or light. It may also indicate an emergency.

FIG. 28B is a block diagram showing the configuration of the robot 2000. As shown in FIG. Arithmetic device 2001
determines whether the light 2003 is turned on or off from information such as an image obtained by the sensor 2002,
Adjust brightness. It also adjusts the height of the lift 2004 or controls the drive unit 2005 to align the robot 2000 and sensor 2002 . Also, the drive unit 2
005 can be indicated using the light emitting unit 2010 . Also, the communication means 200
6 can be used to transmit information about the surroundings of the robot 2000 obtained from the sensor 2002 and the microphone 2008 to the administrator or a server owned by the administrator. In addition, using the arithmetic unit 2001 and the speaker 2007 and the display unit 2009 at the discretion of the administrator,
Information can be transmitted around the robot 2000 .

The light 2003 may not be provided when a sensor capable of capturing an image even in a dark environment is used as the sensor 2002 . As such a sensor, selenium (
An image sensor using Se) can be used.

Such a robot 2000 can be used for security of commercial facilities and offices.
Information obtained from the sensor 2002 and the microphone 2008 is stored in the arithmetic device 2001 and server. The stored information is analyzed by an AI system, and lost or damaged items,
Determine whether there is an abnormality such as an intrusion of a suspicious person or a disaster such as a fire. Deep learning may be used to analyze the information. When it is determined that an abnormality has occurred, the robot 2000 contacts the administrator, transmits information to the surroundings, and records the surrounding conditions.

Also, the robot 2000 may be used to monitor the growing conditions of agricultural crops. A robot 2000 installed in a rice field or a field monitors the shape, size, and color of leaves or fruits of agricultural crops using a sensor 2002 to determine whether they are diseased or have insect pests. robot 2
Since 000 is provided with a moving mechanism 2011, it is possible to monitor the growing conditions of agricultural crops over a wide range. In addition, since the robot 2000 is provided with a lift 2004, it is possible to monitor leaves and fruits at arbitrary heights regardless of the type of crops or growth conditions. The monitoring results are sent to the producer using the communication means 2006, and the producer can determine the type, amount, and timing of application of fertilizers and agricultural chemicals required for crops. Also, using the computing device 2001,
The monitoring results may be analyzed by an AI system to determine the type, amount, and timing of application of fertilizers and pesticides required for crops, and notify the producer. Deep learning may be used to analyze the monitoring results.

FIG. 29A shows a sorting system 3000 using a robot 3001. FIG. The robot 3001 has an arithmetic device 3002 , a boom 3003 and an arm 3004 . Also, the robot 3001 may be equipped with wired or wireless communication means 3011 .
The sorting system 3000 also includes a housing 3008 having a sensor 3009 .
Housing 3008 has communication means 3010 . Enclosure 3008 is the sorting system 30
00, or on the ceiling, walls, and beams (none of which are shown) in the sorting work area. Also, the housing 3008 may be provided in the robot 3001 . For example, boom 3003
, or on arm 3004 . When housing 3008 is provided in robot 3001 , information obtained by sensor 3009 may be sent to arithmetic device 3002 and processed without communication means 3010 and 3011 .

Boom 3003 is movable, and arm 3004 can be placed at a desired position. Also, the arm 3004 may be telescopic. After extending the arm placed on the desired article 3007, grasping the desired article 3007, and retracting the arm 3004, the boom 3
003 may move the arm 3004 .

Sortation system 3000 can move items 3007 in container 3005 to container 3006 . The container 3005 and the container 3006 may have the same shape or different shapes. Also, a plurality of articles 3007 placed in one container 3005 are stored in a plurality of containers 3006 .
You may move by dividing it into

As containers 3005 and 3006, containers, cardboard boxes, boxes for packing products, cases, films or bags, bats for food storage, lunch boxes, and the like are used. again,
At least one of container 3005 and container 3006 may be a cooking utensil such as a pot or frying pan.

A semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 3002 . For the arithmetic device 3002, an IC in which the AI system according to one embodiment of the present invention is incorporated can be used.

The sensor 3009 reads the position of the container 3005 , the position of the container 3006 , the state inside the container 3005 and the article 3007 inside the container 3005 , and transmits the information to the computing device 3002 using the communication means 3010 . Information is transmitted wirelessly or by wire. Also, the communication means 30
Instead of using 10, the information may be transmitted by wire. Arithmetic device 3002 analyzes the transmitted information. Here, the state of the articles 3007 refers to the shape, number, overlap of the articles 3007, and the like. The computing device 3002 analyzes based on the information from the sensor 3009,
Detailed information of the article 3007 is derived. The three-dimensional shape and hardness (softness) of the article 3007 are derived by comparing with the data stored in the computing device 3002 or the server that can communicate with the robot 3001 . Also, the three-dimensional shape and hardness (softness) of the article 3007 determine the
04 can be changed.

Analysis using an AI system can be used to derive detailed information about the item 3007 . Deep learning may be used to analyze the information.

FIG. 29(B) shows an arm in which a pair of plates 3021 can move horizontally to sandwich an article 3007 . The article 3007 can be sandwiched by the pair of plates 3021 moving horizontally toward the center. Such an arm can grasp the article 3007 from the surface, and is suitable for grasping the article 3007 having a columnar shape such as a cube or rectangular parallelepiped. Figure 29
(C) is an arm in which a plurality of bars 3022 can move horizontally to sandwich an article 3007 . Horizontal movement of the plurality of bars 3022 toward the center causes the article 30 to
07 can be inserted. Such an arm can grasp the article 3007 at a point,
It is suitable for gripping an article 3007 having a spherical shape, or an article 3007 having an irregular shape, that is, an irregular article 3007 . Although the number of bars 3022 is four in FIG. 29C, the present embodiment is not limited to this. The number of bars 3022 may be three, or five or more. FIG. 29(D) shows an arm capable of sandwiching an article 3007 by rotating a pair of plates 3023 about a common axis so that they approach each other. Such an arm can grasp the article 3007 on its surface, and is suitable for grasping an article 3007 having a thin film shape such as paper or film. FIG. 29(E) is an arm capable of sandwiching an article 3007 by rotating a pair of hook-shaped plates 3024 around a common axis so that the tips thereof approach each other. Such an arm can grasp the article 3007 as a point or a line, and is suitable for grasping an article 3007 having a thin film shape, such as paper or a film, or an article 3007 having a smaller granular shape. . Alternatively, as shown in FIG. 29(F), a spatula 3025 may be attached to the tip of the arm to scoop up articles 3007 having smaller granular shapes.

The arms illustrated in FIGS. 29A to 29F are examples, and one embodiment of the present invention is not limited to these shapes. Further, the description of the application of each arm is also an example, and one embodiment of the present invention is not limited to these descriptions.

Robot 3001 moves boom 3003 and moves arm 3004 onto desired article 3007 in container 3005 based on signals from computing device 3002 . In the case of a telescoping arm 3004 , extend the arm 3004 and lower the tip of the arm 3004 to the height of the article 3007 . Move the tip of the arm to grab the desired item 3007 . The arm is retracted while gripping the article 3007 . Move boom 3003 again to move arm 3004 to container 300
6 to the desired position. At this time, arm 3004 may be rotated to adjust the angle of article 3007 with respect to container 3006 . Arm 3004 is extended to place item 3007 in container 3006 and arm 3004 releases item 3007 . By repeating the above operation, the robot 3001 can move the article 3007 from the container 3005 to the container 3006 .

Since the position information of the container 3005 and the container 3006 and the state of the article 3007 are analyzed using the AI system, the article 3000 can be reliably retrieved regardless of the shape or hardness of the article 3007.
7 can be moved. Examples of goods 3007 include cubic or cuboid boxes, or goods packed in boxes or cases of any shape, as well as molded processed foods such as eggs, hamburgers and croquettes, and unhealthy foods such as potatoes and tomatoes. Examples include foods such as regular vegetables, machine parts such as screws and nuts, and thin films such as paper and film. Since the sorting system 3000 shown in this embodiment can change the shape of the arms in consideration of the shape and hardness of the articles 3007, the articles 3007 exemplified above can be handled as containers regardless of their shape and hardness. 3005
can be moved from to container 3006 .

For example, a storage device using the semiconductor device of one embodiment of the present invention can retain control information, control programs, and the like of the above electronic devices for a long period of time. With the use of the semiconductor device of one embodiment of the present invention, a highly reliable electronic device can be achieved.

Further, for example, an IC in which the AI system is incorporated can be used in an arithmetic unit of the electronic device described above. Thus, the electronic device described in this embodiment can operate accurately according to the situation with low power consumption by the AI system.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

100 storage device 105 control circuit 110 memory cell array 112 memory string 121 row decoder 122 row driver 123 sense amplifier 124 source line driver 125 input/output circuit 126 buffer 126a inverter circuit 126b switch circuit 131 memory cell 132 memory cell 700 semiconductor device 700A storage device 700D Circuit portion 700M Memory cell array 701 Conductive layer 701_m Conductive layer 701_1 Conductive layer 701_6 Conductive layer 701a Conductive layer 701A Conductive film 701b Conductive layer 701B Conductive film 702 Conductive layer 702A Conductive film 702b Insulating layer 702B Conductive film 703 Insulating layer 703_1 Insulating layer 703_3 Insulating layer 703a insulating layer 703A insulating film 703b insulating layer 703c insulating layer 704 oxide layer 704_1 oxide layer 704_3 oxide layer 704a oxide layer 704A oxide film 704b oxide layer 704c oxide layer 705 conductive layer 705_1 conductive layer 705_3 conductive layer 706 Conductive layer 706_1 Conductive layer 706_3 Conductive layer 707 Connection layer 707_m Connection layer 707_1 Connection layer 708 Conductive layer 708_m Conductive layer 708_1 Conductive layer 710 Memory transistor 711 Insulating layer 720 Substrate 721 Insulating film 722 Insulating layer 722A Insulating film 722B Insulating film 723 Mask 723A Mask 724 insulating layer 725 mask 726 insulating layer 727 sacrificial layer 731 mask 750 transistor 751 oxide layer 751a oxide layer 752 conductive layer 753a conductive layer 753b conductive layer 754 insulating layer 761 insulating layer 762 connection layer 763 connection layer 764a connection layer 764b connection layer 765 conductive layer 766a conductive layer 766b conductive layer 1100 USB memory 1101 housing 1102 cap 1103 USB connector 1104 substrate 1105 memory chip 1106 controller chip 1110 SD card 1111 housing 1112 connector 1113 substrate 1114 memory chip 1115 controller chip 1150 SSD
1151 housing 1152 connector 1153 substrate 1154 memory chip 1155 memory chip 1156 controller chip 2000 robot 2001 computing device 2002 sensor 2003 light 2004 lift 2005 driving unit 2006 communication means 2007 speaker 2008 microphone 2009 display unit 2010 light emitting unit 2011 moving mechanism 3100 robot system 3000 3002 Arithmetic device 3003 Boom 3004 Arm 3005 Container 3006 Container 3007 Article 3008 Housing 3009 Sensor 3010 Communication means 3011 Communication means 3021 Plate 3022 Bar 3023 Plate 3024 Plate 3025 Spatula 4010 Calculation unit 4011 Analog calculation circuit 4012 DOSRAM
4013 NOSRAM
4014 FPGA
4020 control unit 4021 CPU
4022 GPUs
4023 PLL
4025 PROMs
4026 memory controller 4027 power supply circuit 4028 PMU
4030 Input/output unit 4031 External storage control circuit 4032 Audio codec 4033 Video codec 4034 General-purpose input/output module 4035 Communication module 4041 AI system 4041_n AI system 4041_1 AI system 4041A AI system 4041B AI system 4098 Bus line 4099 Network 7000 AI system IC
7001 Lead 7002 Printed board 7003 Circuit part 7004 Mounting board 7031 Si transistor layer 7032 Wiring layer 7033 OS transistor layer

Claims (1)

A semiconductor device having a memory transistor, a transistor, and an oxide layer,
The memory transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. a semiconductor layer;
the transistor has a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a fourth insulating layer, and a second semiconductor layer;
The first conductive layer has an opening,
The first insulating layer has a region in contact with the inner side surface of the opening,
The second insulating layer has a region in contact with the inner side surface of the first insulating layer,
The third insulating layer has a region in contact with the inner side surface of the second insulating layer,
The first semiconductor layer has a region in contact with the inner side surface of the third insulating layer, and is provided to protrude vertically beyond the opening of the first conductive layer,
the second conductive layer has a region in contact with the bottom of the first semiconductor layer;
the third conductive layer has a region in contact with the upper portion of the first semiconductor layer;
the fourth conductive layer and the fifth conductive layer have regions in contact with the upper surface of the second semiconductor layer;
The fourth insulating layer has a region in contact with the top surface of the fourth conductive layer, a region in contact with the top surface of the fifth conductive layer, and a region in contact with the top surface of the second semiconductor layer. ,
The sixth conductive layer has a region overlapping with the second semiconductor layer with the fourth insulating layer interposed therebetween,
the first conductive layer is electrically connected to the fourth conductive layer or the fifth conductive layer through the oxide layer;
A semiconductor device in which the oxide layer, the first semiconductor layer, and the second semiconductor layer include the same metal oxide.

Images