JP7433029B2 - 作業負荷の繰り返し冗長化 - Google Patents

作業負荷の繰り返し冗長化 Download PDF

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Publication number
JP7433029B2
JP7433029B2 JP2019218908A JP2019218908A JP7433029B2 JP 7433029 B2 JP7433029 B2 JP 7433029B2 JP 2019218908 A JP2019218908 A JP 2019218908A JP 2019218908 A JP2019218908 A JP 2019218908A JP 7433029 B2 JP7433029 B2 JP 7433029B2
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task
processing
signature
unit
processed
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Japanese (ja)
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JP2020091868A5 (https=
JP2020091868A (ja
Inventor
ダミアン、マクナマラ
ジェイミー、ブルーム
イアン、キング
ウェイ、シャオ
マリオ、ソペナ、ノバレス
ディリップ、バンサル
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Imagination Technologies Ltd
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Imagination Technologies Ltd
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Publication of JP2020091868A5 publication Critical patent/JP2020091868A5/ja
Priority to JP2024015919A priority Critical patent/JP7665811B2/ja
Application granted granted Critical
Publication of JP7433029B2 publication Critical patent/JP7433029B2/ja
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1633Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operations
    • G06F11/1497Time redundant execution of software on a single processing unit
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1641Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/82Solving problems relating to consistency

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Hardware Redundancy (AREA)
  • Image Generation (AREA)
JP2019218908A 2018-12-04 2019-12-03 作業負荷の繰り返し冗長化 Active JP7433029B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2024015919A JP7665811B2 (ja) 2018-12-04 2024-02-05 作業負荷の繰り返し冗長化

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1819808.5A GB2579590B (en) 2018-12-04 2018-12-04 Workload repetition redundancy
GB1819808.5 2018-12-04

Related Child Applications (1)

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JP2024015919A Division JP7665811B2 (ja) 2018-12-04 2024-02-05 作業負荷の繰り返し冗長化

Publications (3)

Publication Number Publication Date
JP2020091868A JP2020091868A (ja) 2020-06-11
JP2020091868A5 JP2020091868A5 (https=) 2022-12-12
JP7433029B2 true JP7433029B2 (ja) 2024-02-19

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JP2019218908A Active JP7433029B2 (ja) 2018-12-04 2019-12-03 作業負荷の繰り返し冗長化
JP2024015919A Active JP7665811B2 (ja) 2018-12-04 2024-02-05 作業負荷の繰り返し冗長化

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Country Status (5)

Country Link
US (4) US11288145B2 (https=)
EP (1) EP3663921B1 (https=)
JP (2) JP7433029B2 (https=)
CN (1) CN111275606B (https=)
GB (1) GB2579590B (https=)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10409614B2 (en) 2017-04-24 2019-09-10 Intel Corporation Instructions having support for floating point and integer data types in the same register
US10474458B2 (en) 2017-04-28 2019-11-12 Intel Corporation Instructions and logic to perform floating-point and integer operations for machine learning
GB2579591B (en) 2018-12-04 2022-10-26 Imagination Tech Ltd Buffer checker
GB2579590B (en) * 2018-12-04 2021-10-13 Imagination Tech Ltd Workload repetition redundancy
WO2020190807A1 (en) 2019-03-15 2020-09-24 Intel Corporation Systolic disaggregation within a matrix accelerator architecture
US12182035B2 (en) 2019-03-15 2024-12-31 Intel Corporation Systems and methods for cache optimization
PL3938914T3 (pl) 2019-03-15 2025-03-31 Intel Corporation Dynamiczna rekonfiguracja pamięci
US11663746B2 (en) 2019-11-15 2023-05-30 Intel Corporation Systolic arithmetic on sparse data
US11861761B2 (en) 2019-11-15 2024-01-02 Intel Corporation Graphics processing unit processing and caching improvements
FR3104278B1 (fr) * 2019-12-06 2021-11-19 Commissariat Energie Atomique Système informatique embarqué à bord d'un porteur mettant en oeuvre au moins un service critique pour la sûreté de fonctionnement du porteur
RU2767018C2 (ru) * 2020-08-11 2022-03-16 Федеральное государственное казённое военное образовательное учреждение высшего образования "Военная академия воздушно-космической обороны имени Маршала Советского Союза Г.К. Жукова" Министерства обороны Российской Федерации Способ функционирования комплексов средств автоматизации систем обработки информации и управления и устройство, его реализующее
US11645185B2 (en) * 2020-09-25 2023-05-09 Intel Corporation Detection of faults in performance of micro instructions
GB202019527D0 (en) 2020-12-10 2021-01-27 Imagination Tech Ltd Processing tasks in a processing system
GB2600789B (en) 2021-04-19 2023-05-31 Imagination Tech Ltd Tile Region Protection using multiple GPUs
IT202100012395A1 (it) * 2021-05-13 2022-11-13 St Microelectronics Srl Circuito controllore, sistema e procedimento corrispondenti
WO2022241652A1 (en) * 2021-05-18 2022-11-24 Nvidia Corporation Hardware-based fault scanner to detect faults in homogeneous processing units
GB2608184B (en) * 2021-06-25 2025-09-17 Graphcore Ltd Signature Generation
GB2605467B (en) 2021-06-29 2023-12-06 Imagination Tech Ltd Verifying processing logic of a graphics processing unit
CN116416115B (zh) * 2022-12-23 2024-01-30 摩尔线程智能科技(北京)有限责任公司 Gpu的控制方法、装置、设备、存储介质和程序产品
CN119782140A (zh) * 2023-10-06 2025-04-08 想象技术有限公司 配置成执行并行处理的处理单元

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010113388A (ja) 2008-11-04 2010-05-20 Renesas Technology Corp 処理結果を照合する比較器を有するマルチコアマイコン
US20180267868A1 (en) 2017-03-15 2018-09-20 International Business Machines Corporation Maintaining system reliability in a cpu with co-processors

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2822932B2 (ja) * 1995-05-29 1998-11-11 日本電気株式会社 ソフトウェア二重化処理装置
US6571363B1 (en) 1998-12-30 2003-05-27 Texas Instruments Incorporated Single event upset tolerant microprocessor architecture
US6981176B2 (en) 1999-05-10 2005-12-27 Delphi Technologies, Inc. Secured microcontroller architecture
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US6772368B2 (en) * 2000-12-11 2004-08-03 International Business Machines Corporation Multiprocessor with pair-wise high reliability mode, and method therefore
US20070277023A1 (en) * 2003-06-24 2007-11-29 Reinhard Weiberle Method For Switching Over Between At Least Two Operating Modes Of A Processor Unit, As Well Corresponding Processor Unit
US7296181B2 (en) * 2004-04-06 2007-11-13 Hewlett-Packard Development Company, L.P. Lockstep error signaling
US7328331B2 (en) * 2005-01-25 2008-02-05 Hewlett-Packard Development Company, L.P. Method and system of aligning execution point of duplicate copies of a user program by copying memory stores
FR2884949B1 (fr) 2005-04-26 2007-06-22 Thales Sa Dispositif de generation graphique comportant des moyens de surveillance de son fonctionnement.
DE102005037228A1 (de) * 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zur Steuerung eines Rechnersystems
US20070088979A1 (en) * 2005-10-14 2007-04-19 Pomaranski Ken G Hardware configurable CPU with high availability mode
US7865770B2 (en) * 2008-01-10 2011-01-04 Advanced Micro Devices, Inc. Processor including efficient signature generation for logic error protection
US7941698B1 (en) 2008-04-30 2011-05-10 Hewlett-Packard Development Company, L.P. Selective availability in processor systems
GB2474114B (en) 2009-09-25 2012-02-15 Advanced Risc Mach Ltd Graphics processing systems
DE102009054637A1 (de) 2009-12-15 2011-06-16 Robert Bosch Gmbh Verfahren zum Betreiben einer Recheneinheit
US9135154B2 (en) * 2010-03-02 2015-09-15 Microsoft Technology Licensing, Llc Algorithm execution output cache
US9104403B2 (en) * 2010-08-18 2015-08-11 Freescale Semiconductor, Inc. Data processing system having selective redundancy and method therefor
US8583971B2 (en) 2010-12-23 2013-11-12 Advanced Micro Devices, Inc. Error detection in FIFO queues using signature bits
US8880961B2 (en) 2012-01-31 2014-11-04 Infineon Technologies Ag System and method of computation by signature analysis
US9027024B2 (en) * 2012-05-09 2015-05-05 Rackspace Us, Inc. Market-based virtual machine allocation
US9047192B2 (en) * 2012-12-21 2015-06-02 Advanced Micro Devices, Inc. Signature-based store checking buffer
US9892479B1 (en) 2013-03-12 2018-02-13 Rockwell Collins, Inc Independent monitoring of graphics processing units
US9274904B2 (en) * 2013-06-18 2016-03-01 Advanced Micro Devices, Inc. Software only inter-compute unit redundant multithreading for GPUs
US9749319B2 (en) * 2015-05-20 2017-08-29 Google Inc. Address validation using signatures
JP6438353B2 (ja) 2015-05-27 2018-12-12 ルネサスエレクトロニクス株式会社 半導体装置及び診断テスト方法
US10297003B2 (en) * 2015-09-21 2019-05-21 Qualcomm Incorporated Efficient saving and restoring of context information for context switches
US9413392B1 (en) * 2015-12-14 2016-08-09 International Business Machines Corporation Post-decoding error check with diagnostics for product codes
US10380185B2 (en) * 2016-02-05 2019-08-13 Sas Institute Inc. Generation of job flow objects in federated areas from data structure
US10013240B2 (en) * 2016-06-21 2018-07-03 Advanced Micro Devices, Inc. Fingerprinting of redundant threads using compiler-inserted transformation code
JP2018107588A (ja) 2016-12-26 2018-07-05 ルネサスエレクトロニクス株式会社 画像処理装置および半導体装置
EP3373178B1 (en) 2017-03-08 2024-09-18 Secure-IC SAS Comparison of execution context data signatures with references
US10380039B2 (en) 2017-04-07 2019-08-13 Intel Corporation Apparatus and method for memory management in a graphics processing environment
CN107222485B (zh) 2017-06-14 2020-08-21 腾讯科技(深圳)有限公司 一种授权方法以及相关设备
US10754760B1 (en) * 2018-05-17 2020-08-25 Xilinx, Inc. Detection of runtime failures in a system on chip using debug circuitry
JP7042709B2 (ja) 2018-06-28 2022-03-28 ルネサスエレクトロニクス株式会社 半導体装置、制御システムおよび半導体装置の制御方法
GB2579590B (en) * 2018-12-04 2021-10-13 Imagination Tech Ltd Workload repetition redundancy
GB2579591B (en) * 2018-12-04 2022-10-26 Imagination Tech Ltd Buffer checker

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010113388A (ja) 2008-11-04 2010-05-20 Renesas Technology Corp 処理結果を照合する比較器を有するマルチコアマイコン
US20180267868A1 (en) 2017-03-15 2018-09-20 International Business Machines Corporation Maintaining system reliability in a cpu with co-processors

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Publication number Publication date
US11288145B2 (en) 2022-03-29
US20250315350A1 (en) 2025-10-09
JP2024050808A (ja) 2024-04-10
CN111275606A (zh) 2020-06-12
GB2579590B (en) 2021-10-13
GB2579590A (en) 2020-07-01
US12360864B2 (en) 2025-07-15
JP2020091868A (ja) 2020-06-11
JP7665811B2 (ja) 2025-04-21
EP3663921A1 (en) 2020-06-10
GB201819808D0 (en) 2019-01-23
US20220171684A1 (en) 2022-06-02
US11782806B2 (en) 2023-10-10
EP3663921B1 (en) 2022-07-13
CN111275606B (zh) 2024-06-25
US20240036995A1 (en) 2024-02-01
US20200174897A1 (en) 2020-06-04

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