JP7426642B2 - Method for manufacturing silicon carbide epitaxial wafer - Google Patents

Description

The present invention relates to a method of manufacturing a silicon carbide epitaxial wafer .

Power electronics, which is responsible for power conversion (DC/AC conversion and voltage conversion) and control, is expected to be a key technology for energy conservation.
Up until now, attempts have been made to improve the performance of power electronics using silicon (Si), but as its theoretical limits have become apparent, silicon carbide (SiC) is attracting attention as a next-generation material.
Silicon carbide (SiC) has excellent performance compared to silicon (Si), such as 10 times the dielectric breakdown field strength and 3 times the band gap, making it ideal for high durability power devices using silicon carbide single crystal substrates. High voltage and low power loss are expected.

A power device is manufactured using a silicon carbide epitaxial wafer in which a silicon carbide epitaxial layer is formed on a silicon carbide single crystal substrate. A silicon carbide single crystal substrate is obtained by processing a bulk single crystal of silicon carbide produced by a sublimation method or the like, and a silicon carbide epitaxial layer is formed by a chemical vapor deposition (CVD) method.

Patent Document 1 states that when the outer diameter is 100 mm or more and the substrate temperature is room temperature, the amount of warpage is -100 μm or more and 100 μm or less (preferably -40 μm or more and 40 μm or less), and when the substrate temperature is 400 ° C. A silicon carbide epitaxial wafer is disclosed in which the amount of warpage is -1.5 mm or more and 1.5 mm or less. Further, the thickness of the epitaxial layer is exemplified as approximately 5 μm or more and 40 μm or less (see paragraph 0032). The definition of the amount of warpage will be described later with reference to FIG.

Patent Document 1 states that the increase in the amount of warpage when the substrate temperature is high is due to stress caused by residual strain in the formed damaged layer, and that a portion of the back surface of the silicon carbide substrate is used to reduce the amount of warpage. A method for removing is disclosed. Further, it is disclosed that whether or not this damaged layer has been sufficiently removed can be confirmed by the surface roughness of the back surface, and that the surface roughness (Ra) is set to 10 nm or less.

JP2015-32787A

SiC power devices have progressed to a medium withstand voltage range of 1kV, a high withstand voltage range of 5kV, and an ultra-high withstand voltage range of 10kV or more, which is expected to be applied to power transmission and distribution. Full-scale research is beginning. At present, target devices in the ultra-high voltage range include high voltage PIN diodes, high voltage MOSFETs, and IGBTs.

In ultra-high withstand voltage power devices (ultra-high withstand voltage region) of 10 kV or more, the epitaxial layer is more than an order of magnitude thicker than power devices in the 1 kV withstand voltage region, so-called thick-film epitaxial layers (100 μm or more). is required.

The present inventors investigated problems that had not become apparent in the medium and high withstand voltage regions regarding silicon carbide epitaxial wafers having such thick (100 μm or more) epitaxial layers.

Considering the thickness of the epitaxial layer (sometimes referred to as an epitaxial growth layer or epi layer) illustrated in Patent Document 1, the current focus of development is medium-voltage SiC-MOS (the thickness of the epitaxial layer is approximately 20 μm). It is assumed that it will be used in The warpage with a film thickness of this level is very different from the warpage when used in SiC devices with a withstand voltage of 10 kV or more, such as IGBTs (in this case, the epitaxial layer thickness is a so-called thick film (100 μm or more)). However, to date, there have been no reports regarding warpage in thick-film silicon carbide epitaxial wafers.
Therefore, the inventors of the present invention conducted extensive studies on warping of thick-film silicon carbide epitaxial wafers.

FIG. 2 is a graph showing the results of investigating the relationship between the film thickness of the epitaxial growth layer of a silicon carbide epitaxial wafer and the amount of warpage of the silicon carbide epitaxial wafer, which is not publicly known but was investigated by the inventors of the present invention prior to the filing of this application. be.
The silicon carbide substrate used had an outer diameter of 3 inches. Note that the technical concept of the present invention does not change even if the outer diameter changes, so the outer diameter may be less than 3 inches or greater than 3 inches.
When the film thickness of the epitaxial growth layer was increased to 65 μm, 140 μm, 200 μm, and 240 μm, the amount of warpage increased almost linearly to 20 μm, 24 μm, 27 μm, and 29 μm, and the change in the amount of warpage (μm) was determined by the film thickness. It can be seen that it is almost proportional to the increase in .
From this result, it can be seen that the amount of warpage of a thick film silicon carbide epitaxial wafer is much larger than the amount of warpage when the film thickness is about 20 μm.

Let us consider a problem caused by a large amount of warpage in a thick silicon carbide epitaxial wafer.
First, there is cracking of the wafer. As the epitaxial layer becomes thicker, the stress applied to the epitaxial wafer increases, making it more likely to crack. Therefore, if the amount of warpage becomes even larger, temperature distribution will occur during the high-temperature process, making it even more likely to crack. The amount of warpage at room temperature of −100 μm or more and 100 μm or less (preferably −40 μm or more and 40 μm or less) as shown in Patent Document 1 is not sufficient for thick-film silicon carbide epitaxial wafers, and the problem of wafer cracking cannot be avoided.

Next, in automatic conveyance, as the epitaxial layer becomes thicker, stricter control of the amount of warpage is required.
This point will be explained using FIG. 3. (a) is a case where the film thickness is about 20 μm, and (b) is a case where the film is thick (100 μm or more).
Even if the amount of warpage is the same, the thicker the epitaxial layer becomes, the larger the pseudo thickness (x) of the epitaxial wafer becomes. When confirming the presence of an epitaxial wafer using a laser or the like during automatic transport, if x is too large, the presence of the epitaxial wafer cannot be accurately confirmed (for example, it will be recognized that two wafers are stacked on top of each other), Increased risk of making errors.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a silicon carbide epitaxial wafer having a smaller amount of warpage than conventional silicon carbide epitaxial wafers, and a method for manufacturing the same.

Typical examples of the present invention are as follows.

(1) A silicon carbide epitaxial wafer according to a first aspect of the present invention includes a silicon carbide substrate and a silicon carbide layer provided on a first main surface of the silicon carbide substrate and having a thickness of 100 μm or more. The silicon carbide epitaxial wafer is a silicon epitaxial wafer, and the amount of warpage of the silicon carbide epitaxial wafer is −20 μm or more and 20 μm or less.

(2) In the above aspect, the second main surface facing the first main surface of the silicon carbide substrate may have a surface roughness of 20 nm or more.

(3) In the above aspect, the total thickness of the silicon carbide substrate and the silicon carbide layer may be 450 μm or more.

(4) In the above aspect, the total thickness of the silicon carbide substrate and the silicon carbide layer may be 600 μm or more.

(5) In the above aspect, the silicon carbide substrate may be 4H-SiC.

(6) In the above aspect, the silicon carbide substrate may have an outer diameter of 75 mm or more.

(7) A method for manufacturing a silicon carbide epitaxial wafer according to a second aspect of the present invention includes preparing a silicon carbide substrate having a first main surface and a second main surface opposing thereto, The method includes processing the silicon carbide substrate so that the main surface side has a convex shape, and epitaxially growing a silicon carbide layer on the first main surface of the silicon carbide substrate.

(8) In the above aspect, the step of processing the silicon carbide substrate may include a step of polishing and/or grinding the second main surface to have a surface roughness of 20 nm or more.

(9) In the above aspect, the step of growing epitaxial crystals may include the step of growing epitaxial crystals of the silicon carbide layer to a thickness of 100 μm or more.

According to the silicon carbide epitaxial wafer of the present invention, it is possible to provide a silicon carbide epitaxial wafer with a smaller amount of warpage than conventional silicon carbide epitaxial wafers.

FIG. 3 is a schematic cross-sectional view for explaining the definition of the amount of warpage of a silicon carbide semiconductor substrate, in which (a) is a case where the surface side facing the growth surface is warped in a convex shape, and (b) is a case where the growth surface side is convexly warped. This is the case when it is warped. It is a graph showing the result of investigating the relationship between the film thickness of the epitaxial growth layer and the amount of warpage of a silicon carbide epitaxial wafer. It is a cross-sectional schematic diagram for explaining the difference in pseudo thickness of an epitaxial wafer depending on the thickness of the epitaxial layer, (a) is when the epitaxial layer is thin, (b) is when the epitaxial layer is thick. . 1 is a cross-sectional view schematically showing a silicon carbide epitaxial wafer according to an embodiment of the present invention. It is a graph showing the relationship between the surface roughness of the second main surface (back surface) of the silicon carbide epitaxial wafer before the hydrogen heating step and the amount of warpage of the silicon carbide substrate. It is a graph showing the relationship between the surface roughness of the second main surface (back surface) of the silicon carbide epitaxial wafer after a hydrogen heating step and the amount of warpage of the silicon carbide substrate. It is a graph showing the relationship between the amount of warpage of a silicon carbide epitaxial wafer and the outer diameter of the wafer. 1A and 1B are process diagrams for explaining a method for manufacturing a silicon carbide epitaxial wafer, in which (a) is a method according to the present invention, and FIG. 2 (b) is a conventional method. The main differences between the method of manufacturing a silicon carbide epitaxial wafer of the present invention and the conventional method of manufacturing a silicon carbide epitaxial wafer will be described with reference to FIG. FIG. 3 is a cross-sectional view schematically showing a silicon carbide epitaxial wafer according to another embodiment of the present invention.

Hereinafter, this embodiment will be described in detail with reference to the drawings as appropriate. In the drawings used in the following explanation, characteristic parts of the present invention may be shown enlarged for convenience in order to make it easier to understand, and the dimensional ratio of each component may differ from the actual one. be. The materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited thereto, and can be implemented with appropriate changes within the scope of achieving the effects of the present invention.

(Silicon carbide epitaxial wafer)
FIG. 4 is a cross-sectional view schematically showing a silicon carbide epitaxial wafer 10 according to an embodiment of the present invention.
Silicon carbide epitaxial wafer 10 is a silicon carbide epitaxial wafer comprising silicon carbide substrate 1 and silicon carbide layer 2 provided on first main surface 1A of silicon carbide substrate 1 and having a film thickness of 100 μm or more, The amount of warpage of the silicon carbide epitaxial wafer is -20 μm or more and 20 μm or less.
<Definition of warp amount>
The "amount of warpage" of a silicon carbide epitaxial wafer is the maximum amount of warpage with respect to the plane S on the main surface (the surface not facing the plane S) of the silicon carbide epitaxial wafer when the silicon carbide epitaxial wafer is placed on the plane S. It is the height difference between the highest position and the lowest position. Here, the sign of the amount of warpage is determined by referring to FIG. Referring to FIG. 1(b), if it is convex upward (the center position of the silicon carbide epitaxial wafer is located higher than the outer circumferential position with respect to the plane S), it is considered a positive value. do.
Hereinafter, with reference to FIG. 1, "plus" and "minus" of "amount of warpage" used in this specification mean "plus" and "minus" when the silicon carbide epitaxial layer is warped in a convex manner toward the growth surface side (corresponding to FIG. 1(b)). If the curve is convex toward the side opposite to the growth surface (in other words, if the curve is concave when viewed with the growth surface facing upward; this corresponds to Fig. 1(a)), it will be given a negative value. do. Further, the definition of the amount of warpage in each of the plus and minus directions is as shown in FIGS. 1(a) and 1(b).
In the case of a silicon carbide substrate before epitaxial layer formation, the epitaxial surface on which the epitaxial layer is formed and the back surface facing it can be defined, so the "amount of warpage" can be similarly defined with the epitaxial surface as the upper side and the back side as the lower side. be done.

<Silicon carbide substrate>
Silicon carbide (SiC) has many crystal polymorphs, and silicon carbide substrates having these crystal polymorphs can be used. 4H-SiC is commonly used to fabricate practical SiC devices, and 4H-SiC substrates are preferred.
Further, as the silicon carbide substrate, a silicon carbide single crystal substrate processed from a silicon carbide bulk crystal produced by a sublimation method or the like can be used.
Therefore, a 4H-SiC single crystal substrate is preferable as the silicon carbide substrate.

Although any off-angle can be used as the off-angle of the silicon carbide substrate, from the viewpoint of cost reduction, a silicon carbide substrate having a small off-angle, for example, one having a small off-angle of 0° or more and 8° or less is preferable.

The thickness of the silicon carbide substrate is not particularly limited, but may be, for example, 200 μm or more and 700 μm or less, preferably 300 μm or more and 600 μm or less.
A 4-degree off-board substrate with a thickness of 350 μm is often used, but one with a thickness of 500 μm is also commercially available.

It is preferable that the surface roughness of the second main surface facing the first main surface of the silicon carbide substrate is 5 nm or more. Furthermore, the surface roughness of the second main surface is preferably 20 nm or more.
The surface roughness of the second main surface is an index of warpage of the convex shape toward the second main surface (back surface) side of the silicon carbide substrate before the silicon carbide epitaxial layer is grown. This serves as an index for compensating for warpage of the convex shape toward the first principal surface (growth surface) as the thickness increases. If the required thickness of the epitaxial growth layer is determined first, the amount of warpage caused by the epitaxial layer can be determined from FIG. 2, so that the surface roughness of the second principal surface required for compensation can be selected from FIG. 6.
Considering the recovery of concave warpage (convex warpage toward the second main surface side) as a silicon carbide substrate due to the hydrogen heating step before silicon carbide epitaxial layer growth, which will be described later (FIGS. 5 and 6), the second If the surface roughness of the main surface is 5 nm or more, the amount of warpage of the wafer can be maintained at around 10 μm (-10 μm) even after hydrogen heating with a 3-inch wafer. can.
According to FIG. 2, if the back surface convex shape treatment before epitaxial growth of the present invention is not performed, in a 3-inch wafer, the amount of warpage of a silicon carbide epitaxial wafer with an epitaxial layer thickness of 100 μm will be approximately 22 μm. If the surface roughness of the second main surface of the silicon substrate is set to 5 nm or more, the amount of warpage of the silicon carbide epitaxial wafer after completion of the silicon carbide epitaxial wafer will be -20 μm or more and 20 μm or less. Based on FIG. 6, when the surface roughness of the second main surface of the silicon carbide substrate is 120 nm, the amount of warpage of the silicon carbide substrate after the hydrogen heating process is about -42 μm. Even when the thickness of the silicon carbide epitaxial wafer is 120 nm, the amount of warpage of the silicon carbide epitaxial wafer after completion of the silicon carbide epitaxial wafer is −20 μm or more and 20 μm or less.
Furthermore, based on FIG. 6, when the surface roughness of the second main surface is about 20 nm, the amount of warpage of the silicon carbide substrate after the hydrogen heating process is about -20 μm. The amount of warpage of the wafer becomes close to zero. That is, it is more preferable that the surface roughness of the second main surface is 20 nm or more for a silicon carbide epitaxial wafer having an epitaxial layer of 100 μm or more. As will be described later, when the wafer is enlarged, the amount of warpage increases compared to the case of 3 inches, so this is suitable for highly accurate control of the amount of warpage.
Note that the method of Patent Document 1 is a method that is the exact opposite of the method of the present invention because the damaged layer on the back surface is removed to lower the surface roughness (Ra) of the back surface.

<Silicon carbide layer>
The silicon carbide layer is preferably a silicon carbide epitaxial layer.
The thickness of the silicon carbide layer is 100 μm or more, which is a so-called thick film. This is to provide a silicon carbide epitaxial wafer suitable for high voltage power devices.
The optimum thickness of this epitaxial film is determined according to the design specifications of the device's withstand voltage, and for ultra-high voltage devices, approximately 150 μm, 200 μm, or 250 μm is required.
An example of an upper limit is about 500 μm from the viewpoint of difficulty in epitaxial growth.

The amount of warpage of the silicon carbide epitaxial wafer is −20 μm or more and 20 μm or less.
In the present invention, the method for reducing the amount of warpage of a silicon carbide epitaxial wafer is to form a convex surface (second principal surface) of the silicon carbide substrate that is not the growth surface before growing an epitaxial layer on the silicon carbide substrate. The key is to keep it that way. This reduces the amount of warpage of the silicon carbide epitaxial wafer after epitaxial layer growth (when the silicon carbide epitaxial wafer is completed).
Note that in this specification, the first main surface (epitlayer growth surface) side may be referred to as the "upper side" and the side of the second main surface opposite to the first main surface may be referred to as the "lower side." In addition, when the entire wafer consisting of a silicon carbide epitaxial layer and a silicon carbide substrate has a convex shape on the first main surface side (upper side), the "wafer as a whole has a convex shape", while on the other hand, the second main surface side (lower side) When the wafer has a convex shape, it is sometimes referred to as "the wafer as a whole has a concave shape."
That is, as the silicon carbide epitaxial layer is grown on the silicon carbide substrate, the wafer made of the silicon carbide epitaxial layer and the silicon carbide substrate becomes increasingly warped in a convex shape on the first main surface side. Therefore, by making the substrate before silicon carbide epitaxial layer growth into a convex shape on the second main surface side, the amount of warping of the silicon carbide epitaxial wafer after epitaxial layer growth (when the silicon carbide epitaxial wafer is completed) can be reduced. do.
The Twyman effect is used as a means to make the silicon carbide substrate, before the silicon carbide epitaxial layer is grown, convex on the second main surface (back surface) side. The Twyman effect refers to the effect that when there is a difference in stress (residual stress) on both sides of a substrate, a force acts to compensate for the balance of stress on both sides, causing warpage. That is, if the surface roughness of the second main surface of the silicon carbide substrate is increased, the silicon carbide substrate will warp in a convex shape toward the second main surface (back surface) due to the Twyman effect (see FIG. 8(a)). (see (ii)).
As the silicon carbide epitaxial layer grows on the first main surface (front surface, growth surface) of the silicon carbide substrate that is curved in a convex shape toward the second main surface (back surface), the silicon carbide epitaxial layer In a wafer made of a silicon carbide substrate, as the film thickness increases, the amount of concave warpage of the wafer as a whole decreases. When the film thickness reaches a predetermined thickness, the amount of warpage becomes zero, and as the film thickness becomes even thicker, the wafer as a whole becomes warped in a convex shape.
When the silicon carbide epitaxial wafer is completed, the amount of warpage of the entire wafer is approximately zero, and the amount of warpage of the silicon carbide substrate before the growth of the silicon carbide epitaxial layer is in a convex shape toward the second main surface side. If processing is performed to increase the surface roughness of the main surface, the amount of warpage of the silicon carbide epitaxial wafer can be set to -20 μm or more and 20 μm or less.

Hereinafter, the relationship between the surface roughness of the second main surface (back surface) of the silicon carbide substrate and the amount of warpage of the wafer will be explained. By the way, during epitaxial growth, it is common to perform heat treatment in a hydrogen atmosphere to clean the surface of the silicon carbide substrate before the start of growth. At this time, the temperature of the silicon carbide substrate increases, so the amount of warpage after heating in a hydrogen atmosphere is important.
Therefore, the relationship between the surface roughness of the second main surface (back surface) of the silicon carbide epitaxial wafer before and after the hydrogen heating step and the amount of warpage is shown in FIGS. 5 and 6, respectively. FIG. 5 shows the result before the hydrogen heating process, and FIG. 6 shows the result after the hydrogen heating process. The horizontal axis is the surface roughness of the second main surface (back surface), and the vertical axis is the amount of warpage.

Figures 5 and 6 show a 4H-SiC single crystal substrate with an outer diameter of 3 inches, a thickness of 350 μm, and an off angle of 4 degrees, processed with the (000-1) C plane side as the second principal surface (back surface). This is the result of increasing the surface roughness.
Comparing FIG. 5 and FIG. 6, the hydrogen heating process recovers the concave warpage (convex warpage toward the second main surface) of the silicon carbide substrate, but the surface roughness of the second main surface recovers. By increasing the thickness, it is possible to increase the concave warpage.
From these results, in order to suppress the warpage of silicon carbide epitaxial wafers to 20 μm or less, the increase in warpage is assumed based on the thickness of the growing epitaxial growth layer, and the surface roughness of the second main surface of the silicon carbide substrate is adjusted appropriately. I know what I need to adjust.

Although the silicon carbide epitaxial layer can be formed on either the Si plane or the C plane, it is preferably formed on the Si plane.

The total thickness of the silicon carbide substrate and the silicon carbide layer (that is, the thickness of the silicon carbide epitaxial wafer) can be 450 μm or more.
For example, this corresponds to a case where the thickness of the silicon carbide substrate is 350 μm and the thickness of the silicon carbide layer is 100 μm.

The total thickness of the silicon carbide substrate and the silicon carbide layer (that is, the thickness of the silicon carbide epitaxial wafer) can be 600 μm or more.
For example, this corresponds to a case where the thickness of the silicon carbide substrate is 350 μm and the thickness of the silicon carbide layer is 250 μm.

The outer diameter of the silicon carbide substrate can be 75 mm or more.
FIG. 7 shows the relationship between the amount of warpage of a silicon carbide epitaxial wafer and the outer diameter of the wafer.
FIG. 7 shows the amount of warpage obtained for a silicon carbide epitaxial wafer in which a 240 μm thick epitaxial layer was formed on a substrate with an outer diameter of 3 inches (75 mm), since the radius of curvature of the warp was approximately 24.2 m. This is the result of calculating the amount of warpage when the outer diameter of the wafer is 100 μm, 150 μm, and 200 μm based on this radius of curvature. As the outer diameter of the wafer increases, the effective amount of warpage increases. Conversely, the effect of warpage correction according to the present invention becomes more pronounced as the outer diameter of the wafer increases. At present, a 6-inch SiC manufacturing line has begun to operate, and the present invention is very effective when using thick-film silicon carbide epitaxial wafers in the manufacturing process of large wafers.

<Relationship between warpage of silicon carbide epitaxial wafer and doping>
The main cause of warpage in silicon carbide epitaxial wafers is that the formed silicon carbide layer is thick. A possible mechanism for further increasing the warpage is a difference in lattice constant caused by doping to the silicon carbide substrate and silicon carbide layer.
Nitrogen (N) is mainly used as a donor to make a silicon carbide semiconductor n-type, but it is known that nitrogen acts in the direction of decreasing the lattice constant of silicon carbide. Further, in order to make a silicon carbide semiconductor p-type, boron (B) or aluminum (Al) is mainly used as an acceptor. Here, it is known that boron works in the direction of decreasing the lattice constant of silicon carbide, whereas aluminum works in the direction of increasing the lattice constant of silicon carbide. Therefore, when a thick silicon carbide layer 2 is grown on a silicon carbide substrate 1, the epitaxial layer growth side tends to warp in a convex shape in the following cases.
(1) When silicon carbide substrate 1 is heavily doped with a dopant that reduces the lattice constant, and silicon carbide layer 2 is non-doped or lightly doped. When silicon carbide substrate 1 is n-type, doping with nitrogen alone, or co-doping with nitrogen and boron or aluminum added at a concentration of 1/5 or less to nitrogen may be considered. When silicon carbide substrate 1 is p-type, doping with boron alone or co-doping with boron and nitrogen at a concentration of ⅕ or less of boron can be considered. The doping concentration of silicon carbide substrate 1 is typically 1×10 ¹⁸ cm ⁻³ or higher, further 5×10 ¹⁸ cm ⁻³ or higher, and further 1×10 ¹⁹ cm ⁻³ or higher. The doping concentration of silicon carbide layer 2 is typically 1/1000 or less, further 1/5000 or less, further 1/10000 or less of the silicon carbide substrate. That is, since silicon carbide layer 2 is non-doped or lightly doped, the lattice constant hardly changes. Therefore, since the dopant in silicon carbide layer 2 is at a low concentration, it may be any one of nitrogen, boron, and aluminum, or a combination thereof. Thereby, the lattice constant of silicon carbide layer 2 becomes relatively larger than that of silicon carbide substrate 1.

(2) When silicon carbide substrate 1 is undoped or doped at a lower concentration than the silicon carbide layer, and silicon carbide layer 2 is doped with aluminum at a high concentration to increase the lattice constant. The doping concentration of silicon carbide substrate 1 is typically 1/1000 or less, further 1/5000 or less, and even 1/10000 or less of the silicon carbide layer. Since silicon carbide substrate 1 is non-doped or lightly doped, the lattice constant hardly changes. At this time, the dopant to silicon carbide substrate 1 may be any one of nitrogen, boron, and aluminum, or a combination thereof, since the dopant is at a low concentration. The aluminum doping concentration in silicon carbide layer 2 is typically 1×10 ¹⁸ cm ⁻³ or higher, further 5×10 ¹⁸ cm ⁻³ or higher, and further 1×10 ¹⁹ cm ⁻³ or higher. Silicon carbide layer 2 may be co-doped with nitrogen added at a concentration of 1/5 or less of aluminum. Thereby, the lattice constant of silicon carbide layer 2 becomes relatively larger than that of silicon carbide substrate 1.
(3) To summarize (1) and (2) above, donors are added to silicon carbide substrate 1 and silicon carbide layer 2 so that the lattice constant of silicon carbide layer 2 is relatively larger than that of silicon carbide substrate 1. Alternatively, one or both of the acceptors may be doped, and the doping concentration difference between silicon carbide substrate 1 and silicon carbide layer 2 may be 1000 times or more, further 5000 times or more, or even 10000 times or more different. .
Applications that require thick silicon carbide epitaxial wafers are currently recognized as IGBTs, high voltage MOSFETs, and PIN diodes. In an IGBT, for example, an n-type epitaxial layer (doped with nitrogen, doping concentration 2×10 ¹⁴ cm ⁻³ or less) is formed on a p-type substrate (doped with boron or co-doped with boron + nitrogen, doping concentration 2×10 ¹⁹ cm ⁻³ or more). The formed silicon carbide epitaxial wafer is used. For high-voltage MOSFETs and PIN diodes, for example, an n-type epitaxial layer (nitrogen doped, impurity concentration 5×10 ¹⁴ cm ^-3 or less) is formed on an n-type substrate (nitrogen doped, doping concentration 5×10 ¹⁸ cm ^-3 or more). The formed silicon carbide epitaxial wafer is used. At this time, a co-doped substrate doped with both nitrogen and an acceptor (boron or aluminum) may be used as the n-type substrate. Note that in the case of a co-doped n-type substrate, the nitrogen concentration is about 5 times higher than that of the acceptor. These applications correspond to cases (1) and (3) above, and the present invention is typically applied.

(Method for manufacturing silicon carbide epitaxial wafer)
The method for manufacturing a silicon carbide epitaxial wafer of the present invention includes preparing a silicon carbide substrate having a first main surface and a second main surface opposite thereto, and placing the second main surface of the silicon carbide substrate with the first main surface facing upward. The method includes processing the silicon carbide substrate so that the surface side has a convex shape, and epitaxially growing a silicon carbide layer on the first main surface of the silicon carbide substrate.

The main differences between the method of manufacturing a silicon carbide epitaxial wafer of the present invention and the conventional method of manufacturing a silicon carbide epitaxial wafer will be described with reference to FIG.

FIG. 8(b) is a schematic cross-sectional view for explaining a conventional method for manufacturing a silicon carbide epitaxial wafer, showing the steps of (i) preparing a substrate and (ii) performing epitaxial growth on the substrate. have As shown in FIG. 8(a), in the method for manufacturing a silicon carbide epitaxial wafer of the present invention, between (i) the step of preparing the substrate and (iii) the step of performing epitaxial growth on the substrate, (ii) the substrate There is a step of machining the lower side into a convex shape.

A method of processing a silicon carbide substrate so that the second main surface side has a convex shape is to increase the surface roughness of the second main surface (back surface) and use the Twyman effect to form a convex shape on the second main surface side (bottom surface). side) has a convex shape.
As a method for increasing the surface roughness of the second main surface (back surface), a known method can be used, and examples thereof include grinding, polishing, and the like. Either polishing or grinding may be used, or polishing and grinding may be used together.

EXAMPLES Hereinafter, the present invention will be explained in more detail by showing Examples, but the present invention is not limited thereto.

(Example 1)
<Preparation and processing of silicon carbide substrate>
A silicon carbide substrate having an outer diameter of 75 mm and having a 4H crystal structure with a (0001) Si plane inclined at 4 degrees in the <11-20> direction was prepared. The (000-1) C-plane side of this silicon carbide substrate was subjected to a grinding process to give a surface roughness of 122 nm. In this grinding process, infeed grinding was performed using a #230 diamond wheel with an abrasive grain diameter of 70 to 80 μm using a commercially available grinding device. The silicon carbide substrate used at this time was a nitrogen-doped n-type substrate, and the specified nitrogen concentration was 5 to 8×10 ¹⁸ cm ⁻³ .
<Hydrogen heating process>
With the silicon carbide substrate introduced into the reactor of the chemical vapor deposition apparatus at a flow rate of 30 slm, the pressure inside the reactor was maintained at 2.7 kPa, and the silicon carbide substrate was heated by a high-frequency induction heating section. The silicon substrate was heated to 1590°C. Heating in this state was performed for 30 minutes.
<Epitaxial growth layer formation process>
Next, silane was introduced into the reactor at a flow rate of 54 sccm, propane was introduced at a flow rate of 21 sccm, and nitrogen was introduced at a flow rate of 8 sccm to give an n-type carrier concentration of 2×10 ¹⁴ cm ⁻³ on the (0001) Si plane of the silicon carbide substrate. An epitaxially grown layer of 240 μm in thickness was formed.
According to the above procedure, a silicon carbide epitaxial wafer according to Example 1 was manufactured.

(Comparative example 1)
A silicon carbide epitaxial wafer according to Comparative Example 1 was produced in the same manner as in Example 1 except that the (000-1) C-plane side surface of the silicon carbide substrate was not subjected to the grinding process and the surface roughness was 0.1 nm. was manufactured.

(Example 2)
Example 1 was prepared in the same manner as in Example 1, except that the (000-1)C side surface of the silicon carbide substrate was subjected to a grinding process to give a surface roughness of 59 nm, and the epitaxial growth layer thickness was 200 μm. A silicon carbide epitaxial wafer according to Example 2 was manufactured. In this grinding process, a #400 diamond wheel with abrasive grain diameter of 30 to 40 μm was used.

(Comparative example 2)
In addition, the silicon carbide according to Comparative Example 2 was prepared in the same manner except that the (000-1) C-plane side surface of the silicon carbide substrate of Example 2 was not subjected to the grinding process and the surface roughness was 0.1 nm. Epitaxial wafers were manufactured.

<Measurement of warp amount>
Warpage measurements of silicon carbide substrates and silicon carbide epitaxial wafers were performed in a non-adsorbed state using a normal incidence interferometer. (0001) With the Si side facing up, the warpage value for the convex shape as shown in Figure 1(b) is +, and the warpage value for the concave shape as shown in Figure 1(a) is -. It is written as.
The results of warpage measurements of silicon carbide substrates and silicon carbide epitaxial wafers are shown in Table 1 below.

As shown in Table 1, by grinding the (000-1) C-plane side of the silicon carbide substrate and making it concave as a whole before forming the epitaxial growth layer, the warpage of the silicon carbide epitaxial wafer can be kept to 20 μm or less. We were able to.
On the other hand, when the (000-1) C-plane side of the silicon carbide substrate was not ground, the warpage of the silicon carbide epitaxial wafer was 20 μm or more.

Although the invention made by the present inventor has been specifically explained based on the embodiments above, the present invention is not limited to the above embodiments, and various changes can be made without departing from the gist thereof. Needless to say.
In the embodiments of the invention described above, a silicon carbide epitaxial wafer in which a single silicon carbide layer is laminated on a silicon carbide substrate is illustrated to be the simplest. However, in actual applications, as shown in FIG. 9, a thin silicon carbide intermediate layer 2B is often used between silicon carbide substrate 1 and thick silicon carbide layer 2A. A silicon carbide epitaxial wafer 10' shown in FIG. 9 includes a silicon carbide substrate 1 and a silicon carbide layer 2' provided on a first main surface 1A of the silicon carbide substrate 1 and having a thickness of 100 μm or more. The epitaxial wafer is a silicon carbide epitaxial wafer whose warp amount is -20 μm or more and 20 μm or less, and the silicon carbide layer 2' is a thick silicon carbide layer 2A (for example, a drift layer with a thickness of about 150 to 350 μm described later). , and a thin silicon carbide intermediate layer 2B (for example, a collector layer with a thickness of about 1 to 10 μm and/or a field stop layer with a thickness of about 0.5 to 2 μm, which will be described later). Since the warpage is caused by having the thick silicon carbide layer 2A, the problem of the present invention is the same even if the thin silicon carbide intermediate layer 2B is used, and the invention based on the embodiment can be suitably applied.
For example, in an n-channel IGBT, in contact with a p-type silicon carbide substrate, a collector layer (p-type, doping concentration of approximately 1×10 ¹⁸ to 1×10 ¹⁹ cm ⁻³ , thickness of approximately 1 to 10 μm), a field stop layer ( n-type, doping concentration approximately 1×10 ¹⁷ to 1×10 ¹⁸ cm ⁻³ , thickness approximately 0.5 to 2 μm), thick drift layer (n-type, doping concentration approximately 2×10 ¹⁴ cm ⁻³ , thickness approximately An epitaxial wafer having a thickness of 150 to 350 μm) formed thereon is prepared. Then, a gate and emitter similar to a vertical MOSFET are formed on the surface of the drift layer. That is, in addition to the thick drift layer, the silicon carbide layer in the embodiment of the invention includes an intermediate layer (a multilayer film such as a collector layer and a field stop layer) that is sufficiently thin (for example, 1/10 or less) of the drift layer. ) is understood to include. The above-mentioned "relationship between warpage of a silicon carbide epitaxial wafer and doping" refers to the relationship between the doping concentration of the thickest silicon carbide layer provided directly or via an intermediate layer on the silicon carbide substrate and the doping concentration of the silicon carbide substrate. It would be better to read it as a relationship. Since the intermediate layer is thin, the doping type and concentration of impurities have little effect on warpage.
In addition, in PIN diodes and high voltage MOSFETs ^{, a} thick drift layer (n An epitaxial wafer is prepared in which a doping concentration of about 5×10 ¹⁴ cm ⁻³ and a thickness of about 100 to 300 μm are sequentially formed. Then, a diode structure or a MOSFET structure is formed on the surface of the drift layer. Here again, the silicon carbide layer in the embodiments and examples of the invention is understood to refer to the entire drift layer and intermediate layer (buffer layer).
As described above, the intermediate layer is not limited to the collector layer, field stop layer, and buffer layer shown above, but is a single layer or multiple layers of silicon carbide used for optimizing the device structure.

(Additional note 1)
A silicon carbide epitaxial wafer comprising a silicon carbide substrate and a silicon carbide layer provided on a first main surface of the silicon carbide substrate and having a thickness of 100 μm or more,
A silicon carbide epitaxial wafer, wherein the amount of warpage of the silicon carbide epitaxial wafer is −20 μm or more and 20 μm or less.
(Additional note 2)
The silicon carbide substrate and the silicon carbide layer are doped with one or both of a donor and an acceptor such that the lattice constant of the silicon carbide layer is relatively larger than the lattice constant of the silicon carbide substrate, and The silicon carbide epitaxial wafer according to Supplementary Note 1, wherein the doping concentration difference between the silicon carbide substrate and the silicon carbide layer is 1000 times or more.
(Additional note 3)
The silicon carbide substrate may be doped with nitrogen alone, doped with boron alone, doped with nitrogen as the main component and doped with boron or aluminum to 1/5 or less of the amount of nitrogen, or doped with boron as the main component with nitrogen as the amount of 1/5 or less of the boron amount. A first impurity is added by either;
The silicon carbide layer is doped with a second impurity, which is either non-doped, doped with nitrogen alone, doped with boron alone, doped with aluminum alone, or doped with a combination of two or three of nitrogen, boron, and aluminum. is,
The silicon carbide epitaxial wafer according to Supplementary Note 1 or 2, wherein the concentration of the first impurity is 1000 times or more the concentration of the second impurity.
(Additional note 4)
The silicon carbide layer has an intermediate layer in contact with the silicon carbide substrate and a drift layer formed on the intermediate layer, and the thickness of the intermediate layer is 1/10 or less of the thickness of the drift layer. A silicon carbide epitaxial wafer according to any one of Supplementary Notes 1 to 3.

1 Silicon carbide substrate 1A First main surface 1B Second main surface 2 Silicon carbide layer 10 Silicon carbide epitaxial wafer

Claims (4)

A method for manufacturing a silicon carbide epitaxial wafer comprising a silicon carbide substrate and a silicon carbide layer provided on a first main surface of the silicon carbide substrate and having a thickness of 100 μm or more,
preparing the silicon carbide substrate having the first main surface and a second main surface opposite thereto, and processing the silicon carbide substrate so that the second main surface side of the silicon carbide substrate has a convex shape;
epitaxially growing the silicon carbide layer on the first main surface of the silicon carbide substrate,
The step of processing the silicon carbide substrate includes the step of polishing and/or grinding the second main surface,
The amount of warpage of the silicon carbide epitaxial wafer is -20 μm or more and 20 μm or less,
A method for manufacturing a silicon carbide epitaxial wafer. The silicon carbide substrate contains nitrogen at a doping concentration of 5×10 ¹⁸ cm ^{−3 or} more,
The doping concentration of the silicon carbide layer is 1/5000 or less of the doping concentration of the silicon carbide substrate,
The silicon carbide substrate is 4H-SiC,
The total thickness of the silicon carbide substrate and the silicon carbide layer is 450 μm or more,
The method for manufacturing a silicon carbide epitaxial wafer according to claim 1. The method for manufacturing a silicon carbide epitaxial wafer according to claim 1 or 2, wherein the total thickness of the silicon carbide substrate and the silicon carbide layer is 600 μm or more. The method for manufacturing a silicon carbide epitaxial wafer according to any one of claims 1 to 3 , wherein the second main surface facing the first main surface of the silicon carbide substrate has a surface roughness (Ra) of 20 nm or more.

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