JP7380179B2 - Multilayer SOI wafer, its manufacturing method, and X-ray detection sensor - Google Patents

Description

The present invention relates to a multilayer SOI wafer, a method for manufacturing the same, and an X-ray detection sensor.

X-rays are used in various fields such as baggage inspection, food foreign substance inspection, medical care, and astronomical observation. Although it was once common to detect X-rays using photosensitive film, as its use expanded, it became possible to use semiconductor wafers such as silicon to measure X-rays at high speed and with high sensitivity. X-ray detection sensors composed of photoelectric conversion elements have attracted attention in recent years.

For example, in the X-ray detection sensor disclosed in Patent Document 1, an SOI (Silicon on Insulator) wafers are used. For example, in an X-ray detection sensor manufactured using this SOI wafer, the support substrate is used as an X-ray sensor section (X-ray light receiving section). This is because, considering the absorption rate of X-rays by silicon single crystal, the X-ray sensor portion needs to have a sufficient thickness. Furthermore, a device such as a CMOS circuit that processes signals transmitted from the X-ray detection sensor section is formed in the p-type semiconductor layer.

Note that in the SOI wafer, generally one BOX layer is provided. However, multilayer SOI wafers are also known in which a plurality of BOX layers are provided and an SOI layer made of single crystal silicon is provided between these BOX layers.

International Publication No. 2011/111754 Japanese Patent Application Publication No. 2007-109961

By the way, when manufacturing a semiconductor device using an SOI wafer, if the active layer is subjected to plasma etching or the like, the BOX layer becomes charged (charged up), which may affect the device element structure such as the gate film. Further, when an SOI wafer is used as an X-ray detection sensor, it is exposed to high-energy X-rays, so there is a fear that the BOX layer may be charged up even during use of the X-ray detection sensor.

Therefore, in order to prevent charge-up of the BOX layer, the present inventor considered supplying a ground potential to the single crystal silicon layer between the BOX layers while using a multilayer SOI wafer known from Patent Document 2 and the like. However, the monocrystalline silicon layer has a limit in increasing its conductivity, and cannot sufficiently prevent charge-up. Therefore, an object of the present invention is to provide a multilayer SOI wafer suitable for use in an X-ray detection sensor and a method for manufacturing the same. A further object of the present invention is to provide an X-ray detection sensor using this multilayer SOI wafer.

The present inventor made extensive studies to solve the above problems, came up with the idea of using a polycrystalline silicon layer as an SOI layer between insulating layers in a multilayer SOI wafer, and completed the present invention. That is, the gist of the present invention is as follows.

(1) Silicon wafer,
a first insulating layer provided on the surface of the silicon wafer;
a polycrystalline silicon layer provided on the surface of the first insulating layer;
a second insulating layer provided on the surface of the polycrystalline silicon layer;
an active layer made of single crystal silicon provided on the surface of the second insulating layer;
A multilayer SOI wafer comprising:

(2) The conductivity type of the silicon wafer is p type, the resistivity is 100 Ω·cm or more, the thickness is 100 μm or more, and the oxygen concentration is 5.0×10 ¹⁷ atoms/cm ³ or less. , the multilayer SOI wafer according to (1) above.

(3) a first insulating layer forming step of forming a first insulating layer on the surface of the silicon wafer;
a polycrystalline silicon layer forming step of forming a polycrystalline silicon layer on the surface of the first insulating layer;
a second insulating layer forming step of forming a second insulating layer on the surface of the polycrystalline silicon layer;
an activation treatment step in which the surface of the second insulating layer and the surface of the active layer silicon wafer are subjected to activation treatment in a vacuum at room temperature to make both surfaces activated surfaces;
Following the activation treatment step, a joining step of joining both activated surfaces by bringing them into contact under the vacuum at room temperature;
After the bonding step, a thinning step of thinning the active layer silicon wafer to obtain an active layer;
A method for manufacturing a multilayer SOI wafer, comprising:

(4) a first insulating layer forming step of forming a first insulating layer on the surface of the silicon wafer;
a second insulating layer forming step of forming a second insulating layer on the surface of the active layer silicon wafer;
a polycrystalline silicon layer forming step of forming a polycrystalline silicon layer on the surface of the first insulating layer;
an activation treatment step in which the surface of the polycrystalline silicon layer and the surface of the second insulating layer are subjected to activation treatment in a vacuum at room temperature to make both surfaces activated surfaces;
Following the activation treatment step, a joining step of joining both activated surfaces by bringing them into contact under the vacuum at room temperature;
After the bonding step, a thinning step of thinning the active layer silicon wafer to obtain an active layer;
A method for manufacturing a multilayer SOI wafer, comprising:

(5) An X-ray detection sensor formed using the multilayer SOI wafer according to (1) or (2) above,
An X-ray detection section is provided on the silicon wafer,
A ground electrode portion is provided that is electrically connected to the polycrystalline silicon layer and is supplied with a ground potential,
An X-ray detection sensor characterized in that the active layer is provided with a MOS type transistor section.

According to the present invention, it is possible to provide a multilayer SOI wafer suitable for use in an X-ray detection sensor and a method for manufacturing the same. Furthermore, according to the present invention, it is possible to provide an X-ray detection sensor using this multilayer SOI wafer.

FIG. 1 is a schematic cross-sectional view illustrating a multilayer SOI wafer according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing steps from a first insulating layer formation step to an activation treatment step in the description of the first embodiment of the method for manufacturing a multilayer SOI wafer according to the present invention. FIG. 2 is a schematic cross-sectional view showing steps from a bonding step to a thinning step in the description of the first embodiment of the method for manufacturing a multilayer SOI wafer according to the present invention. FIG. 6 is a schematic cross-sectional view showing steps from a first insulating layer formation step to an activation treatment step in the description of the second embodiment of the method for manufacturing a multilayer SOI wafer according to the present invention. FIG. 7 is a schematic cross-sectional view showing a process from a bonding process to a thinning process in a second embodiment of the method for manufacturing a multilayer SOI wafer according to the present invention. 1 is a schematic cross-sectional view of an apparatus used when performing vacuum room temperature bonding in an embodiment of the method for manufacturing a multilayer SOI wafer according to the present invention. 1 is a schematic cross-sectional view illustrating an X-ray detection sensor according to an embodiment of the present invention. FIG. 2 is a plan view illustrating a cylindrical electrode formed on a multilayer SOI wafer in an example.

Embodiments of the present invention will be described in detail below with reference to the drawings. In addition, in principle, the same constituent elements are given the same reference number with the last two digits of the number, and redundant explanation will be omitted. In addition, in FIGS. 1 to 5, the thickness of each component is shown in an exaggerated manner, unlike the actual thickness ratio, in order to simplify the drawings. For convenience of explanation, FIGS. 2-1 and 2-2 are collectively referred to as FIG. 2, and FIGS. 3-1 and 3-2 are collectively referred to as FIG. 3.

(Multilayer SOI wafer)
Please refer to FIG. A multilayer SOI wafer 100 according to an embodiment of the present invention includes a silicon wafer 110, a first insulating layer 120 provided on the surface of the silicon wafer 110, and a polycrystalline silicon wafer provided on the surface of the first insulating layer 120. layer 130, a second insulating layer 140 provided on the surface of polycrystalline silicon layer 130, and an active layer 150 made of single crystal silicon provided on the surface of second insulating layer 140. The details of each configuration will be sequentially explained below.

<Silicon wafer>
The silicon wafer 110 is a support substrate for forming the first insulating layer 120 and supports the structure above it. As the silicon wafer 110, a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone melting method (FZ method) can be sliced with a wire saw or the like. When producing an X-ray detection sensor using the multilayer SOI wafer 100, a sensor section is formed on the silicon wafer 110. Although not shown, a polycrystalline silicon layer may be formed (PBS) on the back side of the silicon wafer 110 (the side on which the insulating layer is not formed) in order to obtain gettering ability.

<First insulating layer>
The first insulating layer 120 is provided on the surface of the silicon wafer 110, and typically uses silicon oxide. Further, as long as electrical insulation can be ensured, the material is not limited to silicon oxide, and diamond (polycrystalline, single crystal), diamond-like carbon (DLC), etc. may also be used.

<Polycrystalline silicon layer>
The polycrystalline silicon layer 130 is provided on the surface of the first insulating layer 120 and can be formed by a CVD method or the like. Since polycrystalline silicon includes grain boundaries, resistance can be lowered at these grain boundaries, making it easier for current to flow. Therefore, polycrystalline silicon has lower resistance than single crystal silicon. It is preferable that the polycrystalline silicon layer 130 has a resistivity of 0.0001 Ω·cm or more and 0.001 Ω·cm or less. The conductivity type may be p-type or n-type. Further, it is preferable that the crystal grain size of the polycrystalline silicon is 1 μm or less.

<Second insulating layer>
The second insulating layer 140 is provided on the surface of the polycrystalline silicon layer 130, and like the first insulating layer 120, silicon oxide or the like can be used. The material constituting the second insulating layer 140 may be the same as or different from the first insulating layer 120.

<Active layer>
Active layer 150 is provided on the surface of second insulating layer 140 and is made of single crystal silicon. The active layer 150 may be obtained from a bulk silicon wafer like the silicon wafer 110, or may be obtained from a silicon epitaxial layer formed on the surface of a bulk silicon wafer.

As described above, since the multilayer SOI wafer 100 according to an embodiment of the present invention includes the polycrystalline silicon layer 130, this can be used as a low-resistance conductive layer. Therefore, when forming a semiconductor device using the multilayer SOI wafer 100, it can be used to form a wiring part that is electrically connected to the polycrystalline silicon layer 130 and supplies a ground potential. It is possible to prevent the first and second insulating layers 120 and 140 from being charged up.

Further, since the multilayer SOI wafer 100 can effectively prevent charge-up of the first and second insulating layers 120 and 140, it is particularly preferable to use the multilayer SOI wafer 100 for use as an X-ray detection sensor. In this case, a sensor section of an X-ray detection sensor can be provided on the silicon wafer 110. Note that when the silicon wafer 110 is a p-type high-resistance substrate (specifically, the resistivity is 100 Ω cm or more), the sensor portion and the MOS There is a concern about resistance fluctuations caused by heat treatment when manufacturing device element structures such as type transistors. Therefore, it is preferable to limit the oxygen concentration of the silicon wafer 110 to 5.0×10 ¹⁷ atoms/cm ³ or less, and it is preferable that the oxygen concentration is 3.0×10 ¹⁷ atoms/cm ³ or less, and 2.0× More preferably, it is 10 ¹⁷ atoms/cm ³ or less. Although the lower limit of the oxygen concentration is not limited, an example of the lower limit is 1.0×10 ¹⁵ atoms/cm ³ in consideration of industrial productivity. The silicon wafer 110 that satisfies these oxygen concentration conditions is preferably an MCZ wafer obtained from a single crystal silicon ingot grown by the MCZ (Magnetic field applied Czochralski) method. For the same reason regarding oxygen concentration, it is also preferable that the silicon wafer 110 is an FZ wafer obtained from a single crystal silicon ingot grown by the FZ (Floating Zone) method. Note that the oxygen concentration of the silicon wafer is based on ASTM F121-1979, and a value measured using a Fourier Transform Infrared Spectrometer (FTIR) is used.

Furthermore, in order to make the multilayer SOI wafer 100 applicable to a sensor section of an X-ray detection sensor, it is also preferable to use a silicon wafer that does not contain COPs as the silicon wafer 110. Note that the term "silicon wafer not containing COPs" in this specification means a silicon wafer in which no COPs are detected by observation and evaluation described below. That is, first, a silicon wafer cut out from a single crystal silicon ingot grown by the CZ method is subjected to SC-1 cleaning (that is, ammonia water, hydrogen peroxide solution, and ultrapure water are mixed in a ratio of 1:1:15). The surface of the silicon wafer after cleaning was observed and evaluated using a Surfscan SP-2 manufactured by KLA-Tenchor as a surface defect inspection device, and bright spot defects estimated to be surface pits were detected. (LPD: Light Point Defect). At this time, the observation mode is Oblique mode (oblique incidence mode), and the estimation of surface pits is performed based on the detected size ratio of the Wide Narrow channel. The thus identified LPD is evaluated to determine whether it is a COP using an atomic force microscope (AFM). Note that when grown by the FZ method, no COP is formed on the silicon wafer 110.

As described above, although it is particularly preferable to use the multilayer SOI wafer 100 for producing an X-ray detection sensor, the use thereof is limited if the polycrystalline silicon layer 130 is used as a low-resistance conductive layer. There isn't.

Hereinafter, specific embodiments of the multilayer SOI wafer 100 suitable for application to the present invention will be described.

The conductivity type of the silicon wafer 110 is arbitrary; boron (B) may be used as a dopant to make it p-type, and phosphorus (P), arsenic (As), or antimony can be used to make it n-type. (Sb) etc. may be used. Furthermore, when used in a sensor section of an X-ray detection sensor, the thickness of the silicon wafer 110 may be reduced by grinding, polishing, etc., depending on the application. In that case, the thickness of the silicon wafer 110 is more preferably 200 μm or more, and even more preferably 300 μm or more. The upper limit of the thickness of the silicon wafer 110 is not particularly limited, but for example, if the wafer has a diameter of 300 mm, the upper limit is 775 μm±25 μm.

The film thicknesses of the first insulating layer 120 and the second insulating layer 140 are not particularly limited as long as insulation properties are ensured, but are preferably 100 nm or more in order to ensure voltage resistance as a multilayer SOI wafer. The thickness is preferably 500 nm or more. The upper limit of the film thickness is not particularly limited, but considering industrial productivity, the upper limit of the film thickness is about 50 μm. Note that the thicknesses of both may be the same or different.

The thickness of the polycrystalline silicon layer 130 is also not particularly limited, but is preferably, for example, 100 nm or more and 10 μm or less.

The thickness of the active layer 150 is not particularly limited, and may be set appropriately depending on the intended use of the device to be manufactured, and may be, for example, 1 μm or more and 10 μm or less. Further, the conductivity type of the active layer 150 is arbitrary, and the resistivity is not particularly limited as long as it is, for example, 0.1 Ω·cm or more and 10 Ω·cm or less. These are determined depending on the active layer silicon wafer used to obtain the active layer 150.

In the multilayer SOI wafer 100 described above, two insulating layers called so-called BOX layers are provided, but an additional insulating layer and a single crystal silicon layer or a polycrystalline silicon layer may be provided.

(Method for manufacturing multilayer SOI wafer)
Next, regarding the embodiment of the method for manufacturing the multilayer SOI wafer 100 according to the present invention that has been described so far, an embodiment for manufacturing the multilayer SOI wafer 100 according to the present invention will be described with reference to FIGS. do. As mentioned above, in principle, the same constituent elements are given the same reference numbers with the last two digits, and redundant explanation will be omitted. In the first embodiment of the manufacturing method with reference to FIG. 2, the second insulating layer 240 provided on the silicon wafer 210 serving as the support substrate and the active layer silicon wafer 255 are bonded under vacuum at room temperature. The second embodiment of the manufacturing method with reference to FIG. The layer 340 is bonded under vacuum at room temperature.

(First embodiment)
See FIG. 2. The embodiment of the method for manufacturing the multilayer SOI wafer 200 includes a first insulating layer forming step, a polycrystalline silicon layer forming step, a second insulating layer forming step, an activation treatment step, a bonding step, and a thinning step. It includes at least a step. By performing at least each of these steps, a multilayer SOI wafer 200 can be obtained. Hereinafter, the bonding method using the activation treatment step and the bonding step will be referred to as a "vacuum room temperature bonding method", and the same applies to the second embodiment. Hereinafter, details of each process in the first embodiment will be sequentially explained.

<Step of forming first insulating layer>
In this first embodiment, in the first insulating layer forming step, a first insulating layer 220 is formed on the surface of the silicon wafer 210. When forming the first insulating layer 220 made of silicon oxide, a general method such as a thermal oxidation method or a plasma CVD method may be applied to each of the silicon wafer 210 and the active layer silicon wafer 255.

<Process of forming polycrystalline silicon layer>
After forming the first insulating layer 220, in the polycrystalline silicon layer forming step, a polycrystalline silicon layer 230 is formed on the surface of the first insulating layer 220. For example, by introducing hydrogen gas as a carrier gas and trichlorosilane as a silicon source, the polycrystalline silicon layer 230 can be deposited on the first insulating layer 220. Note that when forming the polycrystalline silicon layer 230, the film formation temperature is preferably 900° C. or lower.

Next, in a second insulating layer forming step, a second insulating layer 240 is formed on the surface of the polycrystalline silicon layer 230. The method for forming the second insulating layer 240 may be the same as or different from the method for forming the first insulating layer 220 described above.

<Activation treatment process>
Next, in the activation treatment step, activation treatment is performed on the surface of the second insulating layer 240 and the surface of the active layer silicon wafer 255 in a vacuum at room temperature, so that both surfaces become activated surfaces 240A and 255A. . This activation treatment under vacuum at room temperature may be performed by irradiating each surface with, for example, an ion beam or a neutral atom beam. Due to the activation effect accompanying the beam irradiation, the surface of the second insulating layer 240 and the surface of the active layer silicon wafer 255 become activated surfaces 240A and 255A, respectively. Dangling bonds (bonding hands) for bonding silicon atoms appear on these activated surfaces 240A and 255A.

Examples of activation treatment methods include a method in which ionized elements are accelerated toward the substrate surface in a plasma atmosphere, and a method in which ionized elements accelerated from an ion beam device are accelerated toward the substrate surface. One form of an apparatus that implements this method will be described with reference to FIG. 4. The vacuum room temperature bonding apparatus 70 includes a plasma chamber 71, a gas inlet 72, a vacuum pump 73, a pulse voltage application device 74, and wafer fixing tables 75A and 75B. In addition, although each wafer is supported in the vertical direction in the vacuum room temperature bonding apparatus 70 of FIG. 4, it is also preferable to support each wafer in the horizontal direction. In this case, silicon atoms originating from the activation wafer 255 adhere to the second insulating layer 240 disposed opposite to each other by ion beam sputtering for activation, which is advantageous in that silicon dangling bonds are easily formed. It is. However, even with silicon oxide, it is possible to form enough silicon dangling bonds to the extent necessary for bonding.

First, the silicon wafer 210 on which the second insulating layer 240 is formed and the active layer silicon wafer 255 are placed and fixed on the wafer fixing tables 75A and 75B in the plasma chamber 71, respectively. Next, the pressure inside the plasma chamber 71 is reduced by the vacuum pump 73, and then the raw material gas is introduced into the plasma chamber 71 from the gas introduction port 72. Subsequently, the pulse voltage application device 74 applies a negative voltage to the wafer fixing tables 75A and 75B (as well as the silicon wafer 210 and the active layer silicon wafer 255) in a pulsed manner. As a result, plasma of the source gas is generated, and ions of the source gas contained in the generated plasma are accelerated toward each of the silicon wafer 210 and the active layer silicon wafer 255, and ions are irradiated onto each surface. I can do it. The element to be irradiated is preferably at least one selected from Ar, Ne, Xe, H, He, and Si.

<<Activation processing conditions>>
Specific conditions of chamber pressure, pulse voltage, and substrate temperature will be described in detail below, but these are only examples.

The chamber pressure in the plasma chamber 71 is preferably 5.0×10 ⁻⁵ Pa or less. The sputtered elements re-deposit onto the surface of the activation target, making it possible to prevent a decrease in the formation rate of dangling bonds.

The pulse voltages applied to the silicon wafer 210 and the active layer silicon wafer 255 may be set so that the acceleration energy of the irradiated element to each irradiated surface is 100 eV or more and 10 keV or less. If the acceleration energy is 100 eV or more, it is possible to suppress the deposition of the irradiated element on the substrate surface, and it is possible to efficiently form dangling bonds on the substrate surface. If the acceleration energy is 10 keV or less, the irradiated element can be prevented from being implanted into the substrate, so that dangling bonds can be efficiently formed on the substrate surface.

The frequency of the pulse voltage determines the number of times the irradiated surfaces of the silicon wafer 210 and the active layer silicon wafer 255 are irradiated with ions. The frequency of the pulse voltage is preferably 10 Hz or more and 10 kHz or less. If the frequency is 10 Hz or more, variations in ion irradiation can be absorbed, so the amount of ion irradiation is stabilized. If the frequency is 10 kHz or less, plasma formation by glow discharge is stable.

The pulse width of the pulse voltage determines the time during which the irradiated surfaces of the silicon wafer 210 and the active layer silicon wafer 255 are irradiated with ions. The pulse width is preferably 1 μsec or more and 10 msec or less. If the time is 1 μsec or more, the silicon wafer 210 and the active layer silicon wafer 255 can be stably irradiated with ions. If the time is 10 msec or less, plasma formation by glow discharge is stable.

In this activation treatment step, the silicon wafer 210 and the active layer silicon wafer 255 are not heated, and their temperature remains at room temperature (usually 30° C. to 90° C.), and the room temperature is maintained in the subsequent bonding step as well.

<Joining process>
Following the activation process described above, both activation surfaces 240A and 255A are brought into contact under vacuum at room temperature. Due to such contact, a bonding force is instantaneously exerted on the two activated surfaces 240A and 255A, and the silicon wafer 210 and the active layer silicon wafer 255 are firmly bonded using the activated surfaces 240A and 255A as bonding surfaces. Joined and integrated. As described above, in the vacuum room temperature bonding method including the above-mentioned activation treatment step and bonding step, both wafers are bonded instantly and firmly at room temperature.

<Thinning process of silicon wafer for active layer>
After bonding the silicon wafer 210 and the active layer silicon wafer 255 using both of the activation surfaces 240A and 255A as bonding surfaces, in the thinning step, the active layer silicon wafer 255 is thinned to obtain the active layer 250. In this way, a multilayer SOI wafer 200 can be obtained. Note that in the film thinning step, any known or arbitrary chemical etching, grinding, and polishing method can be suitably used, and specific examples include surface grinding and mirror polishing. Further, if hydrogen ions or the like are implanted into the active layer silicon wafer 255 for the purpose of peeling before the bonding process, the known smart cut method can be applied in this thin film process.

The multilayer SOI wafer 200 thus obtained includes a silicon wafer 210, a first insulating layer 220 provided on the surface of the silicon wafer 210, a polycrystalline silicon layer 230 provided on the surface of the first insulating layer 220, and a polycrystalline It has a second insulating layer 240 provided on the surface of the silicon layer 230 and an active layer 250 provided on the surface of the second insulating layer 240.

In this embodiment, it is also preferable to polish the surface of the second insulating layer 240 for forming the activated surface 240A prior to vacuum room temperature bonding.

(Second embodiment)
Returning to FIG. 3, a method for manufacturing a multilayer SOI wafer 300 according to the second embodiment will be described. In the first embodiment, vacuum room temperature bonding is performed between the second insulating layer 240 formed on the surface of the polycrystalline silicon layer 230 and the surfaces of the active layer silicon wafer 255. On the other hand, in the second embodiment, vacuum room temperature bonding is performed between the surfaces of the polycrystalline silicon layer 330 and the second insulating layer 340 formed on the surface of the active layer silicon wafer 355. Other configurations and steps are the same as those in the first embodiment. That is, the method for manufacturing the multilayer SOI wafer 300 according to the present embodiment includes a first insulating layer forming step of forming the first insulating layer 320 on the surface of the silicon wafer 310, and a second insulating layer forming step on the surface of the silicon wafer 355 for active layer. a second insulating layer forming step of forming an insulating layer 340, a polycrystalline silicon layer forming step of forming a polycrystalline silicon layer 330 on the surface of the first insulating layer 320, and a surface of the polycrystalline silicon layer 330; An activation treatment step in which the surface of the second insulating layer 340 is subjected to activation treatment under vacuum at room temperature to make both surfaces activated surfaces 330A and 340A; A bonding step in which both activated surfaces 330A and 340A are bonded together by bringing the activated surfaces 330A and 340A into contact with each other, and after the bonding step, a thin film is formed by thinning the active layer silicon wafer 355 to obtain the active layer 350. and a conversion step. As mentioned above, components that are the same as those in the first embodiment are generally designated by the same reference numbers with the last two digits, and redundant explanation will be omitted.

In this embodiment, the second insulating layer 340 is formed on the surface of the silicon wafer 355 for active layer. The formation method can be performed in the same manner as the first insulating layer 320, and the first insulating layer 320 and the second insulating layer 340 may be formed simultaneously, or separately from the first insulating layer forming step. A second insulating layer 340 may also be formed.

In this embodiment, when performing the vacuum room temperature bonding method, activated surfaces 330A and 340A are formed on both surfaces of the polycrystalline silicon layer 330 and the second insulating layer 340 formed on the surface of the active layer silicon wafer 355. Form. If each wafer is placed in the vacuum room temperature bonding apparatus 70 so that the polycrystalline silicon layer 330 and the second insulating layer 340 are placed facing each other, by using the vacuum room temperature bonding method in the same manner as in the first embodiment, Both activated surfaces 330A, 340A can be joined together.

The multilayer SOI wafer 300 obtained in this way includes a silicon wafer 310, a first insulating layer 320 provided on the surface of the silicon wafer 310, a polycrystalline silicon layer 330 provided on the surface of the first insulating layer 320, and a polycrystalline It has a second insulating layer 340 provided on the surface of the silicon layer 330 and an active layer 350 provided on the surface of the second insulating layer 340.

The multilayer SOI wafer according to the present invention can be manufactured using either the first embodiment or the second embodiment of the manufacturing method described above. However, rather than the first embodiment in which the active layer silicon wafer and the second insulating layer formed on the polycrystalline silicon layer are bonded by vacuum room temperature bonding, the second insulating layer is formed on the active layer silicon wafer. The second embodiment in which the polycrystalline silicon layer is then bonded to the polycrystalline silicon layer by a vacuum room temperature bonding method is more advantageous in that the film quality of the second insulating layer becomes denser.

(X-ray detection sensor)
An X-ray detection sensor can be formed using the multilayer SOI wafer 100 described so far. In this X-ray detection sensor, a silicon wafer 110 is provided with an X-ray detection section, and an active layer 150 is provided with a MOS type transistor section. Further, grounding can be achieved by providing a ground electrode section that is electrically connected to the polycrystalline silicon layer 130 and supplied with a ground potential. Therefore, during device formation, etc., charge-up to each insulating layer can be prevented.

A specific example of an X-ray detection sensor formed using the multilayer SOI wafer 100 will be described with reference to FIG. 5. The X-ray detection sensor 400 shown in FIG. layer 420, a conductive layer 430 derived from the polycrystalline silicon layer 130, a second BOX layer 440 derived from the second insulating layer, and a p-type diffusion region 454 and p-type diffusion region 455 derived from the active layer 150. and a mold silicon layer 450 in this order. Furthermore, the X-ray detection sensor 400 is provided with an element isolation groove 470 made of silicon oxide that penetrates from the element surface to the surface of the first BOX layer, and an element isolation groove 470 made of silicon oxide that penetrates so as to reach the surface of the conductive layer 430. A ground electrode section 480 consisting of the like is provided. Further, the back surface of the p-type silicon layer 410, the high concentration n-type diffusion region 414, the n-type diffusion region 454, and the p-type diffusion region 455 are connected with a conductor 460 made of Cu, Al, or the like. The p-type silicon layer 410 corresponds to an X-ray detection section, and the p-type silicon layer 450 corresponds to a MOS transistor section. Note that this X-ray detection sensor 400 uses the back surface of the p-type silicon layer 410 (the side on which the conductor 460 is provided) as the X-ray incident surface. As a method for providing the through groove, known photolithography processing and etching processing can be applied. Note that in order to increase the X-ray detection efficiency, as shown in FIG. 5, an opening 490 may be provided in the conductor 460 so that the back surface of the p-type silicon layer 410 is exposed below the high concentration n-type diffusion region 414. preferable.

Hereinafter, the present invention will be explained in more detail using Examples, but the present invention is not limited to the following Examples.

[Experiment example 1]
(Invention example 1)
A p-type silicon wafer (thickness: 750 μm, dopant type: boron, resistivity: 100 Ω·cm, oxygen concentration: 2×10 ¹⁶ atoms/cm ³ ) obtained from FZ single crystal was prepared as a supporting substrate. Further, as a substrate for the active layer, a COP-free p-type silicon wafer (thickness: 750 μm, dopant: boron, resistivity: 1 Ω·cm) obtained from CZ single crystal was prepared.

Next, a silicon oxide film with a thickness of 500 nm was formed on each surface of the support substrate and the active layer substrate by a thermal oxidation method in an oxygen atmosphere. The silicon oxide film of the active layer substrate is conveniently referred to as a BOX layer. For the supporting substrate, a polycrystalline silicon layer with a thickness of 1.0 μm was further formed on the silicon oxide film by CVD at 400° C. using hydrogen as a carrier gas and trichlorosilane as a source gas.

Subsequently, according to the method shown in FIG. 3, the polycrystalline silicon layer and the BOX layer of the active layer substrate were bonded together as a bonding surface by a vacuum room temperature bonding method. Specifically, first, Ar is flowed into a vacuum chamber at 25° C. and less than 5.0×10 ⁻⁵ Pa to generate plasma, and an accelerating voltage is applied to each irradiated surface of the supporting substrate layer and the active layer substrate. Each surface was activated by irradiating Ar ions at 1.0 keV, frequency: 140 Hz, and pulse width: 55 μsec. Thereafter, the polycrystalline silicon layer and the BOX layer were bonded together by bringing both activated surfaces into contact under vacuum at room temperature. Thereafter, the active layer substrate was ground and polished to obtain an active layer with a thickness of 5.0 μm, and a multilayer SOI wafer according to Invention Example 1 was obtained.

(Conventional example 1)
A support substrate and an active layer substrate similar to those in Invention Example 1 were prepared. Next, a silicon oxide film with a thickness of 500 nm was formed on the surface of the support substrate. Subsequently, this silicon oxide film and the active layer substrate were bonded together in the same manner as the vacuum room-temperature bonding method of Inventive Example 1, to produce an SOI wafer according to Conventional Example 1. Note that, unlike Invention Example 1, in Conventional Example 1, a polycrystalline silicon layer was not formed on the silicon oxide film. For convenience of explanation, the silicon oxide film of the SOI wafer according to Conventional Example 1 will also be referred to as a BOX layer below.

(Comparative example 1)
First, two support substrates and two active layer substrates similar to those in Invention Example 1 were prepared. Next, a silicon oxide film with a thickness of 500 nm was formed on each surface of each wafer by a thermal oxidation method in an oxygen atmosphere, and a support substrate and an active layer substrate were bonded together in an air atmosphere with the silicon oxide film interposed therebetween. Then, a bonding strengthening heat treatment was performed. Then, the active layer substrate was ground and polished to produce two SOI wafers each having an active layer with a thickness of 500 nm. Thereafter, the active layers of both SOI wafers were bonded to each other by a vacuum room temperature bonding method, and the thickness of the silicon single crystal layer between the BOX layers was set to 1 μm. Furthermore, one of the support substrates was ground and polished to form an active layer with a thickness of 5 μm, thereby producing a multilayer SOI wafer according to Comparative Example 1.

(Evaluation 1: TZDB evaluation)
GOI (Gate Oxide Integrity) characteristics are evaluated for each BOX layer of Invention Example 1, Conventional Example 1, and Comparative Example 1 (silicon oxide film formed on the active layer side for Invention Example 1 and Comparative Example 1). Therefore, a cylindrical electrode schematically shown in the plan view of FIG. 6 was formed on each BOX layer. The specific procedure for creating a cylindrical electrode is as follows.

(i) After sputtering Al to form an Al film with a thickness of 300 nm on the surface of the active layer, a photolithography process and a plasma etching process were sequentially performed. Furthermore, the Al film and the active layer were etched to form a through groove of 1 cm diameter for forming a cylindrical electrode.
(ii) After forming a 1 cmφ through groove, a TEOS (tetraethoxysilane) film is formed to a thickness of 500 nm, and a 5 mmφ contact via is formed in the center of the through groove by sequentially performing photolithography and plasma etching. did. Furthermore, in Inventive Example 1 and Comparative Example 1, a 3 mmφ contact via penetrating to the silicon layer immediately below the BOX layer was simultaneously formed 5 mm outside of the 1 cmφ cylindrical electrode.
(iii) Next, after filling the contact vias by sputtering Al, a photolithography process and a plasma etching process are sequentially performed to form a cylindrical electrode with a diameter of 5 mm that conducts to the active layer, and a cylindrical electrode that conducts to the silicon layer. An electrode was formed.

Assuming damage that would occur during plasma etching in the device process, the above contact etching process was repeated three times, and then a TZDB (Time Zero Dielectric Breakdown) evaluation was conducted with the judgment current set to 1 x 10 ^-4 A/ ^cm2 . . In TZDB evaluation, with the back surface of the support substrate set at 0 (zero) V, voltage is applied to the electrode in steps of 0.1 V from 0 V, and the measured current value is divided by the BOX layer thickness (MV /cm) was calculated. In Invention Example 1, it was 9.1 MV/cm, whereas in Conventional Example 1, it was 6.3 MV/cm, and in Comparative Example 1, it was 7.1 MV/cm. Therefore, in Invention Example 1, it was confirmed that the influence of damage caused by plasma etching could be reduced and the charge-up of the BOX layer could be suppressed.

[Experiment example 2]
(Invention example 2-1)
A multilayer SOI wafer according to Invention Example 2-1 was produced in the same manner as Invention Example 1-1 in Experimental Example 1.

(Invention example 2-2)
Invention example 2-1 used an FZ wafer, but this was replaced with a p-type silicon wafer obtained from MCZ single crystal (thickness: 750 μm, dopant type: boron, resistivity: 100 Ω cm, oxygen concentration: 3.0 A multilayer SOI wafer according to Invention Example 2-2 was manufactured under the same conditions as Invention Example 2-1 except that the concentration was changed to 10 ¹⁷ atoms/cm ³ ).

(Invention example 2-3)
Invention Example 2-2 except that the oxygen concentration of the p-type silicon wafer in Invention Example 2-2 was 3.0×10 ¹⁷ atoms/cm ³ and this was changed to 5.0×10 ¹⁷ atoms/cm ³ . A multilayer SOI wafer according to Invention Example 2-3 was manufactured under the same conditions as Example 2.

(Comparative example 2)
Invention Example 2-2 except that the oxygen concentration of the p-type silicon wafer in Invention Example 2-2 was 3.0×10 ¹⁷ atoms/cm ³ and was changed to 7.0×10 ¹⁷ atoms/cm ³ . A multilayer SOI wafer according to Comparative Example 2 was manufactured under the same conditions as Comparative Example 2.

(Evaluation 2: Resistance fluctuation evaluation)
Each of the multilayer SOI wafers according to Invention Examples 2-1, 2-2, 2-3 and Comparative Example 2 was further heat-treated at 450° C. for 10 hours in a nitrogen atmosphere assuming a device fabrication process. . The resistivity of the back side of the silicon wafer before and after the heat treatment was evaluated by the 4-point needle method. The results are listed in Table 1.

Evaluation 2 confirmed that the multilayer SOI wafers according to Invention Examples 2-1, 2-2, and 2-3 all had sufficiently small resistance fluctuations due to heat treatment. However, in Comparative Example 2 with a high oxygen concentration, it was confirmed that the resistance fluctuated with heat treatment.

From the above Experimental Examples 1 and 2, in the multilayer SOI wafer that satisfies the conditions of the present invention, the polycrystalline silicon layer can prevent the charge-up of the BOX layer, and even when the supporting substrate is used as a sensor part, the It was confirmed that the resistance did not change even after heat treatment. Therefore, the multilayer SOI wafer according to the present invention is suitable for use in an X-ray detection sensor.

According to the present invention, it is possible to provide a multilayer SOI wafer suitable for use in an X-ray detection sensor and a method for manufacturing the same. Furthermore, according to the present invention, it is possible to provide an X-ray detection sensor using this multilayer SOI wafer.

100 Multilayer SOI wafer 110 Silicon wafer 120 First insulating layer 130 Polycrystalline silicon layer 140 Second insulating layer 150 Active layer

Claims (5)

silicon wafer and
a first insulating layer provided on the surface of the silicon wafer;
a polycrystalline silicon layer provided on the surface of the first insulating layer;
a second insulating layer provided on the surface of the polycrystalline silicon layer;
an active layer made of single crystal silicon provided on the surface of the second insulating layer,
The thickness of the first insulating layer is 100 nm or more,
the second insulating layer is silicon oxide;
The thickness of the second insulating layer is 500 nm or more,
The conductivity type of the silicon wafer is p type, the resistivity is 100 Ω·cm or more, the thickness is 100 μm or more, and the oxygen concentration is 5.0×10 ¹⁷ atoms/cm ³ or less. Multilayer SOI wafer. The multilayer SOI wafer according to claim 1, wherein the polycrystalline silicon layer has a resistivity of 0.0001 Ωcm or more and 0.001 Ωcm or less. A method for manufacturing a multilayer SOI wafer according to claim 1 or 2 , comprising:
a first insulating layer forming step of forming a first insulating layer on the surface of the silicon wafer;
a polycrystalline silicon layer forming step of forming a polycrystalline silicon layer on the surface of the first insulating layer;
a second insulating layer forming step of forming a second insulating layer on the surface of the polycrystalline silicon layer;
an activation treatment step in which the surface of the second insulating layer and the surface of the active layer silicon wafer are subjected to activation treatment in a vacuum at room temperature to make both surfaces activated surfaces;
Following the activation treatment step, a joining step of joining both activated surfaces by bringing them into contact under the vacuum at room temperature;
After the bonding step, a thinning step of thinning the active layer silicon wafer to obtain an active layer;
A method for manufacturing a multilayer SOI wafer, comprising: A method for manufacturing a multilayer SOI wafer according to claim 1 or 2 , comprising:
a first insulating layer forming step of forming a first insulating layer on the surface of the silicon wafer;
a second insulating layer forming step of forming a second insulating layer on the surface of the active layer silicon wafer;
a polycrystalline silicon layer forming step of forming a polycrystalline silicon layer on the surface of the first insulating layer;
an activation treatment step in which the surface of the polycrystalline silicon layer and the surface of the second insulating layer are subjected to activation treatment in a vacuum at room temperature to make both surfaces activated surfaces;
Following the activation treatment step, a joining step of joining both activated surfaces by bringing them into contact under the vacuum at room temperature;
After the bonding step, a thinning step of thinning the active layer silicon wafer to obtain an active layer;
A method for manufacturing a multilayer SOI wafer, comprising: An X-ray detection sensor formed using the multilayer SOI wafer according to claim 1 or 2 ,
An X-ray detection section is provided on the silicon wafer,
A ground electrode portion is provided that is electrically connected to the polycrystalline silicon layer and is supplied with a ground potential,
An X-ray detection sensor characterized in that the active layer is provided with a MOS type transistor section.

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