JP2014204009A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses a decrease in breakdown voltage while securing electric separation between semiconductor layers, and to provide the method of manufacturing the semiconductor device.SOLUTION: The semiconductor device comprises: a censor portion 70 including a photo diode 30 comprising a second semiconductor layer 15 and a p-type semiconductor region 231, a p-type first semiconductor layer 11 in which a MOS transistor 40 is formed, a third semiconductor layer 13 provided between the second semiconductor layer 15 and the semiconductor layer 11, a buried oxide film 14 provided between the second semiconductor layer 15 and the third semiconductor layer 13, and a buried oxide film 12 provided between the third semiconductor layer 13 and the first semiconductor layer 11; and a guard ring portion 72 which includes a guard ring insulating film region 74 provided in a region between a p-type semiconductor region 232 and an n-type extraction region 233 which are formed on a principal surface of the semiconductor layer 15, the guard ring portion 72 being arranged so as to surround the censor portion 70.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, a semiconductor in which a photodiode for detecting X-rays and a circuit element such as a transistor and a resistor are mixed on the same SOI (Silicon On Insulator) substrate. The present invention relates to an apparatus and a manufacturing method thereof.

  Patent Document 1 discloses a semiconductor device having a structure in which a sensor and a peripheral circuit are formed on the same semiconductor substrate via an insulating film. In the semiconductor device disclosed in Patent Document 1, a high-concentration P-type diffusion layer as an anode electrode and a low-concentration P-type well diffusion layer provided so as to cover the high-concentration P-type diffusion layer are surrounded. A semiconductor region is formed. Since the semiconductor region functions as a field plate, the increase in the potential of the P-type well diffusion layer is suppressed, and as a result, the reverse breakdown voltage of the semiconductor device is increased.

JP2012-080045A

  In the semiconductor device as an X-ray sensor disclosed in Patent Document 1, an SOI substrate is used, and a photodiode for X-ray detection is formed on a semiconductor (silicon) substrate of the SOI substrate as an active element (circuit element). The transistor is formed in a semiconductor layer provided over a semiconductor substrate with an insulating film interposed therebetween. Then, in order to increase the detection sensitivity at the time of X-ray incidence, a low concentration and high resistance semiconductor substrate is used as the semiconductor substrate on which the photodiode is formed, and a bias voltage of several hundred volts is applied to the back surface of the semiconductor substrate, The entire semiconductor substrate is depleted. Therefore, the semiconductor device having such a structure is required to have a high breakdown voltage.

  However, the semiconductor device disclosed in Patent Document 1 has a problem that the bias voltage applied to the semiconductor substrate affects the semiconductor layer in which the transistor is formed, and an unintended current may be generated in the transistor. .

  As one method for avoiding this problem, a method using a Double-SOI (Double-Silicon On Insulator) substrate as a substrate on which an X-ray sensor is formed can be considered. Hereinafter, a semiconductor device using this Double-SOI substrate will be described as a comparative example.

FIG. 17 shows a semiconductor device 500 according to the comparative example.
In the semiconductor device 500, as shown in FIG. 17, the first semiconductor layer 11 above the buried oxide film 12 is a high-concentration low-resistance substrate for forming a circuit element such as a MOS transistor 40 for circuit operation, and the buried oxide film An X-ray sensor unit including peripheral circuits is formed on a single wafer 10 by using the second semiconductor layer 15 below 14 as a low concentration high resistance substrate for forming the photodiode 30. A P-type semiconductor region 231 in FIG. 17 is an anode region of the photodiode 30.

  The P-type semiconductor region 232 and the N-type extraction region 233 are formed to surround the X-ray sensor portion including the photodiode 30 and the MOS transistor 40, and the guard ring portion of the X-ray sensor portion is formed. It is composed. In general, the X-ray sensor unit includes a plurality of photodiodes 30 arranged in an array.

  The basic function of the guard ring part is to reverse the photodiode 30 of the semiconductor device 500 so that the depletion layer spreads uniformly within the semiconductor substrate (second semiconductor layer 15) when a high bias voltage is applied. It is to secure a directional breakdown voltage (breakdown voltage).

  Specifically, the P-type semiconductor region 232 of the guard ring portion has a function of further expanding a depletion layer extending from the P-type semiconductor region 231 outward. As a result, the photodiodes 30 arranged in an array are arranged relatively outside (located near the inside of the P-type semiconductor region 232 of the guard ring portion) and relatively inside. It is also possible to suppress variation in performance with the photodiode 30 to be used.

  On the other hand, the N-type extraction region 233 of the guard ring portion fixes the potential of the semiconductor substrate (second semiconductor layer 15) and suppresses the spread of the depletion layer extending from the P-type semiconductor region 232 in the planar direction. By extending in the depth direction, the semiconductor device 500 has a function of suppressing the depletion layer extending from the P-type semiconductor region 231 from reaching the chip end surface (side surface).

Here, as described above, since the semiconductor device 500 uses the Double-SOI substrate, the third semiconductor layer 13 is formed between the buried oxide film 12 and the buried oxide film 14 in FIG. .
In the semiconductor device 500 according to this comparative example, the third semiconductor layer 13 acts so as to electrically separate the first semiconductor layer 11 and the second semiconductor layer 15, so that the second power is supplied from the power supply 28. The influence of the bias voltage applied to the semiconductor layer 15 on the first semiconductor layer 11 is suppressed.

That is, in the absence of the third semiconductor layer 13, a bias voltage applied to the back surface of the second semiconductor layer 15 by the power supply 28 to deplete the second semiconductor layer 15 causes the buried oxide film 12 to be depleted. In some cases, it is also transmitted to the first semiconductor layer 11 formed on the buried oxide film 12. Then, an unintended current may be generated in the channel region of the MOS transistor 40 formed in the first semiconductor layer 11, and the semiconductor device 500 may malfunction.
In contrast, the generation of such a current is suppressed by providing the third semiconductor layer 13 and electrically separating the first semiconductor layer 11 and the second semiconductor layer 15.

  However, in the semiconductor device 500 according to the comparative example, the third semiconductor layer 13b in the floating state is also present between the P-type semiconductor region 232 and the N-type extraction region 233 constituting the guard ring portion in the manufacturing process. To do. The third semiconductor layer 13b acts to lower the breakdown voltage of the photodiode 30 and lowers the reverse breakdown voltage of the semiconductor device 500.

  That is, as shown in FIG. 17, when P-type semiconductor regions 231 and 232 are grounded and a bias voltage of several hundred volts is applied to the N-type extraction region 233 and the back surface of the substrate, a first potential having a certain potential due to capacitive coupling is obtained. The third semiconductor layer 13b suppresses the spread of the potential potential spreading from the X-ray sensor portion to the outermost region of the guard ring portion (region near the N-type extraction region 233). That is, the third semiconductor layer 13b suppresses the spread of the depletion layer. This phenomenon causes a problem that the reverse breakdown voltage of the semiconductor device 500 is significantly reduced.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device in which a decrease in breakdown voltage is suppressed and a manufacturing method thereof while ensuring electrical isolation between semiconductor layers. And

  In order to achieve the above object, a semiconductor device according to claim 1 includes a photodiode formed in a first semiconductor layer and a circuit element provided on one main surface of the first semiconductor layer. A second semiconductor layer, a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer and the third semiconductor layer. A radiation detecting unit including a first insulating layer provided therebetween, and a second insulating layer provided between the third semiconductor layer and the second semiconductor layer, and the radiation detecting unit And the first region formed on the one main surface of the first semiconductor layer, the first region surrounding the first region, and the first semiconductor layer The second region formed on one main surface and the region on the one main surface of the first semiconductor layer And a guard ring portion comprising a third insulating layer formed to a depth of a region corresponding to the third semiconductor layer sandwiched between the first region and the second region.

  In order to achieve the above object, a semiconductor device according to claim 2 includes a photodiode formed in a first semiconductor layer, and a circuit element provided on one main surface of the first semiconductor layer. A radiation detection unit including the formed second semiconductor layer, and a first insulating layer provided between the first semiconductor layer and the second semiconductor layer, and surrounds the radiation detection unit And a first region formed on the one main surface of the first semiconductor layer and surrounding the first region, and the one main region of the first semiconductor layer. Corresponding to the second semiconductor layer sandwiched between the first region and the second region by the second region formed on the surface and the region on the one main surface of the first semiconductor layer And a second insulating layer formed by chemical vapor deposition in a depth region It has a ring section.

  On the other hand, in the method for manufacturing a semiconductor device according to claim 10, the first semiconductor layer, the first insulating layer on the first semiconductor layer, and the third semiconductor layer on the first insulating layer are provided. And a step of preparing a second insulating layer on the third semiconductor layer and a silicon substrate provided with the second semiconductor layer on the second insulating layer, and a first step formed on the silicon substrate. A second region formed by introducing impurities on the first semiconductor layer surrounding the first region, and an impurity introduced on the first semiconductor layer surrounding the second region. Removing at least the second semiconductor layer, the second insulating layer, and the third semiconductor layer in a region surrounded by the third region, and a first conductive layer in the second region. A step of introducing an impurity of a type, and a second conductivity type opposite to the first conductivity type in the third region. Introducing a pure material; forming a third insulating layer at a depth corresponding to the third semiconductor layer in a region surrounded by the second region and the third region; It has.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device with which the fall of the proof pressure was suppressed, ensuring the electrical isolation of semiconductor layers, and its manufacturing method are provided.

It is a top view which shows an example of schematic structure of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view which shows an example of schematic structure of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view with which it uses for description of an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view which shows an example of schematic structure of the semiconductor device which concerns on 2nd Embodiment. It is a top view which shows an example of the formation pattern of the 3rd semiconductor layer of the semiconductor device which concerns on 2nd Embodiment. It is a longitudinal cross-sectional view which shows an example of schematic structure of the semiconductor device which concerns on 3rd Embodiment. It is a longitudinal cross-sectional view which shows the structure of the semiconductor device which concerns on a comparative example.

[First embodiment]
Hereinafter, the semiconductor device 100 according to the present embodiment will be described in detail with reference to the drawings.
Note that the semiconductor device 100 according to the present embodiment can be configured as a sensor having sensitivity to X-rays, β-rays, visible light, and the like. Hereinafter, the semiconductor device 100 that functions as an X-ray sensor will be exemplified. I will explain.

As shown in FIG. 1, the semiconductor device 100 includes a sensor unit 70 and a guard ring unit 72 formed so as to surround the sensor unit 70. In the figure, a P-type semiconductor region 232 and an N-type extraction region 233, which will be described later, constituting the guard ring portion are also shown.
Below, the structure of the sensor part 70 is demonstrated first.

2 is a longitudinal sectional view of a portion indicated by AA in FIG.
As shown in FIG. 2, the semiconductor device 100 according to the present embodiment includes a first semiconductor layer 11 in which a MOS transistor 40 is formed as a part of a peripheral circuit, and functions as a sensor pixel. 15 and a P-type semiconductor region 231, a third semiconductor layer 13 provided between the first semiconductor layer 11 and the second semiconductor layer 15, and the first semiconductor layer 11. Embedded oxide film 12 provided between the second semiconductor layer 15 and the third semiconductor layer 13, and a buried oxide film 14 provided between the second semiconductor layer 15 and the third semiconductor layer 13.

  The first semiconductor layer 11 and the third semiconductor layer 13 are formed of a P-type semiconductor substrate, and the second semiconductor layer 15 is formed of an N-type semiconductor substrate. A P-type semiconductor region 231 is provided in the region 51 of the main surface 151 of the second semiconductor layer 15. The P-type semiconductor region 231 and the N-type second semiconductor layer 15 form an X-ray photodiode 30 that functions as a sensor pixel. An electrode 280 is provided on the main surface 152 opposite to the main surface 151 of the second semiconductor layer 15. The active region 111 of the first semiconductor layer 11 in which the MOS transistor 40 is formed is provided on a region 61 different from the region 51 of the main surface 151 of the second semiconductor layer 15. The third semiconductor layer 13 provided between the active region 111 of the first semiconductor layer 11 and the second semiconductor layer 15 is provided with a high-concentration P-type extraction region 24.

The sensor unit 70 includes the photodiode 30 and the MOS transistor 40 described above.
As shown in FIG. 2, the third semiconductor layer 13 is formed in the sensor unit 70, and the third semiconductor layer 13 electrically connects the first semiconductor layer 11 and the second semiconductor layer 15. Plays the function of separating.

  Next, the structure of the guard ring part 72 is demonstrated. The guard ring part 72 suppresses the depletion layer from reaching the end face (side face) of the chip after applying a bias voltage to the second semiconductor layer 15 or performing pelleting (chip separation) by scribing or the like. It has a function to do.

  As shown in FIG. 2, the guard ring portion 72 includes a high concentration P-type semiconductor region 232, a guard ring portion insulating film region 74, and a high concentration N-type extraction region 233. Unlike the sensor unit 70 described above, the guard ring insulating film region 74 sandwiched between the P-type semiconductor region 232 and the N-type extraction region 233 is guarded to a depth corresponding to the third semiconductor layer 13. The ring insulating film 76 is formed, and the third semiconductor layer 13 is not formed.

Next, application of a bias voltage in the semiconductor device 100 according to the present embodiment will be described.
In the semiconductor device 100, in order to deplete the N-type second semiconductor layer 15 constituting the photodiode 30 for X-rays, the back surface (main surface 152) of the second semiconductor layer 15 and the high-concentration N-type are used. A positive high voltage is applied from the power supply 28 to the take-out region 233 (cathode electrode). The third semiconductor layer 13, the P-type semiconductor region 231 that serves as the anode electrode of the photodiode 30, and the P-type semiconductor region 232 that is part of the guard ring portion 72 are connected to the negative electrode side of the power supply 28. And connected to a ground (ground) 90 (grounded).

  More specifically, the N-type second semiconductor layer 15 includes an electrode 280 provided on the main surface 152 of the second semiconductor layer 15 and a high concentration provided on the main surface 151 of the second semiconductor layer 15. Is connected to the positive side of the power supply 28 through a potential fixing electrode 276 connected to the N-type extraction region 233. Further, P-type semiconductor regions 231 and 232 provided on the main surface 151 of the second semiconductor layer 15 are connected to the negative electrode side of the power supply 28 and the GND 90 via the extraction electrode 274 and the potential fixing electrode 275, respectively. . The P-type third semiconductor layer 13 is connected to the GND 90 through a potential fixing electrode 271 connected to the high-concentration P-type extraction region 24.

  By fixing the third semiconductor layer 13 formed of a P-type substrate to the ground potential, a power supply 28 is provided on the back surface (main surface 152) of the second semiconductor layer 15 in order to deplete the second semiconductor layer 15. Even when a high voltage is applied from above, the high voltage is not transmitted to the interface of the active region 111 of the first semiconductor layer 11 on the buried oxide film 12 side.

  Thus, the third transistor fixed at the ground potential is between the MOS transistor 40 formed in the active region 111 of the first semiconductor layer 11 and the photodiode 30 as the sensor pixel formed in the second semiconductor layer 15. Because of the semiconductor layer 13, the parasitic capacitance to the sensor pixel is very small. In addition, crosstalk that affects the MOS transistor 40 of the first semiconductor layer 11 when a signal is input to the sensor pixel is almost negligible.

  On the other hand, as described above, since the third semiconductor layer 13 that functions as a field plate does not exist in the guard ring portion 72, the spread of the potential distribution forming the depletion layer is not suppressed, and a constant breakdown voltage is obtained. It can be secured.

Next, a method for manufacturing the semiconductor device 100 according to the present embodiment will be described.
In addition, the numerical value which shows the dimension of each part, an electrical property, etc. below is an example, and this invention is not limited to these values.

  First, as shown in FIG. 3, the first semiconductor layer 11 on the upper side, the second semiconductor layer 15 having a thickness of about 700 μm on the lower side, and the third semiconductor layer 13 on the center as shown in FIG. A double-SOI substrate having each of the above is manufactured. At this time, for example, the first semiconductor layer 11 and the third semiconductor layer 13 are formed of a P-type semiconductor substrate having a specific resistance of about 10 Ω · cm, and the second semiconductor layer 15 is formed of an N-type semiconductor substrate having a specific resistance of about 10 kΩ · cm. To do.

  After a pad oxide film (not shown) and a nitride film (not shown) are formed on the surface of the first semiconductor layer 11, and a field oxide film is formed by a LOCOS (Local Oxidation of Silicon) formation method, FIG. As shown in FIG. 2, all nitride films and pad oxide films are removed. As a result, an active region 111 is formed in the first semiconductor layer 11.

  Further, as shown in FIG. 5, a gate oxide film 16 is formed on the surface of the active region 111 of the first semiconductor layer 11, a polysilicon film is deposited, and polysilicon is patterned with a photoresist (not shown). The film is dry-etched to form the gate electrode 18.

  Next, as shown in FIG. 6, after removing the photoresist (not shown), LDD (Lightly Doped Drain, not shown) ions are implanted into the active region 111 of the first semiconductor layer 11 to form the side After the wall spacer 20 is formed, a high concentration source / drain 19 ion implantation process is performed to form the MOS transistor 40.

Next, as shown in FIG. 7, regions other than the P-type semiconductor regions 231 and 232 and the N-type extraction region 233 to be formed in the second semiconductor layer 15 are covered with a photoresist (not shown). Then, the buried oxide films 12 and 14 and the third semiconductor layer 13 are etched to form the openings 211 and 212, respectively, and then the photoresist is removed. At this time, for the regions where the P-type semiconductor region 232 and the N-type extraction region 233 constituting the guard ring portion 72 are to be formed, the photoresist is not applied including the region between them.
That is, the opening 212 is formed so as to remove the third semiconductor layer 13 and the like existing between the P-type semiconductor region 232 and the N-type extraction region 233.

  Next, as shown in FIG. 8, the region other than the P-type extraction region 24 to be formed in the third semiconductor layer 13 is covered with a photoresist (not shown), and the buried oxide film 12 is etched. After the opening 22 is formed, the photoresist is removed.

  Next, as shown in FIG. 9, a photoresist 300 is applied to the entire surface so as to fill the openings 211, 212, and 22. The application of the photoresist 300 is part of a process for injecting impurities into portions corresponding to the N-type extraction region 233, the P-type semiconductor regions 231 and 232, and the P-type extraction region 24.

Next, as shown in FIG. 10, patterning is performed using a mask (not shown) to form an opening 213 in a portion corresponding to the N-type extraction region 233 of the photoresist 300, and for example, an impurity 31P is formed through the opening 213. After implanting ⁺ , the photoresist 300 is removed.

Similarly, openings of the photoresist 300 are formed in portions corresponding to the P-type semiconductor region 231 that also serves as the anode of the photodiode 30 and the P-type semiconductor region 232 of the guard ring portion 72 by using lithography technology, For example, after the impurity 11B ⁺ is implanted through the opening, the photoresist 300 is removed.
Further, an opening of the photoresist 300 is formed in a portion corresponding to the P-type extraction region 24 of the third semiconductor layer 13 by using a lithography technique, and, for example, an impurity 49BF ₂ ⁺ is implanted through the opening (not shown). )
Thereafter, the remaining photoresist 300 is removed.

  In the above description, the example in which the impurity implantation is performed in the order of the N-type extraction region 233, the P-type semiconductor regions 231 and 232, and the P-type extraction region 24 has been described. However, the order of injection of the disobedients may be changed as appropriate.

Next, as shown in FIG. 11, the openings 211, 212, and 22 are embedded by depositing a CVD (Chemical Vapor Deposition) film. Here, a guard ring insulating film 76 is formed in a region corresponding to the third semiconductor layer 13 in the opening 212. A CVD film in which the openings 211, 212 and 22 are embedded may be used as the interlayer film 25.
After that, by etching a place where an electrode for connecting to each of the active region 111, the second semiconductor layer 15, and the third semiconductor layer 13 of the first semiconductor layer 11 is formed, as shown in FIG. , Contact holes 261, 262, 263, 264, 265,
And 266 are formed. Finally, portions other than the electrode formation region of the metal layer formed by sputtering are etched to form potential fixing electrodes 271, 275, 276, transistor electrodes 272, 273, and an extraction electrode 274, as shown in FIG. To do. An electrode 280 is also formed on the back surface of the second semiconductor layer 15.

  As described above in detail, according to the semiconductor device 100 according to the present embodiment, it is possible to provide a semiconductor device in which a decrease in breakdown voltage is suppressed while ensuring electrical isolation between semiconductor layers and a method for manufacturing the same. Is possible.

[Second Embodiment]
A semiconductor device 200 according to the present embodiment will be described with reference to FIGS.
The semiconductor device 100 according to the first embodiment has a form in which all of the third semiconductor layer 13 is removed in the guard ring portion 72, whereas this embodiment has a structure in which the third semiconductor layer 13 is removed. It is a form that leaves a part. Therefore, the same components as those in FIG.

  In FIG. 14, in the guard ring part insulating film region 74 in the guard ring part 72, the third semiconductor layer 13 is partially separated to form a third semiconductor layer 13a. Thus, by separating the third semiconductor layer 13 into a plurality of parts, the separated third semiconductor layers 13 can be kept at different potentials. As a result, since the third semiconductor layer 13 is kept at a specific potential, the above-described effect that the spread of the depletion layer in the second semiconductor layer 15 is suppressed is less likely to occur. Even when the third semiconductor layer 13 is partially left as described above, the effects of the present invention can be obtained.

FIGS. 15A and 15B show different formation patterns of the third semiconductor layer 13a, and the third semiconductor layer 13a shown in FIG. 14 is viewed from a direction perpendicular to the main surface 151 (152). It is represented by a plan view. 15A shows the case where the third semiconductor layer 13a is formed in a slit (band) shape, and FIG. 15B shows the case where the third semiconductor layer 13a is formed in an island shape. The case where it forms is shown.
Note that the formation pattern of the third semiconductor layer 13a is not limited to the band shape or the island shape shown in FIG. 15, and it is sufficient that there is a portion where the third semiconductor layer is partially formed and a portion where the third semiconductor layer is not formed.
Various patterns can be applied.

  The semiconductor device 200 can be manufactured according to the manufacturing method of the semiconductor device 100 shown in FIGS. In particular, the third semiconductor layer 13a according to the present embodiment is used as a mask for patterning when the buried oxide films 12 and 14 and the third semiconductor layer 13 are etched by patterning a photoresist in FIG. It can be formed including the band-like or island-like part.

  As described above, also by the semiconductor device 200 according to the present embodiment, it is possible to provide a semiconductor device in which a decrease in breakdown voltage is suppressed and a method for manufacturing the same while ensuring electrical isolation between semiconductor layers. Become.

[Third Embodiment]
A semiconductor device 400 according to the present embodiment will be described with reference to FIG.
Although the first embodiment and the second embodiment employ a double-SOI substrate, the present embodiment employs a single-SOI, that is, a normal SOI substrate. Therefore, the same components as those in FIG. 2 may be denoted by the same reference numerals and the description thereof may be omitted.

As shown in FIG. 16, the semiconductor device 400 also includes a circuit unit such as a MOS transistor 40, a sensor unit 70 including a photodiode 30, a P-type semiconductor region 232, an N-type extraction region 233, and a guard ring. A guard ring portion 72 configured to include a partial insulating film region 74 is provided.
However, the semiconductor device 400 does not include the third semiconductor layer 13 illustrated in FIG.
A first semiconductor layer 11 is disposed on the buried oxide film 14, and a MOS transistor 40 is formed in the first semiconductor layer 11.

  In the semiconductor device 400 having the above-described configuration, the first semiconductor layer is formed in a region other than the regions corresponding to the P-type semiconductor regions 231 and 232 and the N-type extraction region 233 unless special consideration is given in the manufacturing process. 11 is arranged. That is, in FIG. 16, the first portion disposed between the P-type semiconductor region 232 and the N-type extraction region 233 is also disposed in a portion other than between the P-type semiconductor region 232 and the N-type extraction region 233. The first semiconductor layer 11 is disposed at the same position as the semiconductor layer 11.

  However, in the present embodiment, in the manufacturing process, the first semiconductor layer 11 disposed in the guard ring part insulating film region 74 between the P-type semiconductor region 232 and the N-type extraction region 233 is removed, A guard ring insulating film 76 is formed at a depth corresponding to the removed first semiconductor layer 11.

  This is because the first semiconductor layer 11 is arranged in a plate shape between the P-type semiconductor region 232 and the N-type extraction region 233, so that the first embodiment and the second embodiment are the same. This is because the plate-like first semiconductor layer 11 causes a reduction in the breakdown voltage of the semiconductor device 400 for the same reason as described.

The semiconductor device 400 can be manufactured according to the manufacturing method of the semiconductor device 100 shown in FIGS. 3 to 13 using Single-SOI (see, for example, Patent Document 1).
In particular, the removal of the first semiconductor layer 11 between the P-type semiconductor region 232 and the N-type extraction region 233 is performed, for example, after forming the MOS transistor 40 in the first semiconductor layer 11 and then removing the P-type semiconductor. This can be done when forming openings for ion implantation in the regions 231 and 232 and the N-type extraction region 233.

  As described above, also by the semiconductor device 400 according to the present embodiment, it is possible to provide a semiconductor device in which a decrease in breakdown voltage is suppressed and a manufacturing method thereof while ensuring electrical isolation between the semiconductor layers. Become.

  Here, in the above description, the semiconductor device 400 has been described by exemplifying the form in which the first semiconductor layer 11 between the P-type semiconductor region 232 and the N-type extraction region 233 is completely removed. However, the first semiconductor layer 11 in the region may be partially formed in a band shape or an island shape as in the second embodiment.

  In each of the above embodiments, the case where the second semiconductor layer 15 is an N-type substrate has been described. However, the second semiconductor layer 15 can also be applied to a P-type semiconductor device.

DESCRIPTION OF SYMBOLS 10 Wafer 11 1st semiconductor layer 12, 14 Embedded oxide film 13, 13a, 13b 3rd semiconductor layer 15 2nd semiconductor layer 16 Gate oxide film 18 Gate electrode 19 Source / drain 20 Side wall spacer 22 Opening 24 P type Extraction region 25 Interlayer film 28 Power supply 30 Photodiode 40 MOS transistor 51 Region 61 Region 70 Sensor portion 72 Guard ring portion 74 Guard ring portion insulating film region 76 Guard ring portion insulating film 90 GND
100, 200, 400, 500 Semiconductor device 111 Active region 151, 152 Main surface 211, 212, 213, Opening 231, 232 P-type semiconductor region 233 N-type extraction region 261, 262, 263, 264, 265, 266 Contact Holes 271, 275, 276 Potential fixed electrode 272, 273 Transistor electrode 274 Extraction electrode 300 Photoresist

Claims (11)

A photodiode formed in the first semiconductor layer, a second semiconductor layer provided on one main surface of the first semiconductor layer and having a circuit element formed thereon, the first semiconductor layer, and the second semiconductor layer A third semiconductor layer provided between the first semiconductor layer, a first insulating layer provided between the first semiconductor layer and the third semiconductor layer, and a third semiconductor layer. And a second insulating layer provided between the second semiconductor layer and a radiation detector,
And a first region formed on the one main surface of the first semiconductor layer, a first region formed around the first region, and the first region. A second region formed on the one main surface of the semiconductor layer, and a region on the one main surface of the first semiconductor layer sandwiched between the first region and the second region A semiconductor device comprising: a guard ring portion including: a third insulating layer formed in a region having a depth corresponding to the third semiconductor layer. A photodiode formed in the first semiconductor layer, a second semiconductor layer provided on one main surface of the first semiconductor layer and having a circuit element formed thereon, the first semiconductor layer, and the second semiconductor layer A radiation detector including a first insulating layer provided between the semiconductor layer and
And a first region formed on the one main surface of the first semiconductor layer, a first region formed around the first region, and the first region. A second region formed on the one main surface of the semiconductor layer, and a region on the one main surface of the first semiconductor layer sandwiched between the first region and the second region A semiconductor device comprising a guard ring portion including a second insulating layer formed by chemical vapor deposition in a region having a depth corresponding to the second semiconductor layer. The semiconductor device according to claim 1, further comprising an application unit configured to apply a negative potential to the first region and a positive potential to the second region. The semiconductor device according to claim 1, wherein the third insulating layer is a film formed by a chemical vapor deposition method. The third semiconductor layer is formed in a plurality of strips when viewed from a direction perpendicular to the one main surface inside the third insulating layer. 2. The semiconductor device according to claim 1. The third semiconductor layer is formed in a plurality of island shapes when viewed from a direction perpendicular to the one main surface inside the third insulating layer. The semiconductor device according to any one of the above. The first semiconductor layer has a first conductivity type, the second semiconductor layer has a second conductivity type opposite to the first conductivity type, and the first region has a first conductivity type. The semiconductor device according to claim 1, wherein the second region is a first conductivity type. The semiconductor device according to claim 2, wherein the second semiconductor layer is formed in a plurality of strip shapes when viewed from a direction perpendicular to the one main surface inside the second insulating layer. The semiconductor device according to claim 2, wherein the second semiconductor layer is formed in a plurality of island shapes when viewed from a direction perpendicular to the one main surface inside the second insulating layer. A first semiconductor layer; a first insulating layer on the first semiconductor layer; a third semiconductor layer on the first insulating layer; and a second insulating layer on the third semiconductor layer. And preparing a silicon substrate comprising a second semiconductor layer on the second insulating layer;
A second region formed by introducing an impurity into the first semiconductor layer surrounding the first region formed on the silicon substrate; and the first semiconductor layer surrounding the second region. At least the second semiconductor layer in a region surrounded by a third region formed by introducing an impurity thereon;
Removing the second insulating layer and the third semiconductor layer;
Introducing an impurity of a first conductivity type into the second region;
Introducing a second conductivity type impurity of a conductivity type opposite to the first conductivity type into the third region;
Forming a third insulating layer at a depth corresponding to the third semiconductor layer in a region surrounded by the second region and the third region;
A method for manufacturing a semiconductor device comprising: The method of manufacturing a semiconductor device according to claim 10, wherein the first region functions as a radiation detection unit.

Images