JP7369811B2 - time gain control circuit - Google Patents

Description

The present invention relates to a time gain control circuit, and, for example, to a time gain control circuit applied to an ultrasonic diagnostic apparatus.

An ultrasonic diagnostic apparatus receives reflected waves of sound waves emitted from an object to be observed, and generates an image of the object from the received reflected waves. At this time, the longer the distance between the object to be observed and the probe of the ultrasonic diagnostic apparatus, the slower the reflected waves reach the probe. Furthermore, the greater the distance between the object to be observed and the probe of the ultrasonic diagnostic apparatus, the greater the amount of attenuation of the reflected wave when it reaches the probe. For this reason, the ultrasonic diagnostic apparatus receives reflected waves using a time gain control circuit whose attenuation decreases over time. An example of this time gain control circuit is disclosed in Patent Document 1.

The probe described in Patent Document 1 is a probe that transmits ultrasonic waves to a diagnostic site and receives a received signal as a reflected wave, and includes a plurality of transducers and a transducer corresponding to each of the plurality of transducers. A plurality of low-noise amplifier circuits and a control signal that increases over time is converted into a first bias signal that increases over time and a second bias signal that decreases over time to control the multiple low-noise amplifier circuits. The low-noise amplifier circuit includes an attenuator that attenuates the electrical signal from the vibrator, and a first bias signal that gradually increases the output signal of the attenuator over time. a first amplification circuit that amplifies the output of the first amplification circuit, a second amplification circuit that amplifies the output of the first and second amplification circuits so that the output becomes smaller as time passes by a second bias signal, and a subtracter that subtracts the outputs of the first and second amplification circuits. Be prepared.

In the probe described in Patent Document 1, a variable attenuator is connected in series with a resistor and a transistor serving as a variable current source to realize a variable function of decreasing the degree of attenuation over time. That is, in the probe described in Patent Document 1, the voltage of the signal is divided by the output impedance of the vibrator, the on-resistance of the transmission/reception switch, and the combined resistance of the resistor and the transistor serving as the variable current source, and the attenuation of the attenuator is (Paragraph 0035 of Patent Document 1).

JP2020-39542A

In recent years, ultrasonic diagnostic devices have become more portable, and there is a need for lower power consumption and lower operating power supply voltage for internal circuits. However, the probe described in Patent Document 1 has a problem in that it cannot achieve sufficiently low power consumption and low voltage.

A time gain control circuit according to an embodiment includes a vibrator whose one end is connected to a ground terminal and which converts a sound wave signal into a reception signal that is an electric signal and outputs it from the other end, and a plurality of resistors connected in series. a resistor string having one end connected to the other end of the vibrator and the other end connected to the ground terminal, and an end of each resistor included in the plurality of resistors on the other end side of the vibrator. a low-noise amplifier circuit whose input is connected to the other end of the plurality of switches; and a switch control circuit that controls the open/close states of the plurality of switches; The switch control circuit switches the switch to be turned on from the lower side to the upper side, when the switch on the ground terminal side among the plurality of switches is set as the lower side, and the switch on the other end side of the vibrator is set as the upper side. , when turning on the switch, only one switch is turned on after a period in which the switch next to the switch to be turned on is turned on at the same time, and when turning off the switch, the switch to be turned off is The switch is turned on from on to off after a period in which it is turned on at the same time as the switch on the next higher level.

The time gain control circuit according to one embodiment can reduce the power consumption and voltage of the probe.

FIG. 2 is a circuit diagram of a time gain control circuit according to the first embodiment. FIG. 3 is a circuit diagram of a switch in the time gain control circuit according to the first embodiment. 1 is a block diagram of a switch control circuit according to Embodiment 1. FIG. FIG. 2 is a circuit diagram of a switch control signal generation circuit according to the first embodiment. 3 is a timing chart illustrating the operation of the switch control circuit according to the first embodiment. FIG. 3 is a diagram illustrating a switch control sequence of the time gain control circuit according to the first embodiment.

For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Further, in each drawing, the same elements are denoted by the same reference numerals, and redundant explanation will be omitted as necessary.

Embodiment 1
The time gain control circuit 1 according to the first embodiment is, for example, a circuit mounted on a probe of an ultrasonic diagnostic apparatus, converts received sound waves into electrical signals, and transmits the received signals to a downstream circuit. At this time, the time gain control circuit 1 repeats a reception cycle in which the received signal is amplified at regular intervals, and is configured so that the gain increases as time passes from the start of the reception cycle.

Therefore, FIG. 1 shows a circuit diagram of a time gain control circuit 1 according to the first embodiment. As shown in FIG. 1, the time gain control circuit 1 according to the first embodiment includes an attenuation stage 2 and an output stage 3. Attenuation stage 2 reduces the amount of attenuation applied to the received signal over time. The output stage 3 amplifies the received signal that has passed through the attenuation stage 2 with a fixed gain. When the attenuation stage 2 and the output stage 3 are combined, the time gain control circuit 1 operates so that the gain increases as time passes from the start of the reception cycle.

Further, in the example shown in FIG. 1, the time gain control circuit 1 is applied to a probe of an ultrasonic diagnostic apparatus, and has a vibrator OSC as an input terminal. The vibrator OSC converts a sound wave signal into an electrical signal. The electrical signal converted by the vibrator OSC becomes the received signal input to the damping stage 2. The vibrator OSC has one end connected to a ground terminal, converts a sound wave signal into a received signal that is an electric signal, and outputs the received signal from the other end.

The attenuation stage 2 includes a resistor string, a plurality of switches (for example, switches SW0 to SW6), and a switch control circuit 11. The resistor string has a plurality of resistors (eg, resistors R0 to R6) connected in series, one end of which is connected to the other end of the vibrator, and the other end connected to a ground terminal. Moreover, one end of each of the plurality of switches is connected to the other end side of the vibrator of the resistor included in the plurality of resistors.

More specifically, in the resistor string, the resistor R6 is placed closest to the ground terminal, the resistor R0 is placed on the other end side of the vibrator OSC, and the resistors R5 to R1 are arranged in the order from the resistor R6 to the resistor R0. Each resistor is placed. In the switches SW0 to SW6, one end of the switch SW6 is connected to the end of the resistor R6 on the oscillator OSC side (for example, a node connecting the resistor R6 and the resistor R5), and one end of the switch SW0 is connected to the oscillator OSC side end of the resistor R6. It is connected to the end on the child OSC side (for example, the node to which the other end of the vibrator OSC is connected). One ends of the switches SW5 to SW1 are connected to the ends of the resistors R5 to R1 on the vibrator OSC side. Furthermore, in the following description, among the switches SW6 to SW0, the switch on the ground terminal side is called the lower side, and the switch on the other end side of the vibrator is called the upper side.

The switch control circuit 11 controls the open/close states of a plurality of switches (for example, switches SW6 to SW0). More specifically, the switch control circuit 11 switches the switches to be turned on from the lower to the upper every reception cycle. At this time, when turning on the switch, the switch control circuit 11 sets a state in which only one switch is turned on after a period in which the lower switch of the switch to be turned on is turned on at the same time, and when turning off the switch, the switch control circuit 11 In this case, the switch is turned on from on to off after a period in which it is turned on at the same time as the switch one level above the switch to be turned off.

Further, the switch control circuit 11 generates switch control signals SWC6 to SWC0 corresponding to the switches SW6 to SW0. Then, the switch control circuit 11 switches the switch control signals SW6 to SW0 whose slopes of rising edges and falling edges are determined by a time constant determined by inputting and outputting a constant current generated by a constant current to and from a capacitor. Generate every time. Details of this switch control circuit 11 will be described later.

The output stage 3 includes an LNA (low noise amplifier circuit) 12 and a bandpass filter 13. The LNA 12 has its input connected to the other ends of the plurality of switches, current-amplifies the input signal, and outputs the amplified signal to the band-pass filter 13 . Bandpass filter 13 outputs a signal having a frequency in a predetermined band to output terminal To. The band of the bandpass filter 13 is, for example, about 1 MHz to 6 MHz. This frequency band is determined as a compromise between the object to be observed, the attenuation rate of the sound waves in the object, and the required distance resolution.

Next, the configuration of switches SW6 to SW0 will be explained. FIG. 2 shows a circuit diagram of the switches of the time gain control circuit 1 according to the first embodiment. Since the switches SW6 to SW0 have the same configuration, one of the switches SW6 to SW0 is shown in FIG. As shown in FIG. 2, the switches SW6 to SW0 each include an NMOS transistor MN and a PMOS transistor MP. In other words, the switches SW6 to SW0 are each configured as a transfer switch. By using a transfer switch as a switch, the received signal can be correctly transmitted to the LNA 12 regardless of the amplitude of the received signal.

In each of the switches SW6 to SW0, the drain of the NMOS transistor MN and the drain of the PMOS transistor MP are connected, forming one end of the switch, and this one end is connected to the resistors R6 to R0. Further, in the switches SW6 to SW0, the source of the NMOS transistor MN and the source of the PMOS transistor MP are connected, and serve as the other end of the switch, and one end of the switch is connected to the LNA12. Further, a switch control signal SWCk (in the example shown in FIG. 2, k is 0 to 6) is applied as a differential signal to the switches SW6 to SW0. In FIG. 2, one of the differential signals is SWCkp, and the other is SWCkn.

Next, the configuration of the switch control circuit 11 will be explained. FIG. 3 shows a block diagram of the switch control circuit 11 according to the first embodiment. As shown in FIG. 3, the switch control circuit 11 includes a counter 21, a decoder 22, a latch 23, and a switch control signal generation circuit 24. Further, clock signals CLK1 and CLK2 and a reset signal RESET are input to the switch control circuit 11 from other circuits (not shown).

The counter 21 counts the number of clock signals CLK1 and increments the count value. Further, the counter 21 resets the count value to the initial value based on the reset signal RESET. The decoder 22 generates a control number according to the count value. The latch 23 captures and holds the control number output by the decoder 22 in response to the clock signal CLK2. The switch control signal generation circuit 24 generates a number of switch control signals (SW6 to SW0) corresponding to the number of switches (for example, switches SW6 to SW0). Here, the switch control signal generation circuit 24 controls the rise and fall of the switch control signal associated with the control number.

Here, the switch control signal generation circuit 24 will be explained in detail. Therefore, FIG. 4 shows a circuit diagram of the switch control signal generation circuit 24 according to the first embodiment. As shown in FIG. 4, the switch control signal generation circuit 24 includes a timing control circuit 31, a common current source, and an individual output stage circuit. The switch control signal generation circuit 24 has an individual output stage circuit for each switch control signal (for example, for each differential signal). In FIG. 4, only the individual output stage circuit that generates the switch control signal SWC6p is shown. Further, it is assumed that one timing control circuit 31 and one common current source are provided for a plurality of individual output stage circuits.

Specifically, the switch control signal generation circuit 24 controls one of the differential signals serving as a timing control signal to either a high level or a low level using a common current source and one individual output stage circuit. At this time, the individual output stage circuit determines the slope of the rising edge and falling edge of the signal using a time constant determined by inputting and outputting a constant current generated by a constant current source to and from a capacitor. At this time, a time constant circuit that combines a common current source and one individual output stage circuit adjusts the slope of the rising or falling edge of the signal with the driving force determined by the transistor size of one transistor. Make it smaller than when switching levels. In the switch control signal generation circuit 24, the common current source and the plurality of individual output stage circuits are combined to form a plurality of time constant circuits, and the individual output stage circuits to be operated according to the control number are switched. , individually controlling the signal levels of the plurality of switch control signals. Specifically, in the switch control signal generation circuit 24 , the timing control circuit 31 switches the time constant circuit to be operated according to the control number transmitted from the latch 23 .

As shown in FIG. 4, the common current source includes constant current sources Is1 and Is2, an NMOS transistor N1, and a PMOS transistor P1. One end of the constant current source Is1 is connected to the power supply wiring AVDD. The NMOS transistor N1 has a source connected to a ground wiring AVSS, and a gate and a drain connected. Further, the other end of the constant current source Is1 is connected to the drain of the NMOS transistor N1. One end of the constant current source Is2 is connected to the ground wiring AVSS. The PMOS transistor P1 has a source connected to a power supply wiring AVDD, and a gate and a drain connected to each other. Further, the other end of the constant current source Is2 is connected to the drain of the PMOS transistor P1.

Further, the individual output stage circuit includes switches SW61 to SW64, a PMOS transistor P62, an NMOS transistor N62, and a capacitor C6. The PMOS transistor P62 has a source connected to the power supply wiring AVDD, and a gate connected to the gate of the PMOS transistor P1 via the switch SW61. Further, the switch SW62 is connected between the gate of the PMOS transistor P62 and the power supply wiring AVDD. In other words, the PMOS transistor P62 and the PMOS transistor P1 are connected to the constant current generated by the constant current source Is2 and the transistor size ratio of the PMOS transistor P1 and the PMOS transistor P62 when the switch SW61 is on and the switch SW62 is off. , constitutes a current mirror that discharges a constant current determined by , from the drain of the PMOS transistor P62.

The NMOS transistor N62 has a source connected to the ground wiring AVSS, and a gate connected to the gate of the NMOS transistor N1 via the switch SW63. Further, the switch SW64 is connected between the gate of the NMOS transistor N62 and the ground wiring AVSS. In other words, when the switch SW63 is on and the switch SW64 is off, the NMOS transistor N62 and the NMOS transistor N1 are connected to the constant current generated by the constant current source Is1 and the transistor size ratio of the NMOS transistor N1 and NMOS transistor N62. , constitutes a current mirror that sucks a constant current determined by , from the drain of the NMOS transistor N62.

The node to which the drain of the PMOS transistor P62 and the drain of the NMOS transistor N62 are connected becomes the output terminal of the individual output stage circuit, and the capacitor C6 is connected between the output terminal and the ground wiring AVSS.

Here, the opening and closing states of the switches SW61 to SW64 are controlled by the timing control circuit 31. When raising the switch control signal, the timing control circuit 31 turns on the switches SW61 and SW64 and turns off the switches SW62 and SW63. When the timing control circuit 31 lowers the switch control signal, it turns on the switches SW62 and SW63 and turns off the switches SW61 and SW64. Furthermore, when maintaining the signal level of the switch control signal, the timing control circuit 31 turns on the switches SW62 and SW64 and turns off the switches SW61 and SW63.

Next, the operation of the switch control circuit 11 according to the first embodiment will be explained. FIG. 5 shows a timing chart explaining the operation of the switch control circuit 11 according to the first embodiment. As shown in FIG. 5, the switch control circuit 11 resets the count value and the latch output to initial values (for example, 0) in response to the fall of the reset signal RESET at timing T1. Further, since the switch control signal generation circuit 24 is given 0 as the control number from the latch 23, the switch control signal generation circuit 24 switches the switch control signal SWC6 to the on state. As a result, the switch SW6 is turned on.

Subsequently, when the rising edge of the clock signal CLK1 is input to the counter 21 at timing T2, the counter 21 counts up the count value from 0 to 1. Thereafter, when the rising edge of the clock signal CLK2 is input to the latch 23 at timing T3, the latch 23 takes in the output value (for example, 1) of the decoder 22 at that time. As a result, the control number is switched from 0 to 1. Thereby, the switch control signal generation circuit 24 switches the switch control signal SWC5 from the off state to the on state while maintaining the switch control signal SWC6 in the on state. As a result, both the switch SW6 and the switch SW5 are turned on.

Subsequently, when the rising edge of the clock signal CLK1 is input to the counter 21 at timing T4, the counter 21 counts up the count value from 1 to 2. Thereafter, when the rising edge of the clock signal CLK2 is input to the latch 23 at timing T5, the latch 23 takes in the output value (for example, 2) of the decoder 22 at that time. As a result, the control number is switched from 1 to 2. Thereby, the switch control signal generation circuit 24 switches the switch control signal SWC6 from the on state to the off state, and maintains the switch control signal SWC5 in the on state. As a result, the switch SW6 is turned off, and the switch SW5 is turned on.

Next, the operation of the time gain control circuit 1 according to the first embodiment will be explained. Therefore, FIG. 6 shows a diagram illustrating the switch control sequence of the time gain control circuit 1 according to the first embodiment. Note that the switch control sequence shown in FIG. 6 is shown for one reception cycle, and the time gain control circuit 1 repeats the switch control sequence shown in FIG. 6 for each reception cycle. Further, the switch control sequence shown in FIG. 6 is mainly executed by the switch control circuit 11. In particular, in FIG. 6, the amount of attenuation when the received signal is attenuated in the attenuation stage 2 by switching the switch state according to the switch control sequence is also shown in association with the switch control sequence.

As shown in FIG. 6, the time gain control circuit 1 according to the first embodiment resets the count value to the initial value (for example, 0) by setting the reset signal REST to a low level at one end at the start of a reception cycle. , turn on switch SW6. As a result, in the attenuation stage 2, the received signal transmitted to the LNA 12 is resistively divided by the combined resistance of the resistor R6 and the resistors R5 to R0, and an attenuation amount of about 15 dB is applied.

In the time gain control circuit 1 according to the first embodiment, the count value is increased one by one, and the switch to be turned on is shifted to the upper side. At this time, when turning on any of the switches SW6 to SW0, the time gain control circuit 1 and the switch control circuit 11 turn on one switch after a period in which the lower switch is simultaneously turned on. When turning off any of the switches SW6 to SW0, the switch is turned on from on to off after a period in which it is turned on at the same time as the switch one level higher than the switch to be turned off. As a result, in the example shown in FIG. 6, when the count value is an odd number, two consecutive switches are turned on, and when the count value is an even number, only one switch is turned on. The switch state changes to

In this way, the time gain control circuit 1 uses seven resistors to control the reception by alternating periods in which two switches are on at the same time and periods in which only one switch is in an on state. It becomes possible to apply 13 levels of attenuation to the signal.

From the above description, in the time gain control circuit 1 according to the first embodiment, the amount of attenuation is varied by alternately passing through a period in which two switches are on at the same time and a period in which only one switch is in an on state. This reduces the amount of change in attenuation per step. As a result, the time gain control circuit 1 according to the first embodiment can reduce the magnitude of the switching noise superimposed on the received signal when switching the switch, compared to when switching the switch without providing a period in which the two switches are simultaneously on. can also be made smaller.

Further, in the time gain control circuit 1 according to the first embodiment, a certain time constant is provided for the voltage change at the time of switching the logic level of the switch control signal that switches the open/close states of the switches SW6 to SW0, so that the slope at the time of the voltage change is make it more gradual. Thereby, the amount of noise superimposed on the received signal can be suppressed to less than half that in the case of switch open/close state switching control without time constant control.

In the time gain control circuit 1 that applies both the time constant control of the switch control signal and the insertion control sequence of the simultaneous on period of the switches, the switch switching noise superimposed on the received signal is reduced when these controls are not performed. The inventors have verified that this can be suppressed to about 1/10 of the above.

In this way, the time gain control circuit 1 according to the first embodiment can obtain a high noise suppression effect, but the switch control circuit 11 that performs switch control at this time is constructed of logic circuits except for the switch control signal generation circuit 24. The power consumption is extremely low. Further, the switch control signal generation circuit 24 uses a common current source that always consumes current, but in order to increase the time constant, it is necessary to reduce the current flowing by the constant current source provided in the common current source. The current consumption of the common current source is extremely small. Further, the resistor string of the attenuation stage 2 also includes many resistors connected in series, and current consumption is suppressed by increasing the combined resistance of these resistors. For this reason, the time gain control circuit 1 according to the first embodiment can perform reception processing that generates a low-noise reception signal while suppressing power consumption.

Although the invention made by the present inventor has been specifically explained based on the embodiments above, the present invention is not limited to the embodiments already described, and various changes can be made without departing from the gist thereof. It goes without saying that it is possible.

1 Time gain control circuit 2 Attenuation stage 3 Output stage 11 Switch control circuit 12 LNA
13 Band pass filter 21 Counter 22 Decoder 23 Latch 24 Switch control signal generation circuit 31 Timing control circuit OSC Oscillator To Output terminal MP PMOS transistor MN NMOS transistor Is1 Constant current source Is2 Constant current source

Claims (3)

a vibrator whose one end is connected to a ground terminal and which converts a sound wave signal into a received signal that is an electrical signal and outputs it from the other end;
a resistor string having a plurality of resistors connected in series, one end connected to the other end of the vibrator, and the other end connected to the ground terminal;
a plurality of switches each having one end connected to an end of a resistor included in the plurality of resistors on the other end side of the vibrator;
a low-noise amplifier circuit whose input is connected to the other end of the plurality of switches;
a switch control circuit that controls the open/close states of the plurality of switches;
The switch control circuit includes:
a counter that counts the number of clock signals and increments the count value;
a decoder that generates a control number according to the count value;
a switch control signal generation circuit that generates a plurality of switch control signals in a number corresponding to the number of the plurality of switches;
The switch control signal generation circuit controls rising and falling of the switch control signal associated with the control number,
The switch control circuit includes:
When the switch on the ground terminal side of the plurality of switches is set as the lower side and the switch on the other end side of the vibrator is set as the upper side, switching the switch to be turned on from the lower side to the upper side,
When the switch is turned on, only one of the switches is turned on after a period in which the switch immediately below the switch to be turned on is simultaneously turned on,
When turning off the switch, the time gain control circuit turns the switch from on to off after a period of turning on simultaneously with a switch one level above the switch to be turned off. The switch control circuit generates a switch control signal for each switch, the slope of a rising edge and a falling edge being determined by a time constant determined by inputting and outputting a constant current generated by a constant current source to a capacitor. The time gain control circuit according to claim 1. The switch control signal generation circuit includes:
a plurality of time constant circuits provided for each of the switch control signals, the slopes of rising edges and falling edges being determined by a time constant determined by inputting and outputting a constant current generated by a constant current source to a capacitor;
a timing control circuit that switches the time constant circuit to operate according to the control number;
The time gain control circuit according to claim 1 , comprising:

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