JP7351230B2 - Synchronous control circuit and synchronous control method - Google Patents

Description

The present invention relates to a synchronous control circuit and a synchronous control method.

BACKGROUND ART As the amount of data handled in information processing increases, when it is difficult to perform information processing with one information processing device, information processing may be performed by operating a plurality of information processing devices in parallel. In an information processing system having multiple information processing devices of this type, synchronization packets that convert the status of input/output pins into data are sent between FPGAs (Field-Programmable Gate Arrays) installed in each information processing device for a predetermined period of time. Sent and received at intervals. Then, the information processing device that has received the synchronization packet reflects the state of the input/output pin, thereby executing state synchronization control of control signals that require synchronization within the plurality of information processing devices (for example, see Patent Document 1). ).

Japanese Patent Application Publication No. 2014-235702

By the way, as the degree of integration of ASICs (Application Specific Integrated Circuits) increases, design verification using a logic simulator is becoming more difficult in terms of time and accuracy. For this reason, in recent years, it has become mainstream to write the logic circuit of an ASIC under design into an FPGA and operate the FPGA to verify the design. At this time, if it is difficult to mount the logic circuit to be mounted on the ASIC in one FPGA, the logic circuit is divided into a plurality of FPGAs and the logic circuit is mounted therein. In order to correctly perform logic verification of a logic circuit that is divided and mounted on a plurality of FPGAs, it is necessary to operate the plurality of FPGAs as one logic circuit in synchronization with each other.

In one aspect, an object of the present invention is to operate logic circuits that are divided and mounted in a plurality of programmable units in synchronization with each other.

According to one aspect, the synchronization control circuit is provided in a programmable part in which a logic circuit is reconfigurably programmed, and synchronizes signals transmitted and received between the programmable part and other programmable parts. a transmission control unit that outputs the output signal to a transmission interface and sets the transmission flag when an output signal is received from a logic circuit programmed in the programmable unit while the transmission flag is being reset; a reception control section that outputs the reception signal to the programmed logic circuit and sets the reception flag when a reception signal is received from the reception interface while the flag is being reset; and a synchronous clock generation unit that outputs a synchronous clock to the programmed logic circuit and resets the transmission flag and the reception flag when set.

In one aspect, the present invention allows logic circuits that are divided and mounted in a plurality of programmable units to operate in synchronization with each other.

FIG. 1 is a block diagram illustrating an example of a verification system including a verification device according to an embodiment. FIG. 2 is an explanatory diagram showing an example of logic installed in each FPGA of the verification device of FIG. 1. FIG. 2 is a block diagram showing an example of a synchronous control circuit installed in the FPGA 10a of FIG. 1. FIG. FIG. 4 is an explanatory diagram showing an example of a packet converted by the packet conversion unit in FIG. 3; 2 is a block diagram showing an example of a signal flow within each FPGA in FIG. 1. FIG. 6 is a flow diagram showing an example of the operation of the synchronous control circuit in the FPGA 10a of FIG. 5. FIG. 6 is a timing diagram showing an example of the operation of a synchronous control circuit in each FPGA of FIG. 5. FIG. 8 is an explanatory diagram showing an example of the state of each FPGA in cycle A of FIG. 7. FIG. 8 is an explanatory diagram showing an example of the state of each FPGA in cycle B of FIG. 7. FIG. 8 is an explanatory diagram showing an example of the state of each FPGA in cycle C of FIG. 7. FIG. 8 is an explanatory diagram showing an example of the state of each FPGA in cycle D of FIG. 7. FIG. 8 is an explanatory diagram showing an example of the state of each FPGA in cycle E of FIG. 7. FIG. 8 is an explanatory diagram showing an example of the state of each FPGA in cycle F of FIG. 7. FIG. 8 is an explanatory diagram showing an example of the state of each FPGA in cycle G of FIG. 7. FIG. FIG. 2 is a block diagram illustrating an example of a verification system including a verification device in another embodiment. 16 is a block diagram showing an example of a synchronous control circuit 30c installed in the FPGA 10c of FIG. 15. FIG. 16 is a block diagram showing an example of a synchronous control circuit 32c installed in the FPGA 10c of FIG. 15. FIG. FIG. 2 is a block diagram illustrating an example of a verification system including a verification device in another embodiment. 19 is a block diagram showing an example of a synchronous control circuit installed in the FPGA 10d of FIG. 18. FIG.

Embodiments will be described below with reference to the drawings. In the following, the same symbols as the signal names are used for signal lines through which information such as signals is transmitted. Further, a single-bit signal or a multi-bit signal is transmitted to the signal line shown as a single line in the figure. A logic circuit or the like connected to a signal line through which multiple-bit signals are transmitted has a circuit for each signal.

FIG. 1 shows an example of a verification system including a verification device in one embodiment. The verification system 100 shown in FIG. 1 includes a verification device 200 including a plurality of FPGAs 10 (10a, 10b), and a server 300 that controls logic verification operations by the verification device 200. The FPGA 10 is an example of a programmable unit in which logic circuits are reconfigurably programmed.

The verification device 200 has a function of synchronizing and operating the mounted logics 40 (40a, 40b), which are logic circuits to be verified, programmed in the FPGAs 10a and 10b, respectively. For this purpose, the FPGA 10a is programmed with the synchronous control circuit 30a together with the on-board logic 40a, and the synchronous control circuit 30b is programmed with the on-board logic 40b into the FPGA 10b.

For example, the FPGAs 10a and 10b and the FPGA 10a and the server 300 are connected through PCIe (Peripheral Component Interconnect express: registered trademark) interfaces. However, the FPGAs 10a and 10b and the FPGA 10a and the server 300 may be connected via other communication interfaces. Furthermore, the interfaces connecting the FPGAs 10a and 10b and between the FPGA 10a and the server 300 may be serial interfaces or parallel interfaces.

A PCIe interface (I/F) 20a, a synchronous control circuit 30a, an onboard logic 40a, and a PCIe interface 22a are programmed in the program area of the FPGA 10a and connected in this order. A PCIe interface 20b, a synchronous control circuit 30b, and an on-board logic 40b are programmed in the program area of the FPGA 10b and connected in this order. For example, the PCIe interface 20 (20a, 22a, 20b) is programmed using IP (Intellectual Property). The PCIe interface 20 is an example of a sending interface and a receiving interface. Note that FIG. 1 shows a state in which the circuit logic is programmed in the FPGAs 10a and 10b, and the route for transferring the logic information to be programmed in the FPGAs 10a and 10b to the FPGAs 10a and 10b and the resources such as memory that holds the logic information. Description is omitted.

For example, when performing logic verification, the PCIe interface 22a converts serial data received from the server 300 into parallel data and outputs it to the mounted logic 40a. Furthermore, the PCIe interface 22a converts parallel data received from the mounted logic 40a into serial data and transmits the serial data to the server 300. Note that the server 300 also transmits control information and the like other than data to the FPGA 10a, but this will be explained below as data. The on-board logic 40a uses the data received from the PCIe interface 22a to execute an operation of a predetermined function, and outputs the data obtained by the operation to the synchronous control circuit 30a. Furthermore, the on-board logic 40a uses the data received from the synchronization control circuit 30a to execute the operation of a predetermined function, and outputs the data obtained by the operation to the PCIe interface 22a.

The synchronization control circuit 30a outputs the transmission data received from the onboard logic 40a to the PCIe interface 20a in accordance with the timing of the reception data received from the FPGA 10b via the PCIe interface 20a. Furthermore, the synchronization control circuit 30a outputs the received data received from the FPGA 10b to the mounted logic 40a. The synchronous control of the synchronous control circuit 30a will be explained with reference to FIGS. 6 and 7.

The PCIe interface 20a converts parallel data received from the synchronous control circuit 30a into serial data and outputs the serial data to the FPGA 10b. Furthermore, the PCIe interface 20a converts serial data received from the FPGA 10b into parallel data and outputs it to the synchronization control circuit 30a.

In the FPGA 10b, the PCIe interface 20b converts serial data received from the FPGA 10a into parallel data and outputs it to the synchronization control circuit 30b. Furthermore, the PCIe interface 20b converts parallel data received from the synchronous control circuit 30b into serial data and outputs the serial data to the FPGA 10a.

The synchronization control circuit 30b outputs the transmission data received from the onboard logic 40b to the PCIe interface 20b in accordance with the timing of the reception data received from the FPGA 10a via the PCIe interface 20b. Furthermore, the synchronization control circuit 30b outputs the received data received from the FPGA 10a to the mounted logic 40b. The onboard logic 40b uses the data received from the synchronous control circuit 30b to perform an operation of a predetermined function, and outputs the data obtained by the operation to the synchronous control circuit 30b.

In the FPGA 10a, the PCIe interface 20a converts serial data received from the FPGA 10b into parallel data and outputs it to the synchronization control circuit 30a. The synchronization control circuit 30a outputs the data received from the PCIe interface 20a to the onboard logic 40a at a timing synchronized with the data received from the onboard logic 40a.

By the above operation, the data transmitted and received by the mounted logic 40a of the FPGA 10a and the data transmitted and received by the mounted logic 40b of the FPGA 10b can be synchronized with each other. This allows the operations of the mounted logics 40a and 40b to be synchronized with each other. Therefore, for example, even if the scale of the logic is large and the logic is divided and installed in a plurality of FPGAs 10a and 10b, synchronous operation can be realized.

FIG. 2 shows an example of logic installed in each FPGA 10a, 10b of the verification device 200 in FIG. FIG. 2 shows an example in which the scale of logic installed in an ASIC to be subjected to logic verification is large, and it is difficult to program the logic into one FPGA 10a of the verification apparatus 200 of FIG. In the example shown in FIG. 2, among the logics installed in the ASIC, logic a is installed in the FPGA 10a as an installed logic 40a, and logic b is installed in the FPGA 10b as an installed logic 40b.

Logic a and logic b each have a combinational circuit CC and a plurality of flip-flops FF. Note that in FIG. 2, logic a and logic b are connected to each other via two flip-flops FF, but within the ASIC, logic a and logic b are connected via one flip-flop FF. In this case, one flip-flop FF is added when dividing the logic.

In this embodiment, even if the logic of the ASIC is larger than the logic that can be mounted on one FPGA, the logic can be divided and mounted on a plurality of FPGAs 10a and 10b, and the FPGAs 10a and 10b can be synchronized. Regardless of the logical scale of the ASIC, logic verification can be performed by operating the circuit (hardware) programmed in the FPGA, so logic verification can be performed faster than when using a logic verification simulator. can.

FIG. 3 shows an example of a synchronous control circuit 30a installed in the FPGA 10a of FIG. Note that the synchronization control circuit 30b installed in the FPGA 10b has the same configuration as in FIG. 3 except that the signal names are different. The synchronization control circuit 30b will be explained with reference to FIG.

The synchronization control circuit 30a includes a transmission control section 50, a reception control section 60, and a synchronization clock generation section 70. The transmission control section 50 includes a packet conversion section 51, an AND circuit AND1, and an RS (set/reset) flip-flop 52. The reception control section 60 includes a packet conversion section 61, an AND circuit AND2, and an RS flip-flop 62. The synchronous clock generation section 70 includes a two-input AND circuit AND3 and a latch circuit 71.

The packet conversion unit 51 generates a packet using the multi-bit output signal OUTa output from the mounted logic 40a, and outputs the generated packet to the AND circuit AND1. The packet converter 51 generates packets for the number of cycles corresponding to the data size of the output data. An example of a packet is explained in FIG.

The AND circuit AND1 issues the packet POUTa (transmission packet) output from the packet converter 51 to the PCIe interface 20a while the transmission flag TFLGa is being reset (eg, logical value 0). The AND circuit AND1 suppresses the output of the packet POUTa from the packet converter 51 while the transmission flag TFLGa is set (eg, logical value 1). The AND circuit AND1 is an example of a packet output control unit that permits or inhibits output of the packet POUTa generated by the packet conversion unit 51 to the PCIe interface 20a.

The RS flip-flop 52 sets the transmission flag TFLGa to a logical value of 1 based on the AND circuit AND1 outputting the packet POUTa. The RS flip-flop 52 resets the transmission flag TFLGa to a logic value of 0 based on the change of the clock enable signal CENa output from the AND circuit AND3 to a valid level (for example, a logic value of 1). The RS flip-flop 52 is an example of a transmission flag setting section.

The packet converter 61 extracts data (payload) from the packet PINa (received packet) received from the PCIe interface 20a via the AND circuit AND2, and outputs the extracted data to the mounted logic 40a as an input signal INa. The packet conversion unit 61 receives the packet PINa for the number of cycles corresponding to the data size of the input data included in the packet PINa. An example of a packet is explained in FIG.

The AND circuit AND2 outputs the packet PINa output from the PCIe interface 20a to the packet converter 61 while the reception flag RFLGa is being reset (eg, logical value 0). The AND circuit AND2 suppresses output of the packet PINa output from the PCIe interface 20a to the packet converter 61 while the reception flag RFLGa is set (eg, logical value 1). The AND circuit AND2 is an example of a packet input control unit that permits or inhibits output of the packet PINa received from the PCIe interface 20a to the packet conversion unit 61.

The RS flip-flop 62 sets the reception flag RFLGa to a logical value of 1 based on the AND circuit AND2 outputting the packet PINa. The RS flip-flop 62 resets the reception flag RFLGa to a logical value of 0 based on the change to the valid level of the clock enable signal CENa output from the AND circuit AND3. The RS flip-flop 62 is an example of a reception flag setting section. Note that the lock marks written on the RS flip-flops 52 and 62 indicate that resetting by the reset terminal R has priority over setting by the set terminal S.

The AND circuit AND3 of the synchronous clock generation unit 70 sets the clock enable signal CENa to a valid level (logical value 1) when both the transmission flag TFLGa and the reception flag RFLGa have a logical value of 1. The AND circuit AND3 sets the clock enable signal CENa to an invalid level (logical value 0) when either the transmission flag TFLGa or the reception flag RFLGa has a logical value of 0. For example, the logical value 1 of the reception flag RFLGa is also supplied to the PCIe interface 20a, and is used to suppress output of the subsequent packet PINa to the synchronization control circuit 30a. The AND circuit AND3 is an example of an enable generation circuit that generates the clock enable signal CENa.

The latch circuit 71 latches the logical value of the clock enable signal CENa in synchronization with the reference clock RCLKa, and generates the synchronized clock SCLKa. For example, the reference clock RCLK is used as an operating clock for the PCIe interfaces 20a and 22a, and the synchronous clock SCLKa is used as an operating clock for the onboard logic 40a. The latch circuit 71 is an example of a clock output section that outputs the synchronous clock SCLKa.

FIG. 4 shows an example of a packet converted by the packet converters 51 and 61 in FIG. 3. For example, the onboard logic 40a shown in FIG. 3 outputs a 384-bit output signal OUTa[383:0] and receives a 384-bit input signal INa[383:0]. In this case, the packet converter 51 generates a 512-bit packet POUTa by adding a 128-bit PCIe header before the output signal OUTa. Then, the packet conversion unit 51 outputs the generated packet POUTa to the PCIe interface 20a in two clock cycles (CYC1, CYC2).

The packet conversion unit 61 converts the 384-bit input signal INa[383:0] by discarding the 128-bit PCIe header from the 512-bit packet PINa received from the PCIe interface 20a in two clock cycles (CYC1, CYC2). generate.

Note that when the output signal OUTa and the input signal INa are 128 bits or less, a 256-bit packet (POUTa, PINa) is generated. Further, when the output signal OUTa and the input signal INa have 385 bits or more, packets (POUTa, PINa) corresponding to the number of clock cycles corresponding to the number of bits are generated.

FIG. 5 shows an example of a signal flow within each FPGA 10a, 10b in FIG. In addition, in FIG. 5, the synchronous clock generation section 70 of the synchronous control circuits 30a and 30b is simplified and only the AND circuit AND3 is shown. The signals shown in FIG. 5 are used for explanation in the timing diagram of FIG. Packet PIN (PINa, PINb) is an example of a received signal.

FIG. 6 shows an example of the operation of the synchronous control circuit 30a in the FPGA 10a of FIG. Note that the operation of the synchronous control circuit 30b in the FPGA 10b is indicated by replacing the suffix "a" of each signal with "b". FIG. 6 shows an example of a synchronization control method for synchronizing signals transmitted and received between a plurality of FPGAs 10.

First, in step S10, when the synchronization control circuit 30a receives a packet PINa from the PCIe interface 20a when the reception flag RFLGa has a logical value of 0, it executes the operation of step S12. The synchronization control circuit 30a executes the operation of step S16 when the reception flag RFLGa has a logical value of 1, or when the reception flag RFLGa has a logical value of 0 and the packet PINa has not been received.

In step S12, the packet converter 61 of the synchronization control circuit 30a discards the PCIe header from the received packet PINa, generates an input signal INa, and outputs it to the mounted logic 40a. Further, the RS flip-flop 62 of the synchronization control circuit 30a sets the reception flag RFLGa to logical value 1 based on the input of the packet PINa. Next, in step S14, the AND circuit AND2 of the synchronization control circuit 30a suppresses the reception of the packet PINa while the reception flag RFLGa has a logical value of 1. After step S14, the synchronous control circuit 30a executes the operation of step S22.

In step S16, the synchronization control circuit 30a executes the operation of step S18 when the transmission flag TFLGa has a logical value of 0, and executes the operation of step S22 when the transmission flag TFLGa has a logical value of 1.

In step S18, the packet converter 51 of the synchronization control circuit 30a converts the output signal OUTa output from the mounted logic 40a into a packet POUTa. The AND circuit AND1 of the synchronization control circuit 30 outputs the packet POUTa to the PCIe interface 20a over two clock cycles. Note that the packet conversion unit 51 may convert the output signal OUTa output from the on-board logic 40a into the packet POUTa before the operation of step S18.

Further, the RS flip-flop 52 of the synchronization control circuit 30a sets the transmission flag TFLGa to a logical value of 1 based on the output of the packet POUTa. Next, in step S20, the AND circuit AND1 of the synchronization control circuit 30a suppresses the output of the packet POUTa while the transmission flag TFLGa has a logical value of 1. After step S20, the synchronous control circuit 30a executes the operation of step S22.

In step S22, the synchronization control circuit 30a executes the operation in step S24 when both the transmission flag TFLGa and the reception flag RFLGa have a logical value of 1. If either the transmission flag TFLGa or the reception flag RFLGa has a logical value of 0, the synchronization control circuit 30a returns to the operation of step S10. In step S24, the synchronous clock generation unit 70 of the synchronous control circuit 30a generates one clock of the synchronous clock SCLKa. The RS flip-flop 52 resets the transmission flag TFLG to a logical value of 0 based on the synchronization clock SCLKa. The RS flip-flop 62 resets the reception flag RFLGa to a logical value of 0 based on the synchronization clock SCLKa. The operation then returns to step S10.

The synchronous clock SCLKa is supplied to the on-board logic 40a, and the on-board logic 40a operates in synchronization with the synchronous clock SCLKa. Note that in the FPGA 10b, the synchronous clock SCLKb is generated at the same frequency as the synchronous clock SCLKa. Therefore, in a predetermined period, the number of pulses of the synchronous clock SCLKa supplied to the mounted logic 40a and the number of pulses of the synchronous clock SCLKb supplied to the mounted logic 40b are the same. As a result, the synchronous control circuits 30a, 30b shown in FIG. 5 can operate the logics 40a, 40b mounted on the FPGAs 10a, 10b in synchronization with each other.

FIG. 7 shows an example of the operation of the synchronous control circuits 30a and 30b in each of the FPGAs 10a and 10b shown in FIG. FIG. 7 shows an example of a synchronization control method for synchronizing signals transmitted and received between a plurality of FPGAs 10. The symbol XX shown in FIG. 7 indicates that the logical value of the signal is undefined. For example, it is assumed that the payloads of packets POUTa and POUTb and input signals INa and INb are 384 bits.

In the initial state of FIG. 7, packets POUTa and POUTb have a logical value of 0 indicating an invalid state in which no packets are generated (FIGS. 7(a) and (b)). The reception flag RFLGa changes to a logical value of 1 during the second clock cycle in FIG. 7 when the synchronization clock SCLKa is generated (FIG. 7(c)). The transmission flag TFLGa changes from a logic value of 1 to a logic value of 0 in the next clock cycle (cycle A) after the clock cycle in which the synchronization clock SCLKa is generated (FIG. 7(d)).

Similarly, the reception flag RFLGb changes to a logical value of 1 during the second clock cycle of FIG. 7 when the synchronization clock SCLKb is generated (FIG. 7(e)). The transmission flag TFLGb changes from a logic value of 1 to a logic value of 0 in the next clock cycle (cycle A) after the clock cycle in which the synchronization clock SCLKb is generated (FIG. 7(f)). Therefore, the synchronization control circuits 30a and 30b are in a state where they can transmit and receive packets in cycle A.

The mounted logic 40a of the FPGA 10a outputs the output signal OUTa (=A1) to the synchronous control circuit 30a in cycle A (FIG. 7(g)). The synchronization control circuit 30a generates a packet POUTa (A1-1, A1-2) based on the output signal OUTa (=A1), and outputs the generated packet POUTa to the PCIe interface 20a in two clock cycles of the reference clock RCLKa. . Data A1-1 is output in cycle A, and data A1-2 is output in cycle B. Based on the completion of the output of packet POUTa (A1-1, A1-2), the transmission flag TFLGa changes from logical value 0 to logical value 1 (FIG. 7(h)). As a result, while the transmission flag TFLGa has a logical value of 1, output of subsequent output signals to the PCIe interface 20a is suppressed.

On the other hand, the mounted logic 40b of the FPGA 10b outputs the output signal OUTb (=B1) in cycle A (FIG. 7(i)). The synchronization control circuit 30b generates a packet POUTb (B1-1, B1-2) based on the output signal OUTb, and outputs the generated packet POUTb in two clock cycles of the reference clock RCLKb. Data B1-1 is output in cycle A, and data B1-2 is output in cycle B. Based on the completion of the output of packet POUTb (B1-1, B1-2), the transmission flag TFLGb changes from a logical value of 0 to a logical value of 1 (FIG. 7(j)). As a result, while the transmission flag TFLGb has a logical value of 1, output of subsequent output signals to the PCIe interface 20b is suppressed.

Thereafter, in cycle C and the next cycle after cycle C, the synchronization control circuit 30a of the FPGA 10a sequentially receives packets PINa (B1-1, B1-2) from the FPGA 10b via the PCIe interface 20a (see FIG. 7). k)). The packet converter 61 generates an input signal INa (B1) based on the data B1-1 and B1-2, and outputs the generated input signal INa (B1) to the mounted logic 40a in cycle D (see FIG. 7). l)).

The synchronization control circuit 30a sets the reception flag RFLGa to logical value 1 based on the completion of reception of the input signal INa (B1) (FIG. 7(m)). Thereby, the synchronous clock generation section 70 of the synchronous control circuit 30a generates the synchronous clock SCLKa (FIG. 7(n)). Further, by generating the synchronization clock SCLKa, the transmission flag TFLGa and the reception flag RFLGa are reset to logical value 0 (FIGS. 7(o) and (p)). As a result, output of the subsequent packet POUTa to the PCIe interface 20a is permitted, and reception of the subsequent packet PINa from the PCIe interface 20a is permitted.

In this way, the synchronization control circuit 30a sets the transmission flag TFLGa based on the completion of the transmission of the signal A1, and sets the reception flag RFLGa based on the completion of the reception of the signal B1. As a result, even if the signal A1 is transmitted over multiple cycles and the signal B1 is received over multiple cycles, the onboard logics 40a and 40b can be operated in synchronization with each other, as shown in FIG. can.

Furthermore, the synchronization control circuit 30a generates a packet POUTa including the output signal OUTa by the packet conversion unit 51, outputs it to the PCIe interface 20a, and extracts the input signal INa from the packet PINa received from the PCIe interface 20a. Thereby, signals can be transmitted and received between the FPGAs 10a and 10b using a standard interface such as PCIe. Even when using a standard interface, the operations of the onboard logic 40a, 40b of the FPGAs 10a, 10b can be synchronized with each other.

Furthermore, by generating the synchronous clock SCLKa using the reference clock RCLKa, which is the operating clock of the PCIe interface 20a, it is possible to generate the synchronous clock SCLKa that is synchronized with the reference clock RCLKa, as shown in FIG. Thereby, packets can be sent and received to and from the PCIe interface 20a in accordance with the operation of the PCIe interface 20a. As a result, compared to the case where the synchronous clock SCLKa that is not synchronized with the reference clock RCLKa is generated, the timing design of the synchronous control circuit 30a can be made easier and a timing margin can be secured.

In cycle E, the mounted logic 40a executes an operation for one clock cycle based on the synchronization clock SCLKa, and outputs the subsequent output signal OUTa (=A2) to the synchronization control circuit 30a (FIG. 7(q)). Additionally, the onboard logic 40a outputs the execution results of the operations to the server 300 via the PCIe interface 22a in FIG.

The synchronization control circuit 30a generates a packet POUTa (A2-1, A2-2) based on the output signal OUTa (=A2), and outputs the generated packet POUTa to the PCIe interface 20a in two clock cycles of the reference clock RCLKa. . Data A2-1 is output in cycle E, and data A2-2 is output in cycle F. Based on the completion of outputting the packet POUTa (A2-1, A2-2), the transmission flag TFLGa changes from a logical value of 0 to a logical value of 1 (FIG. 7(r)). As a result, while the transmission flag TFLGa has a logical value of 1, output of the subsequent packet POUTa to the PCIe interface 20a is suppressed.

On the other hand, in cycle D and cycle E, the synchronization control circuit 30b of the FPGA 10b sequentially receives packets PINb (A1-1, A1-2) from the FPGA 10a via the PCIe interface 20b (FIG. 7(s)). The packet converter 61 generates an input signal INb (A1) based on the data A1-1 and A1-2, and outputs the generated input signal INb (A1) to the on-board logic 40b in cycle F (see FIG. 7). t)).

The synchronization control circuit 30b sets the reception flag RFLGb to a logical value of 1 based on the completion of reception of the input signal INb (A1) (FIG. 7(u)). As a result, the synchronous clock generation section 70 of the synchronous control circuit 30b generates the synchronous clock SCLKb (FIG. 7(v)). Furthermore, due to the generation of the synchronization clock SCLKb, the transmission flag TFLGb and the reception flag RFLGb are reset to logical value 0 in cycle G ((w), (x) in FIG. 7). As a result, output of subsequent output signals to the PCIe interface 20b is permitted, and reception of subsequent input signals from the PCIe interface 20b is permitted.

In cycle G, the mounted logic 40b executes the operation for one clock cycle based on the synchronization clock SCLKb, and outputs the subsequent output signal OUTb (=B2) to the synchronization control circuit 30b (FIG. 7(y)). The synchronization control circuit 30b generates a packet POUTb (B2-1, B2-2) based on the output signal OUTb (=B2), and transfers the data B2-1 and B2-2 to the PCIe interface in two clock cycles of the reference clock RCLKb. 20b.

Data B2-1 is output in cycle G, and data B2-2 is output in the cycle following cycle G. Based on the completion of output of packet POUTb (B2-1, B2-2), the transmission flag TFLGb changes from logical value 0 to logical value 1 (FIG. 7(z)). As a result, while the transmission flag TFLGb has a logical value of 1, output of subsequent output signals to the PCIe interface 20b is suppressed.

Through the above operation, the synchronous clocks SCLKa and SCLKb are each generated twice during the clock cycle shown in FIG. Therefore, the on-board logic 40a, 40b can be operated in synchronization with each other by the synchronous control circuits 30a, 30b provided independently in each FPGA 10a, 10b.

FIG. 8 shows an example of the state of each FPGA 10a and 10b in cycle A of FIG. FIG. 9 shows an example of the state of each FPGA 10a and 10b in cycle B of FIG. FIG. 10 shows an example of the state of each FPGA 10a and 10b in cycle C of FIG. FIG. 11 shows an example of the state of each FPGA 10a, 10b in cycle D of FIG. FIG. 12 shows an example of the state of each FPGA 10a and 10b in cycle E of FIG.

FIG. 13 shows an example of the state of each FPGA 10a and 10b in cycle F of FIG. FIG. 14 shows an example of the state of each FPGA 10a, 10b in cycle G of FIG. Note that in FIGS. 8 to 14, descriptions of the transmission control section 50 and reception control section 60 are omitted. Furthermore, the synchronous clock generation unit 70 is shown in a simplified manner.

As described above, in the embodiments shown in FIGS. 1 to 14, the onboard logics 40a and 40b can be operated in synchronization with each other by the synchronous control circuits 30a and 30b provided in each of the FPGAs 10a and 10b. For example, by controlling the setting/resetting of the transmission flags TFLGa, TFLGb and the reception flags RFLGa, RFLGb for each of the synchronization control circuits 30a, 30b, the mounted logics 40a, 40b can be operated in synchronization with each other.

Therefore, even when the scale of logic is large, for example, when the logic mounted on an ASIC is divided and mounted on a plurality of FPGAs 10a and 10b, synchronous operation can be realized. In other words, synchronous operation can be achieved regardless of the scale of a logic circuit such as an ASIC. As a result, logic verification can be performed by operating circuits (hardware) programmed in the FPGAs 10a and 10b, and logic verification can be performed faster than when using a logic verification simulator.

The synchronization control circuit 30a sets a transmission flag TFLGa based on the completion of transmission of the signal A1, and sets a reception flag RFLGa based on the completion of reception of the signal B1. Thereby, as shown in FIG. 7, even when the signal A1 is transmitted in multiple cycles and the signal B1 is received in multiple cycles, the mounted logics 40a and 40b can be operated in synchronization with each other.

The synchronization control circuit 30a generates a packet POUTa including the output signal OUTa by the packet conversion unit 51, outputs it to the PCIe interface 20a, and extracts the input signal INa from the packet PINa received from the PCIe interface 20a. Thereby, signals can be transmitted and received between the FPGAs 10a and 10b using a standard interface such as PCIe. Even when using a standard interface, the operations of the onboard logic 40a, 40b of the FPGAs 10a, 10b can be synchronized with each other.

By generating the synchronous clock SCLKa using the reference clock RCLKa, which is the operating clock of the PCIe interface 20a, it is possible to generate the synchronous clock SCLKa that is synchronized with the reference clock RCLKa, as shown in FIG. Thereby, packets can be sent and received to and from the PCIe interface 20a in accordance with the operation of the PCIe interface 20a. As a result, compared to the case where the synchronous clock SCLKa that is not synchronized with the reference clock RCLKa is generated, the timing design of the synchronous control circuit 30a can be made easier and a timing margin can be secured.

FIG. 15 shows an example of a verification system including a verification device in another embodiment. Elements similar to those in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The verification system 102 shown in FIG. 15 includes a verification device 202 including a plurality of FPGAs 10a, 10b, and 10c, and a server 300 that controls logic verification by the verification device 202. The FPGAs 10a and 10b have the same configuration and function as the FPGAs 10a and 10b shown in FIG. 1, except that the FPGA 10c is connected between the FPGAs 10a and 10b.

The verification device 202 has a function of synchronizing and operating the onboard logics 40a, 40b, and 40c to be verified that are programmed in the FPGAs 10a, 10b, and 10c, respectively. To this end, similarly to FIG. 1, the FPGA 10a is programmed with the synchronous control circuit 30a together with the on-board logic 40a, and the FPGA 10b is programmed with the synchronous control circuit 30b together with the on-board logic 40b. In addition, the FPGA 10c is programmed with synchronous control circuits 30c and 32c that operate in synchronization with each other, together with the on-board logic 40c.

Although not particularly limited, the FPGAs 10a, 10b, and 10c, and the FPGA 10a and the server 300 are connected by PCIe interfaces, as in FIG. 1. However, the FPGAs 10a, 10b, and 10c and the FPGA 10a and the server 300 may be connected via other communication interfaces.

A PCIe interface 20c, a synchronous control circuit 30c, an onboard logic 40c, a synchronous control circuit 32c, and a PCIe interface 22c are programmed in the program area of the FPGA 10c, and are connected in this order. The PCIe interface 20c is connected to the PCIe interface 20a of the FPGA 10a, and the PCIe interface 22c is connected to the PCIe interface 20b of the FPGA 10b.

FIG. 16 shows an example of a synchronous control circuit 30c installed in the FPGA 10c of FIG. 15. The synchronous control circuit 30c is the same as the synchronous control circuit 30a shown in FIGS. 3 and 5 and the synchronous control circuit 30b shown in FIG. 5, except that the signal names are different and that it does not have the synchronous clock generation section 70. It has the following configuration and functions.

The reception control unit 60 of the synchronization control circuit 30c receives the packet PINc1 from the PCIe interface 20c, and outputs an input signal INc1 including payload information of the packet PINc1 to the onboard logic 40c. The transmission control unit 50 of the synchronization control circuit 30c receives the output signal OUTc1 from the mounted logic 40c, and outputs a packet POUTc1 containing information of the output signal OUTc1 to the PCIe interface 20c.

Note that the RS flip-flop 62 of the reception control section 60 and the RS flip-flop 52 of the transmission control section 50 receive the clock enable signal CENc and the synchronization clock SCLKc from the synchronization control circuit 32c (FIG. 17). Further, the reception flag RFLGc1 outputted from the RS flip-flop 62 and the transmission flag TFLGc1 outputted from the RS flip-flop 52 are outputted to the synchronization control circuit 32c.

FIG. 17 shows an example of the synchronous control circuit 32c installed in the FPGA 10c of FIG. 15. The synchronous control circuit 32c has the same configuration and structure as the synchronous control circuit 30a shown in FIGS. 3 and 5, except that the signal names are different and that the synchronous clock generator 73 is included instead of the synchronous clock generator 70. Has a function.

The transmission control unit 50 of the synchronization control circuit 32c receives the output signal OUTc2 from the onboard logic 40c, and outputs a packet POUTc2 containing information on the output signal OUTc2 to the PCIe interface 22c. The reception control unit 60 of the synchronization control circuit 32c receives the packet PINc2 from the PCIe interface 22c, and outputs an input signal INc2 containing information on the payload of the packet PINc1 to the onboard logic 40c.

Note that the onboard logic 40c executes an operation of a predetermined function using the input signal INc1 received from the synchronous control circuit 30c (FIG. 16), and outputs an output signal OUTc2 obtained by the operation to the synchronous control circuit 32c. do. Furthermore, the mounted logic 40c executes an operation of a predetermined function using the input signal INc2 received from the synchronous control circuit 32c, and outputs an output signal OUTc1 obtained by the operation to the synchronous control circuit 30c.

The synchronous clock generation section 73 includes a four-input AND circuit AND4 and a latch circuit 71. The AND circuit AND4 receives the transmission flag TFLGc1 and reception flag RFLGc1 generated within the synchronous control circuit 30c, and the transmission flag TFLGc2 and reception flag RFLGc2 generated within the synchronous control circuit 32c.

The AND circuit AND4 sets the clock enable signal CENc to a valid level (logical value 1) when all of the transmission flags TFLGc1 and TFLGc2 and the reception flags RFLGc1 and RFLGc2 have a logical value of 1 (set state). The AND circuit AND4 sets the clock enable signal CENc to an invalid level (logical value 0) when any one of the transmission flags TFLGc1, TFLGc2 or the reception flags RFLGc1, RFLGc2 has a logical value of 0 (reset state).

Like the latch circuit 71 in FIG. 3, the latch circuit 71 latches the logical value of the clock enable signal CENc in synchronization with the reference clock RCLKc, and generates the synchronized clock SCLKc. Clock enable signal CENc and synchronous clock SCLKc are supplied to RS flip-flops 52 and 62 in synchronous control circuit 32c and RS flip-flops 52 and 62 in synchronous control circuit 30c.

In this embodiment, the synchronous clock generation unit 73 outputs the synchronous clock SCLKc when all of the transmission flags TFLGc1 and TFLGc2 and the reception flags RFLGc1 and RFLGc2 are set to logical value 1. Then, the synchronization control circuit 30c resets the transmission flag TFLGc1 and the reception flag RFLGc1 to logical value 0 in synchronization with the synchronization clock SCLKc, and is set in a state where signal transmission and reception are possible. Similarly, the synchronization control circuit 32c resets the transmission flag TFLGc2 and the reception flag RFLGc2 to logical value 0 in synchronization with the synchronization clock SCLKc, and is set to a state in which signal transmission and reception are possible.

In this way, by using the common synchronization clock SCLKc, control of signal transmission and reception by the synchronization control circuits 30c and 32c can be synchronized. Thereby, similarly to the embodiment described above, the mounted logics 40a and 40b in the FPGAs 10a and 10b can be operated in synchronization with the operation of the mounted logic 40c in the FPGA 10c.

As described above, the same effects as the embodiments shown in FIGS. 1 to 14 can be obtained in this embodiment as well. Furthermore, in this embodiment, even when the scale of logic is large, for example, when the logic mounted on an ASIC is divided and mounted on three or more FPGAs 10a, 10b, and 10c, synchronous operation can be realized. In other words, synchronous operation can be achieved regardless of the scale of a logic circuit such as an ASIC.

FIG. 18 shows an example of a verification system including a verification device in another embodiment. Elements similar to those in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The verification system 104 shown in FIG. 18 includes a verification device 204 including a plurality of FPGAs 10d, 10b, and 10e, and a server 300 that controls logic verification by the verification device 204. The FPGA 10b has the same configuration and functions as the FPGA 10b shown in FIG. 1 except that it is connected to the FPGA 10d. The FPGA 10e has the same configuration and functions as the FPGA 10b shown in FIG. 1 except that it is connected to the FPGA 10d.

In the program area of the FPGA 10d, PCIe interfaces 20d and 24d, a synchronous control circuit 30d, an onboard logic 40d, and a PCIe interface 22d are programmed and connected in this order. The PCIe interface 20d is connected to the PCIe interface 20b of the FPGA 10b, and the PCIe interface 24d is connected to the PCIe interface 20e of the FPGA 10e.

For example, when performing logic verification, the PCIe interface 22d converts serial data received from the server 300 into parallel data and outputs it to the mounted logic 40d. The onboard logic 40d uses the data received from the PCIe interface 22d to execute a predetermined functional operation, and outputs the data obtained from the operation to the PCIe interfaces 20d and 24d, respectively. Furthermore, the onboard logic 40d executes an operation of a predetermined function using the data received from the PCIe interfaces 20d and 24d, respectively, and outputs the data obtained by the operation to the PCIe interface 22d.

The synchronization control circuit 30d executes control to mutually synchronize data transmitted to and received from the mounted logic 40d, data transmitted to and received from the PCIe interface 20d, and data transmitted to and received from the PCIe interface 24d. An example of the synchronous control circuit 30d will be explained with reference to FIG.

FIG. 19 shows an example of a synchronous control circuit 30d installed in the FPGA 10d of FIG. 18. The same configurations and functions as those in FIGS. 3 and 17 are denoted by the same reference numerals, and detailed explanations will be omitted. The synchronization control circuit 30d includes transmission control sections 501 and 502, reception control sections 601 and 602, and a synchronization clock generation section 73.

Transmission control units 501 and 502 each have the same configuration and function as transmission control unit 50 shown in FIG. 3. The transmission control unit 501 converts the output signal OUTd1 output from the mounted logic 40d into a packet POUTd1. The transmission control unit 502 converts the output signal OUTd2 output from the mounted logic 40d into a packet POUTd2.

Reception control units 601 and 602 each have the same configuration and function as reception control unit 60 shown in FIG. 3. The reception control unit 601 extracts data (payload) from the packet PINd1 received from the PCIe interface 20d, and outputs the extracted data to the mounted logic 40d as an input signal INd1. The reception control unit 602 extracts data (payload) from the packet PINd2 received from the PCIe interface 24d, and outputs the extracted data to the mounted logic 40d as an input signal INd2.

The synchronous clock generation section 73 has the same configuration and function as the synchronous clock generation section 73 in FIG. 17 . When the transmission flags TFLGd1 and TFLGd2 and the reception flags RFLGd1 and RFLGd2 all have a logical value of 1, the synchronous clock generation unit 73 sets the clock enable signal CENd to a valid level (logical value of 1). Then, the synchronous clock generation section 73 latches the logical value of the clock enable signal CENc in synchronization with the reference clock RCLKc, and generates the synchronous clock SCLKd. Furthermore, when any one of the transmission flags TFLGd1 and TFLGd2 or the reception flags RFLGd1 and RFLGd2 has a logical value of 0, the synchronous clock generation unit 73 sets the clock enable signal CENd to an invalid level (logical value of 0). The clock enable signal CENd and the synchronization clock SCLKd are supplied to the RS flip-flop 52 in the transmission control sections 501 and 502 and the RS flip-flop 62 in the reception control sections 601 and 602.

Also in this embodiment, similarly to the embodiments shown in FIGS. 16 and 17, the synchronization control circuit 30d resets the transmission flags TFLGd1, TFLGd2 and the reception flags RFLGd1, RFLGd2 in synchronization with the synchronization clock SCLKd. The synchronization control circuit 30d is then set to a state in which it can transmit and receive signals. Thereby, the mounted logic 40d of the FPGA 10d and the mounted logics 40b and 40e of the FPGAs 10b and 10e connected via the synchronization control circuit 30d can be operated in synchronization with each other.

For example, even when the logic scale on the back side is larger than the logic scale on the entrance side (previous stage side) and the logic on the back side is programmed into multiple FPGAs 10b and 10e, the mounted logic 40d, 40b, 40e of the FPGAs 10d, 10b, 10e can be operated in synchronization with each other.

As described above, the same effects as the embodiments shown in FIGS. 1 to 17 can be obtained in this embodiment as well.

In addition, in the embodiment described above, an example was described in which the present invention is applied to the verification device 200 (or 202, 204) that verifies logic that is divided and programmed into a plurality of FPGAs 10. However, the embodiments described above may be applied to a system including a logic circuit that realizes a predetermined function by operating the logics programmed in a plurality of FPGAs 10 in synchronization with each other.

The features and advantages of the embodiments will become apparent from the above detailed description. It is intended that the appended claims extend to the features and advantages of such embodiments without departing from the spirit and scope thereof. Additionally, all improvements and changes will be readily apparent to those having ordinary knowledge in the relevant technical field. Therefore, it is not intended that the scope of the inventive embodiments be limited to those described above, but suitable modifications and equivalents may be made within the scope disclosed in the embodiments.

10a, 10b, 10c, 10d, 10e FPGA
20a, 20b, 20c, 20d, 20e PCIe interface 22a, 22b, 22c, 22d PCIe interface 24d PCIe interface 30a, 30b, 30c, 30d, 30e Synchronous control circuit 32c Synchronous control circuit 40a, 40b, 40c, 40d, 40e Onboard logic 50, 501, 502 Transmission control section 51 Packet conversion section 52 RS flip-flop 60, 601, 602 Reception control section 61 Packet conversion section 62 RS flip-flop 70 Synchronous clock generation section 71 Latch circuit 100, 102, 104 Verification system 200, 202 , 204 Verification device 300 Server CENa, CENc Clock enable signal INa, INb, INc1, INc2 Input signal INd1, INd2 Input signal OUTa, OUTb, OUTc1, OUTc2 Output signal OUTd1, OUTd2 Output signal PINa, PINb, PINc1, P INc2 Packet PINd1, PINd2 Packet POUTa, POUTb, POUTc1, POUTc2 Packet POUTd1, POUTd2 Packet RCLKa, RCLKb, RCLKc Reference clock RFLGa, RFLGb, RFLGc1, RFLGc2 Reception flag RFLGd1, RFLGd2 Reception flag SC LKa, SCLKb, SCLKc Synchronous clock TFLGa, TFLGb, TFLGc1, TFLGc2 Transmission Flag TFLGd1, TFLGd2 Transmission flag

Claims (6)

A synchronization control circuit provided in a programmable section in which a logic circuit is reconfigurably programmed, and synchronizing signals transmitted and received between the programmable section and another programmable section,
a transmission control unit that outputs the output signal to a transmission interface and sets the transmission flag when an output signal is received from a logic circuit programmed in the programmable unit while resetting the transmission flag;
a reception control unit that outputs the reception signal to the programmed logic circuit and sets the reception flag when a reception signal is received from the reception interface while the reception flag is being reset;
a synchronous clock generation unit that outputs a synchronous clock to the programmed logic circuit and resets the transmission flag and the reception flag when the transmission flag and the reception flag are set;
A synchronous control circuit with Each of the plurality of synchronous control circuits corresponding to the other plurality of programmable parts, included in a programmable part that transmits and receives signals to and from each of the other plurality of programmable parts, is connected to the other plurality of programmable parts. the transmission control section and the reception control section corresponding to each of the above ;
When the plurality of transmission flags corresponding to the plurality of transmission control units and the plurality of reception flags corresponding to the plurality of reception control units are all set, the synchronous clock generation unit The synchronous control circuit according to claim 1, wherein the synchronous clock is output to logic circuits respectively programmed in the programmable section, and resets the plurality of transmission flags and the plurality of reception flags. The transmission control unit includes a transmission flag setting unit that sets the transmission flag based on completion of outputting the output signal to the transmission interface, and resets the transmission flag based on the output of the synchronization clock,
The reception control unit includes a reception flag setting unit that sets the reception flag based on completion of reception of the reception signal from the reception interface, and resets the reception flag based on the output of the synchronization clock.
A synchronous control circuit according to claim 1 or claim 2. The transmission control section includes:
a packet conversion unit that generates a transmission packet including information on the output signal received from the logic circuit;
a packet output control unit that outputs the transmission packet as the output signal to the transmission interface while the transmission flag is being reset, and suppresses output of the transmission packet to the transmission interface while the transmission flag is being set; death,
The reception control section includes:
a packet input control unit that outputs a received packet from the reception interface as the reception signal while the reception flag is reset, and suppresses output of the reception packet from the reception interface while the reception flag is set;
a packet conversion unit that extracts the received signal included in the received packet from the packet input control unit and outputs it to the programmed logic circuit;
The synchronous control circuit according to claim 3, comprising: The synchronous clock generation section includes:
an enable generation circuit that generates a clock enable signal based on the transmission flag and the reception flag being set;
a clock output unit that receives the clock enable signal in synchronization with an operating clock that operates the transmission interface and the reception interface, and outputs the received clock enable signal as the synchronization clock;
A synchronous control circuit according to any one of claims 1 to 4. A synchronous control method for synchronizing signals transmitted and received between a plurality of programmable parts in which logic circuits are reconfigurably programmed, the method comprising:
Each of the plurality of programmable parts,
If an output signal is received from a logic circuit programmed in the programmable part while resetting the transmission flag, outputting the output signal to a transmission interface and setting the transmission flag;
If a receive signal is received from the receive interface while the receive flag is being reset, outputting the receive signal to the programmed logic circuit and setting the receive flag;
A synchronous control method comprising, when the transmission flag and the reception flag are set, outputting a synchronous clock to the programmed logic circuit and resetting the transmission flag and the reception flag.

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