JP2011191893A - Logic verification device for divisionally mounted logic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic verification device allowing correct logic operation even if data of transfer cycle delay are present between FPGAs (Field Programmable Gate Arrays) when mounting large-scale logic in the plurality of FPGAs and performing verification at high speed. <P>SOLUTION: This logic verification device uses parallel-serial conversion, and adopts a time division transfer method when transmitting/receiving signals from a plurality of signal lines through one physical line. At that time, the logic verification device determines an operation frequency of the large-scale logic based on a signal transfer time on the physical line. Time division transfer sets a data signal or the like wherein a clock signal or a reset signal is excluded from a target of the time division transfer as a transfer target, and the logic verification device operates a clock of the large-scale logic when the time division transfer ends, and reflects transferred data in a register of the large-scale logic. Before and after start timing and end timing of time division data transfer processing, a holding cycle for signal stabilization is allocated, and rising and falling of the clock for the large-scale logic are performed in synchronization with the holding cycles of both ends. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a logic verification apparatus for a logic circuit, and more particularly to an apparatus for verifying the logic of a separately mounted logic circuit.

  In general, software logic simulators are used for logic function verification of ASIC (Application Specific Integrated Circuit). However, the verification items for function verification become large when the scale is large. Processing time becomes enormous and it is difficult to confirm the entire verification items within the development period.

  Therefore, I would like to verify the logic of a large-scale ASIC in an FPGA (Field Programmable Gate Array) and perform high-speed verification. However, not all the logic can be contained in one FPGA, but it is divided into several to dozens of FPGAs. It must be built in the installed environment. At this time, the signal dose between the FPGAs does not fit in the number of physical pins, and even in the clock and reset, a time lag occurs between the FPGAs, and inconsistency occurs in the signal transfer with the synchronous clock between the FPGAs. However, the operation may be illegal.

  An object of the present invention is to provide a synchronous connection method between a plurality of FPGAs or ASICs that exist on a board or between boards via a cable, using a transfer clock faster than a clock used in the corresponding logic.

JP 11-33282 A JP 2001-34648 A

  The invention described in Patent Document 1 is a data transfer method that does not use a PLL (Phase Locked Loop) circuit in which the state of the device becomes unstable with a lock time and the chip area becomes large. It is means for sending out in parallel and eliminating reception clock generation on the reception side. This means requires a clock signal line for signal transfer. If the data width becomes large, a state in which the setup time or hold time of the data signal cannot be secured with one clock line occurs.

  Therefore, when the number of clock signal lines is increased, the number of signal lines that can be connected by the number of physical pins between the ASIC and the FPGA is pressed against the clock lines, and the number of transfer signals is reduced.

  Further, Patent Document 1 does not describe how to synchronize with the clock signal of the receiving side with respect to the signal line after transfer, and when the synchronization logic of a large-scale circuit is divided and mounted. May occur when the synchronization logic operates abnormally.

  On the other hand, the invention described in Patent Document 2 relates to a logic verification method using an FPGA, in which a logic verification target circuit is mapped to an FPGA, wiring between FPGAs is easy, and signal transmission delay due to wiring delay is reduced. As means for avoiding and shortening the time required for determining the wiring route, a parallel-serial conversion and serial-parallel conversion logic is incorporated between the FPGAs on which the target logic is mounted, and a switch FPGA for wiring between the FPGA signal lines is provided. This is a technique for mounting and transmitting signals between logic circuits. However, there is no description on how to synchronize after high-speed transfer, and there is a risk that the execution cycle is delayed by several cycles in the logic circuit mounted in each FPGA.

  As a countermeasure to this problem, in order to synchronize clocks between the FPGAs, a physical design in which the lengths of the wirings between the FPGAs are made equal and the delays of the clock generators are made the same using a common FPGA. The clock frequency applied to the logic circuit is adjusted in consideration of the delay time between the FPGAs, and the normal logic operation is started after the clock generation by the PLL of all the FPGAs is stabilized.

  However, in this method, it is necessary to perform equal-length wiring processing of clock supply wiring between FPGAs on the FPGA mounting board, and even if the same FPGA is used, a slight delay difference occurs in the clock generation part, and a short distance is required. A transfer error due to a minimum delay violation may occur in the transfer between FPGAs.

  The present invention has been made in view of such a situation, and an object of the present invention is to provide a logic verification device that can realize a correct logic operation even if data with a transfer cycle delay exists.

  If a large-scale ASIC logic is divided and mounted on a plurality of FPGAs, the signal lines between the logics mounted on each FPGA greatly exceed the number of physical pins of the FPGA. A time division transfer method for transmitting and receiving a plurality of signal lines on one physical line is used. The operating frequency of the large-scale ASIC logic to be verified can be determined by the signal transfer time on the physical line at this time.

  In time-division transfer, when a clock signal or reset signal that directly affects the flip-flop that holds the signal value is excluded from the time-division transfer target, the data signal is the transfer target, and when time-division transfer ends The ASIC logic clock is operated, and the transferred data is reflected in the original ASIC logic register (flip-flop). However, transfer data between FPGAs may not be transferred within one clock depending on the state of the FPGA-mounted logic. Therefore, a holding cycle for signal stabilization is assigned before and after the start timing and end timing of the time division data transfer processing, and the rising and falling of the ASIC logic clock are synchronized with the holding cycles at both ends. Do it. In this way, it is possible to provide a logic verification device that operates correctly even when data with a time division transfer cycle delay exists.

  As an example of an environment using a plurality of FPGAs, on a board on which four FPGAs having 800 input / output pins are mounted, 200 can be used as signal lines between three FPGAs and 200 can be used as external input / output signal lines.

  If there are 4000 inter-FPGA signal lines when the ASIC logic is divided, if 10 control signals for directly controlling flip-flops such as clock lines and reset lines of each FPGA are used, 3990 / Since 190 = 21, 21 signal lines need only be sent out by one FPGA pin. In order to serially transfer 21 pieces of data, if several bits of serial line control data are included, 24 or more signal transfer times are required, and the logical operation at this time is 24 times the signal transfer processing between FPGAs. It takes time. For example, when the inter-FPGA transfer process is realized at 100 MHz, the logic operating frequency of the ASIC is 4.16 MHz. Here, when 1 clock is allocated as the holding time for signal stabilization and the transfer cycle is 25 times, the ASIC logic operation frequency becomes 4 MHz, which reduces to 96% performance, but the logic operation is easily guaranteed. Therefore, it is easy to construct an FPGA environment.

According to a first aspect of the present invention, a logic circuit to be verified is divided into a plurality of logic blocks, and the plurality of logic blocks are incorporated on a plurality of semiconductor chips such as an FPGA, thereby A device that performs logic verification of a circuit,
As means for transferring signals from a plurality of signal lines exceeding the number of physical pins of the semiconductor chip, time-division using parallel-serial conversion that allows signals from the plurality of signal lines to be transmitted by one physical pin Transfer logic and
Logic for obtaining the number of clocks for time division transfer based on the maximum signal transfer quantity calculated from the number of signal lines between the plurality of logic blocks and the number of physical pins of the semiconductor chip;
A source oscillation clock supply source arranged equidistant from all of the plurality of semiconductor chips,
The time division transfer is stopped until the clock generation of the semiconductor chip is stabilized after the power is turned on, and a signal for starting the time division transfer is transmitted from one of the semiconductor chips to the other semiconductor chip at a stable time,
It is characterized in that the clock used in the logic circuit to be verified is changed when the time division transfer is completed.

  According to the logic verification device of the first aspect, even when a clock signal is supplied to each logic circuit divided into each FPGA, there is no influence due to the phase shift. This is because the time-division-transferred data after parallel-serial conversion reaches all the logic circuits, then the clock control of each register is turned OFF to stop transfer data transfer, and then the operation clock for the logic circuit Is to operate.

  Thus, in the first aspect of the invention, the clock for operating the logic circuit and the clock for time division transfer are used separately. The operation clock of the logic circuit is generated at an interval obtained by adding the maximum number of cycles for transferring a signal between FPGAs and the number of signal holding cycles. In the time division transfer process, first, the operation clock of the logic circuit is raised or lowered to instruct the start of the time division transfer process. In the first cycle, the logic signal value is taken into the transfer source register, and at the same time, the transfer destination register is cleared. In the following cycle, data is output from the transfer source and sent to the transfer destination.

The configuration of the logic verification device according to claim 2 is the logic verification device according to claim 1,
A means for checking the legitimacy of the transfer signal during time division transfer and reporting the portion of the time division transfer that resulted in an error if a transfer error occurred;
And a means for stopping the supply of the clock signal.

  According to the logic verification device of the second aspect, both the logic clock and the transfer clock can be stopped based on the transfer error signal, and the cause of the error can be easily pursued. Furthermore, according to this method, signal stability during the behavior of the logical clock can be ensured without transferring signals between FPGAs, so that no malfunction occurs.

  By implementing the present invention, it is possible to easily secure a setup time and a hold time sufficient for a flip-flop operation between a clock signal line of a logic circuit and a data signal line for transfer between FPGAs, and start-up adjustment of a verification device As a result, signal transfer between FPGAs in the system is simplified and the verification operation is smoothly performed. As a result, a verification period can be shortened and verification cost can be reduced.

  In addition, if the present invention is implemented, the manufacturing cost is reduced because no special wiring is required to ensure sufficient setup time and hold time for flip-flop operation at the stage of designing a board for a verification device. it can.

Schematic diagram of a logic verification apparatus according to the present invention Schematic diagram of verification configuration in logic verification device according to the present invention Schematic diagram of clock connection when logic is divided into three Schematic diagram of clock generation mechanism Schematic diagram of time division transfer logic Time chart of time division transfer processing Schematic of time division transfer check logic Time division transfer processing time chart when a transfer error occurs

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out a logic verification apparatus for a separately mounted logic circuit according to the present invention will be described below in detail with reference to the accompanying drawings. 1 to 8 are diagrams illustrating embodiments of the present invention. In these drawings, the same reference numerals denote the same components, and the basic configuration and operation are the same. To do.

  As an embodiment of the present invention, a method using an FPGA for a semiconductor will be described in detail with reference to the drawings. FIG. 1 shows an outline of a verification target device. As shown in FIG. 1, the entire verification target device 100 is generally composed of a plurality of logic blocks such as logic 1, logic 2, logic 3, and logic 4. The clock generated by the clock generation circuit 101 operates the sequential circuit of the entire device. The signal input from the input signal 102 to the device is processed by logic 1, and the result is sent to the logic 2 from the signal line 103. The The logic 2 sends the result of performing a predetermined operation based on the input from the signal line 103 to the logic 3 from the signal line 104. Similarly, the logic 3 sends a result of performing a predetermined operation based on the input from the signal line 104 to the logic 4 from the signal line 105, and the logic 4 performs a predetermined operation based on the input from the signal line 105. The result of the above is sent as an output signal 106 from the entire verification target device 100.

  When such a logical configuration is mounted on an FPGA or the like, it is often impossible to mount all on a single FPGA, and it is necessary to divide and mount the target logic circuit on a plurality of FPGAs or the like.

  FIG. 2 shows a schematic diagram of a verification configuration of an apparatus in which the logical configuration of FIG. 1 is divided into two FPGAs, FPGA 1 (201) and FPGA 2 (202). Since signal propagation between FPGAs has a delay, when a clock signal generated by a clock generation circuit in one FPGA is sent to another FPGA and used, the logic operation is synchronized by the signal delay. It becomes difficult. Therefore, in order to synchronize the logic operation across a plurality of FPGAs, clock generation circuits 203 and 204 are provided in FPGA 1 (201) and FPGA 2 (202), respectively, and each FPGA is generated by a source clock 200 from an oscillator or the like. The clock generation circuits 203 and 204 are driven, and a clock signal is supplied to each sequential circuit.

  The clock synchronization means is as follows. Signals Lock1 and Lock2 indicating that the PLL used in the clock generation circuits 203 and 204 in each FPGA has started the stable operation with the source clock are reported to the synchronous reset generation circuit 205 that monitors the stable operation of all the FPGAs. The Then, a synchronous reset 206 is generated from the synchronous reset generation circuit 205 and transmitted to all the FPGAs, and the clock supply circuits F1 and F2 of the FPGA1 (201) and the gates of the clock supply circuits F3 and F4 of the FPGA2 (202) are connected. Open and clock is supplied to each logic.

  On the other hand, between the FPGA1 (201) and the FPGA2 (202), the number of signal lines that can be connected is restricted by the number of physical pins. However, if the logic of the device to be verified is installed in a plurality of FPGAs, the number of signal lines required between the FPGAs often exceeds this restriction. As a countermeasure, for example, when a signal is transmitted from the logic 1 in the FPGA 1 (201) to the logic 2 in the FPGA 2 (202), the four output signal lines of the logic 1 are time-division logic 1 that performs parallel-serial conversion. In summary, signal transfer is performed with one transfer signal S 0, and on the FPGA 2 (202) side, the transfer signal S 0 is parallelized by time-division logic 2 such as a serial-parallel conversion mechanism, and is transferred to logic 2 via the signal line 103. Tell.

  Similarly, when a signal is transmitted from the logic 3 in the FPGA 2 to the logic 4 in the FPGA 1, the four output signal lines of the logic 3 are grouped together by the time division logic 3 that performs parallel-serial conversion, and one transfer signal S 1 is used. Signal transfer is performed, and on the FPGA 1 side, the transfer signal S 1 is parallelized by the time division logic 4 such as a serial-parallel conversion mechanism and transmitted to the logic 4 via the signal line 105.

  At this time, while the clocks C0 and C1 for logic operation change once, the clocks T0 and T1 for time division transfer need to change in the number of cycles necessary for completing the time division transfer. In other words, if time-division transfer processing is required for n cycles, the clock generation circuits 203 and 204 require 1/2 times of C0 and C1 because n times are required at the rising edge of the logic operation clock and n times at the falling edge. Clocks T0 and T1 must be generated with a period.

  FIG. 3 shows a schematic diagram of clock connection when the target logic circuit is divided into three FPGAs. As in FIG. 2, the FPGA 3 also has a clock generation circuit, and the Lock3 signal from the corresponding clock generation circuit is connected to the synchronization reset circuit for synchronization, and the clock generation circuits of all FPGAs have shifted to stable operation. Sometimes, the synchronization operation of the entire apparatus is realized by starting driving the logic clock and transfer clock of all FPGAs.

  FIG. 4 is a schematic diagram of clock generation, and FIG. 5 is a schematic diagram of time division transfer logic. The logic clock of the logic circuit drives a sequential circuit such as a flip-flop in each FPGA. The input signal value to each flip-flop usually propagates as an output signal value after a certain delay time has elapsed. Due to the physical distance between the receiving-side FPGA and the transmitting-side FPGA, the arrival time of the transfer signal is further delayed.

  Therefore, in signal transfer between FPGAs, it is necessary to take in a signal value for transfer in consideration of a certain delay time after fluctuation of the logic clock. On the receiving side, in consideration of arrival time of the transfer signal, It is necessary to change the next logic clock.

  The clock generation method will be described with reference to FIG. A source clock supplied from an oscillator or the like arranged at an equal distance from any FPGA is connected to the PLL 410 in the FPGA. When the clock output is stabilized by the PLL 410, a Lock signal is sent to the synchronous reset generation circuit. The sum of the maximum signal transfer quantity 401 set in advance by a parameter or the like and the number of logical clock issuance wait cycles 402 (described later) is a logical clock period 403. The count value 412 of the counter 411 updated with the clock generated by the PLL 410 and the logical clock cycle 403 are compared with each other by the comparator 404. If they are equal, the enable signal 409 is supplied to the flip-flop 405. Inverted, the transfer clock is controlled. When the logic clock changes, a transfer start (SE) is generated by the exclusive OR 408 of the output signal of the flip-flop 405 and the output signal of the flip-flop 407, and is output to the time division transfer logic unit in FIG. The

  The time division transfer logic of FIG. 5 is a logic that operates with a transfer clock, and the number of shift stages of the transmission-side shift flip-flop is the same as the number of shift stages of the reception-side shift flip-flop. The outline of the operation is as follows. In the selector 521, when the transfer activation (SE) becomes High, the transfer start bit (High) and the output signal line of the combinational circuit 511 in the verification target logic unit 501 or the output signal of the flip-flop 512 at the rising edge of the transfer clock. The line is taken into the transmission flip-flop 522 of the transmission side time division transfer logic 502. When the transfer activation (SE) becomes Low, the logic signal values fetched following the transfer start bit (High) are sequentially sent to the reception side time division transfer logic 503 of the reception side FPGA as a transmission signal.

  In the receiving side time division transfer logic 503 in the receiving side FPGA, the received signals are sequentially fetched using the transfer clock. When the transfer start bit reaches the final flip-flop 532, the clock enable of the reception flip-flop 531 is turned off, and the shift operation of the reception flip-flop 531 is stopped. The fetched transfer signal is set in the subsequent flip-flop 533 at the next transfer clock, and is output to the verification target logic unit 504. At the same time, the reception flip-flop 531 is initialized by the output signal of the flip-flop 534. By this initialization, the reception flip-flop 531 is cleared to zero, so that when the next transfer signal is High, it is guaranteed that it is a transfer start bit.

  In this way, the transfer start (SE) is output in the cycle in which the change of the logic clock occurs, and in the next transfer clock cycle, the transmission side logic signal is taken into the time-division transfer logic, and sequentially received by the receiving side FPGA. Send to the receiver time division transfer logic.

  FIG. 6 shows a time chart of the time division transfer process. Here, the situation is shown when 4-bit time division transfer processing is performed in 8 cycles. The maximum number of signal transfers is 5, and the breakdown is 4 cycles for the signal and 1 cycle for the transfer start bit. In addition, the number of logical clock issuance wait cycles is 3, and the breakdown is 1 cycle from the logical clock as a setup guarantee for time division transfer logic, 1 cycle as a transfer guarantee between FPGAs, and a logic from the time division transfer logic on the receiving side. One cycle is used to guarantee the clock setup.

  Next, a method for checking a transfer signal in the time division transfer logic will be described. FIG. 7 shows an outline of the time division transfer check logic for checking the transfer signal value in the time division transfer logic. The parity check circuit 703 in the transmission side time division transfer logic 701 of the transmission side FPGA performs a parity check of the transfer target signal line, adds the transmission side check result 704 to the transmission signal, and receives the time division of the reception side of the reception side FPGA. Send to transfer logic 702. The reception side time division transfer logic 702 of the reception side FPGA extracts the transmission side parity data 705 from the reception signal, further performs a parity check of the reception signal by the parity check circuit 706, and obtains the reception side check result 707. The transmission side parity data 705 and the reception side check result 707 are compared, and if they do not match, an error signal is generated. If this error signal is used as the transfer error signal shown in FIG. 4, the logic clock and the transfer clock are stopped. Therefore, when an error occurs, the signal line used for data transfer can be specified, and the cause of the error can be investigated. It becomes easy.

  FIG. 8 shows an outline of a time division transfer time chart when a transfer error occurs. According to this method, since signal stability during the behavior of the logical clock can be ensured without transferring signals between FPGAs, no malfunction occurs.

  As described above, the logic verification apparatus for the divided and mounted logic circuit according to the present invention has been described by showing specific embodiments, but the present invention is not limited to these. A person skilled in the art can make various changes and improvements to the configuration and function of the circuit in each of the above embodiments without departing from the scope of the present invention.

  The present invention can be applied to logic prototyping of a large scale integrated circuit, and can be applied to a logic verification apparatus such as a large scale logic simulation accelerator, in particular, a large scale ASIC or the like mounted on an FPGA to verify its logic function. It is.

  In addition, when the external interface is modeled by FPGA and the function of the device is verified by a logic emulator, it can be widely adopted.

100: Entire verification target device 101: Clock generation circuit 102: Input signals 103, 104, 105 to the device: Signal line 106: Output signal from the device 200: Source clock from an oscillator etc. 201: FPGA1
202: FPGA2
203, 204: Clock generation circuit 205: Synchronous reset generation circuit 206: Synchronous reset 401: Maximum signal transfer quantity 402: Number of logical clock issuance wait cycles 403: Logical clock period 404: Comparator 405, 406, 407: Flip-flop 408: Exclusive OR 409: Enable signal 410: PLL
411: Counters 501 and 504: Verification target logic unit 502: Transmission-side time division transfer logic 503: Reception-side time division transfer logic 521: Selector 522: Transmission flip-flop 531: Reception flip-flop 532: Final stage flip-flop 533 : Flip-flop 701 at the subsequent stage on the reception side: Transmission side time division transfer logic 702: Reception side time division transfer logic 703, 706: Parity check circuit 704: Transmission side check result 705: Transmission side parity data 707 extracted from the reception signal: Receiver check result

Claims (2)

A device that divides a logic circuit to be verified into a plurality of logic blocks, incorporates the plurality of logic blocks on a plurality of semiconductor chips such as FPGA, and performs logic verification of the logic circuit to be verified,
As means for transferring signals from a plurality of signal lines exceeding the number of physical pins of the semiconductor chip, time-division using parallel-serial conversion that allows signals from the plurality of signal lines to be transmitted by one physical pin Transfer logic and
Logic for obtaining the number of clocks for time division transfer based on the maximum signal transfer quantity calculated from the number of signal lines between the plurality of logic blocks and the number of physical pins of the semiconductor chip;
A source oscillation clock supply source arranged equidistant from all of the plurality of semiconductor chips,
The time division transfer is stopped until the clock generation of the semiconductor chip is stabilized after the power is turned on, and a signal for starting the time division transfer is transmitted from one of the semiconductor chips to the other semiconductor chip at a stable time,
A logic verification device characterized in that the clock used in the logic circuit to be verified is changed when the time division transfer is completed. The logic verification device according to claim 1,
A means for checking the legitimacy of the transfer signal during time division transfer and reporting the portion of the time division transfer that resulted in an error if a transfer error occurred;
And a logic verification device comprising means for stopping the supply of the clock signal.