CN115186616A - Data transmission control method across field programmable gate array and related equipment - Google Patents

Abstract

The invention provides a method for controlling data transmission of a cross-field programmable logic gate array and related equipment. The method comprises the following steps: latching a group of data from a first field programmable gate array by utilizing a first register device according to a first clock, wherein the group of data is sorted according to data load and pointer signal attributes and is divided into a plurality of groups of local data; sequentially transmitting the groups of local data from the first register device to the second register device at a plurality of time points respectively by using a time division multiplexing interface according to a time division multiplexing clock; and utilizing the second register device to receive the multiple groups of local data in sequence so as to output the multiple groups of data to a second field programmable gate array, wherein the second field programmable gate array operates according to a second clock different from the first clock.

Description

Data transmission control method across field programmable gate array and related equipment

Technical Field

The present invention relates to cross-device high-speed communication, and more particularly, to a method and related apparatus for controlling data transmission across a Field Programmable Gate Array (FPGA).

Background

A Field Programmable Gate Array (FPGA) is often used in a system development process, where for some systems, hardware resources of one FPGA may not be enough, so that multiple FPGAs may be required to respectively play roles of different partitions in the system, and the FPGAs are connected to each other to perform prototyping and simulation (emulation) of the whole system. In a complex system, the signal transmission width between different partitions in the FPGA often reaches tens of thousands of bits, so the number of Input/Output (IO) of the FPGA is a significant limitation in the development process. In addition, in the related art, the interconnected FPGAs may not be able to operate at their respective optimized operating frequencies in order to match each other's operating frequencies, and the overall performance is therefore limited.

Therefore, there is a need for a novel data transmission control method and related apparatus to perform data transmission across FPGAs (inter-FPGAs) with a limited number of inputs and outputs of the FPGAs, and to allow each FPGA to operate at a respective optimal frequency.

Disclosure of Invention

It is therefore an object of the present invention to provide a method and related apparatus for controlling data transmission across field programmable gate arrays (fpga's) to allow different fpga's to operate at respective optimum frequencies.

At least one embodiment of the invention provides a method for data transmission control across a field programmable gate array. The method may comprise: latching a set of data from a first Field Programmable Gate Array (FPGA) by using a first register device according to a first clock, wherein the set of data is sorted according to load (payload) and pointer (pointer) attributes and is divided into a plurality of groups of local data; transmitting the groups of local data from the first register device to the second register device at a plurality of Time points in sequence by using a Time-Division Multiplexing (TDM) interface according to a TDM clock; and utilizing the second register device to receive the plurality of groups of local data in sequence so as to output the group of data to a second field programmable gate array, wherein the second field programmable gate array operates according to a second clock different from the first clock.

At least one embodiment of the invention provides an apparatus for simulation of an electronic system, where the apparatus may include a first field programmable gate array, a second field programmable gate array, a first register means, a second register means, and a time division multiplexing interface. The first register device is coupled to the first field programmable gate array, and the second register device is coupled to the second field programmable gate array, wherein the time division multiplexing interface is coupled between the first register device and the second register device. The first field programmable gate array may be used for simulation of a first subsystem of the electronic system, where the first field programmable gate array operates according to a first clock. The second field programmable gate array may be used for simulation of a second subsystem of the electronic system, where the second field programmable gate array operates according to a second clock different from the first clock. In particular, the first register device latches a set of data from the first fpga according to the first clock, wherein the set of data is sorted according to load and pointer attributes and divided into a plurality of sets of local data to allow the tdm interface to sequentially transfer the plurality of sets of local data from the first register device to the second register device at a plurality of time points according to the tdm clock. In addition, the second register device can receive the plurality of groups of local data in sequence to output the group of data to the second field programmable gate array.

The method and apparatus provided by the embodiments of the present invention can completely isolate the clock domains of the first and second field programmable gate arrays by means of the asynchronous transfer interface ordered by data load and pointer signal attributes, so that both the first and second field programmable gate arrays can operate at their respective optimized frequencies. In particular, the embodiments of the present invention do not significantly increase the additional cost. Accordingly, the present invention can solve the problems of the related art without side effects or with less side effects.

Drawings

FIG. 1 is a schematic diagram of an apparatus for simulation of an electronic system according to one embodiment of the present invention.

Fig. 2 is an example of an asynchronous fifo register corresponding to a channel.

FIG. 3 is an example of an asynchronous FIFO register corresponding to another channel.

Fig. 4 is an example of arranging data of the same direction in a plurality of channel types to generate a set of data.

Fig. 5 is an example of a further arrangement for the data in the set of data in fig. 4.

FIG. 6 is a diagram of an apparatus for simulation of an electronic system, in accordance with one embodiment of the present invention.

Fig. 7 is a view of some details of the connection device shown in fig. 6 according to one embodiment of the invention.

Fig. 8 is a workflow of a method for data transfer control across an array of field programmable logic gates in accordance with one embodiment of the invention.

Detailed Description

FIG. 1 is a schematic diagram of an apparatus 10 for simulation of an electronic system, where the apparatus 10 may comprise a first field programmable gate array FPGA, according to one embodiment of the present invention _A And a second FPGA _B . In this embodiment, the first field programmable gate array FPGA _A Can be used for simulation of a first subsystem of the electronic system, and a second FPGA _B Can be used for simulation of a second subsystem of the electronic system, wherein the first field programmable gate array FPGA _A Operating according to a first clock, and a second FPGA _B Operating according to a second clock. For example, a first field programmable gate array FPGA _A And a second FPGA _B May be implemented with a field programmable gate array from a vendor such as Xilinx, although the invention is not so limited.

As shown in fig. 1, a first field programmable gate array FPGA _A Can be connected with a second field programmable gate array FPGA through the connecting device 100 _B The connection apparatus 100 may conform to an Advanced eXtensible Interface (AXI) bus protocol, but the invention is not limited thereto. In this embodiment, the first field programmable gate array FPGA _A Can be used as a master (master)The device, therefore the connection device 100, connects to a first field programmable gate array FPGA _A May be used as the AXI master, while a second field programmable gate array FPGA may be used as the AXI master _B Can be used as slave (slave) device, so that the connection device 100 is connected with second field programmable gate array FPGA _B May serve as an AXI slave, wherein the connection device 100 may be connected with a first field programmable gate array FPGA at the AXI master _A Two-way handshake (two way handshake) is performed, and the connection device 100 can connect with a second Field Programmable Gate Array (FPGA) at the AXI slave end _B Two-way handshaking occurs, but the invention is not limited thereto.

As shown in FIG. 1, a first FPGA _A And a second field programmable gate array FPGA _B For example, the channels described by the AXI bus protocol may include Address Read (AR), address Write (AW), write (W), read (R), and response (B) channels. In the present embodiment, the connection device 100 may include a plurality of asynchronous First-In First-Out (FIFO) registers (hereinafter referred to as "asynchronous FIFOs") such as asynchronous FIFOs 110,120,130,140 and 150 for the plurality of channel types, respectively.

In this embodiment, each of the plurality of channel types may include two directions of data transmission. Fig. 2 illustrates an asynchronous FIFO 110 corresponding to an AR (i.e., address read) channel, wherein the asynchronous FIFO 110 may receive relevant data/instructions for the AR channel from the AXI master and transfer to the AXI slave in a first-in-first-out manner. As shown in fig. 2, the asynchronous FIFO 110 may comprise an asynchronous FIFO master 111 (which may be a register file of registers) and an asynchronous FIFO slave 112 (which may be a plurality of multiplexers), wherein relevant data/instructions for the AR channel are received from the AXI master through the asynchronous FIFO master 111 and then transmitted to the AXI slave through the asynchronous FIFO slave 112. In this embodiment, communication between asynchronous FIFO master 111 and asynchronous FIFO slave 112 may include data transfer in two directions, where data transfer in the first direction may include an AR write pointer and an AR payload (e.g., a data payload) transmitted from asynchronous FIFO master 111 to asynchronous FIFO slave 112, and data transfer in the second direction may include an AR read pointer transmitted from asynchronous FIFO slave 112 to asynchronous FIFO master 111.

Additionally, fig. 3 illustrates an asynchronous FIFO 140 corresponding to an R (i.e., read) channel, wherein the asynchronous FIFO 140 may receive relevant data/instructions for the R channel from the AXI slave and transfer to the AXI master in a first-in-first-out manner. As shown in fig. 3, the asynchronous FIFO 140 may comprise an asynchronous FIFO master 141 (which may be a register file of registers) and an asynchronous FIFO slave 142 (which may be a plurality of multiplexers), wherein relevant data/instructions for the R-channel are received from the AXI slave via the asynchronous FIFO master 141 and then transferred to the AXI master via the asynchronous FIFO slave 142. In this embodiment, communication between asynchronous FIFO master 141 and asynchronous FIFO slave 142 may include two directions of data transfer, wherein a first direction of data transfer may include the R write pointer and R load from asynchronous FIFO master 141 to asynchronous FIFO slave 142, and a second direction of data transfer may include the R read pointer from asynchronous FIFO slave 142 to asynchronous FIFO master 141.

Based on the descriptions of fig. 2 and fig. 3, the details of the related data/instructions of other channel types such as AW channel, W channel and B channel can be analogized, and are not repeated herein for brevity.

Thus, data transfer of individual channels between an AXI master and an AXI slave may include: data transmitted by the AXI master to the AXI slave, if distinguished by data attributes, such as AR write pointer, AR load, AW write pointer, AW load, W write pointer, W load, R read pointer, and B read pointer; and data transferred by the AXI slave to the AXI master, if distinguished by data attributes, such as an AR read pointer, an AW read pointer, a W read pointer, an R write pointer, an R payload, a B write pointer, and a B payload. As shown in fig. 4, among the plurality of channel types, dataDATA that is the same in the direction of transmission (e.g., from AXI master to AXI slave, or from AXI slave to AXI master) may be arranged together to produce a set of DATA, e.g., an AXI master may arrange together an AR write pointer, an AR payload, an AW write pointer, an AW payload, a W write pointer, a W payload, an R read pointer, and a B read pointer to produce a set of transfer DATA DATA _TX The AXI slave may arrange together the AR read pointer, the AW read pointer, the W read pointer, the R write pointer, the R payload, the B write pointer, and the B payload to produce a set of received DATA DATA _RX . Thus, the set of DATA (e.g. the set of transfer DATA DATA) _TX Or the set of received DATA DATA _RX ) At least one read pointer, at least one load, or at least one write pointer may be included. It is noted that the time point of the at least one load being transferred from the AXI master to the AXI slave is preferably earlier than the time point of the at least one write pointer being transferred from the AXI master to the AXI slave, and the time point of the at least one read pointer being transferred from the AXI master to the AXI slave is preferably earlier than the time point of the at least one load being transferred from the AXI master to the AXI slave. Thus, in the embodiment of FIG. 5, the set of transfer DATA DATA may be _TX The AR write pointer, AR payload, AW write pointer, AW payload, W write pointer, W payload, R read pointer, and B read pointer within are further ordered (e.g., transferred in order) according to payload and pointer attributes into R read pointer, B read pointer, AR payload, AW payload, W payload, AR write pointer, AW write pointer, and W write pointer, and the set of received DATA DATA can be sorted _RX The AR read pointer, AW read pointer, W read pointer, R write pointer, R load, B write pointer, and B load within are further ordered (e.g., transfer order) into AR read pointer, AW read pointer, W read pointer, R load, B load, R write pointer, and B write pointer according to load and pointer attributes.

FIG. 6 is a schematic diagram of an apparatus 60 for simulation of an electronic system, where apparatus 60 may be used as an example of apparatus 10 shown in FIG. 1, according to one embodiment of the invention. As shown in fig. 6, a first field programmable gate array FPGA _A And a second FPGA _B The external devices can be connected to each other by a connection device 600, wherein the connection device 600 can be coupled to the first FPGA _A And a transmitter 600TX coupled to a second FPGA _B And the transmitter 600TX and the receiver 600RX may be connected to each other by a cable.

FIG. 7 shows some details of the connection device 600 shown in FIG. 6, where FIG. 7 is used to transmit DATA DATA according to one embodiment of the invention _TX For example, and receive the DATA DATA _RX Only in the DATA transmission direction, the remaining details being dependent on the DATA transmitted _TX Examples of (c) and (d) are known by analogy. As shown in fig. 7, the connection device 600 may include a first register device 610, a second register device 620, and a time division multiplexing interface such as a Low Voltage Differential Signaling (LVDS) Serializer/Deserializer (SerDes) 630. In the present embodiment, the transmitter 600TX and the receiver 600RX may be embedded in the LVDS serializer/deserializer 630, but the present invention is not limited thereto. In some embodiments, at least a part (e.g. a part or all) of the first register means 610 may be arranged outside the connection means 600, e.g. at least a part (e.g. a part or all) of the first register means 610 may be a first field programmable gate array, FPGA _A But the present invention is not limited thereto. In some embodiments, at least a portion (e.g., a portion or all) of the second register means 620 may be disposed outside the connection means 600, for example, at least a portion (e.g., a portion or all) of the second register means 620 may be a second field programmable gate array FPGA _B But the present invention is not limited thereto.

In the embodiment, the first register device 610 is coupled to the first field programmable gate array FPGA _A To latch data from a first FPGA according to the first clock (e.g. master clock) _A Of the transfer DATA DATA _TX (which includes the reordered R read pointer, B read pointer, AR load, AW load, W load, AR write pointer, AW write pointer, and W write pointer described above), whereinTransmitting DATA DATA _TX May be divided into groups of local data. The LVDS serializer/deserializer 630 is coupled between the first and second register devices 610 and 620, and the LVDS serializer/deserializer 630 may transmit the sets of local data from the first register device 610 to the second register device 620 at a plurality of time points respectively according to a time division multiplexing clock such as a pixel clock pxclk, wherein the first field programmable gate array FPGA _A The master clock MASTERCLK may be transmitted to the connection device 600, and the connection device 600 may generate the pixel clock pxclk according to the master clock MASTERCLK. For example, a first field programmable gate array FPGA _A May be on the order of several megahertz (MHz), while the data transfer rate between the transmitter 600TX and the receiver 600RX (e.g., the frequency of the pixel clock pxclk) may be on the order of several gigahertz (GHz). In addition, the second register 620 is also coupled to the second field programmable gate array FPGA _B And may receive the sets of local DATA in sequence to transmit DATA DATA _TX (which includes the reordered R read pointer, B read pointer, AR load, AW load, W load, AR write pointer, AW write pointer, and W write pointer) output to a second FPGA _B 。

In accordance with the above operation, the first register device 610 can be regarded as an outbound register file (outbound register file), and the second register device 620 can be regarded as an inbound register file (inbound register file), wherein any one (e.g., each) of the first register device 610 and the second register device 620 can include a plurality of registers or a plurality of Static Random Access Memory (SRAM) cells, but the invention is not limited thereto.

In addition, each of the sets of local data can be transmitted from the first register device 610 to the second register device 620 together with the corresponding identification code. After the second register device 620 receives all of the sets of local DATA, the second register device 620 can restore the transmission DATA DATA according to the corresponding identification code _TX 。

For example, LVDS serializer/deserializerThe serializer 630 may be an LVDS source synchronous 7. Assuming that the cable data width (e.g., the number of wires) of the transmitter 600TX is 40 bits, the data width of the data pxdata received by the LVDS source synchronizer 7. In the present embodiment, the data pxdata may reserve 5 bits as the identification code tdm _ id, wherein when tdm _ id [4]When the value is 0, the DATA pxdata is regarded as invalid (invalid) DATA, and therefore, the DATA DATA is transmitted _TX Has a maximum data width of (280-5) × (2 ^ 5-1) =8525 bits. Suppose DATA _TX = { w _ write _ pointer, aw _ write _ pointer, ar _ write _ pointer, w _ payload, aw _ payload, ar _ payload, b _ read _ pointer, r _ read _ pointer }, and DATA _TX The DATA width of (1) is 5000 bits, it can be known from the calculation result of 5000/(280-5) that the LVDS serializer/deserializer 630 can finish transmitting DATA DATA by transmitting 19 times _TX In which DATA _TX The transfer is started from the lowest bit (e.g., from R _ read _ pointer), and R _ read _ pointer, B _ read _ pointer, AR _ payload, AW _ payload, W _ payload, AR _ write _ pointer, AW _ write _ pointer, and W _ write _ pointer may represent the data values of the R read pointer, B read pointer, AR load, AW load, W load, AR write pointer, AW write pointer, and W write pointer, respectively. Specifically, the master clock MASTERCLK and the pixel clock pxclk are asynchronous, wherein the first register device 610 stores the transfer DATA DATA according to the master clock MASTERCLK _TX All values at the same time when the first register device 610 has acquired the transmission DATA DATA _TX And these values have stabilized, the first register device 610 may send a signal READY to the LVDS serializer/deserializer 630. When the LVDS serializer/deserializer 630 receives the signal READY, the LVDS serializer/deserializer 630 may start to sequentially time-division multiplex each set of local DATA in accordance with the pixel clock pxclk _TX [m:n]Together with the identification code tdm _ id [4]From the transmitter 600TX to the receiver 600RX (e.g., time-division multiplexing the { tdm _ id [4 [ 0 ]],DATA _TX [m:n]From transmitter 600TX to receiver 600 RX), where m, n are positive integers and m-n =275-1, representing each set of local DATA _TX [m:n]May be 275 a. For exampleOn the first cycle of the pixel clock pxclk, pxdata = {5'd1, DATA _TX [274:0]}; in the second cycle of the pixel clock pxclk, pxdata = {5'd2, data _TX [549:275]}; by analogy, in the nineteenth cycle of the pixel clock pxclk, pxdata = {5'd19,225d'0, DATA _TX [4999:4950]}; wherein retransmission is required if no DATA value has been available (e.g. DATA is transmitted) _TX Has all transfers completed), pxdata =280'd0. Therefore, the second register device 620 can sequentially latch the data pxdata received by the pixel clock pxclk according to the pixel clock pxclk. The x' dy values shown above represent the decimal value y as a binary value of x bits for simplicity.

In accordance with the above example, the AXI slave (e.g., the second register 620 or the second field programmable gate array FPGA) _B ) It can be known how to recover the transfer DATA DATA according to the DATA pxdata in each period of the pixel clock pxclk (for example, it can be known how to arrange the DATA pxdata in each period) according to the identification code carried in the DATA pxdata in each period of the pixel clock pxclk _TX . Upon transfer of DATA DATA _TX After all the data is transmitted, the LVDS serializer/deserializer 630 can send a signal CAPTURE to the first register 610, and the first register 610 can update the data value registered therein again (for example, from the first FPGA) _A Get the next data to be transferred).

In addition, the entirety of any one of the at least one read pointer and the at least one write pointer is included in the same set of partial data among the plurality of sets of partial data. For example, any one (e.g., each) of the R read pointer, the B read pointer, the AR write pointer, the AW write pointer, and the W write pointer is transferred within one cycle of the pixel clock pxdata, so that the respective data value of any one (e.g., each) pointer is not divided into multiple cycles of pxdata for transfer. Since each pointer is not truncated at the AXI slave, data transfer errors due to FIFO status update exceptions are avoided. Furthermore, by means of the above-mentioned configuration of the transmission order (e.g. the configuration of having the transmission time point of the at least one data payload earlier than the transmission time point of the at least one write pointer), it can be ensured that the second register means (e.g. the non-synchronous FIFO therein) correctly performs the data transfer on the AXI channel.

In this embodiment, the maximum value of the number of sets of the plurality of sets of local data is determined by the number of bits of the corresponding identification code. For example, when the corresponding identification code is N bits, it indicates that DATA is transmitted _TX Can be divided into at most (2 ^ N-1) sets of local data and the (2 ^ N-1) sets of local data are sequentially transferred at (2 ^ N-1) cycles of the pixel clock pxclk. Accordingly, the time division multiplexing ratio (TDM ratio) of the LVDS serializer/deserializer 630 also corresponds to the number of bits of the identification code.

In some embodiments, in addition to the identification code, the pxdata may reserve one or more bits for the corresponding check code, so that each set of local data of the plurality of sets of local data may be transferred from the first register device to the second register device along with the corresponding check code (e.g., the pxdata transferred at each cycle of the pixel clock pxclk may include one or more bits for carrying (carry) the corresponding check code), and the corresponding check code may be used for the operations of error detection (error detection), error correction (error correction) or data retransmission (retry) of each set of local data.

In some embodiments, a pipe register (pipe register) may be inserted anywhere on the transmission path of pixel data pxdata (e.g., the path between transmitters 600TX and 600 RX) to ensure the timing of the overall system without affecting the overall functionality. In addition, the AXI bus protocol is taken as an example in the present invention for illustrative purposes only, and is not a limitation of the present invention. For example, the above data transmission mechanisms across FPGAs are all applicable to point-to-point transmission protocols such as Open Core Protocol (OCP) or Advanced Microcontroller Bus Architecture (AMBA).

Fig. 8 is a workflow of a method for data transmission control across an fpga according to an embodiment of the present invention, wherein the workflow is applicable to the apparatus 60 shown in fig. 6 and the connection device 600 therein. It should be noted that one or more steps may be added, modified or deleted in the flowchart shown in fig. 8 as long as the overall result is not hindered, and the steps do not necessarily have to be completely executed in the order shown in fig. 8.

In step S810, the apparatus 60 can latch the clock from the first FPGA by using the first register device 610 according to the first clock (e.g. master clock MASTERCLK) _A A set of DATA (e.g. transfer DATA) _TX ) Wherein the set of DATA is sorted according to load and pointer attributes and divided into sets of local DATA (e.g., DATA as described above) _TX [274:0]、DATA _TX [549:275]"\8230;" and DATA _TX [4999:4950])。

In step S820, the apparatus 60 may transmit the sets of local data from the first register device 610 to the second register device 620 at a plurality of time points (e.g., at a plurality of cycles of the pixel clock pxdata) respectively according to the time division multiplexing clock (e.g., the pixel clock pxclk) by using the time division multiplexing interface (e.g., the LVDS serializer/deserializer 630).

In step S830, the apparatus 60 can utilize the second register device 620 to sequentially receive the plurality of sets of local data to output the set of data to the second FPGA _B Wherein the second FPGA _B Operating according to a second clock different from the first clock.

To sum up, the embodiments of the present invention provide a method and related apparatus for completely isolating field programmable logic gate arrays (fpgas) of different clock domains (clock domains) by using bus flow control and master-slave mechanism by means of a source synchronous serializer/deserializer interface with high speed transmission features. In this way, the fpgas can operate at their respective optimized frequencies without being affected by the operating frequency and/or the time division multiplexing ratio of the time division multiplexing. In particular, by identifying the control of the number of code bits, the sharing of the inputs and outputs of these field programmable gate arrays can be made more flexible to accommodate the increase in data width. In addition, as long as the mechanism between the master and the slave of the source synchronous serializer/deserializer interface can be paired, the transmission control mechanism across the field programmable gate array can also be applied to data transmission of a chip-to-chip or a chip-to-field programmable gate array. Compared with the related art, the embodiment of the invention does not greatly increase the additional cost. Accordingly, the present invention can solve the problems of the related art without side effects or with less side effects.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims of the present invention should fall within the scope of the present invention.

Description of reference numerals:

10 device

100 connecting device

110,120,130,140,150 asynchronous FIFO

FPGA _A ,FPGA _B In-situ programmable logic gate array

111,141 asynchronous FIFO master

112,142 asynchronous FIFO slave

DATA _TX ,DATA _RX Data (A)

60: device

600 connecting device

600TX transmitter

600RX receiver

610,620 register device

630

Master clock

pixel clock of pxclk

Data of pxdata

READY, CAPTURE, SIGNAL

S810, S820, S830.

Claims (10)

1. A method for data transfer control across a field programmable gate array, comprising:

latching a set of data from a first field programmable gate array by a first register device according to a first clock, wherein the set of data is sorted according to load and pointer attributes and is divided into a plurality of sets of local data;

transmitting the groups of local data from the first register device to the second register device at a plurality of time points in sequence by utilizing a time division multiplexing interface according to a time division multiplexing clock; and

sequentially receiving the plurality of groups of local data by using the second register device to output the group of data to a second field programmable gate array, wherein the second field programmable gate array operates according to a second clock different from the first clock.

2. The method of claim 1, wherein the data transfer between the first field programmable gate array and the second field programmable gate array comprises a plurality of channel types, each of the plurality of channel types comprises transfer of data in two directions, and the set of data is generated by permuting data in the same direction in the plurality of channel types.

3. The method of claim 1, wherein the set of data is distinguished by attributes including at least one read pointer, at least one payload, or at least one write pointer.

4. The method of claim 3, wherein an entirety of any of the at least one read pointer and the at least one write pointer is contained in a same set of partial data of the plurality of sets of partial data.

5. A method as claimed in claim 3, wherein a point in time at which said at least one load is transferred from said first register means to said second register means is earlier than a point in time at which said at least one write pointer is transferred from said first register means to said second register means.

6. A method as claimed in claim 5, wherein a point in time at which said at least one read pointer is transferred from said first register means to said second register means is earlier than a point in time at which said at least one load is transferred from said first register means to said second register means.

7. A method as claimed in claim 1, wherein each of said plurality of sets of local data is transferred from said first register means to said second register means together with a corresponding identification code, and said second register means restores said set of data in accordance with said corresponding identification code after all of said plurality of sets of local data have been received by said second register means.

8. The method of claim 7, wherein a maximum value of the number of sets of the plurality of sets of local data is determined by the number of bits of the corresponding identification code.

9. The method as claimed in claim 1, wherein each set of local data of the plurality of sets of local data is transferred from the first register device to the second register device along with a corresponding check code, and the corresponding check code is used for error detection, error correction or data re-transmission of the each set of local data.

10. An apparatus for simulation of an electronic system, comprising:

a first field programmable gate array for simulation of a first subsystem of the electronic system, wherein the first field programmable gate array operates according to a first clock;

a second field programmable gate array for simulation of a second subsystem of the electronic system, wherein the second field programmable gate array operates according to a second clock different from the first clock;

a first register device coupled to the first field programmable gate array;

a second register device coupled to the second field programmable gate array;

a time division multiplexing interface coupled between the first register means and the second register means;

wherein the first register means latches a set of data from the first field programmable gate array in accordance with the first clock; the group of data is sorted according to load and pointer attributes and is divided into a plurality of groups of local data so as to allow the time division multiplexing interface to sequentially transmit the plurality of groups of local data from the first register device to the second register device at a plurality of time points according to a time division multiplexing clock; and the second register device receives the plurality of groups of local data in sequence to output the group of data to the second field programmable gate array.

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