KR101928942B1 - Apparatus and method for processing digital video data having verification module - Google Patents

Abstract

The present invention relates to a digital image processing apparatus capable of performing transmission and reception of a digital image according to an RS485 communication method, and more particularly, to a digital image processing apparatus capable of performing transmission and reception of a digital image according to an RS485 communication method, A digital transmission processing module including a ground station module for converting into a protocol; A data integration processor for integrating the digital video message received from the digital transmission processing module; And a verification module for generating a digital image simulation message at predetermined intervals and providing the generated digital image simulation message to the digital transmission processing module to perform reliability verification of the digital image simulation message transmitted and received through the digital transmission processing module to check the performance of the digital transmission processing module The transmission processing of the digital image is performed using the RS485 communication with high communication speed, and the performance inspection of the digital transmission processing module can be performed through the verification module.

Description

TECHNICAL FIELD [0001] The present invention relates to a digital image processing apparatus having a verification module,

The present invention relates to an apparatus for transmitting and receiving digital images according to an RS485 communication method, and more particularly, to a digital image processing apparatus having a verification module.

Generally, after configuring a plurality of devices, the devices can be connected to one centralized control system. For this purpose, a network configuration for connecting a plurality of devices is a prerequisite. One of the technologies that make up the network is to use serial communication technology, the most commonly used being RS232. RS232 serial communication is a one-to-one communication method, in which communication lines are established between two systems to communicate, and communication is possible only between the two systems, and is mainly used to connect PCs and peripheral devices.

However, RS232 serial communication has a disadvantage in that it is impossible to exchange data with a newly added system if there is no extra RS232 port in the control system or if a communication board can not be additionally installed. Therefore, RS485 communication was developed as another communication protocol that can overcome the disadvantages of RS232 serial communication.

The RS485 communication is a communication method that performs one-to-N communication by allowing a plurality of ports to be simultaneously connected to one bus by applying a bus system. In this RS485 communication method, the wiring structure uses a daisy chain method. The daisy chain is a method of connecting a central server and a peripheral device in series, and then connecting the peripheral device to a plurality of other devices in series, thereby forming a network between the central server and peripheral devices.

However, the daisy-chain method is advantageous in that it can reduce the length of the cable when each device is connected because the current loss is small and the influence of noise is small. However, if one or more devices are not operated normally, The disadvantage is that not all devices after a difficult and anomalous device may fail. In addition, it is difficult to find out if the cable is broken or broken in the middle.

Accordingly, it is an object of the present invention to provide a digital image processing apparatus capable of transmitting and receiving digital image data according to the RS485 communication standard and the UART protocol.

It is another object of the present invention to provide a digital image processing apparatus capable of performing a performance check of a digital image transmission processing module by simulating a message transmitted and received through a digital image transmission processing module.

In order to achieve the above object, a digital image processing apparatus according to an embodiment of the present invention includes a loading module for processing data transmitted in an RS485 communication standard on a per message basis and converting the received digital image message into a UART protocol A digital transmission processing module including a ground station module; A data integration processor for integrating the digital video message received from the digital transmission processing module; And a verification module for generating a digital image simulation message at predetermined intervals and providing the generated digital image simulation message to the digital transmission processing module to perform reliability verification of the digital image simulation message transmitted and received through the digital transmission processing module to check the performance of the digital transmission processing module .

According to an embodiment of the present invention, the mount module includes a 1485-line driver for receiving data transmitted in the RS485 communication standard; A first FPGA for detecting valid data in the data received through the 1485 line driver and storing the digital video message in a buffer; And a first FIFO in which a digital video message stored in a buffer of the first FPGA is written in units of one word and is transmitted to a data integration processor.

According to an embodiment of the present invention, the first FPGA includes a first logic processing unit for detecting the start of a message from data of the RS485 communication standard, storing one digital video message in a buffer, and generating an interrupt signal; And a first NIOS-II processor for performing validation of a digital video message stored in the buffer when the interrupt signal is received from the first logic processor and writing an ACK message to the first FIFO and outputting an ACK message to the verification module, 1 logic processor may generate an interrupt signal to the first NIOS-II processor whenever a digital video message is stored in the buffer.

According to an embodiment of the present invention, when the interrupt signal is received, the first NIOS-II processor reads the digital video message stored in the buffer of the first logic processor to validate the start of the message, the message length, If the result is normal, the message is written into the FIFO on a word-by-word basis, and the ACK message is transmitted to the first logic processing unit. The ACK message is output to the log module in a serial manner in accordance with the RS 485 communication standard in the logic processing unit .

According to an embodiment of the present invention, the overhead module comprises: a second FIFO storing a digital video message received from the data integration processor; A second FPGA for performing validation of a digital video message stored in the second FIFO to store each message in a buffer and convert the message into a UART protocol; And a 2485-line driver for transmitting the digital video message converted by the UART protocol to the verification module in accordance with the RS485 communication standard.

According to an embodiment of the present invention, the second FPGA may include a second NIOS-II processor for reading a digital image message from a second FIFO to validate a message start item and storing one message at a time; And a second logic processor for converting the message into serial data of the UART protocol and outputting the serial data to the 2485-line driver when each digital video message is stored in the buffer by the second NIOS-II processor.

According to an embodiment of the present invention, the verification module includes a 3485-line driver and a third FPGA, the third FPGA includes a third NIOS-II processor for constructing a digital image simulation message according to an interrupt signal; And outputting an interrupt signal to the third NIOS-II processing unit at a predetermined cycle, converting the digital image simulation message configured in the third NIOS-II processing unit into a UART protocol, and outputting the converted signal to the digital transmission processing module according to the RS485 communication standard And a logic processing unit.

According to the embodiment of the present invention, the third NIOS-II processor increments the frame number for each digital image simulation message and increases the increment value from 1 to 65535 (16 bits) in the image data area by 1, Messages can be configured.

According to an embodiment of the present invention, the third logic processing unit receives the ACK message for the digital image simulation message or the digital image simulation message from the digital transmission processing module to the data integration processor, The third NIOS-II processor may store the one or more ACK messages or the received digital image simulation message in the buffer of the third logic processor, have.

According to an embodiment of the present invention, the third NIOS-II processor may include (a) a fixed value SOM (Start of Message), a message length, a No. of Total MSG check, (C) checking whether the digital image simulation message is received at a rate of 964 per second, thereby verifying the validity of the digital image simulation message.

According to an embodiment of the present invention, the third NIOS-II processor outputs an error message through the JTAG UART port when an error is detected as a result of the validation of the items (a) and (b) If the receiving period of the video simulated message is 964 per second, the validity verification can be performed by outputting the toggle signal.

According to the embodiment of the present invention, digital image data is processed in units of messages according to the RS485 communication standard and the UART protocol through the digital image transmission processing module of the present invention, a simulated message is generated through the digital image verification module It is possible to perform the self-performance check of the digital image transmission processing module by performing the reliability verification of the simulated message transmitted / received through the digital image transmission processing module.

1 is a configuration diagram of a digital image processing apparatus according to an embodiment of the present invention;
FIG. 2 is a hardware configuration diagram of a mounting unit module constituting the digital transmission processing module 1000 according to the present invention. FIG.
3 is a diagram illustrating a data processing structure in an FPGA constituting a mounting unit module in the present invention.
4 is a hardware block diagram of a ground station module constituting a digital transmission processing module according to the present invention;
5 is a diagram illustrating a data processing structure in an FPGA constituting a land top module according to the present invention.
6 is a diagram illustrating a data processing structure in an FPGA for generating a digital image simulation message in the present invention.
7 is a data processing structure for performing reliability verification of a digital image simulation message transmitted and received through a digital image transmission processing module in a verification module.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which like or similar elements are denoted by the same or similar reference numerals, and redundant description thereof will be omitted. The suffix "module" and " part "for the components used in the following description are given or mixed in consideration of ease of specification, and do not have their own meaning or role.

In the following description of the embodiments of the present invention, a detailed description of related arts will be omitted when it is determined that the gist of the embodiments disclosed herein may be blurred. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. , ≪ / RTI > equivalents, and alternatives.

Recently, as demands for real-time wireless transmission of lossless digital images have been developed, there is a need for a device capable of real-time transmission and processing of large-capacity digital images. Therefore, the present invention proposes a design method of a digital image transmission processing module and a verification module for performance verification using an RS485 communication method having a communication speed of 10 Mbps.

The communication standard applied to the digital video transmission processing module according to the present invention is RS485, the communication speed is 10 Mbps, the communication protocol is UART (Universal Asynchronous Receiver Transmitter), and LSB (Least Significant Bit) . Also, the digital image transmission processing module according to the present invention can process 3,794,304 bit / s digital image data and process 964 messages at a message processing period of 1.037 msec.

1 is a configuration diagram of a digital image processing apparatus according to an embodiment of the present invention.

Referring to FIG. 1, a digital image processing apparatus according to an exemplary embodiment of the present invention includes a digital transmission processing module 1000, a data integration processor 2000, and a verification module 3000.

The digital transmission processing module 1000 transmits and receives digital image data according to the RS485 communication standard. The digital transmission processing module 1000 includes a loading module 100 for processing data transmitted in the RS485 communication standard on a per message basis and transmitting the data to the data integration processor 2000 And a ground station module 200 for processing the digital video message received from the data integration processor 2000 and transmitting the processed digital video message to the RS485 communication standard.

The data integration processor 2000 integrates and transmits the digital video messages transmitted from the plurality of digital transmission processing modules 1000, separates the wirelessly received integrated digital video messages, and transmits them to the respective digital transmission processing modules 1000 .

The verification module 3000 is a part for performing reliability verification of the digital transmission processing module 1000. The verification module 3000 generates a digital image simulation message and outputs the generated digital image simulation message to the digital transmission processing module 1000, And performs reliability verification of the message transmitted / received through the network.

2 is a hardware configuration diagram of a mounting module 100 constituting the digital transmission processing module 1000 according to the present invention.

2, the mounting module 100 is mainly divided into a 485-line driver 110, an FPGA 120, and a FIFO 130. As shown in FIG. The mount module 110 receives the data transmitted in the RS485 communication standard from the partner device (not shown) or the verification module 3000 through the 485 line driver 110 and transmits the 492 byte digital video message (1 message), and performs validity checking. When the digital video message is normal, the digital video message is transmitted to the data integration processor 200 through the FIFO 130, and the ACK And transmits the data to the partner device or the verification module 3000.

FIG. 3 shows a data processing structure in the FPGA 120 of the mounting module 100. FIG.

Referring to FIG. 3, the data processing in the FPGA 120 is divided into a logic processing unit 10 and a NIOS-II processing unit 11.

When the data satisfying the RS485 communication standard and the UART protocol is received, the logic processor 10 removes noise through glitch filtering and then transmits the message using the 80 MHz clock signal output from the phase locked loop (PLL) II processor 11 every time a valid data stream of 492 bytes, that is, one message, is stored in the buffer, the start of message (SOM) is detected and the valid data stream is stored in a buffer (not shown) To generate an interrupt signal. When the ACK is inputted from the NIOS-II processor 11, the logic processor 10 outputs an ACK message, which is a serial data, in synchronization with a clock signal of 80 MHz, which is the standard promised by the protocol processing logic.

When the interrupt signal is received from the logic processing unit 10, the NIOS-II processing unit 11 reads the message stored in the buffer of the logic processing unit 10 and performs validation. At this time, the validity check is performed on the SOM, the message length, and the No. of Total MSG items, and if the result is OK, the received message (492 Bytes) writes to the FIFO 103 in units of 16 bits and transmits an ACK message to the logic processing unit 10. [

FIG. 4 is a hardware configuration diagram of the ground station module 200 constituting the digital transmission processing module 1000 according to the present invention, and FIG. 5 shows a data processing structure in the FPGA 120 of the ground station module 200.

Referring to FIG. 4, the hardware configuration of the overhead module 200 is roughly divided into a 485-line driver 210, an FPGA 220, and a FIFO 230. The FPGA 220 processes the digital video message received from the integrated data processor 2000 through the FIFO 230 and transmits the digital video message to the partner device or the verification module 3000 through the RS485 communication standard through the 485 line driver 210 .

The data processing structure in the FPGA 220 is roughly divided into a logic processing unit 20 and a NIOS-II processing unit 21, as shown in FIG. The NIOS-II processor 21 checks the status of the FIFO 230 and if the FIFO 230 is not in the EMPTY state, it reads the stored data to validate the SOM item, (21). This validation is repeated in a folding fashion.

When the message is stored in the buffer, the logic processor 21 converts the stored message into UART protocol data (serial data), and outputs the UART protocol data to the 485 line driver 210 in synchronization with the 10 MHz clock signal.

As described above, the digital transmission processing module 1000 validates the data of the RS485 communication standard with the data integration processor 2000 and performs transmission processing on a per-message basis, thereby realizing high-capacity digital image data in real time Transmission processing can be performed.

In the present invention, the verification module 3000 is designed for reliability verification of the digital transmission processing module 1000 and can perform a digital image simulation message generation function and a received simulation message verification function. That is, the verification module 3000 generates a digital image simulation message and outputs the digital image simulation message to the data integration processor 2000 through the digital transmission processing module 1000, and then transmits the digital image simulation message from the data integration processor 2000 to the digital transmission processing module 1000 And performs reliability verification of the received digital image simulation message (data).

The verification module 3000 according to the embodiment of the present invention mainly comprises a 485-line driver and an FPGA. 6 shows a data processing structure in an FPGA for generating a digital image simulation message.

Referring to FIG. 6, data processing in an FPGA for generating a digital simulated message is largely divided into a logic processing unit 300 and a NIOS-II processing unit 400. The logic processor 300 generates an interrupt signal at a period of 1.037 ms (964 messages per second), and the NIOS-II processor 400 forms a digital image simulation message according to the interrupt signal and outputs it to the buffer of the logic processor 300 . The digital image simulation message includes a frame number item for each message, and an image data value is incremented by 1 from 1 to 65535 (16 bits). The logic processor 300 converts the digital image simulation message stored in the buffer into the UART protocol and then transmits the serialized image to the digital transmission processing module 1000 according to the RS485 communication standard.

The logic processor 300 detects a message start (SOM) of the ACK data received from the digital transmission processing module 1000 and stores the SOM in the reception buffer. When one message is stored in the buffer, the logic processor 300 outputs an interrupt signal to the NIOS- II processor 400 proceeds ACK validity checking.

7 shows a data processing structure for performing reliability verification of a digital image simulation message transmitted and received through a digital image transmission processing module in a verification module.

Referring to FIG. 7, reliability verification of a digital image simulation message transmitted and received through the digital image transmission processing module 1000 is divided into a logic processor 300 and a NIOS-II processor 400. The logic processor 300 performs a CLICK filtering on a digital image simulation message received and separated from the digital image transmission processing module 1000 and then synchronizes the signal with a clock signal of 80 MHz and detects a message start (SOM) Store the data in the buffer. The logic processor 300 generates an interrupt signal to be read by the NIOS-II processor 400 and the NIOS-II processor 400 receives the interrupt signal from the logic processor 300 according to the interrupt signal. The simulated video message stored in the buffer is read and the following three items are checked.

① Fixed value SOM (Start of Message), message length, number of total message (No. of Total MSG)

② Check the continuity of the increment value simulated in the data (image data) item of the simulated video message and check the continuity of the frame number

③ Checking 964 messages received / sec

If an error occurs in the items ① and ②, the NIOS-II processing unit 400 outputs an error message through the JTAG UART port, and 964 messages per second of the item ③ are received, And outputs a Toggle signal to verify data reliability.

As described above, according to the present invention, digital image data is transmitted and processed in units of messages according to the RS485 communication standard and the UART protocol through the digital image transmission processing module of the present invention, a simulated message is generated through the digital image verification module, The performance verification of the digital image transmission processing module can be performed by performing the reliability verification of the simulated message transmitted and received through the processing module.

The digital image processing apparatus having the verification module according to the present invention is not limited to the above-described embodiments, but the embodiments may be embodied in other specific forms without changing their technical ideas or essential features It can be understood that Therefore, it should be understood that the above-described embodiments are to be considered in all respects as illustrative and not restrictive.

10, 21, 300: logic processor 11, 20, 400: NIOS-II processor
100: mount module 200: ground module
110, 210: 485 line driver 120, 220: FPGA
130, 230: FIFO
1000: digital image transmission processing module 2000: data integration processor
3000: verification module

Claims (11)

A digital transmission processing module including a mounting module for processing data transmitted in the RS485 communication standard in units of messages and a ground module for converting a received digital video message into a UART protocol;
A data integration processor for integrating the digital video message received from the digital transmission processing module; And
And a verification module for generating a digital image simulation message at predetermined intervals and providing the generated digital image simulation message to the digital transmission processing module to perform reliability verification of the digital image simulation message transmitted and received through the digital transmission processing module to check the performance of the digital transmission processing module and,
The verification module includes a 3485-line driver and a third FPGA,
The third FPGA
A third NIOS-II processor for constructing a digital image simulation message according to an interrupt signal; And
A third logic unit for generating an interrupt signal in a predetermined cycle and outputting the generated interrupt signal to the third NIOS-II processor, converting the digital image simulation message configured in the third NIOS-II processor into a UART protocol, and outputting the signal to the digital transmission processing module according to the RS485 communication standard And a processor for processing the digital image. 2. The apparatus of claim 1, wherein the mount module
A 1485 line driver for receiving data transmitted in the RS485 communication standard;
A first FPGA for detecting valid data in data received via a line driver and storing a digital video message in a buffer; And
And a first FIFO, wherein the digital video message stored in the buffer of the first FPGA is written in units of one word and transferred to a data integration processor. 3. The apparatus of claim 2, wherein the first FPGA
A first logic processing unit for detecting the start of a message from the data of the RS485 communication standard, storing one digital video message in a buffer and generating an interrupt signal; And
And a first NIOS-II processor for validating a digital video message stored in the buffer when the interrupt signal is received from the logic processor, for writing to the first FIFO and for outputting an ACK message to the verification module,
The first logic processing unit
And generates an interrupt signal to the first NIOS-II processor whenever a digital video message is stored in the buffer. 4. The apparatus of claim 3, wherein the first NIOS-II processor
(a) receiving an interrupt signal, reading the digital video message stored in the buffer of the first logic processing unit,
(b) performs validation on the start of the message, the message length and the total number of messages item,
(c) if the result is normal, write the message to the first FIFO in units of one word and transmit the ACK message to the first logic processor,
Wherein the ACK message is output to the verification module in a serial manner in accordance with the RS485 communication standard in the logic processing unit. 2. The apparatus of claim 1,
A second FIFO storing a digital video message received from the data integration processor;
A second FPGA for performing validation of a digital video message stored in the second FIFO to store each message in a buffer and convert the message into a UART protocol; And
And a 2485-line driver for transmitting the digital video message converted by the UART protocol to the verification module in the RS485 communication standard. 6. The apparatus of claim 5, wherein the second FPGA
A second NIOS-II processor for reading the digital image message from the second FIFO to validate the message start item and storing one message at a time; And
And a second logic processor for converting the message into serial data of the UART protocol and outputting the serial data to the 2485-line driver when each digital video message is stored in the buffer by the second NIOS-II processor. . delete The apparatus according to claim 1, wherein the third NIOS-II processor
Wherein a digital image simulation message is formed by increasing a frame number for each digital image simulation message and including an increment value increasing by 1 from 1 to 65535 (16 Bits) in the image data area. The apparatus of claim 1, wherein the third logic processing unit
An ACK message for the digital image simulation message or the digital image simulation message is transmitted from the digital transmission processing module to the data integration processor and then the digital image simulation data received by the digital transmission processing module is stored in a buffer in units of a message,
Wherein the third NIOS-II processor performs validity verification of the corresponding message when one ACK message or a received digital image simulation message is stored in the buffer of the third logic processor. 10. The apparatus according to claim 9, wherein the third NIOS-II processor
(a) fixed value SOM (Start of Message), message length, number of total messages (No. of Total MSG)
(b) checking the continuity of the increment value of the digital image simulation message and the frame number, and
(c) a validity check of the digital image simulation message is performed by performing a check as to whether the reception period of the digital image simulation message is 964 per second. 11. The apparatus according to claim 10, wherein the third NIOS-II processor
If an error occurs as a result of the validation of items (a) and (b), an error message is output through the JTAG UART port, and if the period of receiving the digital image simulation message is 964, And outputs the digital image data to the digital image processing device.

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