JP7339548B2 - LAYOUT DEVICE, LAYOUT METHOD AND LAYOUT PROGRAM - Google Patents

Description

The present invention relates to a layout device, layout method, and layout program.

Algorithms for detailed wiring in conventional automatic wiring tools basically perform wiring processing by repeatedly connecting connection points, which are intersections of wires in a wiring route, and correcting errors. Therefore, in long-distance connections, there is a tendency for detour wiring to be created due to jogging that causes a step in wiring and switching of wiring layers in a disorderly manner. In general, custom layouts have a high percentage of critical paths, so an increase in wiring load due to detour wiring often leads to fatal problems. Moreover, in the custom layout, since hierarchical design is performed for each functional module, there has been a problem that the reserved wiring route reserved for the upper layer module is excessively consumed.

Patent document 1 discloses assignment of through wiring positions to nets indicating wiring between elements, which requires through wiring, which is wiring that needs to straddle a plurality of cell rows in global wiring, and trunk wiring. Assignment to the channel, which is the area where the wiring for connecting the input and output parts of the is arranged, determines the general wiring route, and then sequentially wiring for each channel by the channel wiring method based on the result A wiring method is disclosed in which processing is performed to determine a detailed wiring route between cells and to connect the cells. In the invention of Patent Document 1, when determining detailed wiring routes between cells and connecting them, the allocation of through wiring positions and the allocation of trunk lines to channels are not sequentially processed for each net, but through wiring is performed. For the required nets, the trunks (horizontal wiring parallel to the cell row) required for each net are extracted, and the set of trunks is defined as the allowable range of the allocation channel for preventing detours in wiring and Considering the presence or absence of through-wiring possible locations in the cell as conditions, a combination that realizes placement and filling with the minimum number of tracks is obtained. After that, the wiring positions are determined all at once by allocating the trunks to channels according to the combination of placement and filling of the trunks.

The invention of Cited Document 1 is based on channel wiring processing by the conventional channel wiring method, and assigns through wiring positions to nets requiring through wiring in general wiring and assignment of trunk lines to channels to the minimum track. It is collectively decided based on the layout combination of trunk lines that can be realized by the number. Therefore, it is possible to always allocate a trunk line to a nearly optimal channel and to allocate a through-wiring position determined depending thereon. As a result, it is possible to effectively compress the wiring area by taking advantage of the channel wiring method that can achieve a wiring rate of almost 100%.

Further, in Japanese Patent Laid-Open No. 2002-200013, for nets that require through wiring in the general wiring, the through wiring positions are assigned and the assignments of trunk lines to channels are determined, and the general wiring route is determined. Based on the channel wiring method, a wiring method is disclosed in which wiring is sequentially performed for each channel, and detailed wiring paths between cells are determined and connected. In the invention of Patent Document 2, when performing the above wiring, instead of sequentially processing the allocation of through wiring positions and the allocation of trunk lines to channels for each net, all nets that require through wiring are processed for each net. Extract the trunks (horizontal wiring parallel to the cell row) required for each cell, and determine the allowable range of allocated channels to prevent detours in the wiring of the set of trunks, and whether or not there is a place where through wiring is possible in the cell In consideration of such conditions as conditions, allocation channels are obtained based on trunks with a narrow channel allocation range, combinations of placement and filling to tracks from the trunks and channels are obtained, and wiring positions are determined.

According to the method of Patent Document 2, since the assignment of through-wiring positions and the assignment of trunk channels to nets requiring through-wiring in the general wiring are processed based on trunks with narrow channel allocations for trunks, other trunks are used. Processing is performed starting from those that are least likely to be placed on the same channel, and many combinations are performed on a limited number of channels. This has the effect of enabling allocation.

Furthermore, Patent Document 3 discloses a semiconductor integrated circuit device that reinforces power supply by using an empty area where no element is formed as a wiring area, and is suitable for automatic design of pattern layout.

In the invention of Cited Document 3, empty wiring tracks on unused cells and logic cells included in one cell row and space regions between cell rows are searched, and metal wiring is formed in these regions to reinforce the power supply. It reinforces the supply of power to the logic cells that require it.

JP-A-63-278249 JP-A-64-81249 JP-A-9-199601

As described above, although there have been attempts to effectively utilize the wiring area without wasting it in the past, there has been no appropriate wiring design from the viewpoint of suppressing an increase in the wiring load. The present invention has been made in view of the current state of the conventional layout technology, and its object is to provide a layout device, a layout method, and a layout program capable of suppressing an increase in wiring load and performing wiring appropriately. to provide.

A layout device according to an embodiment of the present invention is a layout device that arranges one or more elements in each layer of a plurality of layers and performs design for providing necessary wiring between each element. a priority determination means for predicting the magnitude of the resistance value of the wiring that occurs when elements are arranged in each row, and determining the priority of the row for designing the wiring based on the prediction result; and the priority of the determined row. track wiring means for sequentially providing wiring of connection target nodes to wiring tracks for each ROW.

1 is a block diagram of a computer system that implements a layout device according to an embodiment of the present invention; FIG. 4 is a diagram showing an example of programs and data stored in an external storage device 23 in this embodiment of the present invention; FIG. 4 is a flow chart showing the operation according to the embodiment of the present invention; FIG. 10 is a diagram showing each ROW and wiring generated in step S13 in the embodiment according to the present invention, and is a plan view of a wiring surface on which a plurality of ROWs are arranged; FIG. 4 is a diagram showing elements arranged in each row and row priority information obtained for each row in the embodiment according to the present invention, and is a plan view of a wiring surface on which a plurality of rows are arranged; A diagram for explaining pins connected to elements on layers in the longitudinal direction of the ROW and pins connected to elements on layers perpendicular to the longitudinal direction of the ROW in the embodiment according to the present invention. FIG. 10 is a diagram showing an example of weighting when there are ROWs to be weighted for obtaining ROW priority order information, and is a plan view of a wiring surface on which a plurality of ROWs are arranged; FIG. 4 is a diagram for explaining two priority orders used when wiring to a plurality of wiring tracks in the embodiment according to the present invention; FIG. 4 is a diagram showing an example of providing wiring using a left edge algorithm; FIG. 11 is a plan view of a wiring surface showing a process of searching for tracks that can be wired in the order of priority wiring tracks set in advance in ROW3; FIG. 9 is a diagram showing an example in which branch lines are arranged for wiring B arranged in ROW 3 as shown in FIG. 8, and is a plan view of a wiring surface on which a plurality of ROWs are arranged; FIG. 10 is a plan view of a wiring surface on which a plurality of ROWs are arranged, showing an example in which wirings of power supply lines are arranged so as to sandwich wirings other than the power supply lines by wirings of power supply lines;

A layout device, a layout method, and a layout program according to embodiments of the present invention will be described below with reference to the accompanying drawings. In each figure, the same components are denoted by the same reference numerals, and overlapping descriptions are omitted. The layout device according to the present embodiment is a layout device that performs design by arranging one or more elements in each of a plurality of layers and providing necessary wiring between the elements. In this embodiment, the target device for layout is a semiconductor device, but it may be an electronic device other than a semiconductor device made of a multi-layer substrate.

FIG. 1 is a block diagram of a computer system that implements a layout device 1 according to an embodiment. This computer system can be composed of a personal computer, workstation, or other computer system. In this computer system, the CPU 10 controls each unit based on programs and data stored in the main memory 11 or read into the main memory 11, and executes necessary processing, thereby performing the present embodiment and other embodiments. It operates as the layout device 1 .

An external storage interface 13 , an input interface 14 , a display interface 15 and a communication interface 16 are connected to the CPU 10 via a bus 12 . The external storage interface 13 is connected to an external storage device 23 in which programs such as a layout program and necessary data are stored. Connected to the input interface 14 are an input device 24 such as a keyboard for inputting commands and data, and a mouse 22 as a pointing device.

A display device 25 having a display screen such as an LED or LCD is connected to the display interface 15 . The communication interface 16 is connected to ports 26-1, 26-2, . . . , 26-m for obtaining necessary information from the outside. This computer system may have other configurations, and the configuration of FIG. 1 is only an example. The configuration of this computer system is not limited to the first embodiment, and is also used in the configurations of the second and subsequent embodiments and modifications thereof.

FIG. 2 shows programs and data stored in the external storage device 23 in this embodiment. That is, the external storage device 23 stores a layout program for causing the CPU 10 to function as a priority determination means 231 and a track wiring means 232, and also stores a net list 233, an element layout information file 234, and a node list 235. It is

The priority order determining means 231 determines the element layout information (stored in the netlist 233, the element layout information file 234, and the node list 235) on the element layout. The magnitude of the resistance value of the wiring is predicted, and the priority of the ROW for designing the wiring is determined based on the prediction result. Each ROW is provided with a plurality of wiring tracks. In this embodiment, a ROW to which wiring should be preferentially performed is determined among the plurality of ROWs, and which of the plurality of wiring tracks in the determined ROW is to be wired is determined. have decided. The track wiring means 232 arranges the wiring of the connection target node for the wiring track for each ROW according to the priority order of the ROWs determined by the priority determination means 231 . As described above, one ROW is determined, a wiring track to be wired in that ROW is determined, and wiring is performed at nodes (connection target nodes) between elements to be wired in that wiring track.

The net list 233 describes signal names (net names), circuit numbers of elements (components) connected to the nets, terminal numbers, and the like. The element layout information file 234 describes the circuit numbers of the elements used in the device, the arrangement coordinates of the elements, and the like. The node list 235 describes the signal name of the signal sent to the node, the length of the wiring, the coordinates of the start point and the end point, and the like. The element layout information file 234 and node list 235 may be combined into one file.

FIG. 3 is a flow chart showing the operations of the priority determination means 231 and the track wiring means 232 of this embodiment. That is, as described above, since the external storage device 23 stores a layout program for causing the CPU 10 to function as the priority determining means 231 and the track wiring means 232, when the above program is started, the CPU 10 executes the layout shown in FIG. The operations shown in the flowchart are performed. The operation will be described below according to the flowchart shown in FIG. First, a list of connection target nodes to be connected in this process is extracted from the node list 235 (S11).

Steps S13 and S14 sandwiched between the repetition processing mark K11 and the repetition processing mark K12 are sequentially repeated for each of the connection target nodes of the number extracted in the above step S11.

The processes of steps S13 and S14 are processes performed by the priority determining means 231. Elements are assigned to each ROW based on the number of elements arranged in each ROW, the number of connection points of each ROW, and the unit resistance value of the node. This is the process of predicting the magnitude of the resistance value of the wiring caused by the wiring when arranged, and determining the priority of the ROW. For example, when elements are arranged in a row, the number of wires increases when the number of elements is large. It becomes a parameter when predicting the magnitude of the value. Moreover, since it is predicted that the number of wirings between the connection points increases as the number of connection points of the ROW increases, the parameter for predicting the magnitude of the resistance value of the wiring caused by the wiring when arranging the elements in the ROW is becomes. Although the unit resistance value of the node also depends on the length of the wiring, it is a parameter for predicting the magnitude of the resistance value of the wiring caused by the wiring when the elements are arranged in the ROW. Using all of the above three parameters, it is possible to simply obtain the result of an operation such as addition or multiplication of the three parameters for each ROW, compare the results, and obtain the order of priority. If it is predicted that the importance of the above three parameters will change depending on the wiring work, the calculation can be performed after multiplying each parameter with a weight. Also, any two of the three parameters can be used, or any one of the three parameters can be used. In addition, regarding the use of parameters, for example, regarding the unit resistance value of a node, the result obtained by multiplying the lengths of all nodes in the row is obtained for each row, and the result is compared to obtain the priority. can. In this embodiment, the number of connection points of each ROW is used as a parameter, and the usage of this parameter is as follows. That is, in step S13, using the information of the element layout information file 234 and the node list 235, the maximum value (Max) and the minimum value (Min) of the arrangement coordinates of the elements connected to the node are detected, and these maximum and Wiring corresponding to the coordinates of the minimum is generated (S13).

In the present embodiment, numerical processing such as wiring length comparison and element position comparison may be performed. Here, the processing will be described with reference to the drawings. FIG. 4 is a diagram showing each ROW (0 to 4) and wiring generated in step S13, and is a plan view of a wiring surface on which a plurality of ROWs are arranged. Here, as an example, it is assumed that the number of ROWs is five, and ROW0, ROW1, .

ROW0 has no elements, element C1 is arranged in ROW1, elements C2 to C4 are arranged in ROW2, elements C5 to C9 are arranged in ROW3, and elements C10 to C13 are arranged in ROW4. ing. Here, assuming that the coordinates are larger on the right side, the maximum value (Max) of the arrangement coordinates of the elements is the coordinates of the element C4, and the minimum value (Min) of the coordinates of the elements is the coordinates of the element C1. The wiring generated in S13 has a length like the wiring B shown below ROW0.

Among the ROWs, the ROWs having the most connection points with the wiring B are detected in order, and the ROWs with the most connection points are associated with the connection target nodes and stored as ROW priority order information (S14). In this embodiment, the connection point of one element is calculated as "1". FIG. 5 is a diagram showing elements arranged in each row and row priority information obtained for each row in the embodiment according to the present invention, and is a plan view of a wiring surface on which a plurality of rows are arranged. be. ROW priority information matches the number of elements arranged in a ROW, and its values are ROW0=0, ROW1=1, ROW2=3, ROW3=5, ROW4, as shown on the right side of each ROW in FIG. =4. As a result, the priority order is ROW3>ROW4>ROW2>ROW1>ROW0, which is stored as ROW priority information. In this embodiment, it is assumed that the resistance of the wiring to the layer in the direction perpendicular to the longitudinal direction of the ROW indicated by the arrow Y in the drawing is greater than the resistance of the wiring to the layer in the longitudinal direction of the ROW indicated by the arrow X in the drawing, Since it is connected to the element provided in the ROM, it is assumed that the wiring is made to the layers in the longitudinal direction of the ROW.

In the present embodiment, the number of connection points of each ROW is used to determine the ROW priority order information. ROW priority information may also be obtained. In addition, in the case of this embodiment, the resistance of the wiring to the layer in the direction orthogonal to the longitudinal direction of the ROW indicated by the arrow Y in the drawing is greater than the resistance of the wiring to the layer in the longitudinal direction of the ROW indicated by the arrow X in the drawing. The number of pins connected to the elements of the layers in the longitudinal direction of the ROW may be added with a greater weight than the number of pins connected to the elements of the layers perpendicular to the longitudinal direction of the ROW. FIG. 5A is a diagram for explaining pins connected to elements on layers in the longitudinal direction of the ROW and pins connected to elements on layers perpendicular to the longitudinal direction of the ROW, and is a perspective view showing wiring in the ROW. As shown in FIG. 5A, the wiring H1 in the ROW extends in the longitudinal direction of the ROW indicated by the arrow X, and the elements DX1, DX2, . Elements DY1, DY2, DY3, DY4, . Elements DX1, DX2, DX3, . . . and elements DY1, DY2, DY3, DY4, . Wiring is between these pins. Due to the material used for the wiring, the resistance of the wiring to the layer in the direction orthogonal to the longitudinal direction of the ROW indicated by the arrow Y in the figure is greater than the resistance of the wiring to the layer in the longitudinal direction of the ROW indicated by the arrow in the figure. The number of pins connected to the elements DX1, DX2, . It will carry a lot of weight.
FIG. 6 is a diagram showing an example of weighting when there are ROWs to be weighted for obtaining ROW priority order information, and is a plan view of a wiring surface on which a plurality of ROWs are arranged. In FIG. 6, when an element C00 having a pin connected in the longitudinal direction of the ROW is arranged for ROW2, in addition to the usual number of elements of 3, addition by the element C00 with a weight of "5" is performed. , indicates that the total point is "8". Assuming that elements having pins connected in the longitudinal direction of the ROW are not weighted, the point of ROW2 is "3", and the resistance value of the wiring caused by the wiring when the elements are arranged in the ROW. It becomes impossible to properly predict the size of Furthermore, the unit resistance value of the node may be described in the node list 235, and the ROW with the smaller value may be prioritized by multiplying the distance from the connected cell.

By obtaining the ROW priority order information through the above process, it is possible to predict the magnitude of the wiring resistance value that will occur when elements are arranged in each ROW, which is each layer, based on the element arrangement information, and to provide wiring based on the prediction results. Since the design is being carried out, priority is given to the ROW with the light wiring load, which is expected to lead to a reduction in the wiring load. When the above process is completed for all connection target nodes, the process proceeds to step S15 in FIG. In step S15, it is detected whether or not the ROW to be processed is congested by an obstacle for each ROM of priority order, and if the ROW is not congested by an obstacle, wiring is provided using a left edge algorithm, When the ROW is congested with obstacles, the wiring of the node with the long wiring length is preferentially provided. Here, an obstacle refers to an element or other wiring that obstructs wiring.

In this step S15, in step S16 sandwiched between the repeat processing mark K13 and the repeat processing mark K14, processing is intended to minimize the number of consumed tracks by, for example, increasing empty tracks (unwired tracks). Alternatively, avoiding detour wiring that increases the load and increasing the probability of placing low-priority (short) wiring in other ROWs so that the wiring is suitable.

In the process of step S15, the obstacle may be an element that is not connected to the wiring. In addition, it can be defined that the area is crowded when the occupation ratio of obstacles to the area of the ROM is, for example, 40% or more.
The following process describes wiring to multiple wiring tracks. Here, two priority orders are given to the wiring tracks. FIG. 6A is a diagram for explaining two priority orders used when wiring to a plurality of wiring tracks. FIG. 6A(a) is a diagram showing that the priority order of wiring (wiring graphics) L1 to L6 to be wired to tracks is determined. In FIG. 6A(a), the order of priority of the wires L1 to L6 is from left to right in left edge sort. Or in order of the length of the wiring. The program decides which one to use.
The order of the wiring tracks is set in advance for each ROW (FIG. 6A(b)). Search in the order shown in 6A(b).

After step S15, wiring is performed by the processing method determined in step S15 (S16). 7A to 7C are diagrams showing an example in which the CPU 10 functions as the track wiring means 232 stored in the external storage device 23 and wiring is provided using the left edge algorithm. Assume that there are 6 routing tracks in the priority ROW to be processed. As the track wiring means 232, the CPU 10 first generates wiring L1 to L6 at default positions according to the information of the net list 233, the element layout information file 234, and the node list 235 (FIG. 7(Aa)).

Next, left edge sort is performed. In other words, for the wirings L1 to L6 at the default positions, since the order of occurrence at positions near the left end of the ROW is L3, L1, L2, L4, L6, and L5, the wiring tracks are changed from the bottom in this order. (Fig. 7(b)). In this case, the wiring track, which is the vertical position, is changed without changing the coordinates of the wiring (horizontal coordinates in the figure).

Next, the short wirings arranged in the upper wiring track are moved to the empty area of the wiring track to close the empty area in the lower wiring track (FIG. 7(c)). In this example, lines L5 and L6 have been moved. By processing the wiring tracks with the left edge algorithm, there is an effect that the number of consumed tracks can be minimized. In addition, since an empty wiring track can be generated on the upper side, it becomes possible to place upper-level functional blocks in hierarchical design in the custom layout on the upper empty wiring track.

The processing in the case where the processing method determined in step S15 is to preferentially provide wiring for nodes with long wiring lengths will be described below. Empty wiring tracks of the priority ROW to be processed are searched for, for example, in order from the wiring track on the lower side. Generate long node wires in the empty wire tracks found above.

FIG. 8 is a plan view of the wiring surface showing the process of searching for tracks that can be wired in the order of priority wiring tracks set in advance in ROW3. It is assumed that when the process in ROW is started, the wiring B0 has already been placed on the 0th wiring track, the wiring B1 has been placed on the first wiring track, and the wiring B4 has been placed on the fourth wiring track. (FIG. 8(a)). Further, the wiring to be wired is the wiring B in FIG. 8(a). In this case, for example, empty tracks are searched for in order from the lower wiring track, and it is detected that the second wiring track is an empty wiring track. Then, the wiring B to be wired is arranged on this second wiring track (FIG. 8(b)). Such processing can be expected to avoid detour wiring that increases the load, increase the probability of arranging low-priority (short) wiring in another ROW, and obtain appropriate wiring.

Following the processing of step S16 as described above, it is detected whether or not the necessary wiring has been placed in the ROW of the priority order for the node to be connected (S17). Proceeding to step S18, the process from step S15 onwards is performed.

If branched to YES in step S17, branch lines of the placed wiring are placed according to the information of the netlist 233, the element layout information file 234, and the node list 235 (S19). FIG. 9 is a diagram showing an example of arrangement of branch lines P1 to P8 for wiring B arranged in ROW3 as shown in FIG. 8, and is a plan view of a wiring surface on which a plurality of ROWs are arranged. In FIG. 9, the branch lines P1 to P8 are indicated by thin short bars extending from the wiring line B. As shown in FIG. As described above, the wiring of the connection target nodes in ROW3 can suppress an increase in the wiring load.

In the above embodiment, it is possible to generate an empty wiring track above a plurality of wiring tracks in FIG. 7, so it is shown that the upper functional block is arranged in the upper empty wiring track. In another embodiment (second embodiment), the track wiring unit 232 arranges the wiring of the power supply line so that the wiring other than the power supply line is sandwiched between the wirings of the power supply line. FIG. 10 is a diagram showing an example in which wires of power supply lines are arranged so that wires other than power supply lines are sandwiched by wires L _DD and L _SS of power supply lines, and is a plan view of a wiring surface on which a plurality of ROWs are arranged. be. In FIG. 10, the wiring _LDD of the power supply V _DD is arranged on the wiring track of the highest order in the figure, and the wiring _LSS of the power supply _VSS is arranged on the wiring track of the lowest order of the figure. Wirings N1 to N3 of ordinary signal lines are arranged between the wiring L _DD of the power supply V _DD and the wiring L _SS of the power supply V _SS to produce a shield effect.

In still another embodiment, the node list 235 holds information in which the order of processing is prioritized for each node. An optimum solution for track selection may be obtained. For example, it is possible to set the processing order of nodes corresponding to upper functional blocks earlier, and arrange wiring corresponding to upper functional blocks in empty wiring tracks in upper positions in the ROW. As a result, it can be expected to prevent the situation in which there is no wiring track for the functional block and the situation in which detour wiring occurs in the wiring track for the functional block and the load increases.

While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and equivalents thereof.

Reference Signs List 1 layout device 11 main memory 12 bus 13 external storage interface 14 input interface 15 display interface 16 communication interface 22 . . Mouse 23 .. External storage device 24 .. Input device 25 .. Display device 26-1 to 26-m . , 232... track wiring means, 233... net list, 234... element layout information file, 235... node list

Claims (8)

In a layout device that performs a design in which one or more elements are arranged in each layer of a plurality of layers and wiring necessary for the one or more elements is provided,
Priority order determining means for predicting the magnitude of the resistance value of the wiring that occurs when the element is arranged in each row of each layer based on the arrangement information of the element, and determining the priority of the row for designing the wiring based on the prediction result. and,
and track wiring means for providing wiring of nodes to be connected to wiring tracks of each row in accordance with the determined priority order of the rows. 2. The method according to claim 1, wherein said priority determining means determines the priority of said ROW based on the number of elements arranged in each ROW, the number of connection points of each ROW, and the unit resistance value of a node. Layout device as described. When the layer in the longitudinal direction of the ROW has a low resistance and the layer in a direction perpendicular to the longitudinal direction of the ROW has a high resistance, the priority determining means determines the number of pins connected to the elements in the layer in the longitudinal direction of the ROW, 3. The layout device according to claim 1, wherein a weight greater than the number of pins connected to elements in a layer in a direction perpendicular to the longitudinal direction of the row is given and addition is performed to determine the order of priority. The track wiring means is characterized in that when the wiring of the connection object node is provided to the wiring track of each ROW, the wiring is provided by using a left edge algorithm when the ROW is not congested due to obstacles. 4. The layout device according to any one of claims 1 to 3. When the wiring of the node to be connected is provided to the wiring track of each ROW, the track wiring means preferentially provides the wiring of the node having the long wiring length when the ROW is congested with obstacles. 5. A layout device according to any one of claims 1 to 4. 6. The layout device according to claim 1, wherein the track wiring means arranges the wiring of the power supply line so that the wiring other than the power supply line is sandwiched by the wiring of the power supply line. In a layout method for designing by arranging one or more elements in each layer of a plurality of layers and providing necessary wiring for the one or more elements,
The layout device predicts the magnitude of the resistance value of the wiring that will occur when the elements are arranged in each row of each layer based on the arrangement information of the elements, and determines the priority of the rows in which the wiring is designed based on the prediction result. a prioritization process to
A layout method, comprising: a track wiring step of providing wiring of connection target nodes to wiring tracks of each of the ROWs by the layout device in accordance with the determined priority order of the ROWs. A computer of a layout device that performs design by arranging one or more elements in each layer of a plurality of layers and providing necessary wiring between each element,
Priority order determining means for predicting the magnitude of the resistance value of the wiring that occurs when the element is arranged in each row of each layer based on the arrangement information of the element, and determining the priority of the row for designing the wiring based on the prediction result. ,
A layout program for functioning as track wiring means for providing wiring of nodes to be connected to wiring tracks of each row in accordance with the determined priority order of the rows.

Images