JP2022056271A - Layout device, layout method and program for layout - Google Patents

Abstract

To provide a layout device in which an increase in wiring load is suppressed and wiring is appropriately performed.SOLUTION: A layout device according to an embodiment of the present invention performs designing by arranging one or more elements in each layer of a plurality of layers and providing wiring necessary for the one or more elements and includes: priority order determination means 231 for predicting the magnitude of a resistance value of wiring generated when the elements are arranged in each ROW of each layer based on arrangement information of the elements and determining a priority order of a ROW where the wiring is designed based on the prediction result; and track wiring means 232 for providing wiring of a line connection target node for a wiring track of each ROW according to the determined priority order of the ROW.SELECTED DRAWING: Figure 2

Description

The present invention relates to a layout device, a layout method and a layout program.

The detailed wiring algorithm in the conventional automatic wiring tool basically repeats the wiring process by repeatedly connecting the connection points at the intersections of the wiring and the wiring in the wiring path and correcting the error. For this reason, in long-distance connections, jogs that cause steps in the wiring and switching of wiring layers occur randomly, and detour wiring tends to be created. In general, custom layouts have a high ratio of critical paths, so an increase in wiring load due to detour wiring often leads to fatal problems. In addition, in the custom layout, since the hierarchical design is performed for each functional module, there is a problem that the reserved wiring route reserved for the upper module is consumed extra.

In Patent Document 1, a through wiring position is assigned to a net indicating wiring between elements and a trunk line, which requires through wiring, which is wiring that needs to straddle a plurality of cell rows in rough wiring (global wiring). Determine the allocation to the channel, which is the area where the wiring to connect the input / output parts of the above is arranged, determine the approximate wiring route, and then sequentially wire to each channel by the channel wiring method based on the result. A wiring method for performing processing, determining a detailed wiring route between cells, and making a connection is disclosed. In the invention of Patent Document 1, when the detailed wiring path between the above cells is determined and the connection is made, the through wiring is not sequentially processed for each net, but the allocation of the through wiring position and the allocation to the trunk line channel are sequentially performed. For the required nets, the trunk lines (horizontal wiring parallel to the cell row) required for each net are extracted, and the set of the trunk lines is used as the allowable range of the allocated channel so that the wiring does not bypass. Considering the presence or absence of a through-wiring location in the cell as a condition, a combination that realizes placement and filling with the minimum number of tracks is obtained. After that, the wiring position is determined at once by allocating the trunk line to the channel according to the combination of the arrangement and filling of the trunk line.

The invention of Reference 1 is based on the channel wiring process by the conventional channel wiring method, and the allocation of the through wiring position to the net requiring the through wiring in the schematic wiring and the allocation to the trunk channel of the trunk line is the minimum track. It is decided collectively according to the arrangement combination of trunk lines that can be realized by the number. Therefore, it is possible to always allocate the trunk line to the channel that is close to the optimum and to allocate the through wiring position that is determined subordinately to the channel. This makes it possible to effectively compress the wiring area by taking advantage of the channel wiring method that can achieve a wiring ratio of almost 100%.

Further, in Patent Document 2, the allocation of the through wiring position and the allocation to the channel of the trunk line are determined for the net requiring the through wiring in the schematic wiring, the approximate wiring route is determined, and then the result is obtained. Based on this, a wiring method is disclosed in which wiring processing is sequentially performed for each channel by the channel wiring method, a detailed wiring route between cells is determined, and wiring is performed. In the invention of Patent Document 2, when making the above connection, the allocation of the through wiring position and the allocation to the channel of the trunk line are not sequentially processed for each net, but for each net for all the nets requiring the through wiring. Extract the trunk line (horizontal wiring parallel to the cell row) required for the cell, and allow the allocation channel so that the wiring does not bypass the set of trunk lines, and whether there is a through wiring location in the cell. In consideration of the conditions such as the above, the allocation channel is obtained based on the trunk line having a narrow channel allocation range of the trunk line, the combination of the trunk line and the channel to be arranged and filled in the track is obtained, and the wiring position is determined.

According to the method of Patent Document 2, the allocation of the through wiring position and the allocation of the trunk line channel to the net requiring the through wiring in the rough wiring is processed based on the trunk line having a narrow trunk line allocation, so that the trunk line and the other trunk lines are used. Since processing is performed from the one with the smallest possibility of being placed on the same channel, and many combinations are performed on a limited channel, the trunk line and channel allocation are determined at the same time, and the trunk line is set with the number of tracks close to the minimum number of tracks. It has the effect of being able to be assigned.

Further, Reference Document 3 discloses a semiconductor integrated circuit device that reinforces power supply by utilizing an empty area in which an element is not formed as a wiring area and is suitable for automatic design of a pattern layout.

In the invention of Reference Document 3, an unused cell included in one cell row, an empty wiring track on a logical cell, and a space area between cell rows are searched, metal wiring is formed in those areas, and a power supply is reinforced. It reinforces and supplies power to the required logic cells.

Japanese Unexamined Patent Publication No. 63-278249 Japanese Unexamined Patent Publication No. 64-81249 Japanese Unexamined Patent Publication No. 9-199601

As described above, there have been some cases in which the wiring area can be effectively used without waste, but the wiring is not designed appropriately from the viewpoint of suppressing the increase in the wiring load. The present invention has been made in view of the current state of such conventional layout technology, and an object thereof is to provide a layout device, a layout method, and a layout program in which an increase in wiring load is suppressed and wiring is appropriately performed. To provide.

The layout device according to the embodiment of the present invention is a layout device designed by arranging one or more elements in each layer of a plurality of layers and providing necessary wiring between the elements, and is the above-mentioned layer based on the information of the element arrangement. Priority determination means for predicting the magnitude of the resistance value of the wiring generated when the element is arranged in each ROW, and determining the priority of the ROW for designing the wiring based on the prediction result, and the priority of the determined ROW. It is characterized by providing a track wiring means for providing wiring of a connection target node for a wiring track for each ROW in order.

The block diagram of the computer system which realizes the layout apparatus which concerns on embodiment of this invention. The figure which shows an example of the program and data stored in the external storage device 23 in this embodiment of this invention. The flowchart which shows the operation which concerns on this embodiment of this invention. It is a figure which shows the wiring generated in each ROW and step S13 in this embodiment which concerns on this invention, and is the top view of the wiring surface which a plurality of ROWs are arranged. In the present embodiment according to the present invention, it is a figure which shows the element arranged in each ROW and the ROW priority order information obtained for each ROW, and is the top view of the wiring surface in which a plurality of ROWs are arranged. FIG. 5 is a diagram for explaining a pin connected to an element of a layer in the longitudinal direction of ROW and a pin connected to an element of a layer in a direction orthogonal to the longitudinal direction of ROW in the present embodiment according to the present invention. It is a figure which shows the example of weighting at the time of the existence | weight | weighting for obtaining the ROW priority information, and is the top view of the wiring surface in which a plurality of ROWs are arranged. In the present embodiment according to the present invention, a diagram illustrating two types of priorities used when wiring to a plurality of wiring tracks. The figure which shows the example which provides the wiring by using the left edge algorithm. The plan view of the wiring surface which shows the process of searching the track which can be wired in the order of the priority wiring track preset in ROW3. FIG. 8 is a diagram showing an example in which a branch line for wiring B arranged in ROW3 is arranged as shown in FIG. 8, and is a plan view of a wiring surface in which a plurality of ROWs are arranged. It is a figure which shows the example which arranged the wiring of a power source line so that the wiring other than a power source line is sandwiched by the wiring of a power source line, and is the top view of the wiring surface where a plurality of ROWs are arranged.

Hereinafter, a layout device, a layout method, and a layout program according to an embodiment of the present invention will be described with reference to the accompanying drawings. In each figure, the same components are designated by the same reference numerals, and duplicate description will be omitted. The layout device according to the present embodiment is a layout device designed by arranging one or more elements in each layer of a plurality of layers and providing necessary wiring between the elements. In this embodiment, the target device for layout is a semiconductor device, but it may be an electronic device outside the semiconductor device made of a multilayer substrate.

FIG. 1 is a block diagram of a computer system that realizes the layout device 1 according to the embodiment. This computer system can be configured by a personal computer, a workstation, or other computer system. This computer system relates to the present embodiment and other embodiments by controlling each part based on a program or data stored in the main memory 11 or read into the main memory 11 by the CPU 10 and executing necessary processing. It operates as a layout device 1.

An external storage interface 13, an input interface 14, a display interface 15, and a communication interface 16 are connected to the CPU 10 via a bus 12. A program such as a layout program and an external storage device 23 in which necessary data and the like are stored are connected to the external storage interface 13. An input device 24 such as a keyboard as an input device for inputting commands and data and a mouse 22 as a pointing device are connected to the input interface 14.

A display device 25 having a display screen such as an LED or an LCD is connected to the display interface 15. Ports 26-1, 26-2, ..., 26-m for obtaining necessary information from the outside are connected to the communication interface 16. This computer system may be provided with other configurations, and the configuration of FIG. 1 is only an example. The configuration by this computer system is not limited to this first embodiment, but is also adopted in the configuration as each embodiment after the second embodiment and as a modification thereof.

FIG. 2 shows a program and data stored in the external storage device 23 in the present embodiment. That is, the external storage device 23 stores a layout program that causes the CPU 10 to function as the priority determination means 231 and the track wiring means 232, and also stores the netlist 233, the element layout information file 234, and the node list 235. Has been done.

The priority order determining means 231 is generated when the elements are arranged in each ROW, which is each layer, based on the element arrangement information (stored in the net list 233, the element layout information file 234, and the node list 235). The magnitude of the resistance value of the wiring is predicted, and the priority of the ROW for designing the wiring based on the prediction result is determined. Each ROW is provided with a plurality of wiring tracks. In the present embodiment, the ROW to be preferentially wired in the plurality of ROWs is determined, and which of the plurality of wiring tracks in the determined ROW is to be wired. I have decided. The track wiring means 232 provides wiring of the connection target node to the wiring track for each ROW according to the priority order of the ROW determined by the priority order determining means 231. As described above, one ROW is determined, the wiring track to be wired in the ROW is determined, and wiring is performed at the node (connection target node) between the elements to be wired in the wiring track.

The netlist 233 describes a signal name (net name), a circuit number of an element (component) connected to the net, a terminal number, and the like. The element layout information file 234 describes the circuit numbers of the elements used in the apparatus, the arrangement coordinates of the elements, and the like. In the node list 235, the signal name of the signal sent to the node, the length of the wiring, the coordinates of the start point and the end point, and the like are described. The element layout information file 234 and the node list 235 may be combined into one file.

FIG. 3 is a flowchart showing the operation of the priority order determining means 231 and the track wiring means 232 of the present embodiment. That is, as described above, the external storage device 23 stores a layout program that causes the CPU 10 to function as the priority order determining means 231 and the track wiring means 232. Therefore, when the program is started, the CPU 10 displays FIG. The operation shown in the flowchart is performed. The operation will be described below according to the flowchart shown in FIG. First, a list of connection target nodes to be connected in this process is taken out from the node list 235 (S11).

Steps S13 and S14 sandwiched between the iterative processing mark K11 and the iterative processing mark K12 are sequentially repeated for each node for all of the number of connection target nodes taken out in the above step S11.

The processes of steps S13 and S14 are the processes performed by the priority order determining means 231, and the elements are attached to each ROW based on the number of elements arranged in each ROW, the number of connection points of each ROW, and the unit resistance value of the node. This is a process of predicting the magnitude of the resistance value of the wiring caused by the wiring when arranged and determining the priority of the ROW. For example, with respect to the elements arranged in the ROW, it is predicted that the number of wires will increase when the number of elements is large, and the resistance value will increase when the elements are wired. Therefore, the resistance of the wiring caused by the wiring when the elements are arranged in the ROW is expected. It is a parameter when predicting the magnitude of the value. Also, regarding the ROW connection points, it is predicted that the number of wirings between the connection points will increase if there are many connection points. Therefore, a parameter for predicting the magnitude of the resistance value of the wiring generated by the wiring when the element is arranged in the ROW. Will be. The unit resistance value of the node also depends on the length of the wiring, but it becomes a parameter when predicting the magnitude of the resistance value of the wiring generated by the wiring when the element is arranged in the ROW. By using all the above three parameters, it is possible to simply obtain the results of operations such as addition and multiplication of the three parameters for each ROW, and compare the results to obtain the priority. If it is predicted that the importance of the above three parameters will change depending on the wiring work, the calculation can be performed after multiplying each parameter by a weight. Further, any two of the three parameters can be used, and any one of the three parameters can also be used. As for how to use the parameters, for example, for the unit resistance value of a node, the result of multiplying by the length of all the nodes in the ROW can be obtained for each ROW, and the results can be compared to obtain the priority. can. In the present embodiment, the number of connection points of each ROW is used as a parameter, and the usage of this parameter is as follows. That is, in step S13, the maximum value (Max) and the minimum value (Min) of the arrangement coordinates of the element connected to the corresponding node are detected by using the information of the element layout information file 234 and the node list 235, and these maximum values and the minimum values (Min) are detected. The wiring corresponding to the coordinates with the minimum is generated (S13).

In the present embodiment, processing by numerical values such as wiring length comparison and element position comparison may be performed, but here, the processing will be described while illustrating. FIG. 4 is a diagram showing each ROW (0 to 4) and the wiring generated in step S13, and is a plan view of a wiring surface in which a plurality of ROWs are arranged. Here, as an example, it is assumed that the number of ROWs is 5 layers, the lowest layer is ROW0, ROW1, ..., And the uppermost layer is ROW4.

There is no element arrangement in ROW0, elements C1 are arranged in ROW1, elements C2 to C4 are arranged in ROW2, elements C5 to C9 are arranged in ROW3, and elements C10 to C13 are arranged in ROW4. ing. Here, assuming that the right side of the coordinates is large, the maximum value (Max) of the arrangement coordinates of the element is the coordinates of the element C4, and the minimum value (Min) of the coordinates of the element is the coordinates of the element C1. The wiring generated in S13 has a length similar to that of the wiring B shown below ROW0.

In each ROW, the ROW having the most connection points with the wiring B is detected in order, and the ROW is associated with the connection target node in the order of the most connection points and stored as ROW priority information (S14). In this embodiment, the connection point of one element is calculated as "1". FIG. 5 is a diagram showing elements arranged in each ROW and ROW priority order information obtained for each ROW in the present embodiment according to the present invention, and is a plan view of a wiring surface in which a plurality of ROWs are arranged. be. The ROW priority information matches the number of elements arranged in the ROW, and the values thereof are ROW0 = 0, ROW1 = 1, ROW2 = 3, ROW3 = 5, ROW4 as shown on the right side of each ROW in FIG. = 4. As a result, the priority order is in the order of ROW3> ROW4> ROW2> ROW1> ROW0, and this is stored as ROW priority information. In the present embodiment, the resistance of the wiring to the layer in the direction orthogonal to the longitudinal direction of the ROW indicated by the arrow Y in the figure is larger than the resistance of the wiring to the layer in the longitudinal direction of the ROW indicated by the arrow X in the figure. Since it is connected to the element provided in the ROM, it is premised that wiring to the layer in the longitudinal direction of the ROW is made.

In the present embodiment, the ROW priority information is obtained using the number of connection points of each ROW, but since the terminal number and the like are described in the netlist 233, the number of the terminal numbers is calculated for each element. Then, ROW priority information may be obtained. Further, in the case of the present embodiment, the resistance of the wiring to the layer in the direction orthogonal to the longitudinal direction of the ROW indicated by the arrow Y in the figure is larger than the resistance of the wiring to the layer in the longitudinal direction of the ROW indicated by the arrow X in the figure. The number of pins connected to the elements of the layer in the longitudinal direction of the ROW may be added with a weight larger than the number of pins connected to the elements of the layer in the direction orthogonal to the longitudinal direction of the ROW. FIG. 5A is a diagram for explaining a pin connected to the element of the layer in the longitudinal direction of the ROW and a pin connected to the element of the layer in the direction orthogonal to the longitudinal direction of the ROW, and is a perspective view showing wiring in the ROW. As shown in FIG. 5A, the wiring H1 in the ROW extends in the longitudinal direction of the ROW indicated by the arrow X, and the elements DX1, DX2, ... Of the layers in the longitudinal direction of the ROW are arranged. The elements DY1, DY2, DY3, DY4, ... Of the layers in the direction orthogonal to the longitudinal direction of the ROW are connected to the side portion of the wiring H1 by the wirings V1, V2, V3, V4, .... The elements DX1, DX2, DX3, ... And the elements DY1, DY2, DY3, DY4, ... Have one output pin and a plurality of input pins. Wiring is between these pins. Because the resistance of wiring to the layer in the direction orthogonal to the longitudinal direction of ROW indicated by the arrow Y in the figure is larger than the resistance of wiring to the layer in the longitudinal direction of ROW indicated by the arrow in the figure due to the material used for wiring. The number of pins connected to the elements DX1, DX2, ... Of the layer in the longitudinal direction of the ROW is larger than the number of pins connected to the elements DY1, DY2, DY3, DY4, ... In the direction orthogonal to the longitudinal direction of the ROW. It will have a large weight.
FIG. 6 is a diagram showing an example of weighting when there is a ROW that is weighted for obtaining ROW priority information, and is a plan view of a wiring surface on which a plurality of ROWs are arranged. In FIG. 6, when the element C00 having a pin connected in the longitudinal direction of the ROW is arranged with respect to the ROW 2, addition is performed by the element C00 having a weight “5” in addition to the normal number of elements 3. , Indicates that the point is "8" as a whole. Assuming that no weight is applied when an element having a pin connected in the longitudinal direction of the ROW is arranged, the point of the ROW2 becomes "3", and the resistance value of the wiring generated by the wiring when the element is arranged in the ROW. It becomes impossible to properly predict the size of. Further, the unit resistance value of the node may be described in the node list 235, and the ROW having a small value may be prioritized by multiplying the unit resistance value by the distance from the cell to which the node is connected.

By obtaining the ROW priority information by the above processing, the magnitude of the resistance value of the wiring generated when the elements are arranged in each ROW of each of the above layers is predicted based on the information of the element arrangement, and the wiring is provided based on the prediction result. Since the design is performed, ROW with a small wiring load is given priority, and it is expected that the wiring load will be reduced. When the above processing is completed for all the connection target nodes, the process proceeds to step S15 in FIG. In step S15, it is detected for each priority ROM whether or not the inside of the ROW to be processed is congested by obstacles, and when the inside of the ROW is not congested by obstacles, wiring is provided by using the left edge algorithm. When the inside of the ROW is congested by obstacles, the wiring of the node having a long wiring length is preferentially provided. Here, the obstacle means an element or other wiring that interferes with the wiring.

In step S15, in step S16 sandwiched between the iterative processing mark K13 and the iterative processing mark K14, the processing aims to minimize the number of consumed trucks by increasing the number of empty trucks (unwired trucks). Or, it is performed to avoid the detour wiring that increases the load and to increase the probability of arranging the low priority (short) wiring to another ROW so that the wiring becomes appropriate.

In the process of step S15, the obstacle may be an element that is not connected to the wiring. Further, it can be defined that the congestion is when the occupancy rate of the obstacle with respect to the area of the ROM is, for example, 40% or more.
The following processing describes wiring to a plurality of wiring tracks. Here, there are two priorities for the wiring track. FIG. 6A is a diagram illustrating two types of priorities used when wiring to a plurality of wiring tracks. FIG. 6A (a) is a diagram showing that the priority order of the wiring (wiring figure) L1 to L6 to be wired to the truck is determined. In FIG. 6A (a), the priority order of the wirings L1 to L6 is from the left of the left edge sort. Or the order of the longest wiring. The program decides which one to use.
The order of the wiring tracks is preset for each ROW (FIG. 6A (b)), and for the wiring track in which the wirings L1 to L6 selected in the order shown in FIG. 6A (a) are arranged, this figure is shown. 6 Search in the order shown in A (b).

After step S15, wiring is performed by the processing method determined in step S15 (S16). 7 (a) to 7 (c) are diagrams showing an example in which the CPU 10 functions as the track wiring means 232 stored in the external storage device 23 and wiring is provided by using the left edge algorithm. It is assumed that there are six wiring tracks in the priority ROW to be processed. As the track wiring means 232, the CPU 10 first generates wirings L1 to L6 at default positions according to the information of the netlist 233, the element layout information file 234, and the node list 235 (FIG. 7Aa).

Next, left edge sorting is performed. That is, with respect to the wirings L1 to L6 at the default positions, the order of occurrence near the left end of the ROW is L3, L1, L2, L4, L6, L5, so the wiring tracks are changed from the bottom in this order. (Fig. 7 (b)). In this case, the wiring track at the upper and lower positions is changed without changing the coordinates of the wiring (coordinates in the left-right direction in the figure).

Next, the short wiring arranged in the upper wiring track is moved to the empty area of the wiring track to fill the empty area in the lower wiring track (FIG. 7 (c)). In this example, the wirings L5 and L6 are moved. By processing the wiring tracks with the left edge algorithm, there is an effect that the number of tracks consumed can be minimized. Further, since an empty wiring track can be generated on the upper side, it is possible to arrange the upper functional block in the case of hierarchical design in the custom layout on the empty wiring track on the upper side.

The processing when the processing method determined in step S15 is the processing for preferentially providing the wiring of the node having a long wiring length will be described below. For example, the empty wiring track of the priority ROW to be processed is searched in order from the lower wiring track, and when an empty track is found, the wiring length is the longest among the unwired nodes according to the information in the node list 235. Long node wiring occurs in the empty wiring track found above.

FIG. 8 is a plan view of a wiring surface showing a process of searching for tracks that can be wired in the order of priority wiring tracks preset in ROW3. It is assumed that the wiring B0 is already arranged on the 0th wiring track, the wiring B1 is arranged on the 1st wiring track, and the B4 is arranged on the 4th wiring track when the processing in the ROW is started. (FIG. 8 (a)). Further, what should be wired is the wiring B in FIG. 8A. In this case, for example, an empty wiring track is searched for in order from the lower wiring track, and it is detected that the second wiring track is an empty wiring track. Then, the wiring B to be wired is arranged on the second wiring track (FIG. 8 (b)). It is expected that such processing avoids detour wiring that increases the load, increases the probability of arranging low-priority (short) wiring in other ROWs, and becomes appropriate wiring.

Following the process of step S16 as described above, it is detected whether the necessary wiring can be arranged in the ROW of the priority order for the node to be connected (S17), and when branching to NO, the wiring process for the ROW of the next priority is performed. Proceed (S18), and further perform the processing after step S15.

When branching to YES in step S17, the branch line of the arranged wiring is arranged according to the information of the netlist 233, the element layout information file 234, and the node list 235 (S19). FIG. 9 is a diagram showing an example in which branch lines P1 to P8 are arranged with respect to wiring B arranged in ROW3 as shown in FIG. 8, and is a plan view of a wiring surface in which a plurality of ROWs are arranged. In FIG. 9, branch lines P1 to P8 are shown by thin and short bars from wiring B. As described above, the increase in the wiring load can be suppressed by the wiring of the connection target node in this ROW3.

In the above embodiment, since an empty wiring track can be generated on the upper side of the plurality of wiring tracks in FIG. 7, it is shown that the upper functional block is arranged on the upper empty wiring track. In another embodiment (second embodiment), the track wiring means 232 arranges the wiring of the power supply line so as to sandwich the wiring other than the power supply line by the wiring of the power supply line. FIG. 10 is a diagram showing an example in which the wiring of the power supply line is arranged so as to sandwich the wiring other than the power supply line by the wiring LDD and _LSS of the power supply line, and is a plan view of the wiring surface in which a plurality of _ROWs are arranged. be. In FIG. 10, the wiring L _DD of the power supply V _DD is arranged on the wiring track at the top of the figure, and the wiring L _SS of the power supply _VS S is arranged on the wiring track at the bottom of the figure. Wiring N1 to N3 of normal signal lines are arranged between the wiring L _{DD of the power supply V DD and} the wiring L _SS of the power supply _VS S to generate a shielding effect.

In still another embodiment, information in which the processing order is prioritized for each node is stored in the node list 235, and the track wiring means 232 wires the track selection process in the ROW according to the above priority order. The optimum solution for track selection may be obtained. For example, it is possible to set the processing order of the node corresponding to the upper functional block to be faster, and to arrange the wiring corresponding to the upper functional block in the empty wiring track at the upper position in the ROW. This can be expected to prevent a situation in which there is no wiring track for the above-mentioned functional block and a situation in which detour wiring occurs in the wiring track for the functional block and an increase in load occurs.

Although a plurality of embodiments according to the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 ... Layout device, 11 ... Main memory, 12 ... Bus, 13 ... External storage interface, 14 ... Input interface, 15 ... Display interface, 16 ... Communication interface, 22 ... Mouse, 23 ... External storage device, 24 ... Input device, 25 ... Display device, 26-1 to 26-m ... Port, 231 ... Priority determination means 232 ... Track wiring means, 233 ... Net list, 234 ... Element layout information file, 235 ... Node list

Claims (8)

In a layout device in which one or more elements are arranged in each layer of a plurality of layers and the wiring required for the one or more elements is provided.
Priority determination means for predicting the magnitude of the resistance value of the wiring generated when the element is arranged in each ROW of each layer based on the arrangement information of the element, and determining the priority of the ROW for designing the wiring based on the prediction result. When,
A layout device comprising: a track wiring means for providing wiring of a node to be connected to the wiring track of each ROW according to the determined priority order of the ROW. The first aspect of the present invention is characterized in that the priority order determining means determines the priority of the ROW based on the number of elements arranged in each ROW, the number of connection points of each ROW, and the unit resistance value of a node. The layout device described. The priority determining means determines the number of pins connected to the elements of the layer in the longitudinal direction of the ROW when the layer in the longitudinal direction of the ROW has a low resistance and the layer in the direction orthogonal to the longitudinal direction of the ROW has a high resistance. The layout device according to claim 1 or 2, wherein the layout device is characterized in that the priority is determined by adding weights with a weight larger than the number of pins connected to the elements of the layer in the direction orthogonal to the longitudinal direction of the ROW. The track wiring means is characterized in that when wiring of the connection target node is provided for the wiring track for each ROW, wiring is provided by using a left edge algorithm when the inside of the ROW is not congested by an obstacle. The layout device according to any one of claims 1 to 3. When the track wiring means provides the wiring of the connection target node for the wiring track for each ROW, when the inside of the ROW is congested by an obstacle, the wiring of the node having a long wiring length is preferentially provided. The layout device according to any one of claims 1 to 4, which is characterized. The layout device according to any one of claims 1 to 5, wherein the track wiring means arranges the wiring of the power supply line so as to sandwich the wiring other than the power supply line by the wiring of the power supply line. In a layout method in which one or more elements are arranged in each layer of a plurality of layers and the wiring required for the one or more elements is provided.
The layout device predicts the magnitude of the resistance value of the wiring that occurs when the element is arranged in each ROW of each layer based on the arrangement information of the element, and determines the priority of the ROW that designs the wiring based on the prediction result. Prioritization process and
A layout method comprising: a track wiring step of providing wiring of a node to be connected to a wiring track of each ROW according to the determined priority order of the ROWs by the layout device. A computer of a layout device that arranges one or more elements in each layer of multiple layers and designs to provide necessary wiring between each element.
Priority determination means for predicting the magnitude of the resistance value of the wiring generated when the element is arranged in each ROW of each layer based on the arrangement information of the element, and determining the priority of the ROW for designing the wiring based on the prediction result. ,
A layout program characterized by functioning as a track wiring means for providing wiring of a node to be connected to the wiring track of each ROW according to the determined priority order of the ROW.

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