JP7332529B2 - 異常検出装置 - Google Patents
異常検出装置 Download PDFInfo
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- JP7332529B2 JP7332529B2 JP2020075208A JP2020075208A JP7332529B2 JP 7332529 B2 JP7332529 B2 JP 7332529B2 JP 2020075208 A JP2020075208 A JP 2020075208A JP 2020075208 A JP2020075208 A JP 2020075208A JP 7332529 B2 JP7332529 B2 JP 7332529B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0736—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
- G06F11/0778—Dumping, i.e. gathering error/state information after a fault for later diagnosis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/85—Active fault masking without idle spares
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Health & Medical Sciences (AREA)
- Biomedical Technology (AREA)
- Debugging And Monitoring (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
図1に示すように、異常検出装置1は、例えば車両に搭載された複数の車載機器2に接続されている。車載機器2が検出対象に該当する。各車載機器2の一例は、車両ドアの施解錠を実行するドアロック装置や、エンジンの始動を実行するエンジン装置、トランスミッションの制御を行うトランスミッション装置等である。異常検出装置1は、例えば各車載機器2に設けられたセンサ等を通じて、各車載機器2の異常の有無を検出する。
図3に示すように、S101(Sはステップの略、以下同様)では、判定部22は、RAM5に異常が発生しているか否かを判定する。判定部22は、例えば各車載機器2から検出情報D1を入力した場合に、RAM5の異常判定を実行する。判定部22は、例えば所定の数値をRAM5に書き込むとともに、書き込んだ数値が正しくRAM5から読み出せるか否かを確認することで、RAM5の異常を検出する。判定部22は、RAM5に異常が有ると判定した場合、S102へ移行する。一方、判定部22は、RAM5に異常が無い場合、S105へ移行する。
(5)プロセッサの作動時に使用されるメモリとは、プロセッサの作業領域として使用されるRAM5である。この構成によれば、プロセッサ作業領域にRAM5が用いられる装置に適用できる。
・判定部22は、RAM5のリセット後に、再判定を行わなくてもよい。これは、仕様に応じて適宜変更可能である。
・第1レジスタ11は、第2レジスタ12及び第3レジスタ13のリセットを行うものでもよいし、その他の回路をリセットするものであってもよい。
・異常検出データは、DTCに限定されず、外部診断装置によって読み出し可能であれば、例えば各車載機器2に設けられたセンサの検出値など、他のデータとしてもよい。
・異常検出データD2が書き込まれる記憶装置は、外部メモリ3に限定されず、異常検出装置1内に設けられてもよい。
Claims (6)
- 検出対象の異常を検出した場合に、外部診断装置によって読み出し可能な異常検出データを記憶装置へ書き込む書込部と、
前記書込部の書き込みにおいてプロセッサの作動時に使用されるメモリに異常が発生しているか否かを判定する判定部と、
前記判定部により前記メモリが異常有りと判定された場合、前記プロセッサの機能である複数のリセット機能のうち規定のリセット機能を起動させて、前記メモリのリセットを行うリセット処理部と、を備え、
前記書込部は、前記判定部により前記メモリが異常有りと判定された場合、前記規定のリセット機能による前記メモリのリセット後に、前記異常検出データの書き込みを実行する異常検出装置。 - 前記規定のリセット機能は、前記メモリが異常有りと判定された場合にのみ使用される専用のリセット機能である
請求項1に記載の異常検出装置。 - 前記書込部は、前記メモリのリセットが前記規定のリセット機能によるものか否かを、前記規定のリセット機能からの入力を記憶する特殊機能レジスタを確認することによって判定する
請求項1又は請求項2に記載の異常検出装置。 - 前記メモリのリセットには、前記メモリの初期化を含む
請求項1から請求項3のうちいずれか一項に記載の異常検出装置。 - 前記メモリは、前記プロセッサの作業領域として使用されるRAMである
請求項1から請求項4のうちいずれか一項に記載の異常検出装置。 - 前記判定部は、前記メモリのリセット後、前記メモリに異常が発生しているか否かを再度判定し、
前記書込部は、前記判定部による再判定によって前記メモリに異常が発生していないことを確認できた場合に、前記異常検出データの書き込みを実行する
請求項1から請求項5のうちいずれか一項に記載の異常検出装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020075208A JP7332529B2 (ja) | 2020-04-21 | 2020-04-21 | 異常検出装置 |
DE102021109088.1A DE102021109088A1 (de) | 2020-04-21 | 2021-04-12 | Anomaliedetektor |
US17/232,655 US11379310B2 (en) | 2020-04-21 | 2021-04-16 | Anomaly detector |
Applications Claiming Priority (1)
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JP2020075208A JP7332529B2 (ja) | 2020-04-21 | 2020-04-21 | 異常検出装置 |
Publications (2)
Publication Number | Publication Date |
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JP2021172142A JP2021172142A (ja) | 2021-11-01 |
JP7332529B2 true JP7332529B2 (ja) | 2023-08-23 |
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JP2020075208A Active JP7332529B2 (ja) | 2020-04-21 | 2020-04-21 | 異常検出装置 |
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US (1) | US11379310B2 (ja) |
JP (1) | JP7332529B2 (ja) |
DE (1) | DE102021109088A1 (ja) |
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US11994951B2 (en) * | 2022-02-23 | 2024-05-28 | Micron Technology, Inc. | Device reset alert mechanism |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004017676A (ja) | 2002-06-12 | 2004-01-22 | Denso Corp | 車両用通信システム、初期化装置及び車両用制御装置 |
US20060156194A1 (en) | 2004-12-09 | 2006-07-13 | Infineon Technologies Ag | Method for reallocation of a memory of a subsystem, and subsystem |
JP2012133458A (ja) | 2010-12-20 | 2012-07-12 | Toyota Motor Corp | マイコン、リソース割り当て方法 |
JP2015171853A (ja) | 2014-03-12 | 2015-10-01 | 日立オートモティブシステムズ株式会社 | 自動車用電子制御装置 |
JP2016135634A (ja) | 2015-01-23 | 2016-07-28 | 株式会社デンソー | 電子制御装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3342085B2 (ja) * | 1993-03-24 | 2002-11-05 | 富士通テン株式会社 | 電子制御装置 |
JPH0827733B2 (ja) * | 1993-07-06 | 1996-03-21 | 日本電気株式会社 | 障害処理システム |
EP2232660A4 (en) | 2008-01-04 | 2013-11-27 | Leach Int Corp | NON-VOLATILE STATUS INDICATOR SWITCH |
US10353769B2 (en) * | 2017-07-25 | 2019-07-16 | Apple Inc. | Recovering from addressing fault in a non-volatile memory |
EP3454216B1 (en) * | 2017-09-08 | 2020-11-18 | Nxp B.V. | Method for protecting unauthorized data access from a memory |
US20210256349A1 (en) * | 2020-02-14 | 2021-08-19 | Micron Technology, Inc. | Optimization of quality of service of data storage devices |
-
2020
- 2020-04-21 JP JP2020075208A patent/JP7332529B2/ja active Active
-
2021
- 2021-04-12 DE DE102021109088.1A patent/DE102021109088A1/de not_active Withdrawn
- 2021-04-16 US US17/232,655 patent/US11379310B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004017676A (ja) | 2002-06-12 | 2004-01-22 | Denso Corp | 車両用通信システム、初期化装置及び車両用制御装置 |
US20060156194A1 (en) | 2004-12-09 | 2006-07-13 | Infineon Technologies Ag | Method for reallocation of a memory of a subsystem, and subsystem |
DE102004059392B4 (de) | 2004-12-09 | 2015-09-10 | Infineon Technologies Ag | Verfahren zur Neubelegung eines Befehlsspeichers, Subsystem zur Durchführung eines derartigen Verfahrens, sowie Mikrokontroller |
JP2012133458A (ja) | 2010-12-20 | 2012-07-12 | Toyota Motor Corp | マイコン、リソース割り当て方法 |
JP2015171853A (ja) | 2014-03-12 | 2015-10-01 | 日立オートモティブシステムズ株式会社 | 自動車用電子制御装置 |
JP2016135634A (ja) | 2015-01-23 | 2016-07-28 | 株式会社デンソー | 電子制御装置 |
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Publication number | Publication date |
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US20210326209A1 (en) | 2021-10-21 |
US11379310B2 (en) | 2022-07-05 |
JP2021172142A (ja) | 2021-11-01 |
DE102021109088A1 (de) | 2021-10-21 |
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