JP7329748B2 - Imaging device and imaging system - Google Patents

Description

The present disclosure relates to imaging devices and imaging systems.

Various imaging devices are known. A CMOS (Complementary Metal Oxide Semiconductor) image sensor is exemplified as an imaging device. A CMOS image sensor according to an example includes a readout circuit group for each column, and outputs a digital signal AD-converted for each row. Patent Literature 1 describes an example of a CMOS image sensor.

JP 2011-082813 A

An imaging device may have a plurality of voltage lines to which different voltages are applied. Different noise components are applied to pixel signals from these voltage lines, which may degrade image quality. The present disclosure provides a technique that can help reduce noise when there are multiple voltage lines to which different voltages are applied.

This disclosure is
a plurality of pixels including a first pixel and a second pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension,
An imaging device is provided.

The technology according to the present disclosure can help reduce noise when there are multiple voltage lines to which different voltages are applied.

FIG. 1 is a block diagram of an imaging device according to the first embodiment. FIG. 2 is a diagram showing a specific example of an imaging device according to the first embodiment. FIG. 3 is a configuration diagram of a pixel array in the first embodiment. FIG. 4 is a configuration diagram of the second circuit, the first circuit, the AD conversion circuit, and the control circuit in the first embodiment. FIG. 5 is an explanatory diagram of signal paths in the first embodiment. FIG. 6 is an explanatory diagram of signal paths in the first embodiment. FIG. 7 is an explanatory diagram of signal paths in the first embodiment. FIG. 8 is a cross-sectional view of the imaging device in the first embodiment. FIG. 9 is an explanatory diagram of signal paths in the first embodiment. FIG. 10 is an explanatory diagram of signal paths in the first embodiment. FIG. 11 is an explanatory diagram of signal paths in the first embodiment. FIG. 12 is an explanatory diagram of signal paths in the first embodiment. FIG. 13 is an explanatory diagram of signal paths in the second embodiment. FIG. 14 is an explanatory diagram of signal paths in the second embodiment. FIG. 15 is an explanatory diagram of signal paths in the second embodiment. FIG. 16 is an explanatory diagram of signal paths in the second embodiment. FIG. 17 is an explanatory diagram of signal paths in the second embodiment. FIG. 18 is an explanatory diagram of signal paths in the second embodiment. FIG. 19A is an explanatory diagram of signal paths in the second embodiment. FIG. 19B is an explanatory diagram of signal paths in the second embodiment. FIG. 20 is an explanatory diagram of signal paths in the third embodiment. FIG. 21A is an explanatory diagram of signal paths in the fourth embodiment. FIG. 21B is an explanatory diagram of signal paths in the fourth embodiment. FIG. 21C is an explanatory diagram of signal paths in the fourth embodiment. FIG. 22A is an explanatory diagram of signal paths in the fourth embodiment. FIG. 22B is an explanatory diagram of signal paths in the fourth embodiment. FIG. 22C is an explanatory diagram of signal paths in the fourth embodiment. FIG. 23 is an explanatory diagram of signal paths in the fifth embodiment. FIG. 24 is an explanatory diagram of signal paths in the fifth embodiment. FIG. 25 is an explanatory diagram of signal paths in the fifth embodiment. FIG. 26 is an explanatory diagram of signal paths in the sixth embodiment. FIG. 27 is an explanatory diagram of signal paths in the seventh embodiment. FIG. 28 is a configuration diagram of a selector in the seventh embodiment. FIG. 29 is a block diagram of an imaging system, according to an example.

(Overview of one aspect of the present disclosure)
An imaging device according to a first aspect of the present disclosure includes:
a plurality of pixels including a first pixel and a second pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is positioned upstream of the second extension.

The technique according to the first aspect can help reduce noise when there are a plurality of voltage lines to which different voltages are applied. Note that in the present disclosure, a “signal path” includes, for example, one or more signal lines through which signals flow. A portion of the "signal path" may be a signal line included in the first circuit and/or the second circuit described later.

In the second aspect of the present disclosure, for example, in the imaging device according to the first aspect,
The first voltage may be a power supply voltage,
The second voltage may be a ground voltage.

The technique according to the second aspect can help reduce noise when there are a voltage line to which a power supply voltage is applied and a voltage line to which a ground voltage is applied.

In the third aspect of the present disclosure, for example, in the imaging device according to the first aspect or the second aspect,
The plurality of pixels may form a pixel array having at least one row and a plurality of columns;
A column to which the first pixels belong in the pixel array and a column to which the second pixels belong in the pixel array may be adjacent to each other.

The layout of the third aspect is a specific example of the layout of the imaging device.

In the fourth aspect of the present disclosure, for example, in the imaging device according to any one of the first to third aspects,
In the plan view, the one or more first voltage lines, the one or more second voltage lines, the first extension, and the second extension extend parallel to each other. good too.

The parallel layout of the fourth aspect is advantageous from the viewpoint of miniaturization. On the other hand, this parallel layout is not necessarily advantageous for noise reduction. Therefore, in this parallel layout, the noise reduction described above is likely to exhibit its effect.

In a fifth aspect of the present disclosure, for example, the imaging device according to any one of the first to fourth aspects includes multilayer wiring including a first wiring layer and a second wiring layer different from the first wiring layer. It may comprise layers,
The first wiring layer may include the first intersection,
The second wiring layer may include the second intersection.

According to the fifth aspect, it is easy to realize the intersection of the first signal path and the second signal path in plan view.

In the sixth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fifth aspects,
In the planar view,
the first signal path may further include a first connection point and a second connection point;
the second signal path may further include a third connection point and a fourth connection point;
In the signal flow of the first pixel, the first connection point is located upstream of the first intersection, and the second connection point is between the first intersection and the first extension. may be located,
In the signal flow of the second pixel, the third connection point is located upstream of the second intersection, and the fourth connection point is between the second intersection and the second extension. may be located,
The imaging device may further comprise a selector,
The selector is
a first switch connected between the first connection point and the fourth connection point;
a second switch connected between the first connection point and the second connection point;
a third switch connected between the third connection point and the fourth connection point;
and a fourth switch connected between the third connection point and the second connection point.

According to the sixth aspect, the path of the pixel signal can be switched.

In a seventh aspect of the present disclosure, for example, an imaging device according to any one of the first to sixth aspects includes: a third wiring section including one or more voltage lines; a fourth wiring section including a plurality of voltage lines; A second circuit including a wiring part may be further provided,
The one or more voltage lines of the third wiring portion may include a third voltage line,
The plurality of voltage lines of the fourth wiring portion may include a fourth voltage line and a fifth voltage line adjacent to the third voltage line,
The third voltage line may be positioned between the fourth voltage line and the fifth voltage line,
In the planar view,
The pitch of the one or more first voltage lines and the one or more second voltage lines and the pitch of the fourth voltage line, the third voltage line and the fifth voltage line are different from each other. may be
When the region between the third voltage line and the fourth voltage line is defined as a first pitch region, and the region between the third voltage line and the fifth voltage line is defined as a second pitch region. ,
the first signal path may further include a first pitch portion extending within the first pitch region;
the second signal path may further include a second pitch portion extending within the second pitch region;
In the signal flow of the first pixel, the first pitch portion may be located upstream of the first intersection,
In the signal flow of the second pixel, the second pitch portion may be positioned upstream of the second intersection.

The case where there is a pitch difference of the seventh aspect is an example of the case where the layout with the intersection can contribute to noise reduction.

In the eighth aspect of the present disclosure, for example, in the imaging device according to any one of the first to seventh aspects,
The first circuit may further include a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type;
the first transistor may be connected to any of the one or more first voltage lines;
The second transistor may be connected to any of the one or more second voltage lines.

According to the eighth aspect, the first voltage of the first voltage line can be used to operate the first transistor. A second voltage on the second voltage line may be used to operate the second transistor.

In the ninth aspect of the present disclosure, for example, the imaging device according to any one of the first to sixth aspects may further include a second circuit,
The first circuit may further include a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type;
The second circuit may include a third transistor of the first conductivity type and a fourth transistor of the second conductivity type;
When the center of gravity of the gate of the first transistor and the gate of the second transistor is defined as a first center of gravity, and the center of gravity of the gate of the third transistor and the gate of the fourth transistor is defined as a second center of gravity, the planar view in
The alignment direction of the first transistor and the second transistor may be different from the alignment direction of the third transistor and the fourth transistor,
The first signal path may include a portion closest to the second center of gravity and a portion closest to the first center of gravity,
The second signal path may include a portion closest to the second center of gravity and a portion closest to the first center of gravity,
In the signal flow of the first pixel, the portion closest to the second center of gravity may be located upstream of the portion closest to the first center of gravity,
In the signal flow of the second pixel, the portion closest to the second center of gravity may be located upstream of the portion closest to the first center of gravity.

The case where there is a difference in the direction in which the transistors are arranged in the ninth aspect is an example of the case where the layout involving the intersection can contribute to noise reduction.

In the tenth aspect of the present disclosure, for example, in the imaging device according to any one of the first to ninth aspects,
the plurality of pixels may include a first OB pixel that is an optical black pixel;
The imaging device may further include a signal processing circuit and a first OB path through which signals of the first OB pixels flow,
In the plan view, the first OB path may include a first OB extension extending within the second region,
The signal processing circuit performs optical black correction on the signal of the first pixel that has passed through the first extension section, using the signal of the first OB pixel that has passed through the first OB extension section. You may

The tenth aspect is suitable for reducing the noise component superimposed on the signal of the first pixel in the second area. Note that, in the present disclosure, “OB path” includes, for example, one or more signal lines through which signals flow. A part of the "OB path" may be a signal line included in the first circuit and/or the second circuit described later.

In the eleventh aspect of the present disclosure, for example, in the imaging device according to any one of the first to ninth aspects,
The plurality of pixels may include a third pixel,
The imaging device may further include a third signal path through which the signal of the third pixel flows,
In the plan view, the third signal path may include a third extending portion extending within the second region.

The eleventh aspect facilitates correction for reducing noise in the signals of the first and third pixels.

In the twelfth aspect of the present disclosure, for example, in the imaging device according to the eleventh aspect,
The plurality of pixels may include a fourth pixel,
The imaging device may further include a fourth signal path through which the signal of the fourth pixel flows,
In the plan view, the fourth signal path may include a fourth extending portion extending within the first region.

The twelfth aspect facilitates correction for reducing noise in the signal of the second pixel and the signal of the fourth pixel.

In the thirteenth aspect of the present disclosure, for example, in the imaging device according to the twelfth aspect,
In the planar view,
the third signal path may include a portion extending from the third pixel to the second region;
the fourth signal path may include a portion extending from the fourth pixel to the first region;
The portion extending from the third pixel to the second region may not intersect the portion extending from the fourth pixel to the first region.

The layout of the thirteenth mode is an example of the layout of the imaging device.

In the fourteenth aspect of the present disclosure, for example, in the imaging device according to any one of the eleventh to thirteenth aspects,
The first pixel may include a first color filter,
The second pixel may include a second color filter,
The third pixel may include a third color filter,
The first color filter and the third color filter may be color filters of a first color,
The second color filter may be a color filter of a second color different from the first color.

The fourteenth aspect is suitable for reducing noise in signals of the first pixel and the third pixel, which are pixels including color filters of the first color, under similar correction conditions.

In the fifteenth aspect of the present disclosure, for example, in the imaging device according to any one of the eleventh to thirteenth aspects,
The first pixel and the third pixel may be pixels of a first type selected from four types of R pixels, B pixels, Gr pixels and Gb pixels,
The second pixels may be pixels of a second type selected from four types of R pixels, B pixels, Gr pixels, and Gb pixels,
The first type pixels and the second type pixels may be different from each other.

The fifteenth aspect is suitable for reducing the noise of the signals of the first pixel and the third pixel, which are the first type pixels, under similar correction conditions.

In the sixteenth aspect of the present disclosure, for example, the imaging device according to any one of the eleventh to fifteenth aspects may further include a signal processing circuit,
The signal processing circuit controls both the signal of the first pixel that has passed through the first extension portion and the signal of the third pixel that has passed through the third extension portion. Corrections may be performed to reduce the component.

According to the sixteenth aspect, it is easy to apply similar correction conditions to the correction of the signal of the first pixel and the correction of the signal of the third pixel.

In the seventeenth aspect of the present disclosure, for example, in the imaging device according to any one of the eleventh to fifteenth aspects,
the plurality of pixels may include a first OB pixel that is an optical black pixel;
The imaging device may further include a signal processing circuit and a first OB path through which signals of the first OB pixels flow,
In the plan view, the first OB path may include a first OB extension extending within the second region,
The signal processing circuit performs optical black correction on the signal of the first pixel that has passed through the first extension section, using the signal of the first OB pixel that has passed through the first OB extension section. You may

The seventeenth aspect is suitable for reducing the noise component superimposed on the signal of the first pixel in the second area.

An imaging system according to an eighteenth aspect of the present disclosure includes:
an imaging device according to any one of the first to ninth aspects and the eleventh to fifteenth aspects;
and a signal processing device provided outside the imaging device,
the plurality of pixels includes a first OB pixel that is an optical black pixel;
The imaging device further includes a first OB path through which signals of the first OB pixels flow,
In the plan view, the first OB path includes a first OB extension extending within the second region,
The signal processing device performs optical black correction using the signal of the first OB pixel that has passed through the first OB extension section on the signal of the first pixel that has passed through the first extension section. do.

The eighteenth aspect is suitable for reducing the noise component superimposed on the signal of the first pixel in the second area.

An imaging system according to a nineteenth aspect of the present disclosure includes:
an imaging device according to any one of the eleventh to fifteenth aspects;
and a signal processing device provided outside the imaging device,
The signal processing device controls both the signal of the first pixel via the first extension section and the signal of the third pixel via the third extension section with noise superimposed in the second region. Perform a correction that reduces the component.

According to the nineteenth aspect, it is easy to apply similar correction conditions to the correction of the signal of the first pixel and the correction of the signal of the third pixel.

An imaging device according to a twentieth aspect of the present disclosure includes:
a plurality of pixels including a first pixel, a second pixel, a third pixel and a fourth pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
a third signal path through which the signal of the third pixel flows;
a fourth signal path through which the signal of the fourth pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
In the planar view,
the first signal path includes a first extension extending within the second region;
the second signal path includes a second extension extending within the first region;
the third signal path includes a third extension extending within the second region;
The fourth signal path includes a fourth extension extending within the first region.

In the 21st aspect of the present disclosure, for example, in the imaging device according to the 20th aspect,
The first pixel may include a first color filter,
The second pixel may include a second color filter,
The third pixel may include a third color filter,
The fourth pixel may include a fourth color filter,
The first color filter and the third color filter may be color filters of a first color,
The second color filter and the fourth color filter may be color filters of a second color different from the first color.

In the 22nd aspect of the present disclosure, for example, in the imaging device according to the 20th aspect,
The first pixel and the third pixel may be pixels of a first type selected from four types of R pixels, B pixels, Gr pixels and Gb pixels,
The second pixel and the fourth pixel may be pixels of a second type selected from four types of R pixels, B pixels, Gr pixels, and Gb pixels,
The first type pixels and the second type pixels may be different from each other.

In the 23rd aspect of the present disclosure, for example, the imaging device according to any one of the 20th to 22nd aspects may further include a signal processing circuit,
The signal processing circuit controls both the signal of the first pixel that has passed through the first extension portion and the signal of the third pixel that has passed through the third extension portion. A correction may be performed to reduce the component,
The signal processing circuit controls both the signal of the second pixel that has passed through the second extension section and the signal of the fourth pixel that has passed through the fourth extension section to generate noise superimposed in the first region. Corrections may be performed to reduce the component.

An imaging system according to a twenty-fourth aspect of the present disclosure includes:
an imaging device according to twentieth to twenty-third aspects;
and a signal processing device provided outside the imaging device,
The signal processing device controls both the signal of the first pixel via the first extension section and the signal of the third pixel via the third extension section with noise superimposed in the second region. A correction may be performed to reduce the component,
The signal processing device controls both the signal of the second pixel via the second extension section and the signal of the fourth pixel via the fourth extension section with noise superimposed in the first region. Corrections may be performed to reduce the component.

The techniques of the first to nineteenth aspects can be applied to the twentieth to twenty-fourth aspects.

An imaging device according to an embodiment will be described below with reference to the drawings.

More detailed description than necessary may be omitted. For example, detailed descriptions of well-known matters, redundant descriptions of substantially the same configurations, and the like may be omitted. This is to avoid unnecessary verbosity in the following description and to facilitate understanding by those skilled in the art. It should be noted that the accompanying drawings and the following description are provided for those skilled in the art to fully understand the technology according to the present disclosure, and are not intended to limit the subject matter of the claims.

In the drawings, elements having substantially the same configuration, operation, and effect are denoted by the same reference numerals. In addition, the numerical values described below are all examples for specifically describing the technology according to the present disclosure, and the technology according to the present disclosure is not limited to the illustrated values. Furthermore, the connection relationship between the components is an example for specifically describing the technology according to the present disclosure, and the connection relationship for realizing the function of the technology according to the present disclosure is not limited to this.

In this specification, ordinal numbers such as first, second, third, and so on may be used. If an element is given an ordinal, it is not essential that there be a lower numbered element of the same kind. Ordinal numbers can be changed if necessary.

(First embodiment)
FIG. 1 shows an imaging device 100 according to this embodiment. The imaging device 100 is, for example, the image sensor chip shown in FIG.

The imaging device 100 shown in FIG. 1 has a pixel array 1 and an electric circuit 47 . A pixel array refers to an element that may have one or more columns and one or more rows. In the example of FIG. 1, electrical circuit 47 is a peripheral circuit.

A pixel array 1 includes a plurality of pixels. FIG. 3 shows an example of the pixel array 1. As shown in FIG. In the example of FIG. 3, the pixels in the pixel array 1 are arranged in rows and columns on the semiconductor substrate. The area provided with these pixels functions as an imaging area. Each pixel photoelectrically converts incident light to generate an electric charge, and outputs a pixel signal obtained thereby (an example of the signals of the first to fourth pixels of the present disclosure). A pixel signal is an electrical signal corresponding to an electric charge.

In FIG. 3, "Row" means a row of the pixel array 1. In FIG. "Col" means a column of the pixel array 1; In FIG. 3, the 0th, 1st, 2nd and 3rd lines are drawn. In FIG. 3, "Col0" represents the 0th column and "Col1" represents the 1st column.

In the example of FIG. 3, the pixel array 1 employs a Bayer arrangement. Specifically, for example, in even-numbered rows such as the 0th row and the 2nd row, Gr pixels and R pixels are alternately and repeatedly arranged. In odd rows, such as rows 1 and 3, B pixels and Gb pixels are alternately repeated. Gr pixels and B pixels are alternately and repeatedly arranged in even-numbered columns such as the 0th column. In odd-numbered columns such as the first column, R pixels and Gb pixels are alternately and repeatedly arranged.

R pixels are red pixels. B pixels are blue pixels. Gr and Gb pixels are green pixels.

Specifically, for example, the R pixel includes an R color filter. The R color filter is a red color filter. A B pixel includes a B color filter. The B color filter is a blue color filter. A Gr pixel includes a Gr color filter. A Gb pixel includes a Gb color filter. The Gr color filter and the Gb color filter are green color filters.

In the example of FIG. 3, the pixels are color pixels. Specifically, in the example of FIG. 3, the pixels are primary color pixels. However, the pixels may be pixels of complementary colors. In addition, in the example of FIG. 3, a pixel array is configured by pixels of a plurality of different colors. Specifically, in the example of FIG. 3, the multiple colors are three colors. However, the plurality of colors may be four colors. The plurality of colors may include white. Alternatively, the pixels may be monochrome pixels without filters. This point also applies to embodiments described later.

In the example of FIG. 3, one pixel is connected to one signal line, and there are multiple sets of such combinations of pixels and signal lines. In FIG. 3, each signal line extends vertically. In the example of FIG. 3, multiple signal lines are associated with the 0th column, and multiple signal lines are associated with the first column. These signal lines form part or all of a signal path through which pixel signals flow. Some of these signal lines or signal paths may be omitted in FIG. 5, which will be described later. A plurality of signal lines associated with one column may be aggregated in the middle to reduce the number. The number of signal lines associated with one column may be one.

In this embodiment, the center of each pixel is positioned on a lattice point of a virtual square lattice. Of course, each pixel center may be located on a lattice point such as a virtual triangular lattice or a virtual hexagonal lattice. Also, each pixel may be arranged one-dimensionally. In this case, the imaging device 100 can be used as a line sensor.

In the example of FIG. 1, the electric circuit 47 includes the second circuit 14, the first circuit 6, the AD conversion circuit 40, the signal processing circuit 43, the output circuit 44, the row scanning circuit 41 and the control circuit . The electric circuit 47 may be arranged on the semiconductor substrate on which the pixel array 1 is formed. A portion of the electrical circuit 47 may be placed on another substrate.

The row scanning circuit 41 selects some rows of pixels among the plurality of pixels in the pixel array 1 . As a result, readout of the signal of the selected pixel is executed.

FIG. 4 schematically shows a configuration example of the second circuit 14, the first circuit 6, the AD conversion circuit 40 and the control circuit 42. As shown in FIG.

In the example of FIG. 4, second circuit 14 includes current source circuit 50 . Current source circuit 50 includes a constant current source 51 . Constant current source 51 is connected to ground 52 .

The first circuit 6 includes a pre-stage circuit 53 and a RAMP comparator 54 . Pre-stage circuit 53 includes a buffer circuit. RAMP comparator 54 includes a first input 54a, a second input 54b, and an output 54c.

AD conversion circuit 40 includes a counter circuit 55 and a memory circuit 56 . The counter circuit 55 includes an AD conversion clock.

Control circuit 42 includes a digital-to-analog converter (DAC) 57 . A control circuit 42 controls the second circuit 14 , the first circuit 6 and the AD conversion circuit 40 .

A signal of a pixel in a certain column in the pixel array 1 is input to the current source circuit 50 . The current source circuit 50 uses the constant current source 51 to output a signal corresponding to the input pixel signal as an analog voltage signal. The voltage signal of the pixel is input to the first input section 54 a of the RAMP comparator 54 via the pre-stage circuit 53 .

DAC 57 outputs a reference signal RAMP. The reference signal RAMP is a voltage signal that changes over time. In one example, the reference signal RAMP is a voltage signal that increases over time. In another example, the reference signal RAMP is a voltage signal that decreases over time. A change in the voltage signal may be monotonically increasing or monotonically decreasing. A change in the voltage signal may be a linear change. The reference signal RAMP is input to the second input 54b of the RAMP comparator 54. FIG.

A voltage is output from the output section 54c of the RAMP comparator 54 as an output signal. In one example, a high level voltage or a low level voltage is output from the output section 54c. The voltage level is reversed when the sign of the difference between the input voltage to the first input 54a and the input voltage to the second input 54b is reversed.

The counter circuit 55 counts the period from when the voltage signal of the reference signal RAMP54 starts to change to when the above-mentioned inversion is performed, using the AD conversion clock. The counter circuit 55 outputs a larger digital signal as the counted period is longer. Thus, the pixel signal is converted from an analog signal to a digital signal by the RAMP comparator 54 and the counter circuit 55 .

The digital pixel signal is stored in the memory circuit 56 . Pixel signals stored in the memory circuit 56 are processed by the signal processing circuit 43 and then output from the output circuit 44 to the outside of the imaging apparatus 100 .

A current source circuit 50, a RAMP comparator 54 and an AD conversion circuit 40 are provided for each column. Current source circuit 50 , RAMP comparator 54 and AD conversion circuit 40 are controlled by control circuit 42 .

Hereinafter, it will be described with reference to FIG. 5 how the signal of the pixel in the pixel array 1 traces from the pixel. One of the plurality of pixels may be referred to as a first pixel 2 hereinafter. One of the multiple pixels may be referred to as a second pixel 3 . A path through which the signal of the first pixel 2 flows may be referred to as a first signal path 4 . A path through which the signal of the second pixel 3 flows may be referred to as a second signal path 5 .

In the first example, the first pixels 2 are pixels of the first type selected from four types of R pixels, B pixels, Gr pixels, and Gb pixels. The second pixels 3 are pixels of the second type selected from four types of R pixels, B pixels, Gr pixels and Gb pixels. The pixels of the first type and the pixels of the second type are different from each other.

In a second example, the first pixel 2 is a pixel of the first color. The second pixels 3 are pixels of the second color. The first color and the second color are different from each other. Specifically, for example, the first pixel 2 includes a color filter of a first color. The second pixels 3 contain color filters of a second color. Also in the first example, the color of the first pixel 2 and the color of the second pixel 3 can be different from each other.

In the example of FIG. 5, the first circuit 6 includes a first voltage line 7 and a second voltage line 8 . A first voltage is applied to the first voltage line 7 . A second voltage is applied to the second voltage line 8 . The first voltage and the second voltage are different from each other.

Hereinafter, the term "first wiring part J1" may be used. The first wiring portion J1 is a wiring portion to which a first voltage is applied. The first wiring portion J1 can correspond to one first voltage line 7 or a plurality of first voltage lines 7 . In the example of FIG. 6, which will be described later, the first wiring portion J1 corresponds to one first voltage line 7. As shown in FIG.

Hereinafter, the term “second wiring portion J2” may be used. The second wiring portion J2 is a wiring portion to which a second voltage is applied. The second wiring portion J2 can correspond to one second voltage line 8 or a plurality of second voltage lines 8 . In the example of FIG. 6, which will be described later, the second wiring portion J2 corresponds to one second voltage line 8. As shown in FIG.

In this embodiment, the first voltage is the power supply voltage. The second voltage is the ground voltage. A first voltage line 7 and a second voltage line 8 are used to operate elements in the first circuit 6 . In one example, first voltage line 7 and second voltage line 8 are utilized as charge transfer paths for operating elements in first circuit 6 . For example, voltage lines 7 and 8 are used in the buffer circuit of the front circuit 53 of FIG. The second voltage may be the power supply voltage and the first voltage may be the ground voltage.

Here, as shown in FIG. 6, a first region 61 is defined as a region closer to the first wiring portion J1 than to the second wiring portion J2 in plan view. A region closer to the second wiring portion J2 than the first wiring portion J1 in plan view is defined as a second region 62 . At this time, in a plan view, in the first signal path 4 , the first intersection portion 4X that intersects the second signal path 5 and the first extension portion 4Z that extends within the second region 62 are the signals of the first pixels 2. are arranged in this order along the flow direction 2F. That is, in the signal flow of the first pixel 2, the first crossing portion 4X is located upstream of the first extending portion 4Z. In the second signal path 5 in a plan view, the second crossing portion 5X crossing the first signal path 4 and the second extending portion 5Z extending in the first region 61 are aligned in the signal flow direction of the second pixel 3. Line up in this order along 3F. That is, in the signal flow of the second pixel 3, the second crossing portion 5X is located upstream of the second extending portion 5Z. As described above, the first wiring portion J1 is a wiring portion to which the first voltage is applied. The second wiring portion J2 is a wiring portion to which a second voltage is applied. In the example of FIG. 6 , the first wiring portion J1 corresponds to one first voltage line 7 . The second wiring portion J2 corresponds to one second voltage line 8 . This can help reduce noise when there are multiple voltage lines 7 and 8 to which different voltages are applied.

Specifically, for example, as shown in FIG. 7, a region in which the ratio of the distance from the first wiring portion J1 to the distance from the second wiring portion J2 in plan view is 1/2 or less is defined as the first one. /2 area 71 . A second 1/2 region 72 is defined as a region in which the ratio of the distance from the second wiring portion J2 to the distance from the first wiring portion J1 in plan view is 1/2 or less. The first extending portion 4Z is a portion where the first signal path 4 extends within the second 1/2 region 72 in plan view. The second extending portion 5Z is a portion where the second signal path 5 extends within the first 1/2 region 71 in plan view. "1/2" in this specific example may be replaced with "1/3" or "1/4". This point also applies to embodiments described later.

Typically, the pixel array 1 is provided on a semiconductor substrate. Planar viewing refers to observation parallel to the thickness direction of the semiconductor substrate, for example. 5 to 7 show the arrangement based on plan view.

An example of the advantages brought about by the above configuration in plan view will be described below.

For example, there may be restrictions on the arrangement order of the first voltage line 7 and the second voltage line 8 in plan view. Such a constraint may be imposed when the first voltage line 7 and the second voltage line 8 are shared between the first circuit 6 and another circuit. Also, the imaging device 100 is an image sensor chip as shown in FIG. 8 may be supplied with a second voltage. In such a case, the arrangement order of the external pads 90 may impose the above restrictions.

Suppose we have the above constraints. In a plan view, in the second circuit 14, the first signal path 4 extends relatively close to the first voltage line 7 (left side position in the example of FIG. 5), and the second signal path 5 extends to the second voltage line. Suppose that it is necessary to extend the position closer to 8 (the right position in the example of FIG. 5). Furthermore, it is assumed that the noise component emitted by the second voltage line 8 is smaller than the noise component emitted by the first voltage line 7 . In such a case, due to the above-described crossing, the first signal path 4 can be brought closer to the second voltage line 8 and the second signal path 5 can be brought closer to the first voltage line 7 in plan view. The noise superimposed on the signal flowing through the first signal path 4 by the first circuit 6 is smaller than the noise superimposed on the signal flowing through the second signal path 5 by the first circuit 6 due to the contribution of the above-described crossing. can be done.

A technique that can reduce the noise superimposed on the signal flowing through the first signal path 4 by the first circuit 6 compared to the noise superimposed on the signal flowing through the second signal path 5 by the first circuit 6 is useful in various situations. obtain. This can be useful, for example, if one wishes to have less noise superimposed on the signal of the first pixel 2 than the noise superimposed on the signal of the second pixel 3 . Also, it is assumed that the drive mode of the imaging device 100 includes a normal mode and a pixel addition mode. Control circuit 42 and row operation circuit 41 control the drive mode. Here, the normal mode is a mode in which the signal of the first pixel 2 flows through the first signal path 4 and the signal of the second pixel 3 flows through the second signal path 5 . The pixel addition mode is a mode in which the signals of the first pixels 2 and the signals of the second pixels 3 are mixed in the pixel array 1 and the resulting mixed signal flows through the first signal path 4 . According to the above technique, the noise superimposed on the mixed signal by the first circuit 6 can be reduced in the pixel addition mode.

The illustrated pixel array 1 and electrical circuit 47 are merely examples. The configurations of the pixel array 1 and the electric circuit 47 are not particularly limited. The presence of all of the second circuit 14, the first circuit 6, the AD conversion circuit 40, the signal processing circuit 43, the output circuit 44, the row scanning circuit 41 and the control circuit 42 is not essential. For example, the second circuit 14 can be omitted. These points are the same in the embodiments described later.

The first circuit 6 and/or the second circuit 14 may be analog circuits such as current source circuits. The first circuit 6 and/or the second circuit 14 may be digital circuits operating with clocks or the like.

FIG. 8 is a cross-sectional view of the imaging device 100 cut along the thickness direction, according to an example. As shown in FIG. 8, imaging device 100 includes insulating layer 91 . In this example, the insulating layer 91 is provided on the semiconductor substrate 92 . A plurality of wiring layers are provided at different depth positions in the insulating layer 91 . In the example of FIG. 8, the multiple wiring layers include a first wiring layer 81, a second wiring layer 82, a third wiring layer 83, and a fourth wiring layer . One or all of the first signal path 4, the second signal path 5, the first voltage line 7 and the second voltage line 8 may be provided in the same wiring layer. One or all of these may be provided in wiring layers different from each other.

In this embodiment, the imaging device 100 includes two wiring layers that are different layers in the multilayer wiring layer. One of the two wiring layers includes a first intersection 4X. The other of the two wiring layers includes a second intersection 5X. By doing so, it is easy to realize the intersection of the first signal path 4 and the second signal path 5 in plan view. Said one of the two wiring layers can be any of the wiring layers 81 to 84 of FIG. Said other of the two wiring layers can be any of the wiring layers 81 to 84 of FIG.

In the example of FIG. 9, the plurality of pixels includes first OB pixel 65, which is an optical black pixel. The imaging device 100 includes a signal processing circuit 43 and a first OB path 66 through which a signal of a first OB pixel 65 flows. In plan view, the first OB path 66 has a first OB extending portion 66Z extending within the second region 62 . The signal processing circuit 43 performs optical black correction using the signal of the first OB pixel 65 via the first OB extension section 66Z on the signal of the first pixel 2 via the first extension section 4Z. do. Doing so is suitable for reducing the noise component superimposed on the signal of the first pixel 2 in the second region 62 . Although not shown in FIG. 9, an AD conversion circuit 40 may be provided between the signal processing circuit 43 and the first circuit 6. FIG.

Specifically, for example, the first OB extension portion 66Z is a portion of the first OB path 66 that extends within the second 1/2 region 72 in plan view. The first extending portion 4Z is a portion of the first signal path 4 that extends within the second 1/2 region 72 in plan view.

In the example of FIG. 10, the plurality of pixels includes second OB pixel 67, which is an optical black pixel. The imaging device 100 includes a signal processing circuit 43 and a second OB path 68 through which signals of second OB pixels 67 flow. In plan view, the second OB path 68 has a second OB extending portion 68Z extending within the first region 61 . The signal processing circuit 43 performs optical black correction using the signal of the second OB pixel 67 via the second OB extension 68Z on the signal of the second pixel 3 via the second extension 5Z. do. Doing so is suitable for reducing the noise component superimposed on the signal of the second pixel 3 in the first region 61 .

Specifically, for example, the second OB extension portion 68Z is a portion of the second OB path 68 that extends within the first 1/2 region 71 in plan view. The second extending portion 5Z is a portion of the second signal path 5 that extends within the first 1/2 region 71 in plan view.

In this embodiment, the pixels form a pixel array 1 having at least one row and a plurality of columns. The column to which the first pixels 2 belong in the pixel array 1 and the column to which the second pixels 3 belong in the pixel array 1 are adjacent to each other.

In the present embodiment, the first wiring portion J1, the second wiring portion J2, the first extending portion 4Z, and the second extending portion 5Z extend parallel to each other in plan view. Here, as described above, the first wiring portion J1 corresponds to one first voltage line 7 in the example of FIG. The second wiring portion J2 corresponds to one second voltage line 8 . Such a parallel layout is advantageous from the viewpoint of miniaturization. On the other hand, this parallel layout is not necessarily advantageous for noise reduction. Therefore, in this parallel layout, the noise reduction described above is likely to exhibit its effect.

In the present embodiment, the first wiring portion J1, the second wiring portion J2, the first extending portion 4Z, and the second extending portion 5Z extend straight in plan view.

The first voltage on the first voltage line 7 may be a fixed voltage or a time-varying voltage. The same is true for the second voltage on the second voltage line 8 . Examples of the fixed voltage include the voltage of the mode signal and the voltage of the register signal. AC voltages with different frequencies are exemplified as time-varying voltages corresponding to the first voltage and the second voltage. A voltage of a clock signal is exemplified as such an AC voltage. One of the first voltage and the second voltage may be the voltage of the clock signal and the other may be the voltage of the data signal. The first voltage and the second voltage may be voltages of pulse signals with mutually different timings and/or mutually different duty ratios.

In plan view, the intersection may be in the region between the first circuit 6 and the second circuit 14, may be in the region above the first circuit 6, or may be in the region above the second circuit 14. may be made in An element isolation region may be provided between the first circuit 6 and the second circuit 14 to electrically isolate the first circuit 6 and the second circuit 14 . In plan view, the intersection may be made at a position overlapping with the element isolation region.

In the present embodiment, the first intersections 4X are portions through which analog signals of the first pixels 2 pass. The second crossing portion 5X is a portion through which the analog signal of the second pixel 3 passes. Further, in the present embodiment, the first extended portion 4Z is a portion through which the analog signal of the first pixel 2 passes. The second extended portion 5Z is a portion through which analog signals of the second pixels 3 pass. The same applies to the first OB extension 66Z and the second OB extension 68Z, which are portions through which corresponding analog signals pass. The same applies to the third extending portion 11Z, the third extending portion 4BZ, the fourth extending portion 5Z, and the fourth extending portion 5BZ, which will be described later, and are portions through which the corresponding analog signals pass.

The intersections at the intersections 4X and 5X may be the only intersections of the first signal path 4 and the second signal path 5 in plan view. In a plan view, the intersection of the first signal path 4 and the second signal path 5 may be further made outside of the portions 4X and 5X. For example, further crossings may be made downstream of the first circuit 6 in plan view. Additional crossovers may be made outside the imaging device 100 downstream of the output circuit 44 in plan view. Here, downstream refers to downstream in the signal flow direction 2F of the pixel 2 and in the signal flow direction 3F of the pixel 3 .

The second circuit 14 may include multiple voltage lines. Specifically, in the example of FIG. 11 , the plurality of voltage lines includes one third voltage line 15 and two fourth voltage lines 16 (fourth and fifth voltage lines in the present disclosure) adjacent to the third voltage line 15 . An example of a voltage line) and The one fourth voltage line 16, the third voltage line 15, and the other fourth voltage line 16 are arranged in this order in plan view. In this example, the pitch of the plurality of voltage lines 16 and 15 in the second circuit 14 differs from the pitch of the voltage lines 7 and 8 in the first circuit 6 in plan view. Here, the pitch of the voltage lines refers to the distance between the center line extending in the longitudinal direction of the voltage line and the center line extending in the longitudinal direction of the adjacent voltage line.

In one specific example, a third voltage is applied to the third voltage line 15 . A fourth voltage is applied to the fourth voltage line 16 . The third voltage and the fourth voltage are different from each other.

The third voltage may be the same as one of the first voltage and the second voltage. The fourth voltage may be the same as the other of the first voltage and the second voltage. The third voltage may be different from both the first voltage and the second voltage. The fourth voltage may be different from both the first voltage and the second voltage.

In this embodiment, the third voltage of the third voltage line 15 is the power supply voltage. A fourth voltage on the fourth voltage line 16 is the ground voltage. A third voltage line 15 and a fourth voltage line 16 are utilized to operate elements in the second circuit 14 . Voltage lines 15 and 16 are used, for example, in current source circuit 50 of FIG. The fourth voltage may be the power supply voltage and the third voltage may be the ground voltage. Voltage line 15 and voltage line 16 are connected to, for example, a transistor in current source circuit 50 to supply a voltage to the transistor.

The third voltage may be a fixed voltage or a time-varying voltage. The same applies to the fourth voltage. Examples of the fixed voltage include the voltage of the mode signal and the voltage of the register signal. AC voltages with different frequencies are exemplified as time-varying voltages corresponding to the third voltage and the fourth voltage. A voltage of a clock signal is exemplified as such an AC voltage. One of the third voltage and the fourth voltage may be the voltage of the clock signal and the other may be the voltage of the data signal. The third voltage and the fourth voltage may be voltages of pulse signals with mutually different timings and/or mutually different duty ratios.

Below, the term "third wiring part J3" may be used. The third wiring portion J3 is a wiring portion to which a third voltage is applied. The third wiring portion J3 may correspond to one third voltage line 15 or multiple third voltage lines 15 . In the example of FIG. 11 , the third wiring portion J3 corresponds to one third voltage line 15 .

Hereinafter, the term "fourth wiring part J4" may be used. The fourth wiring portion J4 is a wiring portion to which a fourth voltage is applied. The fourth wiring portion J4 can correspond to one fourth voltage line 16 or multiple fourth voltage lines 16 . In the example of FIG. 11 , the fourth wiring portion J4 corresponds to two fourth voltage lines 16 .

In the example of FIG. 11, the imaging device 100 includes a second circuit 14 including a third wiring portion J3 and a fourth wiring portion J4. In plan view, the pitch between the first wiring portion J1 and the second wiring portion J2 and the pitch between the third wiring portion J3 and the fourth wiring portion J4 are different from each other. A region between the third wiring portion J3 and the fourth wiring portion J4 in plan view is defined as a pitch region 14P. At this time, in a plan view, in the first signal path 4, the portion extending within the pitch region 14P, the first intersection portion 4X, and the first extension portion 4Z are arranged along the signal flow direction 2F of the first pixels 2. and line up in this order. In a plan view, in the second signal path 5, the portion extending within the pitch region 14P, the second crossing portion 5X, and the second extending portion 5Z are aligned along the signal flow direction 3F of the second pixels 3. Line up in order. In this example, the first wiring portion J1 corresponds to one first voltage line 7 . The second wiring portion J2 corresponds to one second voltage line 8 . The third wiring portion J3 corresponds to one third voltage line 15 . The fourth wiring portion J4 corresponds to two fourth voltage lines 16 . The case where there is a pitch difference as described above is an example of a case where the layout with the intersection can contribute to noise reduction. Specifically, for example, when the pitches of the first circuit 6 and the second circuit 14 are different, if the signal paths 4 and 5 are extended straight in a plan view, there is a possibility that they cannot be brought close to the desired voltage line. , higher compared to when the pitches are the same. However, the crossing facilitates access to the desired voltage line.

Specifically, in the example of FIG. 11 , the pitch between the first wiring portion J1 and the second wiring portion J2 is the pitch between the first voltage line 7 and the second voltage line 8 . The pitch between the third wiring portion J3 and the fourth wiring portion J4 is the pitch between the third voltage line 15 and the fourth voltage line 16 . The pitch region 14P is the region between the third voltage line 15 and the fourth voltage line 16. FIG.

As described above, in the example of FIG. 11, the pitch of the voltage lines 15 and 16 in the second circuit 14 and the pitch of the voltage lines 7 and 8 in the first circuit 6 are different from each other in plan view. Specifically, for example, the pitch of the plurality of voltage lines 15 and 16 in the second circuit 14 is the same as the pitch of the columns of pixels (hereinafter sometimes referred to as one column pitch). The pitch of the voltage lines 7, 8 in the first circuit 6 is different from one column pitch. The voltage lines 7 and 8 have a pitch that is twice the pitch of the columns of pixels (hereinafter sometimes referred to as a 2-column pitch).

As shown in FIG. 12, the pitch of the plurality of voltage lines 15 and 16 in the second circuit 14 and the pitch of the voltage lines 7 and 8 in the first circuit 6 may be the same in plan view.

A pixel signal may be input to the first circuit 6 via a signal path. Pixel signals may not be input to the first circuit 6 .

A pixel signal may be input to the second circuit 14 via a signal path. Pixel signals may not be input to the second circuit 14 .

(Second embodiment)
A second embodiment will be described below. In the second embodiment, the same reference numerals may be assigned to the same contents as in the first embodiment, and description thereof may be omitted.

FIG. 13 shows the pixel array 1, second circuit 14 and first circuit 6 in the second embodiment.

In the example of FIG. 13, the pixel array 1 includes multiple pixels. One of the multiple pixels may be referred to as the third pixel 9 . One of the multiple pixels may be referred to as the fourth pixel 10 . A path through which the signal of the third pixel 9 flows may be referred to as a third signal path 11 . A path through which the signal of the fourth pixel 10 flows may be referred to as a fourth signal path 12 .

In the example of FIG. 13, the first circuit 6 includes multiple first voltage lines 7 and multiple second voltage lines 8 . The first voltage lines 7 and the second voltage lines 8 are alternately and repeatedly arranged in plan view.

In the example of FIG. 13, the number of first voltage lines 7 is plural, and the number of second voltage lines 8 is plural. FIG. 14 shows the first region 61 and the second region 62 in this case. In a plan view, in the first signal path 4, the first intersection 4X that intersects with the second signal path 5 and the first extension 4Z that extends in the second region 62 are aligned in the signal flow direction of the first pixel 2. Line up in this order along 2F. In a plan view, in the second signal path 5, the second intersection 5X that intersects the first signal path 4 and the second extension extending in the first region 61 are arranged in the signal flow direction 3F of the second pixel 3. line up in this order. Here, the first wiring portion J1 is a wiring portion to which a first voltage is applied. The second wiring portion J2 is a wiring portion to which a second voltage is applied. In the example of FIG. 13 , the first wiring portion J1 corresponds to the multiple first voltage lines 7 . The second wiring portion J2 corresponds to the plurality of second voltage lines 8 .

Specifically, for example, as shown in FIG. 15, the first extending portion 4Z is a portion where the first signal path 4 extends within the second 1/2 region 72 in plan view. The second extending portion 5Z is a portion where the second signal path 5 extends within the first 1/2 region 71 in plan view.

In the example of FIG. 13 , the multiple voltage lines in the second circuit 14 include multiple third voltage lines 15 and multiple fourth voltage lines 16 . The third voltage lines 15 and the fourth voltage lines 16 are alternately and repeatedly arranged in plan view. In this example, the pitch of the plurality of voltage lines 15 and 16 in the second circuit 14 differs from the pitch of the voltage lines 7 and 8 in the first circuit 6 in plan view.

In the example of FIG. 13, the multiple voltage lines 15 and 16 in the second circuit 14 have a 1-column pitch. The voltage lines 7, 8 in the first circuit 6 have a pitch different from one column pitch. Specifically, for example, the voltage lines 7 and 8 have a two-column pitch.

In the example of FIG. 13, the imaging device 100 includes a second circuit 14 including a third wiring portion J3 and a fourth wiring portion J4. In plan view, the pitch between the first wiring portion J1 and the second wiring portion J2 and the pitch between the third wiring portion J3 and the fourth wiring portion J4 are different from each other. A region between the third wiring portion J3 and the fourth wiring portion J4 in plan view is defined as a pitch region 14P. At this time, in a plan view, in the first signal path 4, the portion extending within the pitch region 14P (an example of the first pitch portion of the present disclosure), the first intersection portion 4X, and the first extension portion 4Z They are arranged in this order along the signal flow direction 2F of one pixel 2 . In a plan view, in the second signal path 5 , the portion extending within the pitch region 14P (an example of the second pitch portion of the present disclosure), the second intersection portion 5X, and the second extension portion 5Z are arranged in this order along the signal flow direction 3F. In the example of FIG. 13 , the first wiring portion J1 corresponds to the multiple first voltage lines 7 . The second wiring portion J2 corresponds to the plurality of second voltage lines 8 . The third wiring portion J3 corresponds to the plurality of third voltage lines 15 . The fourth wiring portion J4 corresponds to the plurality of fourth voltage lines 16 .

Specifically, in the example of FIG. 13 , the pitch between the first wiring portion J1 and the second wiring portion J2 is the pitch between the first voltage line 7 and the second voltage line 8 . The pitch between the third wiring portion J3 and the fourth wiring portion J4 is the pitch between the third voltage line 15 and the fourth voltage line 16 . The pitch region 14P is the region between the third voltage line 15 and the fourth voltage line 16. FIG.

FIG. 16 shows a detailed example of the second circuit 14 and the first circuit 6. FIG. Specifically, FIG. 16 shows the second circuit 14 and the first circuit 6 in plan view. A portion of the signal path is omitted in FIG. The same applies to FIGS. 19A and 19B described later.

13, in FIG. 16, the first signal path 4 and the second signal path 5 intersect in the area above the first circuit 6 in plan view. As described above, in plan view, this intersection may be in the area between the first circuit 6 and the second circuit 14, or may be in the area above the first circuit 6. It may be done in the area on 14. Also, this intersection may be performed at a position overlapping with the element isolation region in plan view.

In plan view, the pitch direction in which the voltage lines 7 and 8 in the first circuit 6 are arranged is defined as a first horizontal direction HD1, and the direction orthogonal to the first horizontal direction HD1 is defined as a first vertical direction VD1. In a plan view, in the first circuit 6, the first transistor TG1 and the second transistor TG2 are arranged along the first horizontal direction HD1 between the voltage lines 7 and 8 adjacent to each other.

In the example of FIG. 16, the first transistor TG1 is a first conductivity type transistor. The second transistor TG2 is a second conductivity type transistor. The first conductivity type and the second conductivity type are different from each other. Specifically, in the example of FIG. 16, the first conductivity type is the P type. The second conductivity type is N type. More specifically, for example, the first transistor TG1 is a P-channel FET, and the second transistor TG2 is an N-channel FET. The first transistor TG1 may be an N-channel FET and the second transistor TG2 may be a P-channel FET. In this case, the arrangement of voltage lines 7 and 8 is reversed from that in the example of FIG.

The first transistor TG1 is connected to the first voltage line 7 . The second transistor TG2 is connected to the second voltage line 8 .

In plan view, the pitch direction in which the voltage lines 15 and 16 are arranged in the second circuit 14 is defined as a second horizontal direction HD2, and the direction orthogonal to the second horizontal direction HD2 is defined as a second vertical direction VD2. In a plan view, in the second circuit 14, the third transistor TG3 and the fourth transistor TG4 are arranged along the second vertical direction VD2 between the voltage lines 15 and 16 adjacent to each other.

In the example of FIG. 16, the third transistor TG3 is a first conductivity type transistor. The fourth transistor TG4 is a second conductivity type transistor. Specifically, for example, the third transistor TG3 is a P-channel FET, and the fourth transistor TG4 is an N-channel FET. The third transistor TG3 may be an N-channel FET and the fourth transistor TG4 may be a P-channel FET.

A third transistor TG3 is connected to the third voltage line 15 . A fourth transistor TG4 is connected to the fourth voltage line 16 .

In the example of FIG. 16, in plan view, the second circuit 14 outputs pixel signals for each column pitch.

Thus, in the example of FIG. 16, the imaging device includes the second circuit 14 . The first circuit 6 includes a first transistor TG1 of a first conductivity type and a second transistor TG2 of a second conductivity type different from the first conductivity type. The second circuit 14 includes a first conductivity type third transistor TG3 and a second conductivity type fourth transistor TG4. The center of gravity of the gate of the first transistor TG1 and the gate of the second transistor TG2 is defined as a first center of gravity. The center of gravity of the gate of the third transistor TG3 and the gate of the fourth transistor TG4 is defined as a second center of gravity. In plan view, the alignment direction HD1 of the first transistor TG1 and the second transistor TG2 is different from the alignment direction VD2 of the third transistor TG3 and the fourth transistor TG4. At this time, in a plan view, in the first signal path 4, the portion closest to the second center of gravity and the portion closest to the first center of gravity are aligned along the signal flow direction 2F of the first pixels 2. Line up in order. Here, in the first signal path 4, the portion closest to the second center of gravity may be included in the portion extending within the pitch region 14P, and the portion closest to the first center of gravity may be the first extending portion 4Z. may be included in In addition, in the second signal path 5, the portion closest to the second center of gravity may be included in the portion extending within the pitch region 14P, and the portion closest to the first center of gravity may be included in the second extending portion 5Z. may be included.

In a plan view, in the second signal path 5 , the portion closest to the second center of gravity and the portion closest to the first center of gravity are arranged in this order along the signal flow direction 3F of the second pixels 3 . In this way, it is easy to make the first circuit 6 small in the arrangement direction VD1 in plan view. It is easy to make the second circuit 14 smaller in the arrangement direction HD2 in plan view. Therefore, by providing such a difference in arrangement of the transistors, it becomes easy to change the shape of the two circuits 6 and 14 in plan view. This can effectively address space constraints in circuit layouts. However, the difference in arrangement of the transistors may result in layout restrictions of the first signal path 4 and the second signal path 5 in the first circuit 6 and the second circuit 14 . For example, if there is a difference in the arrangement of the transistors, a difference in the pitch of the voltage lines between the circuits 6 and 14 tends to occur due to the voltage application from the voltage lines to the transistors. Therefore, in the example of FIG. 16, the layout with the crossing can contribute to noise reduction.

In one example, the gate of the first transistor TG1 and the gate of the second transistor TG2 are one common electrode. In this case, "the center of gravity of the gate of the first transistor TG1 and the gate of the second transistor TG2" is the center of gravity of this common electrode. In another example, the gate of the first transistor TG1 and the gate of the second transistor TG2 are electrodes independent of each other. In this case, "the center of gravity of the gate of the first transistor TG1 and the gate of the second transistor TG2" is the center of gravity of these two electrodes.

In one example, the gate of the third transistor TG3 and the gate of the fourth transistor TG4 are one common electrode. In this case, "the center of gravity of the gate of the third transistor TG3 and the gate of the fourth transistor TG4" is the center of gravity of this common electrode. In another example, the gate of the third transistor TG3 and the gate of the fourth transistor TG4 are electrodes independent of each other. In this case, "the center of gravity of the gate of the third transistor TG3 and the gate of the fourth transistor TG4" is the center of gravity of these two electrodes.

As is well known, the center of gravity refers to the point at which the resultant force of gravity acting on each part of an object acts. A region in which at least one electrode constituting the gate of the first transistor TG1 and the gate of the second transistor TG2 extends is measured by a measuring instrument such as a scanning electron microscope (SEM), and the first center of gravity can be identified from the measured region. Similarly, a region in which at least one electrode constituting the gate of the third transistor TG3 and the gate of the fourth transistor TG4 extends is measured by a measuring device such as an SEM, and the second center of gravity can be specified from the measured region.

In the example of FIG. 16, the first circuit 6 includes a first conductivity type first transistor TG1 and a second conductivity type second transistor TG2 different from the first conductivity type. The first voltage line 7 of the first wiring portion J1 is connected to the first transistor TG1. A second voltage line 8 of the second wiring portion J2 is connected to the second transistor TG2. In this way, the first transistor TG1 can be operated using the first voltage of the first wiring part J1. The second transistor TG2 can be operated using the second voltage of the second wiring portion J2.

The transistor-related techniques described above are also applicable to other embodiments, such as the first embodiment.

In the example of FIG. 13 , the multiple pixels include the third pixel 9 . The imaging device 100 includes a third signal path 11 through which signals of the third pixels 9 flow. As shown in FIG. 14 , the third signal path 11 has a third extending portion 11Z extending within the second region 62 in plan view. Such a layout facilitates correction to reduce noise in the signals of the first pixel 2 and the third pixel 9 . Specifically, for example, according to such a layout, compared to the case where one of the first signal path 4 and the third signal path 11 extends within the second region 62 and the other extends within the first region 61, the In one circuit 6, the noise components superimposed on the signal of the first pixel 2 and the signal of the third pixel 9 are less likely to vary. Therefore, such a layout is suitable for reducing the noise of these signals with correction of similar correction conditions.

Specifically, for example, as shown in FIG. 15, the third extending portion 11Z is a portion extending within the second 1/2 region 72 in plan view.

In the example of FIG. 13 , the multiple pixels include the fourth pixel 10 . The imaging device 100 includes a fourth signal path 12 through which signals of the fourth pixels 10 flow. As shown in FIG. 14 , the fourth signal path 12 has a fourth extending portion 12Z extending within the first region 61 in plan view. Such a layout facilitates correction to reduce noise in the signal of the second pixel 3 and the signal of the fourth pixel 10 . Specifically, according to such a layout, compared to the case where one of the second signal path 5 and the fourth signal path 12 extends within the first region 61 and the other extends within the second region 62 , the first circuit 6, the noise components superimposed on the signal of the second pixel 3 and the signal of the fourth pixel 10 are less likely to vary. Therefore, such a layout is suitable for reducing the noise of these signals with similar correction conditions.

Specifically, for example, as shown in FIG. 15, the fourth extending portion 12Z is a portion extending within the first 1/2 region 71 in plan view.

An example of a correction method for reducing noise will be described below.

In the example of FIG. 17 , the imaging device 100 has a signal processing circuit 43 . The signal processing circuit 43 removes noise superimposed in the second region 62 on both the signal of the first pixel 2 via the first extension 4Z and the signal of the third pixel 9 via the third extension 11Z. Perform a correction that reduces the component. According to this example, it is easy to apply similar correction conditions to the correction of the signal of the first pixel 2 and the correction of the signal of the third pixel 9 .

Specifically, for example, the first extending portion 4Z is a portion of the first signal path 4 that extends within the second 1/2 region 72 in plan view. The third extending portion 11Z is a portion of the third signal path 11 that extends within the second 1/2 region 72 in plan view. The signal processing circuit 43 processes both the signal of the first pixel 2 via the first extension 4Z and the signal of the third pixel 9 via the third extension 11Z in the second 1/2 region 72. Correction is performed to reduce the superimposed noise component.

In one specific example, the correction is an optical black correction. This particular implementation utilizes the first OB pixel 65 and first OB path 66 previously described. The signal processing circuit 43 processes both the signal of the first pixel 2 via the first extension 4Z and the signal of the third pixel 9 via the third extension 11Z via the first OB extension 66Z. Optical black correction using the signal of the first OB pixel 65 is performed.

In the example of FIG. 18 , the imaging device 100 has a signal processing circuit 43 . The signal processing circuit 43 removes noise superimposed in the first region 61 on both the signal of the second pixel 3 via the second extension 5Z and the signal of the fourth pixel 10 via the fourth extension 12Z. Perform a correction that reduces the component. According to this example, it is easy to apply similar correction conditions to the correction of the signal of the second pixel 3 and the correction of the signal of the fourth pixel 10 .

Specifically, for example, the second extending portion 5Z is a portion of the second signal path 5 that extends within the first 1/2 region 71 in plan view. The fourth extending portion 12Z is a portion of the fourth signal path 12 that extends within the first 1/2 region 71 in plan view. The imaging device 100 superimposes both the signal of the second pixel 3 via the second extension 5Z and the signal of the fourth pixel 10 via the fourth extension 12Z in the first half area 71. perform a correction that reduces the noise component that is

In one specific example, the correction is an optical black correction. This particular implementation utilizes the second OB pixel 67 and second OB path 68 previously described. The signal processing circuit 43 processes both the signal of the second pixel 3 via the second extension 5Z and the signal of the fourth pixel 10 via the fourth extension 12Z via the second OB extension 68Z. Optical black correction using the signal of the second OB pixel 67 is performed.

In the example of FIG. 13, in plan view, the portion of the third signal path 11 extending from the third pixel 9 to the second region 62 and the portion of the fourth signal path 12 extending from the fourth pixel 10 to the first region 61 are , not crossed.

Specifically, for example, in plan view, a portion extending from the third pixel 9 to the second 1/2 region 72 in the third signal path 11 and a portion extending from the fourth pixel 10 to the first 1/2 area 72 in the fourth signal path 12 It does not intersect with the portion extending to the /2 region 71 .

In the first example, the first pixel 2 and the third pixel 9 are first-type pixels selected from four types of R pixels, B pixels, Gr pixels, and Gb pixels. The second pixels 3 are pixels of the second type selected from four types of R pixels, B pixels, Gr pixels and Gb pixels. The pixels of the first type and the pixels of the second type are different from each other. The first example is suitable for reducing the signal noise of the first pixel 2 and the third pixel 9, which are the first type pixels, by correction under similar correction conditions.

Furthermore, the fourth pixel 10 may be a second type pixel. This example is suitable for reducing the signal noise of the second pixel 3 and the fourth pixel 10, which are the type 2 pixels, by correction under similar correction conditions.

In the specific example of the first example, all of the signal paths of the first type pixels have portions extending within the first region 61 in plan view. All of the signal paths of the second-type pixels have portions extending within the second region 62 in plan view.

More specifically, for example, all of the signal paths of the first-type pixels have portions extending within the first 1/2 region 71 in plan view. All of the signal paths of the second type pixels have portions extending within the second 1/2 region 72 in plan view.

In a second example, the first pixel 2 contains a first color filter. The second pixel 3 contains a second color filter. A third pixel 9 includes a third color filter. The first color filter and the third color filter are color filters of the first color. The second color filter is a color filter of a second color different from the first color. The second example is suitable for reducing the signal noise of the first pixel 2 and the third pixel 9, which are pixels including color filters of the first color, by correction under similar correction conditions.

Furthermore, the fourth pixel 10 may contain a fourth color filter of the second color. This example is suitable for reducing the signal noise of the second pixel 3 and the fourth pixel 10, which are pixels including color filters of the second color, by correction under similar correction conditions.

In the specific example of the second example, all of the signal paths of the pixels including the color filters of the first color have portions extending within the second region 62 in plan view. All of the signal paths of the pixels including the color filter of the second color have portions extending within the first region 61 in plan view.

More specifically, for example, all of the signal paths of the pixels including the color filters of the first color have portions extending within the second 1/2 region 72 in plan view. All of the signal paths of the pixels including the color filters of the second color have portions extending within the first 1/2 region 71 in plan view.

In the example of FIG. 16 , in plan view, the second signal path 5 and the fourth signal path 12 are different from each other in the first region 61 (specifically, in the first 1/2 region 71). 1 extends the portion based on the voltage line 7 . However, in plan view, the second signal path 5 and the fourth signal path 12 are connected to the same first voltage line 7 in the first region 61 (specifically, in the first 1/2 region 71). It may extend the base portion.

In the example of FIG. 16 , in plan view, the first signal path 4 and the third signal path 11 are located in the same second region 62 (specifically, in the second 1/2 region 72). It extends the part based on the voltage line 8 . However, in plan view, the first signal path 4 and the third signal path 11 are different from each other in the second region 62 (specifically, in the second 1/2 region 72). may extend the portion based on

In the specific example of FIG. 16, the first voltage on the first voltage line 7 is the power supply voltage. A second voltage on the second voltage line 8 is the ground voltage. In FIG. 16, "VDD" represents power supply voltage. "GND" represents ground voltage. The second voltage may be the power supply voltage and the second voltage may be the ground voltage.

By the way, as measures against noise, it is known to provide a shield line or widen the interval between signal paths. However, these measures lead to an increase in layout area. On the other hand, in the second embodiment, some signal paths are provided in the first area 61 and another part of the signal paths are provided in the second area 62 to realize noise countermeasures. That is, in the second embodiment, a part of the signal path is provided near the first voltage line 7 and another part of the signal path is provided near the second voltage line 8, thereby realizing noise countermeasures. . In this way, an increase in layout area can be suppressed.

By using a plurality of signal paths provided within one pixel column pitch, it is possible to speed up processing by parallel processing and to reduce noise by feedback to the pixel array 1 or the like. Such high speed and low noise are achieved, for example, in an image sensor with a laminated structure. According to the noise countermeasures described above, such high speed and low noise can be achieved while suppressing an increase in layout area.

When the first signal path 4 has a feedback path feeding back to the pixel array 1, the feedback path may have a portion extending within the second region 62 in plan view. When the second signal path 5 has a feedback path feeding back to the pixel array 1, the feedback path may have a portion extending within the first region 61 in plan view. When the third signal path 11 has a feedback path feeding back to the pixel array 1, the feedback path may have a portion extending within the second region 62 in plan view. When the fourth signal path 12 has a feedback path feeding back to the pixel array 1, the feedback path may have a portion extending within the first region 61 in plan view.

Specifically, when the first signal path 4 has a feedback path that feeds back to the pixel array 1, the feedback path has a portion extending within the second 1/2 region 72 in plan view. may When the second signal path 5 has a feedback path feeding back to the pixel array 1, the feedback path may have a portion extending within the first 1/2 region 71 in plan view. When the third signal path 11 has a feedback path feeding back to the pixel array 1, the feedback path may have a portion extending within the second 1/2 region 72 in plan view. When the fourth signal path 12 has a feedback path feeding back to the pixel array 1, the feedback path may have a portion extending within the first 1/2 region 71 in plan view.

In FIG. 13, the second voltage line 8, the first voltage line 7, the second voltage line 8, and the first voltage line 7 are arranged in this order in plan view. Here, consider the case where the first circuit 6 is expanded and a second voltage line 8 is further provided at the position of the dotted line D. FIG. In this case, in a plan view, the first signal path 4 extends within the portion of the second region 62 (specifically, the second 1/2 region 72) based on the second voltage line 8 at the position of the dotted line D. Alternatively, the layout of the first signal path 4 may be changed. Generally speaking, in a plan view, the first signal path 4 extends within any portion of the second region 62 (specifically, the second 1/2 region 72) based on the second voltage line 8. good too. Similarly, the second signal path 5 may extend within any portion of the first region 61 (specifically, the first half region 71 ) based on the first voltage line 7 . The same is true for other signal paths.

As described above, in the example of FIG. 16, the pitch of the voltage lines 15 and 16 in the second circuit 14 and the pitch of the voltage lines 7 and 8 in the first circuit 6 are different from each other in plan view. Specifically, for example, the plurality of voltage lines 15 and 16 in the second circuit 14 have one column pitch. The voltage lines 7, 8 in the first circuit 6 have a two-column pitch instead of a one-column pitch.

In plan view, the pitch of the voltage lines 15 and 16 in the second circuit 14 and the pitch of the voltage lines 7 and 8 in the first circuit 6 may be the same.

19A and 19B, the situation in which the technique of the second embodiment is advantageous when the pitch of the voltage lines 15, 16 and the pitch of the voltage lines 7, 8 are the same will be described.

In the example of FIG. 19A, the imaging device comprises a circuit 94 separate from the first circuit 6 and the second circuit 14. In the example of FIG. Circuit 94 is supplied with voltage by a plurality of voltage lines 95 and 96 . Voltage lines 95 and 96 are power lines used by another circuit 94 but can be noise sources for signal paths 97 and 98 .

In this example, the voltage on voltage line 95 is the power supply voltage. The voltage on voltage line 96 is the ground voltage. In FIG. 19A, "VDD2" represents the power supply voltage. "GND2" represents a ground voltage. The voltage of the voltage line 96 may be the power supply voltage, and the voltage of the voltage line 95 may be the ground voltage.

In the example of FIG. 19A, in a plan view, signal paths 97 for Gr pixel signals and signal paths 98 for Gb pixel signals are alternately and repeatedly arranged. Intervals between the signal paths 97 and 98 and the voltage lines 95 and 96 are secured in plan view. This suppresses superimposition of noise from the voltage lines 95 and 96 onto the signals of the signal paths 97 and 98 .

For further noise reduction, the signal path 97s and the signal path 98s intersect in the area M1 as shown in FIG. 98s can extend at a position near the first voltage line 7 . In plan view, by crossing the signal path 97t and the signal path 98t in the region M2, the signal path 97t extends near the second voltage line 8 and the signal path 98t extends near the first voltage line 7. can be done. This realizes a configuration in which all the signal paths 97 extend near the second voltage line 8 and all the signal paths 98 extend near the first voltage line 7 in plan view. In this way, by correcting the signals of the plurality of signal paths 97 to reduce the noise derived from the second voltage line 8, the noise of these signals can be preferably reduced. By correcting the signals of the plurality of signal paths 98 to reduce the noise derived from the first voltage line 7, the noise of these signals can be preferably reduced. For this reason, even when the pitch of the voltage lines 15 and 16 and the pitch of the voltage lines 7 and 8 are the same, the technique of the second embodiment can provide advantages. Here, the position near the first voltage line 7 in plan view corresponds to the first region 61 , specifically to the first 1/2 region 71 , for example. A position closer to the second voltage line 8 in plan view corresponds to the second region 62 , specifically, for example, the second half region 72 .

In the example of FIG. 19B , in the second circuit 14 , a signal path 97 extends near the third voltage line 15 and another signal path 97 extends near the fourth voltage line 16 . In the second circuit 14 , one signal path 98 extends near the third voltage line 15 and another signal path 98 extends near the fourth voltage line 16 . This does not necessarily pose a problem in terms of noise countermeasures. For example, when the length of the second circuit 14 is short, the effect of noise superposition on the second circuit 14 is limited. Even if the distance between the signal paths 97 and 98 whose noise should be suppressed and the voltage lines 15 and 16 which are noise sources run in parallel is short, the influence of noise superimposition on the second circuit 14 is limited. Also, in the second circuit 14, the influence of noise superimposition may be suppressed by a shield or the like.

(Third Embodiment)
A third embodiment will be described below. In the third embodiment, the same reference numerals may be assigned to the same contents as in the second embodiment, and description thereof may be omitted.

As shown in FIG. 20, in the third embodiment, in plan view, the first signal path 4 has a portion 4X that intersects with the second signal path 5, a portion that intersects with the third signal path 11, and a second A portion intersecting the straight line 8L including the voltage line 8 and a portion 4Z extending within the second region 62 are arranged in this order along the signal flow direction 2F of the first pixel 2. FIG.

Specifically, for example, in plan view, the first signal path 4 has a portion 4X that intersects with the second signal path 5, a portion that intersects with the third signal path 11, and a straight line 8L that includes the second voltage line 8. and the portion 4Z extending within the second 1/2 region 72 are arranged in this order along the signal flow direction 2F of the first pixel 2 .

In a plan view, in the third signal path 11, a portion that intersects the straight line 8L including the second voltage line 8, a portion that intersects the first signal path 4, and a portion that extends within the second region 62 are the third voltage lines. They are arranged in this order along the signal flow direction of the pixels 9 .

Specifically, for example, in a plan view, the third signal path 11 has a portion that intersects the straight line 8L including the second voltage line 8, a portion that intersects the first signal path 4, and a second 1/2 A portion extending within the region 72 is arranged in this order along the signal flow direction of the third pixel 9 .

In the example of FIG. 20, the first signal path 4, the second signal path 5, the third signal path 11, and the fourth signal path 12 are arranged in this order in the output section from the pixel array 1 in plan view. In a region closer to the first circuit 6 than the intersections 4X and 5X, the second signal path 5, the third signal path 11, the first signal path 4 and the fourth signal path 12 are arranged in this order in a plan view. .

In the third embodiment, in plan view, the first signal path 4 has a portion 4X that intersects the second signal path 5 and a portion that intersects the third signal path 11 side by side. In plan view, the first signal path 4 may cross another signal path. That is, in a plan view, the number of crossings with other signal paths in the first signal path 4 may be two, or may be three or more.

In the third embodiment, the first signal path 4 has a portion that intersects a straight line 8L including one second voltage line 8 in plan view. In plan view, the first signal path 4 may intersect a straight line including another voltage line. That is, in a plan view, the number of intersections with the straight line including the voltage line in the first signal path 4 may be one, or may be two or more.

(Fourth embodiment)
A fourth embodiment will be described below. In the fourth embodiment, the same reference numerals may be given to the same contents as in the first embodiment, and the description thereof may be omitted.

In the first embodiment and the like, the correction for reducing noise was performed inside the imaging apparatus 100 . However, correction for reducing noise may be performed outside the imaging device 100 . A fourth embodiment will be described below with reference to FIGS. 21A to 21C. Although not shown in FIG. 21A, an AD conversion circuit 40 or the like may be provided between the first circuit 6 and the output circuit 44 .

As the correction, for example, optical black correction can be adopted. Optical black correction may utilize the techniques described above using first OB pixel 65 and first OB path 66 . For optical black correction, the techniques using the second OB pixel 67 and second OB path 68 previously described may be used.

In one specific example, the imaging system 200 shown in FIGS. 21A-21C includes an imaging device 100 and a signal processing device 18 provided external to the imaging device 100 . The plurality of pixels includes a first OB pixel 65 which is an optical black pixel. The imaging device 100 includes a first OB path 66 through which the signal of a first OB pixel 65 flows. In plan view, the first OB path 66 has a first OB extending portion 66Z extending within the second region 62 . The signal processing device 18 performs optical black correction using the signal of the first OB pixel 65 via the first OB extension section 66Z on the signal of the first pixel 2 via the first extension section 4Z. do.

Specifically, for example, the first OB extension portion 66Z is a portion of the first OB path 66 that extends within the second 1/2 region 72 in plan view. The first extending portion 4Z is a portion of the first signal path 4 that extends within the second 1/2 region 72 in plan view.

In one specific example, the imaging system 200 shown in FIGS. 21A-21C includes an imaging device 100 and a signal processing device 18 provided external to the imaging device 100 . The plurality of pixels includes a second OB pixel 67 which is an optical black pixel. The imaging device 100 includes a second OB path 68 through which the signal of a second OB pixel 67 flows. In plan view, the second OB path 68 has a second OB extending portion 68Z extending within the first region 61 . The signal processing device 18 performs optical black correction using the signal of the second OB pixel 67 via the second OB extension 68Z on the signal of the second pixel 3 via the second extension 5Z. do.

Specifically, for example, the second OB extension portion 68Z is a portion of the second OB path 68 that extends within the first 1/2 region 71 in plan view. The second extending portion 5Z is a portion of the second signal path 5 that extends within the first 1/2 region 71 in plan view.

The correction described in the second embodiment may be performed outside the image capturing apparatus 100 . An imaging system 200 suitable for making such corrections is shown in FIGS. 22A-22C. The imaging system 200 of FIGS. 22A to 22C includes an imaging device 100 and a signal processing device 18 provided outside the imaging device 100. FIG. The signal processing device 18 removes noise superimposed in the second region 62 on both the signal of the first pixel 2 via the first extension 4Z and the signal of the third pixel 9 via the third extension 11Z. Perform a correction that reduces the component.

Specifically, for example, the first extending portion 4Z is a portion of the first signal path 4 that extends within the second 1/2 region 72 in plan view. The third extending portion 11Z is a portion of the third signal path 11 that extends within the second 1/2 region 72 in plan view. The signal processing device 18 processes both the signal of the first pixel 2 via the first extension 4Z and the signal of the third pixel 9 via the third extension 11Z in the second 1/2 region 72. Correction is performed to reduce the superimposed noise component.

In one specific example, the correction is an optical black correction. This particular implementation utilizes the first OB pixel 65 and first OB path 66 previously described. The signal processing device 18 processes both the signal of the first pixel 2 via the first extension 4Z and the signal of the third pixel 9 via the third extension 11Z via the first OB extension 66Z. Optical black correction using the signal of the first OB pixel 65 is performed.

In one example, the signal processing device 18 superimposes both the signal of the second pixel 3 via the second extension 5Z and the signal of the fourth pixel 10 via the fourth extension 12Z in the first region 61. perform a correction that reduces the noise component that is

Specifically, for example, the second extending portion 5Z is a portion of the second signal path 5 that extends within the first 1/2 region 71 in plan view. The fourth extending portion 12Z is a portion of the fourth signal path 12 that extends within the first 1/2 region 71 in plan view. The signal processing device 18 processes both the signal of the second pixel 3 via the second extension 5Z and the signal of the fourth pixel 10 via the fourth extension 12Z in the first 1/2 region 71. Correction is performed to reduce the superimposed noise component.

In one specific example, the correction is an optical black correction. This particular implementation utilizes the second OB pixel 67 and second OB path 68 previously described. The signal processing device 18 passes both the signal of the second pixel 3 via the second extension 5Z and the signal of the fourth pixel 10 via the fourth extension 12Z via the second OB extension 68Z. Optical black correction using the signal of the second OB pixel 67 is performed.

The technique of performing correction outside the imaging apparatus 100 can also be applied to other embodiments.

(Fifth embodiment)
A fifth embodiment will be described below. In the fifth embodiment, the same reference numerals may be assigned to the same contents as in the first embodiment, and description thereof may be omitted.

FIG. 23 shows the pixel array 1 and the first circuit 6 in the fifth embodiment.

As shown in FIG. 23 , in the pixel array 1 of the fifth embodiment, the plurality of pixels includes third pixels 21 and fourth pixels 22 in addition to first pixels 2 and second pixels 3 .

In the example of FIG. 23, the first pixel 2 and the third pixel 21 belong to the same column in the pixel array 1. In the example of FIG. The second pixel 3 and the fourth pixel 22 belong to the same column in the pixel array 1. FIG. The column to which the first pixel 2 and the third pixel 21 belong and the column to which the second pixel 3 and the fourth pixel 22 belong are adjacent to each other.

In the first example, the first pixel 2 and the third pixel 21 are first-type pixels selected from four types of R pixels, B pixels, Gr pixels, and Gb pixels. The second pixels 3 and the fourth pixels 22 are pixels of the second type selected from four types of R pixels, B pixels, Gr pixels and Gb pixels. Specifically, for example, the first pixel 2 and the third pixel 21 are Gr pixels. The second pixel 3 and the fourth pixel 22 are Gb pixels.

In the second example, the first pixel 2 and the third pixel 21 are pixels of the first color. The second pixel 3 and the fourth pixel 22 are pixels of the second color. Specifically, for example, the first pixel 2 and the third pixel 21 include color filters of the first color. The second pixel 3 and the fourth pixel 22 contain color filters of the second color.

Below, the path through which the signal of the third pixel 21 flows may be referred to as a third signal path 4B. A path through which the signal of the fourth pixel 22 flows may be referred to as a fourth signal path 5B.

In the example of FIG. 23, in the output section from the pixel array 1, the first signal path 4, the third signal path 4B, the fourth signal path 5B, and the second signal path 5 are arranged in this order in plan view. In a region closer to the first circuit 6 than the intersections 4X and 5X, the fourth signal path 5B, the second signal path 5, the first signal path 4 and the third signal path 4B are arranged in this order in a plan view. .

In the example of FIG. 23, in a plan view, in the first signal path 4, the crossing portion 4X crossing the second signal path 5 and the first extending portion 4Z extending within the second region 62 are the first pixels 2. They are arranged in this order along the signal flow direction 2F. In a plan view, in the third signal path 4B, the crossing portion that intersects the fourth signal path 5B and the third extending portion 4BZ that extends within the second region 62 are aligned along the signal flow direction 21F of the third pixel 21. and line up in this order. Such a layout facilitates correction for reducing noise in the signals of the first pixel 2 and the third pixel 21 . Specifically, according to such a layout, compared to the case where one of the first signal path 4 and the third signal path 4B extends within the second region 62 and the other extends within the first region 61, the first circuit 6, the noise components superimposed on the signal of the first pixel 2 and the signal of the third pixel 21 are less likely to vary. Therefore, such a layout is suitable for reducing these signal noises with similar correction conditions.

In the example of FIG. 23 , in the second signal path 5 in plan view, the intersection 5X that intersects the first signal path 4 and the second extension 5Z that extends within the first region 61 correspond to the second pixels 3. They are arranged in this order along the signal flow direction 3F. In a plan view, in the fourth signal path 5B, the crossing portion crossing the third signal path 4B and the fourth extending portion 5BZ extending within the first region 61 are aligned along the signal flow direction 22F of the fourth pixel 22. and line up in this order. Such a layout facilitates correction to reduce noise in the signal of the second pixel 3 and the signal of the fourth pixel 22 . Specifically, according to such a layout, compared to the case where one of the second signal path 5 and the fourth signal path 5B extends within the first region 61 and the other extends within the second region 62, the first circuit 6, the noise components superimposed on the signal of the second pixel 3 and the signal of the fourth pixel 22 are less likely to vary. Therefore, such a layout is suitable for reducing these signal noises with similar correction conditions.

Specifically, for example, the first extending portion 4Z is a portion where the first signal path 4 extends within the second 1/2 region 72 in plan view. The third extending portion 4BZ is a portion where the third signal path 4B extends within the second 1/2 region 72 in plan view. The second extending portion 5Z is a portion where the second signal path 5 extends within the first 1/2 region 71 in plan view. The fourth extending portion 5BZ is a portion where the fourth signal path 5B extends within the first 1/2 region 71 in plan view.

An example of a correction method for reducing noise will be described. In the example of FIG. 23, the signal processing circuit 43 processes both the signal of the first pixel 2 via the first extension 4Z and the signal of the third pixel 21 via the third extension 4BZ in the second region. A correction is performed to reduce the superimposed noise component at 62 . According to this example, it is easy to apply similar correction conditions to the correction of the signal of the first pixel 2 and the correction of the signal of the third pixel 21 .

Specifically, for example, the first extending portion 4Z is a portion of the first signal path 4 that extends within the second 1/2 region 72 in plan view. The third extending portion 4BZ is a portion of the third signal path 4B that extends within the second 1/2 region 72 in plan view. The signal processing circuit 43 processes both the signal of the first pixel 2 via the first extended portion 4Z and the signal of the third pixel 21 via the third extended portion 4BZ in the second 1/2 region 72. Correction is performed to reduce the superimposed noise component.

In one specific example, the correction is an optical black correction. This particular implementation utilizes the first OB pixel 65 and first OB path 66 previously described. The signal processing circuit 43 processes both the signal of the first pixel 2 via the first extension 4Z and the signal of the third pixel 21 via the third extension 4BZ via the first OB extension 66Z. Optical black correction using the signal of the first OB pixel 65 is performed.

In the example of FIG. 23, the signal processing circuit 43 processes both the signal of the second pixel 3 via the second extension 5Z and the signal of the fourth pixel 22 via the fourth extension 5BZ in the first region. A correction is performed to reduce the superimposed noise component at 61 . According to this example, it is easy to apply similar correction conditions to the correction of the signal of the second pixel 3 and the correction of the signal of the fourth pixel 22 .

Specifically, for example, the second extending portion 5Z is a portion of the second signal path 5 that extends within the first 1/2 region 71 in plan view. The fourth extending portion 5BZ is a portion of the fourth signal path 5B that extends within the first 1/2 region 71 in plan view. The signal processing circuit 43 processes both the signal of the second pixel 3 via the second extended portion 5Z and the signal of the fourth pixel 22 via the fourth extended portion 5BZ in the first half area 71. Correction is performed to reduce the superimposed noise component.

In one specific example, the correction is an optical black correction. This particular implementation utilizes the second OB pixel 67 and second OB path 68 previously described. The signal processing circuit 43 processes both the signal of the second pixel 3 via the second extension 5Z and the signal of the fourth pixel 22 via the fourth extension 5BZ via the second OB extension 68Z. Optical black correction using the signal of the second OB pixel 67 is performed.

The first example is suitable for reducing the noise of the signals of the first pixel 2 and the third pixel 21, which are the first type pixels, by correction under similar correction conditions. The first example is suitable for reducing the noise of the signals of the second pixel 3 and the fourth pixel 22, which are the second type pixels, by correction under similar correction conditions.

The second example is suitable for reducing noise in the signals of the first pixel 2 and the third pixel 21, which are pixels including color filters of the first color, by correction under similar correction conditions. The second example is suitable for reducing noise in the signals of the second pixel 3 and the fourth pixel 22, which are pixels including color filters of the second color, by correction under similar correction conditions.

As shown in FIG. 24, a first voltage line 7B may be added. Like the first voltage line 7, the first voltage is applied to the first voltage line 7B. In the example of FIG. 24, the first voltage line 7, the fourth signal path 5B, the second signal path 5, and the first voltage line 7B are arranged in this order in plan view. In plan view, the distance between the first voltage line 7 and the fourth signal path 5B is the same as the distance between the second signal path 5 and the first voltage line 7B. In this way, the difference between the noise superimposed on the signal of the fourth signal path 5B in the first region 61 and the noise superimposed on the signal of the second signal path 5 in the first region 61 becomes small. Therefore, the example of FIG. 24 is suitable for reducing the noise of the signals of the second pixel 3 and the fourth pixel 22 by correction under similar correction conditions.

As shown in FIG. 24, a second voltage line 8B may be added. A second voltage is applied to the second voltage line 8</b>B, similarly to the second voltage line 8 . In the example of FIG. 24, the second voltage line 8B, the first signal path 4, the third signal path 4B, and the second voltage line 8 are arranged in this order in plan view. In plan view, the distance between the second voltage line 8B and the first signal path 4 and the distance between the third signal path 4B and the second voltage line 8 are the same. This reduces the difference between the noise superimposed on the signal of the first signal path 4 in the second region 62 and the noise superimposed on the signal of the third signal path 4B in the second region 62 . Therefore, the example of FIG. 24 is suitable for reducing the noise of the signals of the first pixel 2 and the third pixel 21 by correction under similar correction conditions.

As shown in FIG. 25, the first signal path 4 and the third signal path 4B may intersect at the midpoint of the length of the second voltage line 8 in plan view. Here, the halfway point is, for example, the middle portion when the length is divided into three equal parts, specifically, for example, the position where the length is divided into two equal parts. By doing so, the difference between the coupling capacitance between the first signal path 4 and the second voltage line 8 and the coupling capacitance between the third signal path 4B and the second voltage line 8 can be reduced. . This reduces the difference between the noise superimposed on the signal of the first signal path 4 in the second region 62 and the noise superimposed on the signal of the third signal path 4B in the second region 62 . Therefore, the example of FIG. 25 is suitable for reducing the noise of the signals of the first pixel 2 and the third pixel 21 by correction under similar correction conditions.

As shown in FIG. 25, the second signal path 5 and the fourth signal path 5B may intersect at the midpoint of the length of the first voltage line 7 in plan view. Here, the halfway point is, for example, the middle portion when the length is divided into three equal parts, specifically, for example, the position where the length is divided into two equal parts. By doing so, the difference between the coupling capacitance between the second signal path 5 and the first voltage line 7 and the coupling capacitance between the fourth signal path 5B and the first voltage line 7 can be reduced. . This reduces the difference between the noise superimposed on the signal of the second signal path 5 in the first region 61 and the noise superimposed on the signal of the fourth signal path 5B in the first region 61 . Therefore, the example of FIG. 25 is suitable for reducing the noise of the signals of the second pixel 3 and the fourth pixel 22 by correction under similar correction conditions.

(Sixth embodiment)
The sixth embodiment will be described below. In the sixth embodiment, the same reference numerals may be assigned to the same contents as in the second embodiment, and description thereof may be omitted.

FIG. 26 shows the pixel array 1 and the first circuit 6 in the sixth embodiment.

As shown in FIG. 26, in the pixel array 1 of the sixth embodiment, the plurality of pixels are a first pixel 23, a second pixel 24, a third pixel 25, a fourth pixel 26, and a fifth pixel. 23C, a sixth pixel 24C, a seventh pixel 25C, and an eighth pixel 26C.

Hereinafter, the path along which the signal of the first pixel 23 flows may be referred to as the first signal path 4 . A path through which the signal of the second pixel 24 flows may be referred to as a second signal path 5 . A path through which the signal of the third pixel 25 flows may be referred to as a third signal path 11 . A path through which the signal of the fourth pixel 26 flows may be referred to as a fourth signal path 12 . A path through which the signal of the fifth pixel 23C flows may be referred to as a fifth signal path 4C. A path through which the signal of the sixth pixel 24C flows may be referred to as a sixth signal path 5C. A path through which the signal of the seventh pixel 25C flows may be referred to as a seventh signal path 11C. A path through which the signal of the eighth pixel 26C flows may be referred to as an eighth signal path 12C.

The first signal path 4, the second signal path 5, the third signal path 11 and the fourth signal path 12 may have similar features as in the second embodiment. For example, in plan view, the first signal path 4 and the second signal path 5 intersect.

In plan view, the fifth signal path 4</b>C has a portion extending within the first region 61 . In plan view, the sixth signal path 5</b>C has a portion extending within the second region 62 . In plan view, the seventh signal path 11</b>C has a portion extending within the first region 61 . In plan view, the eighth signal path 12</b>C has a portion extending within the second region 62 .

Specifically, for example, the fifth signal path 4</b>C has a portion extending within the first 1/2 region 71 in plan view. In plan view, the sixth signal path 5</b>C has a portion extending within the second half area 72 . In plan view, the seventh signal path 11</b>C has a portion extending within the first 1/2 region 71 . In plan view, the eighth signal path 12</b>C has a portion extending within the second half area 72 .

In this example, the second signal path 5, the fourth signal path 12, the fifth signal path 4C, and the seventh signal path 11C have portions extending within the first region 61 in plan view. Specifically, for example, in plan view, the second signal path 5, the fourth signal path 12, the fifth signal path 4C, and the seventh signal path 11C have portions extending within the first 1/2 region 71. . Therefore, variations in noise components superimposed in the first circuit 6 are less likely to occur in the second signal path 5, the fourth signal path 12, the fifth signal path 4C, and the seventh signal path 11C. Therefore, this example is suitable for reducing the noise of these signals by correction with similar correction conditions. These signals can be corrected to reduce the noise component superimposed in the first region 61 as described above. Specifically, for example, these signals can be corrected to reduce the noise component superimposed in the first 1/2 region 71 described above.

In this example, the first signal path 4, the third signal path 11, the sixth signal path 5C, and the eighth signal path 12C have portions extending within the second region 62 in plan view. Specifically, for example, in plan view, the first signal path 4, the third signal path 11, the sixth signal path 5C, and the eighth signal path 12C have portions extending within the second 1/2 region 72. . Therefore, the noise components superimposed by the first circuit 6 are less likely to vary in the first signal path 4, the third signal path 11, the sixth signal path 5C, and the eighth signal path 12C. Therefore, this example is suitable for reducing the noise of these signals by correction with similar correction conditions. These signals can be corrected to reduce the noise component superimposed in the second region 62 as described above. Specifically, these signals can be corrected to reduce the noise component superimposed in the second 1/2 region 72, as described above.

In the example of FIG. 26, in the output portion from the pixel array 1, in plan view, the first signal path 4, the fifth signal path 4C, the sixth signal path 5C, the second signal path 5, the third signal path 11, the 7 signal path 11C, 8th signal path 12C and 4th signal path 12 are arranged in this order. In a region closer to the first circuit 6 than the intersections 4X and 5X, when viewed from above, the fifth signal path 4C, the second signal path 5, the first signal path 4, the sixth signal path 5C, the third signal path 11, The eighth signal path 12C, the seventh signal path 11C and the fourth signal path 12 are arranged in this order.

The paths intersect so that the paths are arranged differently between the output portion from the pixel array 1 and the area close to the first circuit 6 in plan view. Specifically, for example, the first signal path 4 and the fifth signal path 4C intersect between the output portion from the pixel array 1 and the region near the first circuit 6 in plan view. Between them, the second signal path 5 and the sixth signal path 5C intersect. Between these, a first signal path 4 and a second signal path 5 intersect. Between them, a seventh signal path 11C and an eighth signal path 12C intersect.

In the example of FIG. 26, the first pixel 23 and the fifth pixel 23C belong to the same column in the pixel array 1. In the example of FIG. The second pixel 24 and the sixth pixel 24C belong to the same column in the pixel array 1. FIG. The third pixel 25 and the seventh pixel 25C belong to the same column in the pixel array 1. FIG. The fourth pixel 26 and the eighth pixel 26C belong to the same column in the pixel array 1. FIG. These four columns are adjacent in the order described.

In the first example, the first pixel 23 and the third pixel 25 are first-type pixels selected from four types of R pixels, B pixels, Gr pixels, and Gb pixels. The second pixel 24 and the fourth pixel 26 are the second type of pixels selected from the four types. The fifth pixel 23C and the seventh pixel 25C are pixels of the third type selected from the four types. The sixth pixel 24C and the eighth pixel 26C are pixels of the fourth type selected from the four types. The first type pixels, the second type pixels, the third type pixels and the fourth type pixels are different from each other.

Specifically, for example, the first pixel 23 and the third pixel 25 are Gr pixels. The second pixel 24 and the fourth pixel 26 are R pixels. The fifth pixel 23C and the seventh pixel 25C are B pixels. The sixth pixel 24C and the eighth pixel 26C are Gb pixels.

In a second example, the first pixel 23 and the third pixel 25 are pixels of the first color. The second pixel 24 and the fourth pixel 26 are pixels of the second color. The fifth pixel 23C and the seventh pixel 25C are pixels of the third color. The sixth pixel 24C and the eighth pixel 26C are pixels of the fourth color. The first, second, third and fourth colors are different from each other.

Specifically, for example, the first pixel 23 and the third pixel 25 include color filters of the first color. The second pixel 24 and the fourth pixel 26 contain color filters of the second color. The fifth pixel 23C and the seventh pixel 25C contain color filters of the third color. The sixth pixel 24C and the eighth pixel 26C contain color filters of the fourth color.

The readout order of pixels is not particularly limited. The first pixel 23, the second pixel 24, the third pixel 25 and the fourth pixel 26 may be read, and then the fifth pixel 23C, the sixth pixel 24C, the seventh pixel 25C and the eighth pixel 26C may be read. The first pixel 23, the second pixel 24, the third pixel 25, the fourth pixel 26, the fifth pixel 23C, the sixth pixel 24C, the seventh pixel 25C and the eighth pixel 26C may be read simultaneously.

(Seventh embodiment)
The seventh embodiment will be described below. In the seventh embodiment, the same reference numerals may be assigned to the same contents as in the first embodiment, and the description thereof may be omitted.

As shown in FIG. 27, the imaging device of the seventh embodiment has a selector 27. In FIG. In the seventh embodiment, part of the first signal path 4 is configured by the selector 27. FIG. A part of the second signal path 5 is configured by the selector 27 . FIG. 28 shows the configuration of the selector 27. As shown in FIG.

In the seventh embodiment, in plan view, in the first signal path 4, the first connection point 29A, the first crossing portion 4X, the second connection point 29B, and the first extension portion 4Z are the first pixels. 2 are arranged in this order along the signal flow direction 2F. In a plan view, in the second signal path 5, the third connection point 29C, the second crossing portion 5X, the fourth connection point 29D, and the second extension portion 5Z are arranged in the signal flow direction 3F of the second pixel 3. line up in this order. The imaging device has a selector 27 . The selector 27 includes a first switch 28A, a second switch 28B, a third switch 28C and a fourth switch 28D. The first switch 28A electrically connects the first connection point 29A and the fourth connection point 29D. The second switch 28B electrically connects the first connection point 29A and the second connection point 29B. The third switch 28C electrically connects the third connection point 29C and the fourth connection point 29D. The fourth switch 28D electrically connects the third connection point 29C and the second connection point 29B. The selector 27 can switch the path of the pixel signal.

In other words, the first switch 28A is connected between the first connection point 29A and the fourth connection point 29D. The second switch 28B is connected between the first connection point 29A and the second connection point 29B. The third switch 28C is connected between the third connection point 29C and the fourth connection point 29D. The fourth switch 28D is connected between the third connection point 29C and the second connection point 29B.

A second switch 28 B is provided on the first signal path 4 . A third switch 28</b>C is provided on the second signal path 5 .

In this example, the selector 27 includes a first connection point 29A, a second connection point 29B, a third connection point 29C, and a fourth connection point 29D.

The first switch 28A, the second switch 28B, the third switch 28C, and the fourth switch 28D may be configured to switch between an ON state and an OFF state by electrical control. These switches may be fixed in an ON state or an OFF state. The control circuit 42 may control switching between the ON state and the OFF state of the first to fourth switches 28A to 28D.

When the first switch 28A and the fourth switch 28D are in the OFF state and the second switch 28B and the third switch 28C are in the ON state, the signal of the first pixel 2 and the signal of the second pixel are the same as in the first embodiment. 3 signals flow.

How to use the selector 27 will be further described below.

For example, assume that the noise component on the second voltage line 8 is smaller than the noise component on the first voltage line 7 . In this situation, pixels may be read row by row. Specifically, the first pixel 2 may be read, and then the second pixel 3 may be read. In this case, the first pixel 2 can be read by first setting the second switch 28B to the ON state and setting the first switch 28A, the third switch 28C and the fourth switch 28D to the OFF state. can. After that, by setting the fourth switch 28D to the ON state and setting the first switch 28A, the second switch 28B, and the third switch 28C to the OFF state, the reading of the second pixel 3 can be performed. By doing so, both the signal of the first pixel 2 and the signal of the second pixel 3 can be passed through the vicinity of the second voltage line 8 with relatively small noise components. Thereby, the first pixel 2 and the second pixel 3 can be read with low noise. For example, the row operation circuit 41 and the control circuit 42 control the reading of these images.

After configuring the imaging device, ON/OFF of the first switch 28A, the second switch 28B, the third switch 28C, and the fourth switch 28D may be switched by electrical control. For example, after configuring the imaging device, the noise of the voltage lines 7 and 8 is actually measured, and depending on the result, the pixel signal is routed through the vicinity of the voltage line 8 or through the vicinity of the voltage line 7. It is also possible to select whether to In this way, noise can be reduced only by electrically controlling the selector 27 without reconfiguring the imaging device.

(Specific example of imaging system)
A specific example of the imaging system will be described below. The imaging system according to this specific example can be used for smartphones, video cameras, digital still cameras, surveillance cameras, cameras for vehicles, and the like.

FIG. 29 shows an imaging system 200 according to a specific example. The system 200 includes a lens 110 , an imaging device 100 , a signal processing section 120 and a system controller 130 .

The lens 110 is an optical element for guiding incident light to the pixel array 1 included in the imaging device 100 .

The image pickup apparatus 100 converts image light formed on an image pickup surface by the lens 110 into an electric signal on a pixel-by-pixel basis, and outputs the obtained image signal. An image signal is a set of signals of a plurality of pixels in the above-described embodiments. As the imaging device 100, the imaging device according to the embodiment described above can be used. Using the imaging apparatus according to the above-described embodiments can contribute to formation of images with less noise.

The signal processing unit 120 is a circuit that performs various processes on image signals generated by the imaging device 100 . In one example, the image signal processed by the signal processing unit 120 is recorded as a still image or moving image in a recording medium such as a memory. In another example, the image signal is displayed as a moving image on a monitor such as a liquid crystal display. The signal processor 120 may include the signal processor 18 of FIG.

The system controller 130 is a control section that drives the imaging device 100 and the signal processing section 120 .

Although the imaging device and imaging system according to the embodiments of the present disclosure have been described above, the present disclosure is not limited to these embodiments.

For example, division of functional blocks in a block diagram is an example, and a plurality of functional blocks can be realized as one functional block, one functional block can be divided into a plurality of functional blocks, and some functions can be moved to other functional blocks. may

Each processing unit included in each device according to the above embodiments is typically implemented as an LSI, which is an integrated circuit. These may be made into one chip individually, or may be made into one chip so as to include part or all of them.

Circuit integration is not limited to LSIs, and may be realized with dedicated circuits or general-purpose processors. An FPGA (Field Programmable Gate Array) that can be programmed after the LSI is manufactured, or a reconfigurable processor that can reconfigure connections and settings of circuit cells inside the LSI may be used.

In each of the above embodiments, part of each component may be implemented by executing a software program suitable for that component. The components may be implemented by a program execution unit such as a CPU or processor reading and executing a software program recorded in a recording medium such as a hard disk or semiconductor memory.

The intersection at the portions 4X and 5X in plan view is not essential. The technical features shown in the above-described embodiments and modifications may be replaced or Combinations are possible. Moreover, technical features that are not described as essential in the present disclosure can be deleted as appropriate.

The imaging device according to the present disclosure can be used for various camera systems and sensor systems such as digital still cameras, medical cameras, surveillance cameras, vehicle-mounted cameras, digital single-lens reflex cameras, and digital mirrorless single-lens cameras.

1 pixel array 2, 23 first pixels 3, 24 second pixels 4 first signal path 5 second signal path 6 first circuits 7, 7B first voltage lines 8, 8B second voltage lines 9, 21, 25 third Pixels 10, 22, 26 Fourth pixel 11 Third signal path 12 Fourth signal path 4C Fifth signal path 5C Sixth signal path 11C Seventh signal path 12C Eighth signal path 14 Second circuit 14P Pitch region 15 Third voltage Line 16 Fourth voltage line 18 Signal processing device 23C Fifth pixel 24C Sixth pixel 25C Seventh pixel 26C Eighth pixel 27 Selectors 28A, 28B, 28C, 28D Switches 29A, 29B, 29C, 29D Connection point 40 AD conversion circuit 41 Row scanning circuit 42 Control circuit 43 Signal processing circuit 44 Output circuit 50 Current source circuit 51 Constant current source 52 Ground 53 Pre-stage circuit 54 RAMP comparator 54a First input section 54b Second input section 54c Output section 55 Counter circuit 56 Memory circuit 57 Digital to Analog Converter 61 First Region 62 Second Region 65 First OB Pixel 66 First OB Path 67 Second OB Pixel 68 Second OB Path 71 First Half Area 72 Second Half Area Regions 81, 82, 83, 84 Wiring layer 90 External pad 91 Insulating layer 92 Semiconductor substrate 94 Other circuits 95, 96 Voltage lines 97, 98 Signal path 100 Imaging device 110 Lens 120 Signal processing unit 130 System controller 200 Imaging system

Claims (20)

a plurality of pixels including a first pixel and a second pixel;
A first wiring portion including a plurality of first voltage lines to which a first voltage is commonly applied, and a plurality of second voltage lines to which a second voltage different from the first voltage is commonly applied . a first circuit including a second wiring portion including two voltage lines;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
A region closer to each of the plurality of first voltage lines than any of the plurality of second voltage lines in plan view is defined as a first region, and any one of the plurality of first voltage lines is defined as a first region. When a region closer to each of the plurality of second voltage lines than is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension,
Imaging device. a plurality of pixels including a first pixel and a second pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension,
the first voltage is a power supply voltage;
wherein the second voltage is a ground voltage ;
Imaging device. a plurality of pixels including a first pixel and a second pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a second circuit including a third wiring portion including one or more voltage lines and a fourth wiring portion including a plurality of voltage lines ;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension,
the one or more voltage lines of the third wiring section includes a third voltage line;
the plurality of voltage lines of the fourth wiring section includes a fourth voltage line and a fifth voltage line adjacent to the third voltage line;
the third voltage line is positioned between the fourth voltage line and the fifth voltage line;
In the planar view,
The pitch of the one or more first voltage lines and the one or more second voltage lines and the pitch of the fourth voltage line, the third voltage line and the fifth voltage line are different from each other. cage,
When the region between the third voltage line and the fourth voltage line is defined as a first pitch region, and the region between the third voltage line and the fifth voltage line is defined as a second pitch region. ,
the first signal path further includes a first pitch portion extending within the first pitch region;
the second signal path further includes a second pitch portion extending within the second pitch region;
In the signal flow of the first pixel, the first pitch portion is located upstream of the first intersection,
In the signal flow of the second pixel, the second pitch portion is located upstream of the second intersection .
Imaging device. a plurality of pixels including a first pixel and a second pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension,
the first circuit further includes a first transistor of a first conductivity type and a second transistor of a second conductivity type different from the first conductivity type;
the first transistor is connected to one of the one or more first voltage lines;
the second transistor is connected to any of the one or more second voltage lines ;
Imaging device. a plurality of pixels including a first pixel and a second pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a second circuit ;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension, and the first circuit includes a first transistor of a first conductivity type and a transistor of the first conductivity type. a second transistor of a different second conductivity type;
the second circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type;
When the center of gravity of the gate of the first transistor and the gate of the second transistor is defined as a first center of gravity, and the center of gravity of the gate of the third transistor and the gate of the fourth transistor is defined as a second center of gravity, the planar view in
the alignment direction of the first transistor and the second transistor and the alignment direction of the third transistor and the fourth transistor are different from each other,
the first signal path includes a portion closest to the second center of gravity and a portion closest to the first center of gravity;
the second signal path includes a portion closest to the second center of gravity and a portion closest to the first center of gravity;
In the signal flow of the first pixel, the portion closest to the second center of gravity is located upstream of the portion closest to the first center of gravity;
In the signal flow of the second pixel, the portion closest to the second center of gravity is the first
located upstream of said portion closest to the center of gravity ;
Imaging device. a plurality of pixels including a first pixel, a second pixel, and a first OB pixel that is an optical black pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a signal processing circuit;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
a first OB path through which the signal of the first OB pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension,
In the plan view, the first OB path includes a first OB extension extending within the second region,
The signal processing circuit performs optical black correction on the signal of the first pixel that has passed through the first extension section, using the signal of the first OB pixel that has passed through the first OB extension section. do
Imaging device. a plurality of pixels including a first pixel, a second pixel, and a third pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a signal processing circuit;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
a third signal path through which the signal of the third pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension, and in plan view, the third signal path is a third extension extending within the second region. including
The signal processing circuit controls both the signal of the first pixel that has passed through the first extension portion and the signal of the third pixel that has passed through the third extension portion. perform a correction that reduces the component ,
Imaging device. a plurality of pixels including a first pixel, a second pixel, a third pixel, and a first OB pixel that is an optical black pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a signal processing circuit;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
a third signal path through which the signal of the third pixel flows;
a first OB path through which the signal of the first OB pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension, and in plan view, the third signal path is a third extension extending within the second region. including
In the plan view, the first OB path includes a first OB extension extending within the second region,
The signal processing circuit performs optical black correction on the signal of the first pixel that has passed through the first extension section, using the signal of the first OB pixel that has passed through the first OB extension section. do
Imaging device. the plurality of pixels form a pixel array having at least one row and a plurality of columns;
the column to which the first pixel belongs in the pixel array and the column to which the second pixel belongs in the pixel array are adjacent to each other;
The imaging device according to any one of claims 1 to 8 . In the plan view, the plurality of first voltage lines, the plurality of second voltage lines, the first extension, and the second extension extend parallel to each other.
The imaging device according to claim 1 . In the plan view, the one or more first voltage lines, the one or more second voltage lines, the first extension, and the second extension extend parallel to each other. ,
The imaging device according to any one of claims 2 to 8. The imaging device includes a multilayer wiring layer including a first wiring layer and a second wiring layer different from the first wiring layer,
the first wiring layer includes the first intersection,
wherein the second wiring layer includes the second intersection,
The imaging device according to any one of claims 1 to 11 . In the planar view,
the first signal path further includes a first connection point and a second connection point;
the second signal path further includes a third connection point and a fourth connection point;
In the signal flow of the first pixel, the first connection point is located upstream of the first intersection, and the second connection point is between the first intersection and the first extension. Position to,
In the signal flow of the second pixel, the third connection point is located upstream of the second intersection, and the fourth connection point is between the second intersection and the second extension. Position to,
The imaging device further comprises a selector,
The selector is
a first switch connected between the first connection point and the fourth connection point;
a second switch connected between the first connection point and the second connection point;
a third switch connected between the third connection point and the fourth connection point;
a fourth switch connected between the third connection point and the second connection point;
The imaging device according to any one of claims 1 to 12 . the plurality of pixels includes a third pixel;
The imaging device further comprises a third signal path through which the signal of the third pixel flows,
In the planar view, the third signal path includes a third extending portion extending within the second region,
The imaging device according to any one of claims 1 to 6 . the plurality of pixels includes a fourth pixel;
The imaging device further comprises a fourth signal path through which the signal of the fourth pixel flows,
In the planar view, the fourth signal path includes a fourth extending portion extending within the first region,
15. The imaging device according to claim 14 . In the planar view,
the third signal path includes a portion extending from the third pixel to the second region;
the fourth signal path includes a portion extending from the fourth pixel to the first region;
the portion extending from the third pixel to the second region does not intersect the portion extending from the fourth pixel to the first region;
16. The imaging device according to claim 15 . the first pixel includes a first color filter;
the second pixel includes a second color filter;
the third pixel includes a third color filter;
the first color filter and the third color filter are color filters of a first color;
The second color filter is a color filter of a second color different from the first color,
17. The imaging device according to any one of claims 14-16 . the first pixel and the third pixel are first-type pixels selected from four types of R pixels, B pixels, Gr pixels, and Gb pixels;
the second pixels are pixels of a second type selected from four types of R pixels, B pixels, Gr pixels, and Gb pixels;
the pixels of the first type and the pixels of the second type are different from each other;
17. The imaging device according to any one of claims 14-16 . a plurality of pixels including a first pixel and a second pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
an imaging device, wherein the second intersection is positioned upstream of the second extension in the signal flow of the second pixel ;
and a signal processing device provided outside the imaging device,
the plurality of pixels includes a first OB pixel that is an optical black pixel;
The imaging device further includes a first OB path through which signals of the first OB pixels flow,
In the plan view, the first OB path includes a first OB extension extending within the second region,
The signal processing device performs optical black correction using the signal of the first OB pixel that has passed through the first OB extension section on the signal of the first pixel that has passed through the first extension section. do,
imaging system. a plurality of pixels including a first pixel, a second pixel and a third pixel;
A first wiring section including one or more first voltage lines to which a first voltage is applied, and a first wiring section including one or more second voltage lines to which a second voltage different from the first voltage is applied a first circuit including two wiring portions;
a first signal path through which the signal of the first pixel flows;
a second signal path through which the signal of the second pixel flows;
a third signal path through which the signal of the third pixel flows;
A region closer to each of the one or more first voltage lines than any of the one or more second voltage lines in a plan view is defined as a first region, and the one or more first voltage lines are defined as a first region. When a region closer to each of the one or more second voltage lines than any of the lines is defined as a second region,
the first signal path includes a first intersection that intersects the second signal path and a first extension that extends within the second region;
the second signal path includes a second intersection crossing the first signal path and a second extension extending within the first region;
In the signal flow of the first pixel, the first intersection is located upstream of the first extension,
In the signal flow of the second pixel, the second intersection is located upstream of the second extension, and in plan view, the third signal path is a third extension extending within the second region. an imaging device comprising
and a signal processing device provided outside the imaging device,
The signal processing device controls both the signal of the first pixel via the first extension section and the signal of the third pixel via the third extension section with noise superimposed in the second region. perform a correction that reduces the component,
imaging system.

Images