CN111193842B - Image pickup apparatus and image pickup system - Google Patents

Abstract

The present disclosure provides an imaging device and an imaging system, and provides a technique capable of contributing to noise reduction in the presence of a plurality of voltage lines to which mutually different voltages are applied. The 1 st signal path (4) includes a 1 st intersection (4X) intersecting the 2 nd signal path (5), and a 1 st extension (4Z) extending in the 2 nd region (62). The 2 nd signal path (5) includes a 2 nd intersection (5X) intersecting the 1 st signal path (4), and a 2 nd extension (5Z) extending within the 1 st region (61). In the flow of the signal of the 1 st pixel (2), the 1 st intersection (4X) is located upstream of the 1 st extension (4Z). In the flow of the signal of the 2 nd pixel (3), the 2 nd intersection (5X) is located upstream of the 2 nd extension (5Z).

Description

Image pickup apparatus and image pickup system

Technical Field

The present disclosure relates to an imaging apparatus and an imaging system.

Background

Various imaging devices are known. A CMOS (complementary metal oxide semiconductor: complementary Metal Oxide Semiconductor) image sensor is exemplified as the image pickup device. The CMOS image sensor of an example includes a readout circuit Lu Qun for each column, and outputs a digital signal which is analog-to-digital converted in units of rows. Patent document 1 describes an example of a CMOS image sensor.

Prior art literature

Patent literature

Patent document 1: japanese patent application laid-open No. 2011-082613

Disclosure of Invention

In some cases, the image pickup device includes a plurality of voltage lines to which mutually different voltages are applied. Since different noise components are given to the signals of the pixels from these voltage lines, there is a possibility that the image quality may be lowered. The present disclosure provides a technique capable of contributing to noise reduction in the presence of a plurality of voltage lines to which mutually different voltages are applied.

Means for solving the problems

The present disclosure provides an imaging device, comprising:

a plurality of pixels including a 1 st pixel and a 2 nd pixel;

a 1 st circuit including a 1 st wiring portion including one or more 1 st voltage lines to which a 1 st voltage is applied, and a 2 nd wiring portion including one or more 2 nd voltage lines to which a 2 nd voltage different from the 1 st voltage is applied;

a 1 st signal path through which a signal of the 1 st pixel flows; and

a 2 nd signal path through which a signal of the 2 nd pixel flows,

in a plan view, when a region closer to each of the one or more 1 st voltage lines than to any of the one or more 2 nd voltage lines is defined as a 1 st region, a region closer to each of the one or more 2 nd voltage lines than to any of the one or more 1 st voltage lines is defined as a 2 nd region,

The 1 st signal path includes a 1 st intersection intersecting the 2 nd signal path, and a 1 st extension extending within the 2 nd region,

the 2 nd signal path includes a 2 nd crossing portion crossing the 1 st signal path and a 2 nd extension portion extending in the 1 st region,

in the flow of the 1 st pixel signal, the 1 st intersection is located upstream of the 1 st extension,

in the flow of the signal of the 2 nd pixel, the 2 nd intersection is located upstream of the 2 nd extension.

Effects of the invention

The technology of the present disclosure can contribute to noise reduction in the presence of a plurality of voltage lines to which mutually different voltages are applied.

Drawings

Fig. 1 is a block diagram of an imaging apparatus in embodiment 1.

Fig. 2 is a diagram showing a specific example of the imaging device in embodiment 1.

Fig. 3 is a configuration diagram of a pixel array in embodiment 1.

Fig. 4 is a configuration diagram of the 2 nd circuit, the 1 st circuit, the analog-to-digital conversion circuit, and the control circuit in embodiment 1.

Fig. 5 is an explanatory diagram of a signal path in embodiment 1.

Fig. 6 is an explanatory diagram of a signal path in embodiment 1.

Fig. 7 is an explanatory diagram of a signal path in embodiment 1.

Fig. 8 is a cross-sectional view of the imaging device in embodiment 1.

Fig. 9 is an explanatory diagram of signal paths in embodiment 1.

Fig. 10 is an explanatory diagram of a signal path in embodiment 1.

Fig. 11 is an explanatory diagram of a signal path in embodiment 1.

Fig. 12 is an explanatory diagram of a signal path in embodiment 1.

Fig. 13 is an explanatory diagram of a signal path in embodiment 2.

Fig. 14 is an explanatory diagram of a signal path in embodiment 2.

Fig. 15 is an explanatory diagram of a signal path in embodiment 2.

Fig. 16 is an explanatory diagram of a signal path in embodiment 2.

Fig. 17 is an explanatory diagram of a signal path in embodiment 2.

Fig. 18 is an explanatory diagram of a signal path in embodiment 2.

Fig. 19A is an explanatory diagram of a signal path in embodiment 2.

Fig. 19B is an explanatory diagram of a signal path in embodiment 2.

Fig. 20 is an explanatory diagram of a signal path in embodiment 3.

Fig. 21A is an explanatory diagram of a signal path in embodiment 4.

Fig. 21B is an explanatory diagram of a signal path in embodiment 4.

Fig. 21C is an explanatory diagram of a signal path in embodiment 4.

Fig. 22A is an explanatory diagram of a signal path in embodiment 4.

Fig. 22B is an explanatory diagram of a signal path in embodiment 4.

Fig. 22C is an explanatory diagram of a signal path in embodiment 4.

Fig. 23 is an explanatory diagram of a signal path in embodiment 5.

Fig. 24 is an explanatory diagram of a signal path in embodiment 5.

Fig. 25 is an explanatory diagram of a signal path in embodiment 5.

Fig. 26 is an explanatory diagram of a signal path in embodiment 6.

Fig. 27 is an explanatory diagram of a signal path in embodiment 7.

Fig. 28 is a configuration diagram of a selector in embodiment 7.

Fig. 29 is a block diagram of an imaging system of a specific example.

Description of the reference numerals

1. Pixel array

2. 23 1 st pixel

3. 24 nd pixel 2

4. 1 st signal path

5. 2 nd Signal Path

6. No. 1 circuit

7. 7B 1 st voltage line

8. 8B 2 nd Voltage line

9. 21, 25 rd pixel 3

10. 22, 26 th pixel 4

11. 3 rd Signal Path

12. 4 th Signal Path

4C 5 th Signal Path

5C 6 th Signal Path

11C 7 th Signal Path

12C 8 th Signal path

14. 2 nd circuit

14P pitch region

15. 3 rd voltage line

16. 4 th voltage line

18. Signal processing device

23C 5 th pixel

24C 6 th pixel

25C 7 th pixel

26C 8 th pixel

27. Selector

28A, 28B, 28C, 28D switch

29A, 29B, 29C, 29D connection points

40. Analog-to-digital conversion circuit

41. Line scanning circuit

42. Control circuit

43. Signal processing circuit

44. Output circuit

50. Current source circuit

51. Constant current source

52. Grounded (earth)

53. Front stage circuit

54 RAMP comparator

54a 1 st input section

54b 2 nd input portion

54c output part

55. Counting circuit

56. Memory circuit

57. Digital-to-analog converter

61. Region 1

62. Zone 2

65. 1OB pixel

66. 1 st OB Path

67. 2OB pixel

68. 2OB Path

71. First 1/2 region

72. Second 1/2 region

81. 82, 83, 84 wiring layers

90. External bonding pad

91. Insulating layer

92. Semiconductor substrate

94. Other circuits

95. 96 voltage lines

97. 98 signal path

100. Image pickup apparatus

110. Lens

120. Signal processing unit

130. System controller

200. An image pickup system.

Detailed Description

(summary of one embodiment of the present disclosure)

An imaging device according to claim 1 of the present disclosure includes:

a plurality of pixels including a 1 st pixel and a 2 nd pixel;

a 1 st circuit including a 1 st wiring portion including one or more 1 st voltage lines to which a 1 st voltage is applied, and a 2 nd wiring portion including one or more 2 nd voltage lines to which a 2 nd voltage different from the 1 st voltage is applied;

A 1 st signal path through which a signal of the 1 st pixel flows; and

a 2 nd signal path through which a signal of the 2 nd pixel flows,

in a plan view, when a region closer to each of the one or more 1 st voltage lines than to any of the one or more 2 nd voltage lines is defined as a 1 st region, a region closer to each of the one or more 2 nd voltage lines than to any of the one or more 1 st voltage lines is defined as a 2 nd region,

the 1 st signal path includes a 1 st intersection intersecting the 2 nd signal path, and a 1 st extension extending within the 2 nd region,

the 2 nd signal path includes a 2 nd crossing portion crossing the 1 st signal path and a 2 nd extension portion extending in the 1 st region,

in the flow of the 1 st pixel signal, the 1 st intersection is located upstream of the 1 st extension,

in the flow of the signal of the 2 nd pixel, the 2 nd intersection is located upstream of the 2 nd extension.

The technique of claim 1 can contribute to noise reduction in the presence of a plurality of voltage lines to which mutually different voltages are applied. In addition, in this disclosure, a "signal path" includes, for example, one or more signal lines through which signals flow. A part of the "signal path" may be a signal line included in the 1 st circuit and/or a 2 nd circuit described later.

In the 2 nd aspect of the present disclosure, for example, in the image pickup apparatus of the 1 st aspect,

the 1 st voltage may also be a supply voltage,

the 2 nd voltage may be a ground voltage.

The technique according to claim 2 can contribute to noise reduction in the presence of the voltage line to which the power supply voltage is applied and the voltage line to which the ground voltage is applied.

In the 3 rd aspect of the present disclosure, for example, in the imaging apparatus of the 1 st or 2 nd aspect,

the plurality of pixels may also form a pixel array having at least one row and a plurality of columns,

the column to which the 1 st pixel in the pixel array belongs and the column to which the 2 nd pixel in the pixel array belongs may also be adjacent to each other.

The layout of the 3 rd aspect is a specific example of the layout of the imaging device.

In the 4 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 1 st to 3 rd aspects,

the one or more 1 st voltage lines, the one or more 2 nd voltage lines, the 1 st extension portion, and the 2 nd extension portion may also extend parallel to each other in the plan view.

The parallel layout of the 4 th aspect is advantageous from the viewpoint of downsizing. On the other hand, this parallel arrangement is not necessarily advantageous for noise reduction. Therefore, in this parallel layout, the above-described noise reduction effect is easily exhibited.

In the 5 th aspect of the present disclosure, for example, any one of the imaging devices of the 1 st to 4 th aspects may be provided with a multilayer wiring layer including a 1 st wiring layer and a 2 nd wiring layer different from the 1 st wiring layer,

the 1 st wiring layer may also include the 1 st intersection,

the 2 nd wiring layer may include the 2 nd intersection.

According to the 5 th aspect, the intersection of the 1 st signal path and the 2 nd signal path in a planar view is easily realized.

In the 6 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 1 st to 5 th aspects,

in the plane view of the device, in the plane view,

the 1 st signal path may also include a 1 st connection point and a 2 nd connection point,

the 2 nd signal path may also include a 3 rd connection point and a 4 th connection point,

in the signal flow of the 1 st pixel, the 1 st connection point may be located upstream of the 1 st intersection, the 2 nd connection point may be located between the 1 st intersection and the 1 st extension,

in the flow of the signal of the 2 nd pixel, the 3 rd connection point may be located upstream of the 2 nd intersection, the 4 th connection point may be located between the 2 nd intersection and the 2 nd extension,

The imaging device may further be provided with a selector,

the selector may also include:

a 1 st switch connected between the 1 st connection point and the 4 th connection point;

a 2 nd switch connected between the 1 st connection point and the 2 nd connection point;

a 3 rd switch connected between the 3 rd connection point and the 4 th connection point; and

and a 4 th switch connected between the 3 rd connection point and the 2 nd connection point.

According to the 6 th aspect, the paths of signals of the pixels can be switched.

In the 7 th aspect of the present disclosure, for example, any one of the 1 st to 6 th aspects may further include a 2 nd circuit including a 3 rd wiring portion including one or more voltage lines and a 4 th wiring portion including a plurality of voltage lines,

the one or more voltage lines of the 3 rd wiring part may also include a 3 rd voltage line,

the plurality of voltage lines of the 4 th wiring portion may also include a 4 th voltage line and a 5 th voltage line adjacent to the 3 rd voltage line,

the 3 rd voltage line may also be located between the 4 th and 5 th voltage lines,

in the plane view of the device, in the plane view,

the pitches of the 4 th voltage line, the 3 rd voltage line, and the 5 th voltage line may be different from those of the one or more 1 st voltage lines and the one or more 2 nd voltage lines,

When the region between the 3 rd voltage line and the 4 th voltage line is defined as a 1 st pitch region and the region between the 3 rd voltage line and the 5 th voltage line is defined as a 2 nd pitch region,

the 1 st signal path may further include: a 1 st pitch portion extending within the 1 st pitch region,

the 2 nd signal path may further include: a 2 nd pitch portion extending within the 2 nd pitch region,

in the flow of the 1 st pixel signal, the 1 st pitch section may also be located upstream of the 1 st intersection,

in the flow of the signal of the 2 nd pixel, the 2 nd pitch portion may also be located upstream of the 2 nd intersection.

The case where the existing pitches are different in the 7 th embodiment is an example of a case where the layout accompanied by the intersections can contribute to noise reduction.

In the 8 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 1 st to 7 th aspects,

the 1 st circuit may further include a 1 st transistor of a 1 st conductivity type and a 2 nd transistor of a 2 nd conductivity type different from the 1 st conductivity type,

the 1 st transistor may also be connected to any one of the one or more 1 st voltage lines,

The 2 nd transistor may also be connected to any one of the one or more 2 nd voltage lines.

According to the 8 th aspect, the 1 st transistor can be operated by the 1 st voltage of the 1 st voltage line. The 2 nd transistor can be operated by the 2 nd voltage of the 2 nd voltage line.

In the 9 th aspect of the present disclosure, for example, any one of the imaging apparatuses according to the 1 st to 6 th aspects may further include a 2 nd circuit,

the 1 st circuit may further include a 1 st transistor of a 1 st conductivity type and a 2 nd transistor of a 2 nd conductivity type different from the 1 st conductivity type,

the 2 nd circuit may also include a 3 rd transistor of the 1 st conductivity type and a 4 th transistor of the 2 nd conductivity type,

when the center of gravity of the gate of the 1 st transistor and the gate of the 2 nd transistor are defined as 1 st center of gravity and the center of gravity of the gate of the 3 rd transistor and the gate of the 4 th transistor are defined as 2 nd center of gravity, in the plan view,

the arrangement direction of the 1 st transistor and the 2 nd transistor may be different from the arrangement direction of the 3 rd transistor and the 4 th transistor,

the 1 st signal path may also include a portion closest to the 2 nd center of gravity and a portion closest to the 1 st center of gravity,

The 2 nd signal path may also include a portion closest to the 2 nd center of gravity and a portion closest to the 1 st center of gravity,

in the flow of the signal of the 1 st pixel, the portion closest to the 2 nd center of gravity may also be located upstream of the portion closest to the 1 st center of gravity,

in the flow of the signal of the 2 nd pixel, the portion closest to the 2 nd gravity center may be located upstream of the portion closest to the 1 st gravity center.

The case where the arrangement directions of the transistors are different in the 9 th embodiment is an example of a case where the layout accompanied by the intersections can contribute to noise reduction.

In the 10 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 1 st to 9 th aspects,

the plurality of pixels may also include a 1OB pixel as an optical black pixel,

the image pickup apparatus may further be provided with a signal processing circuit and a 1 st OB path through which the signal of the 1 st OB pixel flows,

in the plan view, the 1 st OB path may also include: a 1OB extension extending in said 2 nd region,

the signal processing circuit may also perform optical black correction using the signal of the 1 st OB pixel via the 1 st extension for the signal of the 1 st pixel via the 1 st extension.

Mode 10 is adapted to reduce a noise component superimposed on the signal of the 1 st pixel in the 2 nd region. In addition, in the present disclosure, an "OB path" includes, for example, one or more signal lines through which signals flow. Part of the "OB path" may be a signal line included in the 1 st circuit and/or the 2 nd circuit described later.

In the 11 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 1 st to 9 th aspects,

the plurality of pixels may also comprise a 3 rd pixel,

the image pickup device may further include a 3 rd signal path through which the signal of the 3 rd pixel flows,

in the plane view, the 3 rd signal path may also include: a 3 rd extension extending in the 2 nd region.

Mode 11 facilitates correction for reducing noise of the 1 st pixel signal and the 3 rd pixel signal.

In the 12 th aspect of the present disclosure, for example, in the image pickup apparatus of the 11 th aspect,

the plurality of pixels may also include a 4 th pixel,

the image pickup device may further include a 4 th signal path through which the signal of the 4 th pixel flows,

in the plane view, the 4 th signal path may also include: a 4 th extension extending in the 1 st region.

Mode 12 facilitates correction for reducing noise of the signal of the 2 nd pixel and the signal of the 4 th pixel.

In the 13 th aspect of the present disclosure, for example, in the imaging apparatus of the 12 th aspect,

in the plane view of the device, in the plane view,

the 3 rd signal path may also comprise a portion extending from the 3 rd pixel to the 2 nd region,

the 4 th signal path may also include a portion extending from the 4 th pixel to the 1 st region,

the portion extending from the 3 rd pixel to the 2 nd region may not intersect the portion extending from the 4 th pixel to the 1 st region.

The layout of embodiment 13 is an example of the layout of the imaging device.

In the 14 th aspect of the present disclosure, for example, in any one of the 11 th to 13 th aspects of the imaging apparatus,

the 1 st pixel may also contain a 1 st color filter,

the 2 nd pixel may also contain a 2 nd color filter,

the 3 rd pixel may also contain a 3 rd color filter,

the 1 st color filter and the 3 rd color filter may be color filters of 1 st color,

the 2 nd color filter may be a 2 nd color filter different from the 1 st color filter.

Mode 14 is suitable for reducing noise of signals of 1 st pixel and 3 rd pixel, which are pixels including a color filter of 1 st color, under the same correction conditions.

In the 15 th aspect of the present disclosure, for example, in any one of the 11 th to 13 th aspects of the imaging apparatus,

the 1 st pixel and the 3 rd pixel may be 1 st pixel selected from 4 kinds of pixels of R pixel, B pixel, gr pixel and Gb pixel,

the 2 nd pixel may be a 2 nd pixel selected from 4 kinds of R pixel, B pixel, gr pixel and Gb pixel,

the 1 st pixel and the 2 nd pixel may be different from each other.

Mode 15 is suitable for reducing noise of signals of 1 st pixel and 3 rd pixel, which are 1 st pixels, under the same correction conditions.

In the 16 th aspect of the present disclosure, for example, any one of the 11 th to 15 th aspects of the imaging apparatus may further include a signal processing circuit,

the signal processing circuit may perform correction to reduce a noise component superimposed on the 2 nd region for both the 1 st pixel signal via the 1 st extension portion and the 3 rd pixel signal via the 3 rd extension portion.

According to the 16 th aspect, the same correction conditions are easily applied to the correction of the signal of the 1 st pixel and the correction of the signal of the 3 rd pixel.

In the 17 th aspect of the present disclosure, for example, in any one of the image pickup apparatuses of the 11 th to 15 th aspects,

The plurality of pixels may also include a 1OB pixel as an optical black pixel,

the image pickup apparatus may further be provided with a signal processing circuit and a 1 st OB path through which the signal of the 1 st OB pixel flows,

in the plan view, the 1 st OB path may also include: a 1OB extension extending in said 2 nd region,

the signal processing circuit may also perform optical black correction using the signal of the 1 st OB pixel via the 1 st extension for the signal of the 1 st pixel via the 1 st extension.

Mode 17 is adapted to reduce a noise component superimposed on the signal of the 1 st pixel in the 2 nd region.

An imaging system according to claim 18 of the present disclosure includes:

any one of the imaging devices according to aspects 1 to 9 and 11 to 15; and

a signal processing device arranged outside the image pickup device,

the plurality of pixels includes a 1OB pixel as an optical black pixel,

the image pickup apparatus further has a 1 st OB path through which a signal of the 1 st OB pixel flows,

in the plan view, the 1 st OB path includes: a 1OB extension extending in said 2 nd region,

the signal processing means performs optical black correction using the signal of the 1 st pixel via the 1 st extension for the signal of the 1 st pixel via the 1 st extension.

Mode 18 is adapted to reduce a noise component superimposed on the signal of the 1 st pixel in the 2 nd region.

An imaging system according to claim 19 of the present disclosure includes:

any one of the imaging devices according to aspects 11 to 15; and

a signal processing device arranged outside the image pickup device,

the signal processing device performs correction to reduce a noise component superimposed in the 2 nd region for both the 1 st pixel signal via the 1 st extension portion and the 3 rd pixel signal via the 3 rd extension portion.

According to the 19 th aspect, the same correction conditions are easily applied to the correction of the signal of the 1 st pixel and the correction of the signal of the 3 rd pixel.

An imaging device according to claim 20 of the present disclosure includes:

a plurality of pixels including a 1 st pixel, a 2 nd pixel, a 3 rd pixel, and a 4 th pixel;

a 1 st circuit including a 1 st wiring portion including one or more 1 st voltage lines to which a 1 st voltage is applied, and a 2 nd wiring portion including one or more 2 nd voltage lines to which a 2 nd voltage different from the 1 st voltage is applied;

a 1 st signal path through which a signal of the 1 st pixel flows;

a 2 nd signal path through which a signal of the 2 nd pixel flows;

A 3 rd signal path through which a signal of the 3 rd pixel flows; and

a 4 th signal path through which a signal of the 4 th pixel flows,

in a plan view, when a region closer to each of the one or more 1 st voltage lines than to any of the one or more 2 nd voltage lines is defined as a 1 st region, a region closer to each of the one or more 2 nd voltage lines than to any of the one or more 1 st voltage lines is defined as a 2 nd region,

in the plane view of the device, in the plane view,

the 1 st signal path includes: a 1 st extension extending in the 2 nd region,

the 2 nd signal path includes: a 2 nd extension extending in the 1 st region,

the 3 rd signal path includes: a 3 rd extension extending in said 2 nd region,

the 4 th signal path includes: a 4 th extension extending in the 1 st region.

In the 21 st aspect of the present disclosure, for example, in the image pickup apparatus of the 20 th aspect,

the 1 st pixel may also contain a 1 st color filter,

the 2 nd pixel may also contain a 2 nd color filter,

the 3 rd pixel may also contain a 3 rd color filter,

The 4 th pixel may also contain a 4 th color filter,

the 1 st color filter and the 3 rd color filter may be color filters of 1 st color,

the 2 nd color filter and the 4 th color filter may be 2 nd color filters different from the 1 st color filters.

In the 22 nd aspect of the present disclosure, for example, in the image pickup apparatus of the 20 th aspect,

the 1 st pixel and the 3 rd pixel may be 1 st pixel selected from 4 kinds of pixels of R pixel, B pixel, gr pixel and Gb pixel,

the 2 nd pixel and the 4 th pixel may be a 2 nd pixel selected from 4 kinds of pixels of an R pixel, a B pixel, a Gr pixel, and a Gb pixel,

the 1 st pixel and the 2 nd pixel may be different from each other.

In the 23 rd aspect of the present disclosure, for example, any one of the imaging apparatuses according to the 20 th to 22 th aspects may further include a signal processing circuit,

the signal processing circuit may perform correction to reduce a noise component superimposed in the 2 nd region for both the 1 st pixel signal via the 1 st extension portion and the 3 rd pixel signal via the 3 rd extension portion,

the signal processing circuit may perform correction to reduce a noise component superimposed on the 1 st region for both the 2 nd pixel signal via the 2 nd extension portion and the 4 th pixel signal via the 4 th extension portion.

An imaging system according to claim 24 of the present disclosure includes:

imaging devices according to aspects 20 to 23; and

a signal processing device arranged outside the image pickup device,

the signal processing device may perform correction for reducing a noise component superimposed in the 2 nd region on both the 1 st pixel signal via the 1 st extension portion and the 3 rd pixel signal via the 3 rd extension portion,

the signal processing device may perform correction to reduce a noise component superimposed on the 1 st region for both the 2 nd pixel signal via the 2 nd extension portion and the 4 th pixel signal via the 4 th extension portion.

In the 20 th to 24 th aspects, the techniques of the 1 st to 19 th aspects can be applied.

Hereinafter, an imaging device according to an embodiment will be described with reference to the drawings.

A detailed description beyond that is sometimes omitted. For example, detailed descriptions of well-known matters, repeated descriptions of substantially the same configuration, and the like may be omitted. This is to avoid that the following description becomes unnecessarily long, as will be readily understood by those skilled in the art. In addition, the drawings and the following description are provided for those skilled in the art to fully understand the technology of the present disclosure, and are not intended to limit the subject matter recited in the claims.

In the drawings, elements having substantially the same structure, operation, and effect are given the same reference numerals. In the following, the numerical values described below are all exemplified for specifically explaining the technology of the present disclosure, and the technology of the present disclosure is not limited to the exemplified numerical values. The connection relationship between the constituent elements is exemplified for specific explanation of the technology of the present disclosure, and the connection relationship for realizing the functions of the technology of the present disclosure is not limited thereto.

In this specification, ordinal numbers of 1 st, 2 nd, and 3 rd … are sometimes used. When an ordinal word is added to an element, elements of the same category having a lower number are not necessarily present. The numbers of ordinal words can be changed as needed.

(embodiment 1)

Fig. 1 shows an imaging device 100 according to the present embodiment. The imaging device 100 is, for example, an image sensor chip shown in fig. 2.

The image pickup device 100 shown in fig. 1 includes a pixel array 1 and an electric circuit 47. The pixel array means that the number of columns may be one or a plurality of columns and the number of rows may be one or a plurality of elements. In the example of fig. 1, the electrical circuit 47 is a peripheral circuit.

The pixel array 1 includes a plurality of pixels. Fig. 3 shows an example of the pixel array 1. In the example of fig. 3, the pixels in the pixel array 1 are arranged in a matrix on a semiconductor substrate. The region in which these pixels are provided functions as an imaging region. Each pixel generates electric charges by photoelectrically converting incident light, and outputs a pixel signal (an example of signals of 1 st to 4 th pixels of the present disclosure) obtained thereby. The pixel signal is an electrical signal corresponding to the electric charge.

In fig. 3, "Row" means a Row of the pixel array 1. "Col" means a column of the pixel array 1. In fig. 3, row 0, row 1, row 2, and row 3 are depicted. In fig. 3, "Col0" represents column 0, and "Col1" represents column 1.

In the example of fig. 3, a bayer array is employed in the pixel array 1. Specifically, for example, in the even-numbered rows such as the 0 th row and the 2 nd row, gr pixels and R pixels are alternately and repeatedly arranged. In the odd-numbered lines such as the 1 st line and the 3 rd line, the B pixels and the Gb pixels are alternately and repeatedly arranged. In the even number column such as the 0 th column, gr pixels and B pixels are alternately and repeatedly arranged. In the odd columns such as column 1, the R pixels and the Gb pixels are alternately and repeatedly arranged.

The R pixel is a red pixel. The B pixel is a blue pixel. The Gr pixel and the Gb pixel are green pixels.

Specifically, for example, the R pixel includes an R color filter. The R color filter is a red color filter. The B pixel includes a B color filter. The B color filter is a blue color filter. The Gr pixel includes a Gr color filter. The Gb pixel includes a Gb color filter. The Gr color filter and the Gb color filter are green color filters.

In the example of fig. 3, the pixels are color pixels. Specifically, in the example of fig. 3, the pixel is a color pixel of a primary color. However, the pixels may be complementary color pixels. In the example of fig. 3, the pixel array is constituted by pixels of different colors. Specifically, in the example of fig. 3, the plurality of colors is 3 colors. However, the plurality of colors may be 4 colors. The plurality of colors may also comprise white. The pixel may be a black-and-white pixel without a color filter. This point is also the same as in the embodiment described later.

In the example of fig. 3, one pixel is connected to one signal line, and there are plural sets of such a combination of pixels and signal lines. In fig. 3, each signal line extends up and down. In the example of fig. 3, column 0 is associated with a plurality of signal lines and column 1 is associated with a plurality of signal lines. These signal lines constitute part or all of a signal path through which signals of the pixels flow. In fig. 5 and the like described later, illustration of these signal lines and a part of the signal paths may be omitted. In addition, a plurality of signal lines associated with one column may be collected in the middle to reduce the number thereof. The number of signal lines associated with one column may be 1.

In the present embodiment, the center of each pixel is located on a lattice point of a virtual square lattice. Of course, each center of the pixel may be located at a lattice point such as a virtual triangle lattice or a virtual hexagonal lattice. In addition, the pixels may be arranged in 1 dimension. In this case, the imaging apparatus 100 can be used as a line sensor.

In the example of fig. 1, the electric circuit 47 includes the 2 nd circuit 14, the 1 st circuit 6, the analog-to-digital conversion circuit 40, the signal processing circuit 43, the output circuit 44, the line scanning circuit 41, and the control circuit 42. The electric circuit 47 may be disposed on a semiconductor substrate on which the pixel array 1 is formed. A part of the electric circuit 47 may be disposed on another substrate.

The row scanning circuit 41 selects pixels of a row of a part of the plurality of pixels in the pixel array 1. Thereby, readout of the signal of the selected pixel is performed.

Fig. 4 schematically shows an exemplary configuration of the 2 nd circuit 14, the 1 st circuit 6, the analog-to-digital conversion circuit 40, and the control circuit 42.

In the example of fig. 4, the 2 nd circuit 14 includes a current source circuit 50. The current source circuit 50 includes a constant current source 51. The constant current source 51 is connected to the ground 52.

The 1 st circuit 6 includes a pre-stage circuit 53 and a RAMP comparator 54. The pre-stage circuit 53 includes a buffer circuit. RAMP comparator 54 includes a 1 st input 54a, a 2 nd input 54b, and an output 54c.

The analog-to-digital conversion circuit 40 includes a counting circuit 55 and a storage circuit 56. The counter circuit 55 includes a clock for analog-to-digital conversion.

The control circuit 42 includes a digital-to-analog converter (DAC) 57. The control circuit 42 controls the 2 nd circuit 14, the 1 st circuit 6, and the analog-to-digital conversion circuit 40.

A signal of a certain column of pixels in the pixel array 1 is input to the current source circuit 50. The current source circuit 50 outputs a signal corresponding to the input signal of the pixel as an analog voltage signal by using the constant current source 51. The signal of the pixel serving as the voltage signal is input to the 1 st input section 54a of the RAMP comparator 54 via the pre-stage circuit 53.

The DAC57 outputs a reference signal RAMP. The reference signal RAMP is a voltage signal that varies with time. In one example, the reference signal RAMP is a voltage signal that increases with time. In other examples, the reference signal RAMP is a voltage signal that decreases with time. The variation of the voltage signal may be monotonically increasing or monotonically decreasing. The change in the voltage signal may also be a linear change. The reference signal RAMP is input to the 2 nd input 54b of the RAMP comparator 54.

The voltage is outputted from the output section 54c of the RAMP comparator 54 as an output signal. In one example, the output unit 54c outputs a high level voltage or a low level voltage. The voltage level is inverted when the sign of the difference between the input voltage to the 1 st input section 54a and the input voltage to the 2 nd input section 54b is inverted.

The counter circuit 55 counts the period from the start of the change in the voltage signal of the RAMP comparator 54 to the inversion by the analog-to-digital conversion clock. The longer the period of time counted, the larger the digital signal is output from the counting circuit 55. In this way, the signal of the pixel is converted from an analog signal to a digital signal by the RAMP comparator 54 and the counter circuit 55.

The signals of the pixels after the digital signals are stored in the storage circuit 56. The signal of the pixel stored in the storage circuit 56 is subjected to signal processing by the signal processing circuit 43, and then is output from the output circuit 44 to the outside of the image pickup device 100.

The current source circuit 50, RAMP comparator 54, and analog-to-digital conversion circuit 40 are provided for each column. The current source circuit 50, RAMP comparator 54, and analog-to-digital conversion circuit 40 are controlled by the control circuit 42.

Hereinafter, what path a signal of a pixel in the pixel array 1 follows from the pixel will be described with reference to fig. 5. Hereinafter, one of the plurality of pixels may be referred to as a 1 st pixel 2. One of the plurality of pixels is sometimes referred to as a 2 nd pixel 3. The path through which the signal of the 1 st pixel 2 flows is sometimes referred to as a 1 st signal path 4. The path through which the signal of the 2 nd pixel 3 flows is sometimes referred to as a 2 nd signal path 5.

In example 1, the 1 st pixel 2 is a 1 st pixel selected from 4 kinds of R pixels, B pixels, gr pixels, and Gb pixels. The 2 nd pixel 3 is a 2 nd pixel selected from 4 kinds of R pixel, B pixel, gr pixel, and Gb pixel. The 1 st pixel and the 2 nd pixel are different from each other.

In example 2, the 1 st pixel 2 is a 1 st color pixel. Pixel 2 and pixel 3 are pixels of color 2. The 1 st color and the 2 nd color are different from each other. Specifically, for example, the 1 st pixel 2 includes a 1 st color filter. The 2 nd pixel 3 includes a color filter of the 2 nd color. In example 1, the color of the 1 st pixel 2 and the color of the 2 nd pixel 3 may be different from each other.

In the example of fig. 5, the 1 st circuit 6 includes a 1 st voltage line 7 and a 2 nd voltage line 8. The 1 st voltage is applied to the 1 st voltage line 7. The 2 nd voltage is applied to the 2 nd voltage line 8. The 1 st voltage and the 2 nd voltage are different from each other.

Hereinafter, the term 1 st wiring portion J1 is sometimes used. The 1 st wiring portion J1 is a wiring portion to which the 1 st voltage is applied. The 1 st wiring portion J1 can correspond to one 1 st voltage line 7 or a plurality of 1 st voltage lines 7. In the example of fig. 6 described later, the 1 st wiring portion J1 corresponds to one 1 st voltage line 7.

Hereinafter, the term 2 nd wiring portion J2 is sometimes used. The 2 nd wiring portion J2 is a wiring portion to which the 2 nd voltage is applied. The 2 nd wiring portion J2 can correspond to one 2 nd voltage line 8 or a plurality of 2 nd voltage lines 8. In the example of fig. 6 described later, the 2 nd wiring portion J2 corresponds to one 2 nd voltage line 8.

In the present embodiment, the 1 st voltage is a power supply voltage. The 2 nd voltage is the ground voltage. The 1 st voltage line 7 and the 2 nd voltage line 8 are used to operate elements in the 1 st circuit 6. In one example, the 1 st voltage line 7 and the 2 nd voltage line 8 serve as charge transmission/reception paths for operating elements in the 1 st circuit 6. For example, the voltage lines 7 and 8 are used in the buffer circuit of the front stage circuit 53 of fig. 4. The 2 nd voltage may be a power supply voltage, and the 1 st voltage may be a ground voltage.

Here, as shown in fig. 6, a region closer to the 1 st wiring portion J1 than the 2 nd wiring portion J2 is defined as a 1 st region 61 in plan view. In plan view, a region closer to the 2 nd wiring portion J2 than the 1 st wiring portion J1 is defined as a 2 nd region 62. At this time, in the 1 st signal path 4, the 1 st intersection 4X intersecting the 2 nd signal path 5 and the 1 st extension 4Z extending in the 2 nd region 62 are arranged in this order in the signal flow direction 2F of the 1 st pixel 2 in plan view. That is, in the flow of the signal of the 1 st pixel 2, the 1 st intersection 4X is located upstream of the 1 st extension 4Z. In the 2 nd signal path 5, a 2 nd intersection 5X intersecting the 1 st signal path 4 and a 2 nd extension 5Z extending in the 1 st region 61 are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. That is, in the flow of the signal of the 2 nd pixel 3, the 2 nd intersection 5X is located upstream of the 2 nd extension 5Z. As described above, the 1 st wiring portion J1 is a wiring portion to which the 1 st voltage is applied. The 2 nd wiring portion J2 is a wiring portion to which the 2 nd voltage is applied. In the example of fig. 6, the 1 st wiring portion J1 corresponds to one 1 st voltage line 7. The 2 nd wiring portion J2 corresponds to one 2 nd voltage line 8. In this way, in the presence of the plurality of voltage lines 7 and 8 to which mutually different voltages are applied, noise can be reduced.

Specifically, for example, as shown in fig. 7, a region in which the ratio of the distance from the 1 st wiring portion J1 to the distance from the 2 nd wiring portion J2 is 1/2 or less is defined as a first 1/2 region 71 in plan view. In plan view, a region in which the ratio of the distance from the 2 nd wiring portion J2 to the distance from the 1 st wiring portion J1 is 1/2 or less is defined as a second 1/2 region 72. The 1 st extension 4Z is a portion where the 1 st signal path 4 extends in the second 1/2 region 72 in plan view. The 2 nd extension 5Z is a portion of the 2 nd signal path 5 extending in the first 1/2 region 71 in plan view. The "1/2" of this specific example may be replaced with "1/3" or "1/4". This point is also the same as in the embodiment described later.

Typically, the pixel array 1 is provided on a semiconductor substrate. The plan view is, for example, viewed parallel to the thickness direction of the semiconductor substrate. In fig. 5 to 7, an arrangement based on a plan view is shown.

Hereinafter, an example of advantageous points of the above-described configuration in plan view will be described.

For example, there is a limitation in the arrangement order of the 1 st voltage line 7 and the 2 nd voltage line 8 in plan view. Such a limitation may be imposed in the case where the 1 st voltage line 7 and the 2 nd voltage line 8 are shared in other circuits than the 1 st circuit 6. The imaging device 100 is an image sensor chip as shown in fig. 2, and the chip has an external pad 90, and may be configured to supply the 1 st voltage to the 1 st voltage line 7 and the 2 nd voltage to the 2 nd voltage line 8 via the external pad 90. In this case, the above-described limitation may be imposed according to the arrangement order of the external pads 90.

The above limitations are set. In the 2 nd circuit 14, it is necessary that the 1 st signal path 4 extend relatively to a position close to the 1 st voltage line 7 (a position on the left side in the example of fig. 5), and the 2 nd signal path 5 extends to a position close to the 2 nd voltage line 8 (a position on the right side in the example of fig. 5) in plan view. The noise component generated by the 2 nd voltage line 8 is set to be smaller than the noise component generated by the 1 st voltage line 7. In this case, by the above-described crossing action, the 1 st signal path 4 can be made to approach the 2 nd voltage line 8 and the 2 nd signal path 5 can be made to approach the 1 st voltage line 7 in a plan view. By the above-described cross action, noise superimposed in the 1 st circuit 6 on the signal flowing in the 1 st signal path 4 can be reduced compared with noise superimposed in the 1 st circuit 6 on the signal flowing in the 2 nd signal path 5.

The noise superimposed on the signal flowing in the 1 st signal path 4 in the 1 st circuit 6 can be reduced as compared with the noise superimposed on the signal flowing in the 2 nd signal path 5 in the 1 st circuit 6, and the technique can be used in various situations. For example, it can function when it is desired to reduce noise superimposed on the signal of the 1 st pixel 2 as compared with noise superimposed on the signal of the 2 nd pixel 3. The driving mode of the image pickup device 100 includes a normal mode and a pixel addition mode. The control circuit 42 and the line scanning circuit 41 control the driving mode. Here, the normal mode is a mode in which the signal of the 1 st pixel 2 is made to flow in the 1 st signal path 4 and the signal of the 2 nd pixel 3 is made to flow in the 2 nd signal path 5. The pixel addition mode is a mode in which the signal of the 1 st pixel 2 and the signal of the 2 nd pixel 3 are mixed in the pixel array 1, and the resultant mixed signal is made to flow in the 1 st signal path 4. According to the above-described technique, noise superimposed on the mixed signal in the 1 st circuit 6 can be reduced in the pixel addition mode.

The illustrated pixel array 1 and electrical circuit 47 are only one example. The configuration of the pixel array 1 and the electric circuit 47 is not limited thereto. The 2 nd circuit 14, the 1 st circuit 6, the analog-to-digital conversion circuit 40, the signal processing circuit 43, the output circuit 44, the row scanning circuit 41, and the control circuit 42 need not all be present. For example, the 2 nd circuit 14 can be omitted. These points are also the same in the embodiment described later.

The 1 st circuit 6 and/or the 2 nd circuit 14 may be an analog circuit such as a current source circuit. The 1 st circuit 6 and/or the 2 nd circuit 14 may be digital circuits that operate by a clock or the like.

Fig. 8 is a cross-sectional view of the imaging device 100 cut in the thickness direction, as an example. As shown in fig. 8, the image pickup device 100 includes an insulating layer 91. In this example, an insulating layer 91 is provided on a semiconductor substrate 92. A plurality of wiring layers are provided at positions of mutually different depths in the insulating layer 91. In the example of fig. 8, the plurality of wiring layers includes a 1 st wiring layer 81, a 2 nd wiring layer 82, a 3 rd wiring layer 83, and a 4 th wiring layer 84. One or all of the 1 st signal path 4, the 2 nd signal path 5, the 1 st voltage line 7, and the 2 nd voltage line 8 may be provided in the same wiring layer. One or both of these may be provided in different wiring layers.

In the present embodiment, the imaging device 100 includes 2 wiring layers that are mutually different layers among the plurality of wiring layers. One of the 2 wiring layers includes a 1 st intersection 4X. The other of the 2 wiring layers includes a 2 nd intersection 5X. In this way, the intersection of the 1 st signal path 4 and the 2 nd signal path 5 in plan view is easily achieved. The above one of the 2 wiring layers may be any one of the wiring layers 81 to 84 of fig. 8. The other of the 2 wiring layers may be any one of the wiring layers 81 to 84 of fig. 8.

In the example of fig. 9, the plurality of pixels includes a 1OB pixel 65 as an optical black pixel. The image pickup apparatus 100 includes a signal processing circuit 43, and a 1 st OB path 66 through which signals of the 1 st OB pixels 65 flow. In plan view, in the 1 st OB path 66, there is a 1 st OB extension 66Z extending in the 2 nd region 62. The signal processing circuit 43 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st OB extension 66Z for the signal of the 1 st pixel 2 via the 1 st extension 4Z. In this way, it is appropriate to reduce the noise component superimposed on the signal of the 1 st pixel 2 in the 2 nd region 62. Although not shown in fig. 9, the analog-to-digital conversion circuit 40 may be provided between the signal processing circuit 43 and the 1 st circuit 6.

Specifically, for example, the 1 st OB extension 66Z is a portion extending within the second 1/2 region 72 in plan view in the 1 st OB path 66. The 1 st extension 4Z is a portion extending within the second 1/2 region 72 in plan view in the 1 st signal path 4.

In the example of fig. 10, the plurality of pixels includes a 2OB pixel 67 as an optical black pixel. The image pickup apparatus 100 includes a signal processing circuit 43, and a 2 nd OB path 68 through which signals of the 2 nd OB pixels 67 flow. In plan view, in the 2 nd OB path 68, there is a 2 nd OB extension 68Z extending within the 1 st region 61. The signal processing circuit 43 performs optical black correction using the signal of the 2 nd pixel 67 via the 2 nd extended portion 68Z for the signal of the 2 nd pixel 3 via the 2 nd extended portion 5Z. In this way, it is appropriate to reduce the noise component superimposed on the signal of the 2 nd pixel 3 in the 1 st region 61.

Specifically, for example, the 2 nd OB extension 68Z is a portion extending within the first 1/2 region 71 in plan view in the 2 nd OB path 68. The 2 nd extension 5Z is a portion extending within the first 1/2 region 71 in plan view in the 2 nd signal path 5.

In the present embodiment, a plurality of pixels constitute a pixel array 1 having at least one row and a plurality of columns. The column to which the 1 st pixel 2 in the pixel array 1 belongs and the column to which the 2 nd pixel 3 in the pixel array 1 belong are adjacent to each other.

In the present embodiment, the 1 st wiring portion J1, the 2 nd wiring portion J2, the 1 st extension portion 4Z, and the 2 nd extension portion 5Z extend parallel to each other in a plan view. Here, as described above, in the example of fig. 6, the 1 st wiring portion J1 corresponds to one 1 st voltage line 7. The 2 nd wiring portion J2 corresponds to one 2 nd voltage line 8. Such a parallel arrangement is advantageous from the viewpoint of miniaturization. On the other hand, this parallel arrangement is not necessarily advantageous for noise reduction. Therefore, in this parallel layout, the above-described noise reduction effect is easily exhibited.

In the present embodiment, the 1 st wiring portion J1, the 2 nd wiring portion J2, the 1 st extending portion 4Z, and the 2 nd extending portion 5Z extend straight in plan view.

The 1 st voltage of the 1 st voltage line 7 may be a fixed voltage or a time-varying voltage. The same applies to the 2 nd voltage in the 2 nd voltage line 8. The fixed voltage is exemplified by the voltage of the mode signal and the voltage of the register signal. As the time-varying voltages corresponding to the 1 st voltage and the 2 nd voltage, ac voltages of mutually different frequencies are exemplified. As such an ac voltage, a voltage of a clock signal is exemplified. One of the 1 st voltage and the 2 nd voltage may be a voltage of a clock signal, and the other may be a voltage of a data signal. The 1 st voltage and the 2 nd voltage may be voltages of pulse signals having different timings and/or different duty ratios.

The above-described crossing may be performed in a region between the 1 st circuit 6 and the 2 nd circuit 14, in a region on the 1 st circuit 6, or in a region on the 2 nd circuit 14 in a plan view. In addition, an element separation region for electrically separating the 1 st circuit 6 from the 2 nd circuit 14 may be provided between the 1 st circuit 6 and the 2 nd circuit 14. The crossing may be performed at a position overlapping with the element separation region in a plan view.

In the present embodiment, the 1 st intersection 4X is a portion through which the analog signal of the 1 st pixel 2 passes. The 2 nd intersection 5X is a portion through which the analog signal of the 2 nd pixel 3 passes. In the present embodiment, the 1 st extension portion 4Z is a portion through which the analog signal of the 1 st pixel 2 passes. The 2 nd extension portion 5Z is a portion through which the analog signal of the 2 nd pixel 3 passes. The same applies to the 1 st and 2 nd OB extensions 66Z and 68Z, and the corresponding analog signal passes through the same. The 3 rd extension portion 11Z, the 3 rd extension portion 4BZ, the 4 th extension portion 5Z, and the 4 th extension portion 5BZ described later are also the same, and are portions through which the corresponding analog signals pass.

The above-described intersections in the intersecting portions 4X and 5X may be the only intersections of the 1 st signal path 4 and the 2 nd signal path 5 in plan view. In a plan view, the 1 st signal path 4 and the 2 nd signal path 5 may be crossed again in a portion other than the portions 4X and 5X. For example, the first circuit 6 may intersect further downstream in plan view. The image pickup device 100 may further intersect in a plan view on the outside of the image pickup device 100 downstream of the output circuit 44. Here, downstream refers to downstream of the flow direction 2F of the signal of the pixel 2 and the flow direction 3F of the signal of the pixel 3.

The 2 nd circuit 14 may also include a plurality of voltage lines. Specifically, in the example of fig. 11, the plurality of voltage lines includes one 3 rd voltage line 15 and 2 4 th voltage lines 16 (one example of 4 th and 5 th voltage lines of the present disclosure) adjacent to the 3 rd voltage line 15. The 4 th voltage line 16, the 3 rd voltage line 15, and the 4 th voltage line 16 are arranged in this order in plan view. In this example, the pitches of the plurality of voltage lines 16, 15 in the 2 nd circuit 14 are different from the pitches of the voltage lines 7, 8 in the 1 st circuit 6 in plan view. Here, the pitch of the voltage lines refers to a pitch between a center line of the voltage line extending in the longitudinal direction and a center line of the voltage line adjacent to the voltage line extending in the longitudinal direction.

In one embodiment, the 3 rd voltage is applied to the 3 rd voltage line 15. The 4 th voltage is applied to the 4 th voltage line 16. The 3 rd voltage and the 4 th voltage are different from each other.

The 3 rd voltage may be the same as one of the 1 st voltage and the 2 nd voltage. The 4 th voltage may be the same as the other of the 1 st voltage and the 2 nd voltage. The 3 rd voltage may be different from the 1 st voltage and the 2 nd voltage. The 4 th voltage may be different from the 1 st voltage and the 2 nd voltage.

In the present embodiment, the 3 rd voltage of the 3 rd voltage line 15 is a power supply voltage. The 4 th voltage of the 4 th voltage line 16 is a ground voltage. The 3 rd voltage line 15 and the 4 th voltage line 16 are used to operate elements in the 2 nd circuit 14. The voltage lines 15 and 16 are used in the current source circuit 50 of fig. 4, for example. The 4 th voltage may be a power supply voltage, and the 3 rd voltage may be a ground voltage. The voltage lines 15 and 16 are connected to, for example, transistors in the current source circuit 50, and supply voltages to the transistors.

The 3 rd voltage may be either a fixed voltage or a time-varying voltage. The same applies to the 4 th voltage. The fixed voltage is exemplified by the voltage of the mode signal and the voltage of the register signal. As the time-varying voltages corresponding to the 3 rd voltage and the 4 th voltage, ac voltages of mutually different frequencies are exemplified. As such an ac voltage, a voltage of a clock signal is exemplified. One of the 3 rd voltage and the 4 th voltage may be a voltage of a clock signal, and the other may be a voltage of a data signal. The 3 rd voltage and the 4 th voltage may be voltages of pulse signals having different timings and/or different duty ratios.

Hereinafter, the term 3 rd wiring portion J3 is sometimes used. The 3 rd wiring portion J3 is a wiring portion to which the 3 rd voltage is applied. The 3 rd wiring portion J3 can correspond to one 3 rd voltage line 15 or a plurality of 3 rd voltage lines 15. In the example of fig. 11, the 3 rd wiring portion J3 corresponds to one 3 rd voltage line 15.

Hereinafter, the term 4 th wiring portion J4 may be used. The 4 th wiring portion J4 is a wiring portion to which the 4 th voltage is applied. The 4 th wiring portion J4 can correspond to one 4 th voltage line 16 or a plurality of 4 th voltage lines 16. In the example of fig. 11, the 4 th wiring portion J4 corresponds to 2 4 th voltage lines 16.

In the example of fig. 11, the image pickup apparatus 100 includes a 2 nd circuit 14 including a 3 rd wiring portion J3 and a 4 th wiring portion J4. The pitch of the 1 st wiring portion J1 and the 2 nd wiring portion J2, and the pitch of the 3 rd wiring portion J3 and the 4 th wiring portion J4 are different from each other in a plan view. In plan view, a region between the 3 rd wiring portion J3 and the 4 th wiring portion J4 is defined as a pitch region 14P. At this time, in the 1 st signal path 4, the portion extending in the pitch region 14P, the 1 st intersection 4X, and the 1 st extension 4Z are arranged in this order along the flow direction 2F of the signal of the 1 st pixel 2 in plan view. In the 2 nd signal path 5, the portion extending in the pitch region 14P, the 2 nd intersection 5X, and the 2 nd extension 5Z are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. In this example, the 1 st wiring portion J1 corresponds to one 1 st voltage line 7. The 2 nd wiring portion J2 corresponds to one 2 nd voltage line 8. The 3 rd wiring portion J3 corresponds to one 3 rd voltage line 15. The 4 th wiring portion J4 corresponds to 2 4 th voltage lines 16. If there is a difference in the pitch, the layout accompanied by the crossover is an example of a case where noise can be reduced. Specifically, for example, when the pitch is different between the 1 st circuit 6 and the 2 nd circuit 14, if the signal paths 4 and 5 are extended straight in a planar view, the possibility that the desired voltage line cannot be accessed is higher than in the case where the pitch is the same. However, with the above-described intersections, a desired voltage line is easily accessed.

In the example of fig. 11, specifically, the pitch of the 1 st wiring portion J1 and the 2 nd wiring portion J2 is the pitch of the 1 st voltage line 7 and the 2 nd voltage line 8. The pitch of the 3 rd wiring portion J3 and the 4 th wiring portion J4 is the pitch of the 3 rd voltage line 15 and the 4 th voltage line 16. The pitch region 14P is a region between the 3 rd voltage line 15 and the 4 th voltage line 16.

As described above, in the example of fig. 11, the pitches of the plurality of voltage lines 15, 16 in the 2 nd circuit 14 and the pitches of the voltage lines 7, 8 in the 1 st circuit 6 are different from each other in a plan view. Specifically, for example, the pitch of the plurality of voltage lines 15 and 16 in the 2 nd circuit 14 is the same as the pitch of the columns of pixels (hereinafter, sometimes referred to as 1-column pitch). The pitch of the voltage lines 7, 8 in the 1 st circuit 6 is different from the 1-column pitch. The voltage lines 7 and 8 have a pitch 2 times the pitch of the columns of pixels (hereinafter, sometimes referred to as a 2-column pitch).

As shown in fig. 12, the pitches of the plurality of voltage lines 15, 16 in the 2 nd circuit 14 may be the same as the pitches of the voltage lines 7, 8 in the 1 st circuit 6 in plan view.

The signal of the pixel may also be input to the 1 st circuit 6 via a signal path. The signal of the pixel may not be input to the 1 st circuit 6.

The signals of the pixels may also be input to the 2 nd circuit 14 via signal paths. The signal of the pixel may not be input to the 2 nd circuit 14.

(embodiment 2)

Embodiment 2 will be described below. In embodiment 2, the same reference numerals are given to the same contents as those in embodiment 1, and the description thereof may be omitted.

Fig. 13 shows a pixel array 1, a 2 nd circuit 14, and a 1 st circuit 6 in embodiment 2.

In the example of fig. 13, the pixel array 1 includes a plurality of pixels. One of the plurality of pixels is sometimes referred to as a 3 rd pixel 9. One of the plurality of pixels is sometimes referred to as a 4 th pixel 10. The path through which the signal of the 3 rd pixel 9 flows is sometimes referred to as a 3 rd signal path 11. The path through which the signal of the 4 th pixel 10 flows is sometimes referred to as a 4 th signal path 12.

In the example of fig. 13, the 1 st circuit 6 includes a plurality of 1 st voltage lines 7 and a plurality of 2 nd voltage lines 8. The 1 st voltage line 7 and the 2 nd voltage line 8 are alternately and repeatedly arranged in a plan view.

In the example of fig. 13, the number of 1 st voltage lines 7 is plural, and the number of 2 nd voltage lines 8 is plural. Fig. 14 shows the 1 st region 61 and the 2 nd region 62 in this case. In the 1 st signal path 4, in plan view, a 1 st intersection 4X intersecting the 2 nd signal path 5 and a 1 st extension 4Z extending in the 2 nd region 62 are arranged in this order along the flow direction 2F of the signal of the 1 st pixel 2. In the 2 nd signal path 5, the 2 nd intersection 5X intersecting the 1 st signal path 4 and the 2 nd extension extending in the 1 st region 61 are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. Here, the 1 st wiring portion J1 is a wiring portion to which the 1 st voltage is applied. The 2 nd wiring portion J2 is a wiring portion to which the 2 nd voltage is applied. In the example of fig. 13, the 1 st wiring portion J1 corresponds to a plurality of 1 st voltage lines 7. The 2 nd wiring portion J2 corresponds to the plurality of 2 nd voltage lines 8.

Specifically, for example, as shown in fig. 15, the 1 st extension 4Z is a portion where the 1 st signal path 4 extends in the second 1/2 region 72 in plan view. The 2 nd extension 5Z is a portion of the 2 nd signal path 5 extending in the first 1/2 region 71 in plan view.

In the example of fig. 13, the plurality of voltage lines in the 2 nd circuit 14 includes a plurality of 3 rd voltage lines 15 and a plurality of 4 th voltage lines 16. The 3 rd voltage line 15 and the 4 th voltage line 16 are alternately and repeatedly arranged in a plan view. In this example, the pitches of the plurality of voltage lines 15, 16 in the 2 nd circuit 14 are different from the pitches of the voltage lines 7, 8 in the 1 st circuit 6 in plan view.

In the example of fig. 13, the plurality of voltage lines 15, 16 in the 2 nd circuit 14 have a 1-column pitch. The voltage lines 7, 8 in the 1 st circuit 6 have a pitch different from the 1-column pitch. Specifically, for example, the voltage lines 7, 8 have a 2-column pitch.

In the example of fig. 13, the image pickup apparatus 100 includes a 2 nd circuit 14 including a 3 rd wiring portion J3 and a 4 th wiring portion J4. The pitch of the 1 st wiring portion J1 and the 2 nd wiring portion J2, and the pitch of the 3 rd wiring portion J3 and the 4 th wiring portion J4 are different from each other in a plan view. In plan view, a region between the 3 rd wiring portion J3 and the 4 th wiring portion J4 is defined as a pitch region 14P. At this time, in the 1 st signal path 4, in plan view, a portion extending within the pitch region 14P (an example of a 1 st pitch portion of the present disclosure), the 1 st intersection 4X, and the 1 st extension 4Z are arranged in this order along the flow direction 2F of the signal of the 1 st pixel 2. In the 2 nd signal path 5, in plan view, a portion extending within the pitch region 14P (an example of the 2 nd pitch portion of the present disclosure), the 2 nd intersection 5X, and the 2 nd extension 5Z are arranged in this order along the flow direction 3F of the signal of the 2 nd pixel 3. In the example of fig. 13, the 1 st wiring portion J1 corresponds to a plurality of 1 st voltage lines 7. The 2 nd wiring portion J2 corresponds to the plurality of 2 nd voltage lines 8. The 3 rd wiring portion J3 corresponds to the plurality of 3 rd voltage lines 15. The 4 th wiring portion J4 corresponds to the plurality of 4 th voltage lines 16.

In the example of fig. 13, specifically, the pitch of the 1 st wiring portion J1 and the 2 nd wiring portion J2 is the pitch of the 1 st voltage line 7 and the 2 nd voltage line 8. The pitch of the 3 rd wiring portion J3 and the 4 th wiring portion J4 is the pitch of the 3 rd voltage line 15 and the 4 th voltage line 16. The pitch region 14P is a region between the 3 rd voltage line 15 and the 4 th voltage line 16.

Fig. 16 shows a detailed example of the 2 nd circuit 14 and the 1 st circuit 6. Specifically, fig. 16 shows the 2 nd circuit 14 and the 1 st circuit 6 in plan view. In fig. 16, a part of the signal path is omitted. The same applies to fig. 19A and 19B described later.

In addition, unlike fig. 13, in fig. 16, in a plan view, the 1 st signal path 4 intersects with the 2 nd signal path 5 in a region on the 1 st circuit 6. As described above, the intersection may be performed in a plane view in a region between the 1 st circuit 6 and the 2 nd circuit 14, in a region on the 1 st circuit 6, or in a region on the 2 nd circuit 14. The crossing may be performed at a position overlapping with the element isolation region in a plan view.

In a plan view, a pitch direction in which the voltage lines 7, 8 in the 1 st circuit 6 are arranged is defined as a 1 st lateral direction HD1, and a direction orthogonal to the 1 st lateral direction HD1 is defined as a 1 st longitudinal direction VD1. In the 1 st circuit 6, the 1 st transistor TG1 and the 2 nd transistor TG2 are arranged in the 1 st lateral direction HD1 between adjacent voltage lines 7, 8 in a plan view.

In the example of fig. 16, the 1 st transistor TG1 is a 1 st conductive type transistor. The 2 nd transistor TG2 is a 2 nd conductive type transistor. The 1 st conductivity type and the 2 nd conductivity type are different from each other. In the example of fig. 16, specifically, the 1 st conductivity type is P-type. The 2 nd conductivity type is N type. More specifically, for example, the 1 st transistor TG1 is a P-channel FET, and the 2 nd transistor TG2 is an N-channel FET. The 1 st transistor TG1 may be an N-channel FET, and the 2 nd transistor TG2 may be a P-channel FET. In this case, the arrangement of the voltage lines 7 and 8 is opposite to the example of fig. 16.

The 1 st transistor TG1 is connected to a 1 st voltage line 7. The 2 nd transistor TG2 is connected to the 2 nd voltage line 8.

In a plan view, a pitch direction in which the voltage lines 15, 16 in the 2 nd circuit 14 are arranged is defined as a 2 nd lateral direction HD2, and a direction orthogonal to the 2 nd lateral direction HD2 is defined as a 2 nd longitudinal direction VD2. In the 2 nd circuit 14, the 3 rd transistor TG3 and the 4 th transistor TG4 are arranged in the 2 nd longitudinal direction VD2 between adjacent voltage lines 15, 16 in a plan view.

In the example of fig. 16, the 3 rd transistor TG3 is a 1 st conductive type transistor. The 4 th transistor TG4 is a transistor of the 2 nd conductivity type. Specifically, for example, the 3 rd transistor TG3 is a P-channel FET, and the 4 th transistor TG4 is an N-channel FET. The 3 rd transistor TG3 may be an N-channel FET, and the 4 th transistor TG4 may be a P-channel FET.

The 3 rd transistor TG3 is connected to the 3 rd voltage line 15. The 4 th transistor TG4 is connected to a 4 th voltage line 16.

In the example of fig. 16, signals of pixels are output from the 2 nd circuit 14 at each column pitch in a plan view.

Thus, in the example of fig. 16, the imaging device includes the 2 nd circuit 14. The 1 st circuit 6 includes a 1 st transistor TG1 of the 1 st conductivity type and a 2 nd transistor TG2 of the 2 nd conductivity type different from the 1 st conductivity type. The 2 nd circuit 14 includes a 3 rd transistor TG3 of the 1 st conductivity type and a 4 th transistor TG4 of the 2 nd conductivity type. The center of gravity of the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG2 is defined as the 1 st center of gravity. The center of gravity of the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG4 is defined as the 2 nd center of gravity. The arrangement direction HD1 of the 1 st transistor TG1 and the 2 nd transistor TG2 and the arrangement direction VD2 of the 3 rd transistor TG3 and the 4 th transistor TG4 are different from each other in a plan view. At this time, in the 1 st signal path 4, the portion closest to the 2 nd center of gravity and the portion closest to the 1 st center of gravity are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view. Here, in the 1 st signal path 4, a portion closest to the 2 nd center of gravity may be included in a portion extending within the pitch region 14P, and a portion closest to the 1 st center of gravity may be included in the 1 st extension portion 4Z. In the 2 nd signal path 5, a portion closest to the 2 nd center of gravity may be included in the portion extending in the pitch region 14P, and a portion closest to the 1 st center of gravity may be included in the 2 nd extension portion 5Z.

In the 2 nd signal path 5, the portion closest to the 2 nd center of gravity and the portion closest to the 1 st center of gravity are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. In this way, the 1 st circuit 6 is easily reduced in the arrangement direction VD1 in a plan view. The 2 nd circuit 14 is easily reduced in the arrangement direction HD2 in plan view. Therefore, by providing such a difference in arrangement of transistors, the shape of the planar view is easily changed in the two circuits 6 and 14. Which can be an effective countermeasure against space restrictions of the circuit configuration. However, the difference in arrangement of the transistors may cause limitation in layout of the 1 st signal path 4 and the 2 nd signal path 5 in the 1 st circuit 6 and the 2 nd circuit 14. For example, when the transistors are arranged differently, the difference in the pitch of the voltage lines between the two circuits 6 and 14 is likely to occur in order to facilitate the application of a voltage from the voltage line to the transistors. Therefore, in the example of fig. 16, the layout accompanied by the above-described intersections can contribute to noise reduction.

In one example, the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG2 are one electrode in common. In this case, "the center of gravity of the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG 2" is the center of gravity of the common electrode. In other examples, the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG2 are mutually independent electrodes. In this case, "the center of gravity of the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG 2" is the center of gravity of these 2 electrodes.

In one example, the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG4 are one electrode in common. In this case, "the center of gravity of the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG 4" is the center of gravity of the common electrode. In other examples, the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG4 are mutually independent electrodes. In this case, "the center of gravity of the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG 4" is the center of gravity of these 2 electrodes.

As is well known, the center of gravity refers to the point of action of the combined forces of gravity experienced by portions of an object. The 1 st center of gravity can be determined from the region where at least one electrode constituting the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG2 is extended by a measuring instrument such as SEM (Scanning Electron Microscope: scanning electron microscope). Similarly, the region where at least one electrode constituting the gate electrode of the 3 rd transistor TG3 and the gate electrode of the 4 th transistor TG4 is expanded is measured by a measuring instrument such as SEM, and the 2 nd center of gravity can be determined from the measured region.

In the example of fig. 16, the 1 st circuit 6 includes a 1 st transistor TG1 of the 1 st conductivity type and a 2 nd transistor TG2 of the 2 nd conductivity type different from the 1 st conductivity type. The 1 st voltage line 7 of the 1 st wiring section J1 is connected to the 1 st transistor TG 1. The 2 nd voltage line 8 of the 2 nd wiring portion J2 is connected to the 2 nd transistor TG2. In this way, the 1 st transistor TG1 can be operated by the 1 st voltage of the 1 st wiring portion J1. The 2 nd transistor TG2 can be operated by the 2 nd voltage of the 2 nd wiring portion J2.

The technique related to the transistor described above can be applied to other embodiments such as embodiment 1.

In the example of fig. 13, the plurality of pixels includes a 3 rd pixel 9. The image pickup device 100 includes a 3 rd signal path 11 through which a signal of the 3 rd pixel 9 flows. As shown in fig. 14, in a plan view, there is a 3 rd extension 11Z extending in the 2 nd region 62 in the 3 rd signal path 11. Such a layout facilitates correction for reducing noise of the signals of the 1 st pixel 2 and the 3 rd pixel 9. Specifically, for example, according to such a layout, a difference in noise components superimposed on the signal of the 1 st pixel 2 and the signal of the 3 rd pixel 9 in the 1 st circuit 6 is less likely to occur than in the case where one of the 1 st signal path 4 and the 3 rd signal path 11 extends in the 2 nd region 62 and the other extends in the 1 st region 61. Thus, such a layout is suitable for reducing noise of these signals by correction of the same correction conditions.

Specifically, for example, as shown in fig. 15, the 3 rd extension 11Z is a portion extending in the second 1/2 region 72 in plan view.

In the example of fig. 13, the plurality of pixels includes the 4 th pixel 10. The image pickup device 100 includes a 4 th signal path 12 through which a signal of the 4 th pixel 10 flows. As shown in fig. 14, in a plan view, there is a 4 th extension 12Z extending within the 1 st region 61 in the 4 th signal path 12. Such a layout facilitates correction for reducing noise of the signal of the 2 nd pixel 3 and the signal of the 4 th pixel 10. Specifically, according to such a layout, a difference in noise component superimposed on the signal of the 2 nd pixel 3 and the signal of the 4 th pixel 10 in the 1 st circuit 6 is less likely to occur than in the case where one of the 2 nd signal path 5 and the 4 th signal path 12 extends in the 1 st region 61 and the other extends in the 2 nd region 62. Thus, such a layout is suitable for reducing noise of these signals by correction of the same correction conditions.

Specifically, for example, as shown in fig. 15, the 4 th extension 12Z is a portion extending in the first 1/2 region 71 in plan view.

An example of a method for correction for noise reduction is described below.

In the example of fig. 17, the image pickup apparatus 100 includes a signal processing circuit 43. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the 2 nd region 62 for both the 1 st pixel 2 signal via the 1 st extension portion 4Z and the 3 rd pixel 9 signal via the 3 rd extension portion 11Z. According to this example, the same correction conditions are easily applied to the correction of the signal of the 1 st pixel 2 and the correction of the signal of the 3 rd pixel 9.

Specifically, for example, the 1 st extension 4Z is a portion extending within the second 1/2 region 72 in a plan view in the 1 st signal path 4. The 3 rd extension 11Z is a portion extending within the second 1/2 region 72 in plan view in the 3 rd signal path 11. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the second 1/2 region 72 for both the 1 st pixel 2 signal via the 1 st extension portion 4Z and the 3 rd pixel 9 signal via the 3 rd extension portion 11Z.

In one embodiment, the correction is an optical black correction. In this specific example, the 1 st OB pixel 65 and the 1 st OB path 66 described above are used. The signal processing circuit 43 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st extension 66Z for both the signal of the 1 st pixel 2 via the 1 st extension 4Z and the signal of the 3 rd pixel 9 via the 3 rd extension 11Z.

In the example of fig. 18, the image pickup apparatus 100 includes a signal processing circuit 43. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the 1 st region 61 for both the signal of the 2 nd pixel 3 via the 2 nd extension portion 5Z and the signal of the 4 th pixel 10 via the 4 th extension portion 12Z. According to this example, the same correction conditions are easily applied to the correction of the signal of the 2 nd pixel 3 and the correction of the signal of the 4 th pixel 10.

Specifically, for example, the 2 nd extension portion 5Z is a portion extending within the first 1/2 region 71 in plan view in the 2 nd signal path 5. The 4 th extension 12Z is a portion extending within the first 1/2 region 71 in plan view in the 4 th signal path 12. The imaging device 100 performs correction to reduce the noise component superimposed on the first 1/2 region 71 for both the signal of the 2 nd pixel 3 via the 2 nd extension portion 5Z and the signal of the 4 th pixel 10 via the 4 th extension portion 12Z.

In one embodiment, the correction is an optical black correction. In this specific example, the 2 nd OB pixel 67 and the 2 nd OB path 68 described above are used. The signal processing circuit 43 performs optical black correction using the signal of the 2 nd pixel 67 via the 2 nd extended portion 68Z for both the signal of the 2 nd pixel 3 via the 2 nd extended portion 5Z and the signal of the 4 th pixel 10 via the 4 th extended portion 12Z.

In the example of fig. 13, the portion of the 3 rd signal path 11 extending from the 3 rd pixel 9 to the 2 nd region 62 does not intersect with the portion of the 4 th signal path 12 extending from the 4 th pixel 10 to the 1 st region 61 in a plan view.

Specifically, for example, in a plan view, a portion of the 3 rd signal path 11 extending from the 3 rd pixel 9 to the second 1/2 region 72 does not intersect with a portion of the 4 th signal path 12 extending from the 4 th pixel 10 to the first 1/2 region 71.

In example 1, the 1 st pixel 2 and the 3 rd pixel 9 are 1 st pixels selected from 4 kinds of R pixels, B pixels, gr pixels, and Gb pixels. The 2 nd pixel 3 is a 2 nd pixel selected from 4 kinds of R pixel, B pixel, gr pixel, and Gb pixel. The 1 st pixel and the 2 nd pixel are different from each other. The 1 st example is adapted to reduce signal noise of the 1 st pixel 2 and the 3 rd pixel 9 as the 1 st pixel by correction of the same correction condition.

The 4 th pixel 10 may be the 2 nd pixel. This example is suitable for reducing the signal noise of the 2 nd pixel 3 and the 4 th pixel 10 as the 2 nd pixel by correction of the same correction condition.

In the specific example of example 1, all paths of the signals of the 1 st pixel have a portion extending within the 1 st region 61 in plan view. The entire path of the signal of the 2 nd pixel has a portion extending in the 2 nd region 62 in plan view.

More specifically, for example, the entire path of the signal of the 1 st pixel has a portion extending within the first 1/2 region 71 in plan view. The entire path of the signal of the 2 nd pixel has a portion extending within the second 1/2 region 72 in plan view.

In example 2, 1 st pixel 2 includes 1 st color filter. The 2 nd pixel 3 includes a 2 nd color filter. The 3 rd pixel 9 includes a 3 rd color filter. The 1 st color filter and the 3 rd color filter are 1 st color filters. The 2 nd color filter is a 2 nd color filter different from the 1 st color. The 2 nd example is adapted to reduce signal noise of the 1 st pixel 2 and the 3 rd pixel 9 as pixels including the color filter of the 1 st color by correction of the same correction condition.

The 4 th pixel 10 may include a 4 th color filter of the 2 nd color. This example is suitable for reducing signal noise of the 2 nd pixel 3 and the 4 th pixel 10 which are pixels including the color filter of the 2 nd color by correction of the same correction condition.

In the specific example of example 2, all paths of signals of pixels including the color filter of the 1 st color have portions extending in the 2 nd region 62 in plan view. The entire path of the signal of the pixel including the color filter of the 2 nd color has a portion extending within the 1 st region 61 in plan view.

More specifically, for example, the entire path of the signal of the pixel including the color filter of the 1 st color has a portion extending within the second 1/2 region 72 in plan view. The entire path of the signals of the pixels including the color filter of the 2 nd color has a portion extending within the first 1/2 area 71 in plan view.

In the example of fig. 16, the 2 nd signal path 5 and the 4 th signal path 12 extend in a portion based on the 1 st voltage line 7 different from each other in the 1 st region 61 (specifically, in the first 1/2 region 71) in plan view. However, in plan view, the 2 nd signal path 5 and the 4 th signal path 12 may also extend in a portion based on the same 1 st voltage line 7 in the 1 st region 61 (specifically in the first 1/2 region 71).

In the example of fig. 16, the 1 st signal path 4 and the 3 rd signal path 11 extend in a portion based on the same 2 nd voltage line 8 in the 2 nd region 62 (specifically in the second 1/2 region 72) in plan view. However, in plan view, the 1 st signal path 4 and the 3 rd signal path 11 may also extend in a portion based on the 2 nd voltage line 8 different from each other in the 2 nd region 62 (specifically, in the second 1/2 region 72).

In the specific example of fig. 16, the 1 st voltage of the 1 st voltage line 7 is a power supply voltage. The 2 nd voltage of the 2 nd voltage line 8 is a ground voltage. In fig. 16, "VDD" represents a power supply voltage. "GND" represents a ground voltage. The 2 nd voltage may be a power supply voltage, and the 1 st voltage may be a ground voltage.

As a countermeasure against noise, it is known to provide shield lines or to enlarge the interval between signal paths. However, these countermeasures lead to an increase in layout area. In contrast, in embodiment 2, a part of the signal paths are provided in the 1 st region 61, and the other part of the signal paths are provided in the 2 nd region 62, whereby noise countermeasures are realized. That is, in embodiment 2, by setting a part of the signal paths to be close to the 1 st voltage line 7 and another part of the signal paths to be close to the 2 nd voltage line 8, noise countermeasure is realized. In this way, an increase in layout area can be suppressed.

Using a plurality of signal paths provided within one pixel column pitch can achieve a high speed based on parallel processing, or a low noise based on feedback to the pixel array 1, or the like. Such a speed increase and noise reduction are performed in, for example, a laminated image sensor. According to the noise countermeasure described above, it is possible to suppress an increase in layout area and achieve such a high speed and low noise.

In the case where the 1 st signal path 4 has a feedback path that feeds back to the pixel array 1, the feedback path may also have a portion that extends in the 2 nd region 62 in plan view. In the case where the 2 nd signal path 5 has a feedback path that feeds back to the pixel array 1, the feedback path may also have a portion that extends within the 1 st region 61 in plan view. In the case where the 3 rd signal path 11 has a feedback path that feeds back to the pixel array 1, the feedback path may also have a portion that extends in the 2 nd region 62 in plan view. In the case where the 4 th signal path 12 has a feedback path that feeds back to the pixel array 1, the feedback path may have a portion that extends within the 1 st region 61 in plan view.

Specifically, in the case where the 1 st signal path 4 has a feedback path that feeds back to the pixel array 1, the feedback path may have a portion that extends within the second 1/2 region 72 in a plan view. In the case where the 2 nd signal path 5 has a feedback path that feeds back to the pixel array 1, the feedback path may also have a portion that extends within the first 1/2 region 71 in plan view. In the case where the 3 rd signal path 11 has a feedback path that feeds back to the pixel array 1, the feedback path may also have a portion that extends within the second 1/2 region 72 in plan view. In the case where the 4 th signal path 12 has a feedback path that feeds back to the pixel array 1, the feedback path may also have a portion that extends within the first 1/2 region 71 in plan view.

In fig. 13, the 2 nd voltage line 8, the 1 st voltage line 7, the 2 nd voltage line 8, and the 1 st voltage line 7 are arranged in this order in plan view. Here, consider a case where the 1 st circuit 6 is extended, and the 2 nd voltage line 8 is further provided at the position of the broken line D. In this case, the layout of the 1 st signal path 4 may be changed so that the 1 st signal path 4 extends in a plan view in the portion of the 2 nd voltage line 8 in the 2 nd region 62 (specifically, the second 1/2 region 72) based on the position of the broken line D. In general, the 1 st signal path 4 may extend in a portion based on any 2 nd voltage line 8 in the 2 nd region 62 (specifically the second 1/2 region 72) in plan view. Likewise, the 2 nd signal path 5 may extend within a portion of the 1 st region 61 (specifically the first 1/2 region 71) based on any 1 st voltage line 7. The same applies to other signal paths.

As described above, in the example of fig. 16, the pitches of the plurality of voltage lines 15, 16 in the 2 nd circuit 14 and the pitches of the voltage lines 7, 8 in the 1 st circuit 6 are different from each other in a plan view. Specifically, for example, the plurality of voltage lines 15, 16 in the 2 nd circuit 14 have a 1-column pitch. The voltage lines 7, 8 in the 1 st circuit 6 have a 2-column pitch instead of a 1-column pitch.

The pitch of the plurality of voltage lines 15, 16 in the 2 nd circuit 14 may be the same as the pitch of the voltage lines 7, 8 in the 1 st circuit 6 in plan view.

In the case where the pitch of the voltage lines 15, 16 is the same as the pitch of the voltage lines 7, 8, a description will be given of a situation in which the technique according to embodiment 2 achieves advantageous points with reference to fig. 19A and 19B.

In the example of fig. 19A, the imaging device has a different circuit 94 from the 1 st circuit 6 and the 2 nd circuit 14. The circuit 94 is supplied with a voltage via a plurality of voltage lines 95, 96. The voltage lines 95 and 96 are power lines used in the other circuits 94, but may be noise sources for the signal paths 97 and 98.

In this example, the voltage of the voltage line 95 is a power supply voltage. The voltage of the voltage line 96 is a ground voltage. In fig. 19A, "VDD2" represents a power supply voltage. "GND2" represents a ground voltage. The voltage of the voltage line 96 may be a power supply voltage, and the voltage of the voltage line 95 may be a ground voltage.

In the example of fig. 19A, signal paths 97 of signals of Gr pixels and signal paths 98 of signals of Gb pixels are alternately and repeatedly arranged in a plan view. In plan view, the spacing of the signal paths 97, 98 from the voltage lines 95, 96 is ensured. Thereby, the signal superposition noise from the voltage lines 95, 96 to the signal paths 97, 98 is suppressed.

In order to further reduce noise, as shown in fig. 19B, in the area M1, the signal path 97s is made to intersect with the signal path 98s, so that the signal path 97s can be extended to a position close to the 2 nd voltage line 8 and the signal path 98s can be extended to a position close to the 1 st voltage line 7. In the area M2, the signal path 97t and the signal path 98t intersect each other in a plan view, whereby the signal path 97t can be extended to a position close to the 2 nd voltage line 8 and the signal path 98t can be extended to a position close to the 1 st voltage line 7. In this way, in a plan view, the configuration can be realized in which all the signal paths 97 are extended to positions close to the 2 nd voltage line 8, and all the signal paths 98 are extended to positions close to the 1 st voltage line 7. In this way, by performing correction to reduce noise originating from the 2 nd voltage line 8 on the signals of the plurality of signal paths 97, noise of these signals can be appropriately reduced. By performing correction to reduce noise originating from the 1 st voltage line 7 on the signals of the plurality of signal paths 98, noise of these signals can be appropriately reduced. For this reason, the technique according to embodiment 2 can also obtain an advantage in the case where the pitch of the voltage lines 15, 16 is the same as the pitch of the voltage lines 7, 8. Here, a position near the 1 st voltage line 7 in plan view corresponds to the 1 st region 61, specifically, for example, corresponds to the first 1/2 region 71. The position near the 2 nd voltage line 8 in plan view corresponds to the 2 nd region 62, specifically, for example, corresponds to the second 1/2 region 72.

In the example of fig. 19B, in the 2 nd circuit 14, a certain signal path 97 extends to a position close to the 3 rd voltage line 15, and other signal paths 97 extend to a position close to the 4 th voltage line 16. In the 2 nd circuit 14, a certain signal path 98 extends to a position close to the 3 rd voltage line 15, and other signal paths 98 extend to a position close to the 4 th voltage line 16. This is not necessarily a problem in terms of noise countermeasures. For example, in the case where the length of the 2 nd circuit 14 is short, the influence of the superposition of noise in the 2 nd circuit 14 is limited. When the distance between the signal paths 97 and 98, which are to suppress noise, and the voltage lines 15 and 16, which are noise sources, is short, the influence of the superposition of noise in the 2 nd circuit 14 is also limited. Further, the influence of the superposition of noise can be suppressed by other means such as shielding in the 2 nd circuit 14.

(embodiment 3)

Embodiment 3 will be described below. In embodiment 3, the same reference numerals are given to the same contents as those in embodiment 2, and the description thereof may be omitted.

As shown in fig. 20, in embodiment 3, in the 1 st signal path 4, a portion 4X intersecting the 2 nd signal path 5, a portion intersecting the 3 rd signal path 11, a portion intersecting a straight line 8L including the 2 nd voltage line 8, and a portion 4Z extending in the 2 nd region 62 are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view.

Specifically, for example, in the 1 st signal path 4, a portion 4X intersecting the 2 nd signal path 5, a portion intersecting the 3 rd signal path 11, a portion intersecting a straight line 8L including the 2 nd voltage line 8, and a portion 4Z extending in the second 1/2 region 72 are arranged in this order along the flow direction 2F of the signal of the 1 st pixel 2 in plan view.

In the 3 rd signal path 11, a portion crossing the straight line 8L including the 2 nd voltage line 8, a portion crossing the 1 st signal path 4, and a portion extending in the 2 nd region 62 are arranged in this order in the flow direction of the signal of the 3 rd pixel 9 in plan view.

Specifically, for example, in a plan view, in the 3 rd signal path 11, a portion crossing the straight line 8L including the 2 nd voltage line 8, a portion crossing the 1 st signal path 4, and a portion extending in the second 1/2 region 72 are arranged in this order along the flow direction of the signal of the 3 rd pixel 9.

In the example of fig. 20, in the output section from the pixel array 1, the 1 st signal path 4, the 2 nd signal path 5, the 3 rd signal path 11, and the 4 th signal path 12 are arranged in this order in plan view. In the region closer to the 1 st circuit 6 than the intersections 4X and 5X, the 2 nd signal path 5, the 3 rd signal path 11, the 1 st signal path 4, and the 4 th signal path 12 are arranged in this order in plan view.

In embodiment 3, a portion 4X intersecting the 2 nd signal path 5 and a portion intersecting the 3 rd signal path 11 are arranged in the 1 st signal path 4 in plan view. In a plan view, the 1 st signal path 4 may further intersect with other signal paths. In other words, the number of intersections with other signal paths in the 1 st signal path 4 may be 2 or 3 or more in plan view.

In embodiment 3, in a plan view, in the 1 st signal path 4, there is a portion crossing a straight line 8L including one 2 nd voltage line 8. In a planar view, the 1 st signal path 4 may further intersect a straight line including another voltage line. In other words, the number of intersections with the line including the voltage line in the 1 st signal path 4 may be 1 or 2 or more in plan view.

(embodiment 4)

Embodiment 4 will be described below. In embodiment 4, the same reference numerals are given to the same contents as those in embodiment 1, and the description thereof may be omitted.

In embodiment 1 and the like, correction for reducing noise is performed inside the image pickup apparatus 100. However, correction for reducing noise may be performed outside the image pickup apparatus 100. Embodiment 4 will be described below with reference to fig. 21A to 21C. Although not shown in fig. 21A, the analog-to-digital conversion circuit 40 and the like may be provided between the 1 st circuit 6 and the output circuit 44.

As the correction, for example, optical black correction can be employed. For the optical black correction, the already described technique using the 1 st OB pixel 65 and the 1 st OB path 66 can be utilized. For the optical black correction, the already described technique using the 2 nd OB pixel 67 and the 2 nd OB path 68 can be utilized.

In one embodiment, the imaging system 200 shown in fig. 21A to 21C includes the imaging device 100 and the signal processing device 18 provided outside the imaging device 100. The plurality of pixels includes a 1 st OB pixel 65 as an optical black pixel. The image pickup device 100 includes a 1 st OB path 66 through which the signal of the 1 st OB pixel 65 flows. In plan view, there is a 1 st OB extension 66Z in the 1 st OB path 66 that extends within the 2 nd region 62. The signal processing device 18 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st OB extension 66Z for the signal of the 1 st pixel 2 via the 1 st extension 4Z.

Specifically, for example, the 1 st OB extension 66Z is a portion extending within the second 1/2 region 72 in plan view in the 1 st OB path 66. The 1 st extension 4Z is a portion extending within the second 1/2 region 72 in plan view in the 1 st signal path 4.

In one embodiment, the imaging system 200 shown in fig. 21A to 21C includes the imaging device 100 and the signal processing device 18 provided outside the imaging device 100. The plurality of pixels includes a 2OB pixel 67 as an optical black pixel. The image pickup device 100 includes a 2 nd OB path 68 through which signals of the 2 nd OB pixels 67 flow. In plan view, there is a 2 nd OB extension 68Z extending in the 1 st region 61 in the 2 nd OB path 68. The signal processing means 18 performs optical black correction using the signal of the 2 nd pixel 67 via the 2 nd extended portion 68Z for the signal of the 2 nd pixel 3 via the 2 nd extended portion 5Z.

Specifically, for example, the 2 nd OB extension 68Z is a portion extending within the first 1/2 region 71 in plan view in the 2 nd OB path 68. The 2 nd extension 5Z is a portion extending within the first 1/2 region 71 in plan view in the 2 nd signal path 5.

The correction described in embodiment 2 may be performed outside the imaging apparatus 100. Fig. 22A to 22C show an imaging system 200 suitable for such a correction. The imaging system 200 of fig. 22A to 22C includes the imaging device 100 and the signal processing device 18 provided outside the imaging device 100. The signal processing device 18 performs correction to reduce the noise component superimposed on the 2 nd region 62 for both the 1 st pixel 2 signal via the 1 st extension portion 4Z and the 3 rd pixel 9 signal via the 3 rd extension portion 11Z.

Specifically, for example, the 1 st extension 4Z is a portion extending within the second 1/2 region 72 in a plan view in the 1 st signal path 4. The 3 rd extension 11Z is an extension in the second 1/2 region 72 in plan view in the 3 rd signal path 11. The signal processing device 18 performs correction to reduce the noise component superimposed in the second 1/2 region 72 for both the 1 st pixel 2 signal via the 1 st extension portion 4Z and the 3 rd pixel 9 signal via the 3 rd extension portion 11Z.

In one embodiment, the correction is an optical black correction. In this specific example, the 1 st OB pixel 65 and the 1 st OB path 66 described above are used. The signal processing device 18 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st extended portion 66Z for both the signal of the 1 st pixel 2 via the 1 st extended portion 4Z and the signal of the 3 rd pixel 9 via the 3 rd extended portion 11Z.

In one example, the signal processing device 18 performs correction to reduce the noise component superimposed on the 1 st region 61 for both the signal of the 2 nd pixel 3 via the 2 nd extension portion 5Z and the signal of the 4 th pixel 10 via the 4 th extension portion 12Z.

Specifically, for example, the 2 nd extension portion 5Z is a portion extending within the first 1/2 region 71 in plan view in the 2 nd signal path 5. The 4 th extension 12Z is a portion extending within the first 1/2 region 71 in plan view in the 4 th signal path 12. The signal processing device 18 performs correction to reduce the noise component superimposed in the first 1/2 region 71 for both the signal of the 2 nd pixel 3 via the 2 nd extension portion 5Z and the signal of the 4 th pixel 10 via the 4 th extension portion 12Z.

In one embodiment, the correction is an optical black correction. In this specific example, the 2 nd OB pixel 67 and the 2 nd OB path 68 described above are used. The signal processing device 18 performs optical black correction using the signal of the 2 nd pixel 67 via the 2 nd extended portion 68Z for both the signal of the 2 nd pixel 3 via the 2 nd extended portion 5Z and the signal of the 4 th pixel 10 via the 4 th extended portion 12Z.

The technique of correcting the image outside the imaging device 100 can be applied to other embodiments.

(embodiment 5)

Embodiment 5 will be described below. In embodiment 5, the same reference numerals are given to the same contents as those in embodiment 1, and the description thereof may be omitted.

Fig. 23 shows a pixel array 1 and a 1 st circuit 6 in embodiment 5.

As shown in fig. 23, in the pixel array 1 according to embodiment 5, a plurality of pixels include not only the 1 st pixel 2 and the 2 nd pixel 3 but also the 3 rd pixel 21 and the 4 th pixel 22.

In the example of fig. 23, the 1 st pixel 2 and the 3 rd pixel 21 belong to the same column in the pixel array 1. The 2 nd pixel 3 and the 4 th pixel 22 belong to the same column in the pixel array 1. The columns to which the 1 st pixel 2 and the 3 rd pixel 21 belong and the columns to which the 2 nd pixel 3 and the 4 th pixel 22 belong are adjacent to each other.

In example 1, the 1 st pixel 2 and the 3 rd pixel 21 are 1 st pixels selected from 4 kinds of R pixels, B pixels, gr pixels, and Gb pixels. The 2 nd pixel 3 and the 4 th pixel 22 are 2 nd pixels selected from 4 kinds of R pixels, B pixels, gr pixels, and Gb pixels. Specifically, for example, the 1 st pixel 2 and the 3 rd pixel 21 are Gr pixels. The 2 nd pixel 3 and the 4 th pixel 22 are Gb pixels.

In example 2, the 1 st pixel 2 and the 3 rd pixel 21 are 1 st color pixels. The 2 nd pixel 3 and the 4 th pixel 22 are the 2 nd color pixels. Specifically, for example, the 1 st pixel 2 and the 3 rd pixel 21 include a 1 st color filter. The 2 nd pixel 3 and the 4 th pixel 22 include color filters of the 2 nd color.

Hereinafter, a path through which a signal of the 3 rd pixel 21 flows may be referred to as a 3 rd signal path 4B. The path through which the signal of the 4 th pixel 22 flows is sometimes referred to as a 4 th signal path 5B.

In the example of fig. 23, from the output section of the pixel array 1, the 1 st signal path 4, the 3 rd signal path 4B, the 4 th signal path 5B, and the 2 nd signal path 5 are arranged in this order in plan view. In the region closer to the 1 st circuit 6 than the intersections 4X and 5X, the 4 th signal path 5B, the 2 nd signal path 5, the 1 st signal path 4, and the 3 rd signal path 4B are arranged in this order in plan view.

In the example of fig. 23, in the 1 st signal path 4, the intersection 4X intersecting the 2 nd signal path 5 and the 1 st extension 4Z extending in the 2 nd region 62 are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view. In the 3 rd signal path 4B, the intersection intersecting the 4 th signal path 5B and the 3 rd extension 4BZ extending in the 2 nd region 62 are arranged in this order in the flow direction 21F of the signal of the 3 rd pixel 21 in plan view. Such a layout facilitates correction for reducing noise of the signal of the 1 st pixel 2 and the signal of the 3 rd pixel 21. Specifically, according to such a layout, a difference in noise component superimposed on the signal of the 1 st pixel 2 and the signal of the 3 rd pixel 21 in the 1 st circuit 6 is less likely to occur than in the case where one of the 1 st signal path 4 and the 3 rd signal path 4B extends in the 2 nd region 62 and the other extends in the 1 st region 61. Thus, such a layout is suitable for reducing these signal noises by correction of the same correction conditions.

In the example of fig. 23, in the 2 nd signal path 5, the intersection 5X intersecting the 1 st signal path 4 and the 2 nd extension 5Z extending in the 1 st region 61 are arranged in this order in the signal flow direction 3F of the 2 nd pixel 3 in plan view. In the 4 th signal path 5B, the intersection intersecting the 3 rd signal path 4B and the 4 th extension 5BZ extending in the 1 st region 61 are arranged in this order in the flow direction 22F of the signal of the 4 th pixel 22 in plan view. Such a layout facilitates correction for reducing noise of the signal of the 2 nd pixel 3 and the signal of the 4 th pixel 22. Specifically, according to such a layout, a difference in noise component superimposed on the signal of the 2 nd pixel 3 and the signal of the 4 th pixel 22 in the 1 st circuit 6 is less likely to occur than in the case where one of the 2 nd signal path 5 and the 4 th signal path 5B extends in the 1 st region 61 and the other extends in the 2 nd region 62. Thus, such a layout is suitable for reducing these signal noises under correction of the same correction conditions.

Specifically, for example, the 1 st extension 4Z is a portion where the 1 st signal path 4 extends in the second 1/2 region 72 in plan view. The 3 rd extension 4BZ is a portion of the 3 rd signal path 4B extending in the second 1/2 region 72 in plan view. The 2 nd extension 5Z is a portion of the 2 nd signal path 5 extending in the first 1/2 region 71 in plan view. The 4 th extension portion 5BZ is a portion of the 4 th signal path 5B extending in the first 1/2 region 71 in plan view.

A method example of correction for reducing noise is described. In the example of fig. 23, the signal processing circuit 43 performs correction to reduce the noise component superimposed in the 2 nd region 62 for both the 1 st pixel 2 signal via the 1 st extension portion 4Z and the 3 rd pixel 21 signal via the 3 rd extension portion 4 BZ. According to this example, the same correction conditions are easily applied to the correction of the signal of the 1 st pixel 2 and the correction of the signal of the 3 rd pixel 21.

Specifically, for example, the 1 st extension 4Z is a portion extending within the second 1/2 region 72 in a plan view in the 1 st signal path 4. The 3 rd extension 4BZ is a portion extending within the second 1/2 region 72 in plan view in the 3 rd signal path 4B. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the second 1/2 region 72 for both the signal of the 1 st pixel 2 via the 1 st extension portion 4Z and the signal of the 3 rd pixel 21 via the 3 rd extension portion 4 BZ.

In one embodiment, the correction is an optical black correction. In this specific example, the 1 st OB pixel 65 and the 1 st OB path 66 described above are used. The signal processing circuit 43 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st extension 66Z for both the signal of the 1 st pixel 2 via the 1 st extension 4Z and the signal of the 3 rd pixel 21 via the 3 rd extension 4 BZ.

In the example of fig. 23, the signal processing circuit 43 performs correction to reduce the noise component superimposed in the 1 st region 61 for both the signal of the 2 nd pixel 3 via the 2 nd extension portion 5Z and the signal of the 4 th pixel 22 via the 4 th extension portion 5 BZ. According to this example, the same correction conditions are easily applied to the correction of the signal of the 2 nd pixel 3 and the correction of the signal of the 4 th pixel 22.

Specifically, for example, the 2 nd extension portion 5Z is a portion extending within the first 1/2 region 71 in plan view in the 2 nd signal path 5. The 4 th extension portion 5BZ is a portion extending within the first 1/2 region 71 in plan view in the 4 th signal path 5B. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the first 1/2 region 71 for both the signal of the 2 nd pixel 3 via the 2 nd extension portion 5Z and the signal of the 4 th pixel 22 via the 4 th extension portion 5 BZ.

In one embodiment, the correction is an optical black correction. In this specific example, the 2 nd OB pixel 67 and the 2 nd OB path 68 described above are used. The signal processing circuit 43 performs optical black correction using the signal of the 2 nd pixel 67 via the 2 nd extended portion 68Z for both the signal of the 2 nd pixel 3 via the 2 nd extended portion 5Z and the signal of the 4 th pixel 22 via the 4 th extended portion 5 BZ.

The 1 st example is adapted to reduce noise of signals of the 1 st pixel 2 and the 3 rd pixel 21 as the 1 st pixel by correction of the same correction condition. The 1 st example is adapted to reduce noise of signals of the 2 nd pixel 3 and the 4 th pixel 22, which are the 2 nd pixels, by correction of the same correction conditions.

The 2 nd example is adapted to reduce noise of signals of the 1 st pixel 2 and the 3 rd pixel 21 as pixels including the color filter of the 1 st color by correction of the same correction condition. The 2 nd example is adapted to reduce noise of signals of the 2 nd pixel 3 and the 4 th pixel 22, which are pixels including the color filter of the 2 nd color, by correction of the same correction condition.

As shown in fig. 24, the 1 st voltage line 7B may be added. The 1 st voltage is applied to the 1 st voltage line 7B in the same manner as the 1 st voltage line 7. In the example of fig. 24, the 1 st voltage line 7, the 4 th signal path 5B, the 2 nd signal path 5, and the 1 st voltage line 7B are arranged in this order in plan view. The distance between the 1 st voltage line 7 and the 4 th signal path 5B is the same as the distance between the 2 nd signal path 5 and the 1 st voltage line 7B in plan view. Thus, the difference between the noise superimposed on the signal of the 4 th signal path 5B in the 1 st area 61 and the noise superimposed on the signal of the 2 nd signal path 5 in the 1 st area 61 becomes small. Therefore, the example of fig. 24 is suitable for reducing noise of the signals of the 2 nd pixel 3 and the 4 th pixel 22 by correction of the same correction condition.

As shown in fig. 24, the 2 nd voltage line 8B may be added. The 2 nd voltage is applied to the 2 nd voltage line 8B in the same manner as the 2 nd voltage line 8. In the example of fig. 24, the 2 nd voltage line 8B, the 1 st signal path 4, the 3 rd signal path 4B, and the 2 nd voltage line 8 are arranged in this order in plan view. The distance between the 2 nd voltage line 8B and the 1 st signal path 4 is the same as the distance between the 3 rd signal path 4B and the 2 nd voltage line 8 in plan view. Thus, the difference between the noise superimposed on the signal of the 1 st signal path 4 in the 2 nd region 62 and the noise superimposed on the signal of the 3 rd signal path 4B in the 2 nd region 62 becomes small. Therefore, the example of fig. 24 is suitable for reducing noise of the signals of the 1 st pixel 2 and the 3 rd pixel 21 by correction of the same correction conditions.

As shown in fig. 25, the 1 st signal path 4 and the 3 rd signal path 4B may intersect at a point intermediate the lengths of the 2 nd voltage lines 8 in a plan view. Here, the intermediate point is, for example, a portion in the middle of the length 3, and specifically, for example, a position of the length 2. In this way, the difference between the coupling capacitance between the 1 st signal path 4 and the 2 nd voltage line 8 and the coupling capacitance between the 3 rd signal path 4B and the 2 nd voltage line 8 can be reduced. Thus, the difference between the noise superimposed on the signal of the 1 st signal path 4 in the 2 nd region 62 and the noise superimposed on the signal of the 3 rd signal path 4B in the 2 nd region 62 becomes small. Therefore, the example of fig. 25 is suitable for reducing noise of the signals of the 1 st pixel 2 and the 3 rd pixel 21 by correction of the same correction conditions.

As shown in fig. 25, the 2 nd signal path 5 and the 4 th signal path 5B may intersect at a point intermediate the lengths of the 1 st voltage lines 7 in a plan view. Here, the intermediate point is, for example, a portion in the middle of the length 3, and specifically, for example, a position of the length 2. In this way, the difference between the coupling capacitance between the 2 nd signal path 5 and the 1 st voltage line 7 and the coupling capacitance between the 4 th signal path 5B and the 1 st voltage line 7 can be reduced. Thus, the difference between the noise superimposed on the signal of the 2 nd signal path 5 in the 1 st region 61 and the noise superimposed on the signal of the 4 th signal path 5B in the 1 st region 61 becomes small. Therefore, the example of fig. 25 is suitable for reducing noise of the signals of the 2 nd pixel 3 and the 4 th pixel 22 by correction of the same correction condition.

(embodiment 6)

Embodiment 6 will be described below. In embodiment 6, the same reference numerals are given to the same contents as those in embodiment 2, and the description thereof may be omitted.

Fig. 26 shows the pixel array 1 and the 1 st circuit 6 in embodiment 6.

As shown in fig. 26, in the pixel array 1 of embodiment 6, the plurality of pixels includes a 1 st pixel 23, a 2 nd pixel 24, a 3 rd pixel 25, a 4 th pixel 26, a 5 th pixel 23C, a 6 th pixel 24C, a 7 th pixel 25C, and an 8 th pixel 26C.

Hereinafter, a path through which a signal of the 1 st pixel 23 flows may be referred to as a 1 st signal path 4. The path through which the signal of the 2 nd pixel 24 flows is sometimes referred to as a 2 nd signal path 5. The path through which the signal of the 3 rd pixel 25 flows is sometimes referred to as a 3 rd signal path 11. The path through which the signal of the 4 th pixel 26 flows is sometimes referred to as the 4 th signal path 12. The path through which the signal of the 5 th pixel 23C flows is sometimes referred to as a 5 th signal path 4C. The path through which the signal of the 6 th pixel 24C flows is sometimes referred to as a 6 th signal path 5C. The path through which the signal of the 7 th pixel 25C flows is sometimes referred to as a 7 th signal path 11C. The path through which the signal of the 8 th pixel 26C flows is sometimes referred to as an 8 th signal path 12C.

The 1 st signal path 4, the 2 nd signal path 5, the 3 rd signal path 11, and the 4 th signal path 12 can have the same features as embodiment 2. For example, in plan view, the 1 st signal path 4 intersects the 2 nd signal path 5.

In plan view, there is a portion extending within the 1 st region 61 in the 5 th signal path 4C. In plan view, there is a portion extending within the 2 nd region 62 in the 6 th signal path 5C. In plan view, there is a portion extending within the 1 st region 61 in the 7 th signal path 11C. In plan view, there is a portion of the 8 th signal path 12C that extends within the 2 nd region 62.

Specifically, for example, in a plan view, there is a portion extending within the first 1/2 region 71 in the 5 th signal path 4C. In plan view, there is a portion extending within the second 1/2 region 72 in the 6 th signal path 5C. In plan view, there is a portion extending within the first 1/2 region 71 in the 7 th signal path 11C. In plan view, there is a portion extending within the second 1/2 region 72 in the 8 th signal path 12C.

In this example, in the 2 nd signal path 5, the 4 th signal path 12, the 5 th signal path 4C, and the 7 th signal path 11C, there are portions extending within the 1 st region 61 in plan view. Specifically, for example, in the 2 nd signal path 5, the 4 th signal path 12, the 5 th signal path 4C, and the 7 th signal path 11C, there are portions extending within the first 1/2 region 71 in plan view. Therefore, in the 2 nd signal path 5, the 4 th signal path 12, the 5 th signal path 4C, and the 7 th signal path 11C, a difference is less likely to occur in the noise component superimposed on the signal in the 1 st circuit 6. Therefore, this example is suitable for reducing noise of these signals under correction of the same correction conditions. For these signals, the above-described correction of reducing the noise component superimposed in the 1 st area 61 can be performed. Specifically, for example, with respect to these signals, the above-described correction of reducing the noise component superimposed in the first 1/2 region 71 can be performed.

In this example, in the 1 st signal path 4, the 3 rd signal path 11, the 6 th signal path 5C, and the 8 th signal path 12C, there are portions extending in the 2 nd region 62 in plan view. Specifically, for example, in the 1 st signal path 4, the 3 rd signal path 11, the 6 th signal path 5C, and the 8 th signal path 12C, there are portions extending within the second 1/2 region 72 in plan view. Therefore, in the 1 st signal path 4, the 3 rd signal path 11, the 6 th signal path 5C, and the 8 th signal path 12C, a difference is less likely to occur in the noise component superimposed on the signal in the 1 st circuit 6. Therefore, this example is suitable for reducing noise of these signals under correction of the same correction conditions. For these signals, the above-described correction of reducing the noise component superimposed in the 2 nd region 62 can be performed. Specifically, with respect to these signals, the above-described correction of reducing the noise component superimposed in the second 1/2 region 72 can be performed.

In the example of fig. 26, in the output section from the pixel array 1, the 1 st signal path 4, the 5 th signal path 4C, the 6 th signal path 5C, the 2 nd signal path 5, the 3 rd signal path 11, the 7 th signal path 11C, the 8 th signal path 12C, and the 4 th signal path 12 are arranged in this order in plan view. In the region closer to the 1 st circuit 6 than the intersections 4X and 5X, the 5 th signal path 4C, the 2 nd signal path 5, the 1 st signal path 4, the 6 th signal path 5C, the 3 rd signal path 11, the 8 th signal path 12C, the 7 th signal path 11C, and the 4 th signal path 12 are arranged in this order in plan view.

The intersection of the paths is performed in a plan view so that the arrangement of the paths changes in the region from the output portion of the pixel array 1 to the region near the 1 st circuit 6. Specifically, for example, in a plan view, the 1 st signal path 4 and the 5 th signal path 4C intersect between the output portion of the pixel array 1 and a region close to the 1 st circuit 6. Meanwhile, the 2 nd signal path 5 crosses the 6 th signal path 5C. In between, the 1 st signal path 4 crosses the 2 nd signal path 5. Meanwhile, the 7 th signal path 11C crosses the 8 th signal path 12C.

In the example of fig. 26, the 1 st pixel 23 and the 5 th pixel 23C belong to the same column in the pixel array 1. The 2 nd pixel 24 and the 6 th pixel 24C belong to the same column in the pixel array 1. The 3 rd pixel 25 and the 7 th pixel 25C belong to the same column in the pixel array 1. The 4 th pixel 26 and the 8 th pixel 26C belong to the same column in the pixel array 1. The 4 columns are arranged adjacently in the illustrated order.

In example 1, the 1 st pixel 23 and the 3 rd pixel 25 are 1 st pixels selected from 4 kinds of R pixels, B pixels, gr pixels, and Gb pixels. The 2 nd pixel 24 and the 4 th pixel 26 are the 2 nd pixel selected from the 4 kinds. The 5 th pixel 23C and the 7 th pixel 25C are 3 rd pixels selected from the 4 kinds. The 6 th pixel 24C and the 8 th pixel 26C are 4 th pixels selected from the 4 kinds. The 1 st pixel, the 2 nd pixel, the 3 rd pixel, and the 4 th pixel are different from each other.

Specifically, for example, the 1 st pixel 23 and the 3 rd pixel 25 are Gr pixels. The 2 nd pixel 24 and the 4 th pixel 26 are R pixels. The 5 th pixel 23C and the 7 th pixel 25C are B pixels. The 6 th pixel 24C and the 8 th pixel 26C are Gb pixels.

In example 2, the 1 st pixel 23 and the 3 rd pixel 25 are 1 st color pixels. The 2 nd pixel 24 and the 4 th pixel 26 are the 2 nd color pixels. The 5 th pixel 23C and the 7 th pixel 25C are pixels of the 3 rd color. The 6 th pixel 24C and the 8 th pixel 26C are the 4 th color pixels. Color 1, color 2, color 3, and color 4 are different from each other.

Specifically, for example, the 1 st pixel 23 and the 3 rd pixel 25 include color filters of the 1 st color. The 2 nd pixel 24 and the 4 th pixel 26 include color filters of the 2 nd color. The 5 th pixel 23C and the 7 th pixel 25C include a color filter of the 3 rd color. The 6 th pixel 24C and the 8 th pixel 26C include color filters of the 4 th color.

The readout order of the pixels is not particularly limited. After the 1 st pixel 23, the 2 nd pixel 24, the 3 rd pixel 25, and the 4 th pixel 26 are read out, the 5 th pixel 23C, the 6 th pixel 24C, the 7 th pixel 25C, and the 8 th pixel 26C may be read out. The 1 st pixel 23, the 2 nd pixel 24, the 3 rd pixel 25, the 4 th pixel 26, the 5 th pixel 23C, the 6 th pixel 24C, the 7 th pixel 25C, and the 8 th pixel 26C may be read out at the same time.

(embodiment 7)

Embodiment 7 will be described below. In embodiment 7, the same reference numerals are given to the same contents as those in embodiment 1, and the description thereof may be omitted.

As shown in fig. 27, the imaging device according to embodiment 7 includes a selector 27. In embodiment 7, a part of the 1 st signal path 4 is constituted by the selector 27. A part of the 2 nd signal path 5 is constituted by the selector 27. Fig. 28 shows the structure of the selector 27.

In embodiment 7, in the 1 st signal path 4, the 1 st connection point 29A, the 1 st intersection 4X, the 2 nd connection point 29B, and the 1 st extension 4Z are arranged in this order in the signal flow direction 2F of the 1 st pixel 2 in plan view. In the 2 nd signal path 5, the 3 rd connection point 29C, the 2 nd intersection 5X, the 4 th connection point 29D, and the 2 nd extension 5Z are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. The imaging device is provided with a selector 27. The selector 27 includes a 1 st switch 28A, a 2 nd switch 28B, a 3 rd switch 28C, and a 4 th switch 28D. The 1 st switch 28A electrically connects the 1 st connection point 29A to the 4 th connection point 29D. The 2 nd switch 28B electrically connects the 1 st connection point 29A to the 2 nd connection point 29B. The 3 rd switch 28C electrically connects the 3 rd connection point 29C with the 4 th connection point 29D. The 4 th switch 28D electrically connects the 3 rd connection point 29C with the 2 nd connection point 29B. The selector 27 can switch the paths of signals of the pixels.

In other words, the 1 st switch 28A is connected between the 1 st connection point 29A and the 4 th connection point 29D. The 2 nd switch 28B is connected between the 1 st connection point 29A and the 2 nd connection point 29B. The 3 rd switch 28C is connected between the 3 rd connection point 29C and the 4 th connection point 29D. The 4 th switch 28D is connected between the 3 rd connection point 29C and the 2 nd connection point 29B.

The 2 nd switch 28B is disposed on the 1 st signal path 4. The 3 rd switch 28C is disposed on the 2 nd signal path 5.

In this example, the selector 27 includes a 1 st connection point 29A, a 2 nd connection point 29B, a 3 rd connection point 29C, and a 4 th connection point 29D.

The 1 st switch 28A, the 2 nd switch 28B, the 3 rd switch 28C, and the 4 th switch 28D may be configured to be switchable between an ON (ON) state and an OFF (OFF) state by electric control. The switches may also be fixed in a closed state or an open state. The control circuit 42 may control the switching between the on state and the off state of the 1 st to 4 th switches 28A to 28D.

When the 1 st switch 28A and the 4 th switch 28D are in an open state and the 2 nd switch 28B and the 3 rd switch 28C are in a closed state, the signals of the 1 st pixel 2 and the signals of the 2 nd pixel 3 flow similarly to the 1 st embodiment.

The method of using the selector 27 is further described below.

For example, the noise component in the 2 nd voltage line 8 is set smaller than the noise component in the 1 st voltage line 7. In this case, pixels may be read out every 1 line. Specifically, after the 1 st pixel 2 is read out, the 2 nd pixel 3 may be read out. In this case, the 1 st pixel 2 can be read by initially setting the 2 nd switch 28B to the closed state and setting the 1 st switch 28A, the 3 rd switch 28C, and the 4 th switch 28D to the open state. Then, the 4 th switch 28D is set to the closed state, and the 1 st switch 28A, the 2 nd switch 28B, and the 3 rd switch 28C are set to the open state, whereby the 2 nd pixel 3 can be read out. In this way, both the signal of the 1 st pixel 2 and the signal of the 2 nd pixel 3 can be made to pass through the vicinity of the 2 nd voltage line 8 where the noise component is relatively small. This allows the 1 st pixel 2 and the 2 nd pixel 3 to be read out with low noise. The control of the readout of these images is performed by, for example, the line scanning circuit 41 and the control circuit 42.

After the imaging device is configured, the on/off of the 1 st switch 28A, the 2 nd switch 28B, the 3 rd switch 28C, and the 4 th switch 28D may be switched by electric control. For example, after the imaging device is configured, the noise on the voltage lines 7 and 8 may be actually measured, and whether the signal of the pixel passes through the vicinity of the voltage line 8 or the vicinity of the voltage line 7 may be selected based on the result. In this way, noise can be reduced by performing only the electric control of the selector 27 without reconstructing the image pickup apparatus.

(specific example of imaging System)

A specific example of the imaging system will be described below. The imaging system of this specific example can be used for a smart phone, a video camera, a digital camera, a monitoring camera, an in-vehicle camera, and the like.

Fig. 29 shows a specific example of an imaging system 200. The system 200 includes a lens 110, an imaging device 100, a signal processing unit 120, and a system controller 130.

The lens 110 is an optical element for introducing incident light into the pixel array 1 provided in the image pickup device 100.

The image pickup device 100 converts image light imaged on an image pickup surface by the lens 110 into an electric signal in pixel units, and outputs the resultant image signal. The image signal is a set of signals of a plurality of pixels in the above-described embodiment. As the image pickup apparatus 100, the image pickup apparatus of the above-described embodiment can be used. The imaging device according to the embodiment described above can contribute to the formation of an image with less noise.

The signal processing unit 120 is a circuit that performs various processes on an image signal generated in the image pickup device 100. In one example, the image signal processed by the signal processing unit 120 is recorded as a still image or a moving image on a recording medium such as a memory. In another example, an image signal is displayed as a moving image on a monitor made up of a liquid crystal display or the like. The signal processing section 120 can include the signal processing device 18 of fig. 21.

The system controller 130 is a control unit that drives the imaging device 100 and the signal processing unit 120.

The imaging device and the imaging system according to the embodiment of the present disclosure have been described above, but the present disclosure is not limited to this embodiment.

For example, division of functional blocks in a block diagram is an example, and a plurality of functional blocks may be implemented as one functional block, or one functional block may be divided into a plurality of functional blocks, or some of the functions may be transferred to other functional blocks.

Each processing unit included in each device of the above embodiment is typically implemented as an LSI, which is an integrated circuit. Each of the processing units may be individually formed into a single chip, or may be formed into a single chip so as to include a part or all of the processing units.

The integrated circuit is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (field programmable gate array Field Programmable Gate Array) which can be programmed after LSI production, or a reconfigurable processor (reconfigurable processor) which can reconstruct connection and setting of circuit cells inside an LSI, may be used.

In the above embodiments, a part of each component may be realized by executing a software program suitable for the component. The constituent elements may be realized by a program execution unit such as a CPU or a processor reading and executing a software program recorded in a recording medium such as a hard disk or a semiconductor memory.

The intersection in the above-described portions 4X and 5X in plan view is not necessary. In order to solve some or all of the problems or to achieve some or all of the effects, the technical features shown in the above embodiments and modifications may be replaced or combined as appropriate. In addition, technical features not necessarily described in the present disclosure can be appropriately deleted.

Industrial applicability

The imaging device of the present disclosure can be used for various camera systems such as a digital camera, a medical camera, a monitoring camera, an in-vehicle camera, a digital single lens reflex camera, and a digital mirror-less interchangeable lens camera, and a sensor system.

Claims (19)

1. An image pickup device is provided with:

a plurality of pixels including a 1 st pixel and a 2 nd pixel;

a 1 st circuit including a 1 st wiring portion including one or more 1 st voltage lines to which a 1 st voltage is applied, and a 2 nd wiring portion including one or more 2 nd voltage lines to which a 2 nd voltage different from the 1 st voltage is applied;

a 1 st signal path through which a signal of the 1 st pixel flows; and

a 2 nd signal path through which a signal of the 2 nd pixel flows,

In a plan view, when a region closer to each of the one or more 1 st voltage lines than to any of the one or more 2 nd voltage lines is defined as a 1 st region, a region closer to each of the one or more 2 nd voltage lines than to any of the one or more 1 st voltage lines is defined as a 2 nd region,

the 1 st signal path includes a 1 st intersection intersecting the 2 nd signal path, and a 1 st extension extending within the 2 nd region,

the 2 nd signal path includes a 2 nd crossing portion crossing the 1 st signal path and a 2 nd extension portion extending in the 1 st region,

in the flow of the 1 st pixel signal, the 1 st intersection is located upstream of the 1 st extension,

in the flow of the signal of the 2 nd pixel, the 2 nd intersection is located upstream of the 2 nd extension.

2. The image pickup apparatus according to claim 1,

the 1 st voltage is a power supply voltage,

the 2 nd voltage is a ground voltage.

3. The image pickup apparatus according to claim 1 or 2,

the plurality of pixels forms a pixel array having at least one row and a plurality of columns,

The column to which the 1 st pixel in the pixel array belongs and the column to which the 2 nd pixel in the pixel array belong are adjacent to each other.

4. The image pickup apparatus according to claim 1 or 2,

the one or more 1 st voltage lines, the one or more 2 nd voltage lines, the 1 st extension portion, and the 2 nd extension portion extend parallel to each other in the plan view.

5. The image pickup apparatus according to claim 1 or 2,

the imaging device includes a multilayer wiring layer including a 1 st wiring layer and a 2 nd wiring layer different from the 1 st wiring layer,

the 1 st wiring layer includes the 1 st intersection,

the 2 nd wiring layer includes the 2 nd intersection.

6. The image pickup apparatus according to claim 1 or 2,

in the plane view of the device, in the plane view,

the 1 st signal path further comprises a 1 st connection point and a 2 nd connection point,

the 2 nd signal path further comprises a 3 rd connection point and a 4 th connection point,

in the flow of the 1 st pixel signal, the 1 st connection point is located upstream of the 1 st intersection, the 2 nd connection point is located between the 1 st intersection and the 1 st extension,

in the flow of the signal of the 2 nd pixel, the 3 rd connection point is located upstream of the 2 nd intersection, the 4 th connection point is located between the 2 nd intersection and the 2 nd extension,

The image pickup apparatus may further be provided with a selector,

the selector includes:

a 1 st switch connected between the 1 st connection point and the 4 th connection point;

a 2 nd switch connected between the 1 st connection point and the 2 nd connection point;

a 3 rd switch connected between the 3 rd connection point and the 4 th connection point; and

and a 4 th switch connected between the 3 rd connection point and the 2 nd connection point.

7. The image pickup apparatus according to claim 1 or 2,

the image pickup apparatus further includes a 2 nd circuit including a 3 rd wiring portion and a 4 th wiring portion, the 3 rd wiring portion including one or more voltage lines, the 4 th wiring portion including a plurality of voltage lines,

the one or more voltage lines of the 3 rd wiring part include a 3 rd voltage line,

the plurality of voltage lines of the 4 th wiring section include a 4 th voltage line and a 5 th voltage line adjacent to the 3 rd voltage line,

the 3 rd voltage line is located between the 4 th and 5 th voltage lines,

in the plane view of the device, in the plane view,

the pitches of the 4 th voltage line, the 3 rd voltage line, and the 5 th voltage line are different from those of the one or more 1 st voltage lines and the one or more 2 nd voltage lines,

When the region between the 3 rd voltage line and the 4 th voltage line is defined as a 1 st pitch region and the region between the 3 rd voltage line and the 5 th voltage line is defined as a 2 nd pitch region,

the 1 st signal path further comprises: a 1 st pitch portion extending within the 1 st pitch region,

the 2 nd signal path further comprises: a 2 nd pitch portion extending within the 2 nd pitch region,

in the flow of the 1 st pixel signal, the 1 st pitch section is located upstream of the 1 st intersection,

in the flow of the signal of the 2 nd pixel, the 2 nd pitch portion is located upstream of the 2 nd intersection.

8. The image pickup apparatus according to claim 1 or 2,

the 1 st circuit further includes a 1 st transistor of a 1 st conductivity type and a 2 nd transistor of a 2 nd conductivity type different from the 1 st conductivity type,

the 1 st transistor is connected to any one of the one or more 1 st voltage lines,

the 2 nd transistor is connected to any one of the one or more 2 nd voltage lines.

9. The image pickup apparatus according to claim 1 or 2,

the image pickup apparatus further includes a 2 nd circuit,

the 1 st circuit further includes a 1 st transistor of a 1 st conductivity type and a 2 nd transistor of a 2 nd conductivity type different from the 1 st conductivity type,

The 2 nd circuit includes the 3 rd transistor of the 1 st conductivity type and the 4 th transistor of the 2 nd conductivity type,

when the center of gravity of the gate of the 1 st transistor and the gate of the 2 nd transistor are defined as 1 st center of gravity and the center of gravity of the gate of the 3 rd transistor and the gate of the 4 th transistor are defined as 2 nd center of gravity, in the plan view,

the arrangement direction of the 1 st transistor and the 2 nd transistor and the arrangement direction of the 3 rd transistor and the 4 th transistor are different from each other,

the 1 st signal path includes a portion closest to the 2 nd center of gravity and a portion closest to the 1 st center of gravity,

the 2 nd signal path includes a portion closest to the 2 nd center of gravity and a portion closest to the 1 st center of gravity,

in the flow of the signal of the 1 st pixel, the portion closest to the 2 nd center of gravity is located upstream of the portion closest to the 1 st center of gravity,

in the flow of the signal of the 2 nd pixel, the portion closest to the 2 nd center of gravity is located upstream of the portion closest to the 1 st center of gravity.

10. The image pickup apparatus according to claim 1 or 2,

The plurality of pixels includes a 1OB pixel as an optical black pixel,

the image pickup apparatus further includes a signal processing circuit, a 1 st OB path through which a signal of the 1 st OB pixel flows,

in the plan view, the 1 st OB path includes: a 1OB extension extending in said 2 nd region,

the signal processing circuit performs optical black correction using a signal of the 1 st pixel via the 1 st extension for a signal of the 1 st pixel via the 1 st extension.

11. The image pickup apparatus according to claim 1 or 2,

the plurality of pixels includes a 3 rd pixel,

the image pickup apparatus further includes a 3 rd signal path through which a signal of the 3 rd pixel flows,

in the planar view, the 3 rd signal path includes: a 3 rd extension extending in the 2 nd region.

12. The image pickup apparatus according to claim 11,

the plurality of pixels includes a 4 th pixel,

the image pickup apparatus further includes a 4 th signal path through which a signal of the 4 th pixel flows,

in the planar view, the 4 th signal path includes: a 4 th extension extending in the 1 st region.

13. The image pickup apparatus according to claim 12,

In the plane view of the device, in the plane view,

the 3 rd signal path includes a portion extending from the 3 rd pixel to the 2 nd region,

the 4 th signal path includes a portion extending from the 4 th pixel to the 1 st region,

the portion extending from the 3 rd pixel to the 2 nd region does not intersect the portion extending from the 4 th pixel to the 1 st region.

14. The image pickup apparatus according to claim 11,

the 1 st pixel includes a 1 st color filter,

the 2 nd pixel includes a 2 nd color filter,

the 3 rd pixel comprises a 3 rd color filter,

the 1 st color filter and the 3 rd color filter are 1 st color filters,

the 2 nd color filter is a 2 nd color filter different from the 1 st color.

15. The image pickup apparatus according to claim 11,

the 1 st pixel and the 3 rd pixel are 1 st pixels selected from 4 kinds of pixels of an R pixel, a B pixel, a Gr pixel, and a Gb pixel,

the 2 nd pixel is a 2 nd pixel selected from 4 kinds of R pixel, B pixel, gr pixel and Gb pixel,

the 1 st pixel and the 2 nd pixel are different from each other.

16. The image pickup apparatus according to claim 11,

the image pickup apparatus is further provided with a signal processing circuit,

The signal processing circuit performs correction to reduce a noise component superimposed in the 2 nd region for both the 1 st pixel signal via the 1 st extension portion and the 3 rd pixel signal via the 3 rd extension portion.

17. The image pickup apparatus according to claim 11,

the plurality of pixels includes a 1OB pixel as an optical black pixel,

the image pickup apparatus further includes a signal processing circuit, a 1 st OB path through which a signal of the 1 st OB pixel flows,

in the plan view, the 1 st OB path includes: a 1OB extension extending in said 2 nd region,

the signal processing circuit performs optical black correction using a signal of the 1 st pixel via the 1 st extension for a signal of the 1 st pixel via the 1 st extension.

18. An imaging system is provided with:

the image pickup apparatus of any one of claims 1 to 9 and 11 to 15; and

a signal processing device arranged outside the image pickup device,

the plurality of pixels includes a 1OB pixel as an optical black pixel,

the image pickup apparatus further has a 1 st OB path through which a signal of the 1 st OB pixel flows,

In the plan view, the 1 st OB path includes: a 1OB extension extending in said 2 nd region,

the signal processing means performs optical black correction using the signal of the 1 st pixel via the 1 st extension for the signal of the 1 st pixel via the 1 st extension.

19. An imaging system is provided with:

the image pickup apparatus according to any one of claims 11 to 15; and

a signal processing device arranged outside the image pickup device,

the signal processing device performs correction to reduce a noise component superimposed in the 2 nd region for both the 1 st pixel signal via the 1 st extension portion and the 3 rd pixel signal via the 3 rd extension portion.

Images