CN111193842A - Image pickup apparatus and image pickup system - Google Patents

Image pickup apparatus and image pickup system Download PDF

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Publication number
CN111193842A
CN111193842A CN201910806906.5A CN201910806906A CN111193842A CN 111193842 A CN111193842 A CN 111193842A CN 201910806906 A CN201910806906 A CN 201910806906A CN 111193842 A CN111193842 A CN 111193842A
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China
Prior art keywords
pixel
signal
voltage
signal path
region
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CN201910806906.5A
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Chinese (zh)
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CN111193842B (en
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西谷贵幸
小林努
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Color Television Image Signal Generators (AREA)

Abstract

The present disclosure provides an imaging apparatus and an imaging system, and provides a technique capable of contributing to noise reduction in the presence of a plurality of voltage lines to which mutually different voltages are applied. The 1 st signal path (4) includes a 1 st intersection (4X) that intersects the 2 nd signal path (5), and a 1 st extension (4Z) that extends within the 2 nd region (62). The 2 nd signal path (5) includes a 2 nd intersection (5X) intersecting the 1 st signal path (4) and a 2 nd extension (5Z) extending in the 1 st region (61). In the flow of the signal of the 1 st pixel (2), the 1 st intersection (4X) is located upstream of the 1 st extension (4Z). In the flow of the signal of the 2 nd pixel (3), the 2 nd intersection (5X) is located upstream of the 2 nd extension (5Z).

Description

Image pickup apparatus and image pickup system
Technical Field
The present disclosure relates to an imaging apparatus and an imaging system.
Background
Various imaging devices are known. An example of the imaging device is a CMOS (Complementary Metal Oxide Semiconductor) image sensor. An example of the CMOS image sensor includes a group of readout circuits for each column, and outputs digital signals analog-to-digital converted in units of rows. Patent document 1 describes an example of a CMOS image sensor.
Prior art documents
Patent document
Patent document 1: japanese patent laid-open publication No. 2011-082813
Disclosure of Invention
In an image pickup apparatus, there are a plurality of voltage lines to which voltages different from each other are applied. Since the signals of the pixels are given different noise components from these voltage lines, there is a possibility that the image quality is degraded. The present disclosure provides a technique that can contribute to noise reduction in the presence of a plurality of voltage lines to which mutually different voltages are applied.
Means for solving the problems
The present disclosure provides an imaging device including:
a plurality of pixels including a 1 st pixel and a 2 nd pixel;
a 1 st circuit including a 1 st wiring part and a 2 nd wiring part, the 1 st wiring part including one or more 1 st voltage lines to which a 1 st voltage is applied, the 2 nd wiring part including one or more 2 nd voltage lines to which a 2 nd voltage different from the 1 st voltage is applied;
a 1 st signal path through which a signal of the 1 st pixel flows; and
a 2 nd signal path through which a signal of the 2 nd pixel flows,
in a plan view, when a region closer to each of the one or more 1 st voltage lines than any of the one or more 2 nd voltage lines is defined as a 1 st region, and a region closer to each of the one or more 2 nd voltage lines than any of the one or more 1 st voltage lines is defined as a 2 nd region,
the 1 st signal path includes a 1 st intersection intersecting the 2 nd signal path and a 1 st extension extending within the 2 nd region,
the 2 nd signal path includes a 2 nd intersection intersecting the 1 st signal path and a 2 nd extension extending in the 1 st region,
in the flow of the signal of the 1 st pixel, the 1 st intersection is located upstream of the 1 st extension,
in the flow of the signal of the 2 nd pixel, the 2 nd intersection is located upstream of the 2 nd extension.
Effects of the invention
The technique of the present disclosure can contribute to noise reduction in the presence of a plurality of voltage lines to which mutually different voltages are applied.
Drawings
Fig. 1 is a block diagram of an image pickup apparatus according to embodiment 1.
Fig. 2 is a diagram showing a specific example of the imaging apparatus according to embodiment 1.
Fig. 3 is a configuration diagram of a pixel array in embodiment 1.
Fig. 4 is a configuration diagram of the 2 nd circuit, the 1 st circuit, the analog-to-digital conversion circuit, and the control circuit in embodiment 1.
Fig. 5 is an explanatory diagram of a signal path in embodiment 1.
Fig. 6 is an explanatory diagram of a signal path in embodiment 1.
Fig. 7 is an explanatory diagram of a signal path in embodiment 1.
Fig. 8 is a sectional view of the image pickup apparatus in embodiment 1.
Fig. 9 is an explanatory diagram of a signal path in embodiment 1.
Fig. 10 is an explanatory diagram of a signal path in embodiment 1.
Fig. 11 is an explanatory diagram of a signal path in embodiment 1.
Fig. 12 is an explanatory diagram of a signal path in embodiment 1.
Fig. 13 is an explanatory diagram of a signal path in embodiment 2.
Fig. 14 is an explanatory diagram of a signal path in embodiment 2.
Fig. 15 is an explanatory diagram of a signal path in embodiment 2.
Fig. 16 is an explanatory diagram of a signal path in embodiment 2.
Fig. 17 is an explanatory diagram of a signal path in embodiment 2.
Fig. 18 is an explanatory diagram of a signal path in embodiment 2.
Fig. 19A is an explanatory diagram of a signal path in embodiment 2.
Fig. 19B is an explanatory diagram of a signal path in embodiment 2.
Fig. 20 is an explanatory diagram of a signal path in embodiment 3.
Fig. 21A is an explanatory diagram of a signal path in embodiment 4.
Fig. 21B is an explanatory diagram of a signal path in embodiment 4.
Fig. 21C is an explanatory diagram of a signal path in embodiment 4.
Fig. 22A is an explanatory diagram of a signal path in embodiment 4.
Fig. 22B is an explanatory diagram of a signal path in embodiment 4.
Fig. 22C is an explanatory diagram of a signal path in embodiment 4.
Fig. 23 is an explanatory diagram of a signal path in embodiment 5.
Fig. 24 is an explanatory diagram of a signal path in embodiment 5.
Fig. 25 is an explanatory diagram of a signal path in embodiment 5.
Fig. 26 is an explanatory diagram of a signal path in embodiment 6.
Fig. 27 is an explanatory diagram of a signal path in embodiment 7.
Fig. 28 is a block diagram of a selector in embodiment 7.
Fig. 29 is a block diagram of an imaging system of a specific example.
Description of the reference numerals
1 pixel array
2. 23 1 st pixel
3. 24 nd pixel
41 st Signal Path
5 nd2 nd Signal Path
6 st circuit
7. 7B No. 1 voltage wire
8. 8B 2 nd voltage line
9. 21, 25 3 rd pixel
10. 22, 26 th pixel
11 3 rd signal path
12 th signal path
4C 5 th signal path
5C 6 th signal path
11C 7 th Signal Path
12C 8 th Signal Path
14 nd2 circuit
14P pitch region
15 No. 3 voltage wire
16 th voltage line
18 signal processing device
23C 5 th pixel
24C 6 th pixel
25C 7 th pixel
26C 8 th pixel
27 selector
28A, 28B, 28C, 28D switch
29A, 29B, 29C, 29D connection point
40 analog-to-digital conversion circuit
41-line scanning circuit
42 control circuit
43 signal processing circuit
44 output circuit
50 current source circuit
51 constant current source
52 to ground
53 preceding stage circuit
54 RAMP comparator
54a 1 st input unit
54b 2 nd input part
54c output unit
55 counting circuit
56 memory circuit
57D/A converter
61 region 1
62 area 2
65 1 st OB pixel
66 1 st OB Path
67 nd 2OB pixel
68 nd 2OB Path
71 first 1/2 area
72 second 1/2 area
81. 82, 83, 84 wiring layers
90 external pad
91 insulating layer
92 semiconductor substrate
94 other circuits
95. 96 voltage line
97. 98 signal path
100 image pickup device
110 lens
120 signal processing part
130 system controller
200 camera system.
Detailed Description
(outline of one embodiment of the present disclosure)
An imaging device according to claim 1 of the present disclosure includes:
a plurality of pixels including a 1 st pixel and a 2 nd pixel;
a 1 st circuit including a 1 st wiring part and a 2 nd wiring part, the 1 st wiring part including one or more 1 st voltage lines to which a 1 st voltage is applied, the 2 nd wiring part including one or more 2 nd voltage lines to which a 2 nd voltage different from the 1 st voltage is applied;
a 1 st signal path through which a signal of the 1 st pixel flows; and
a 2 nd signal path through which a signal of the 2 nd pixel flows,
in a plan view, when a region closer to each of the one or more 1 st voltage lines than any of the one or more 2 nd voltage lines is defined as a 1 st region, and a region closer to each of the one or more 2 nd voltage lines than any of the one or more 1 st voltage lines is defined as a 2 nd region,
the 1 st signal path includes a 1 st intersection intersecting the 2 nd signal path and a 1 st extension extending within the 2 nd region,
the 2 nd signal path includes a 2 nd intersection intersecting the 1 st signal path and a 2 nd extension extending in the 1 st region,
in the flow of the signal of the 1 st pixel, the 1 st intersection is located upstream of the 1 st extension,
in the flow of the signal of the 2 nd pixel, the 2 nd intersection is located upstream of the 2 nd extension.
The technique of claim 1 can contribute to noise reduction when a plurality of voltage lines to which voltages different from each other are applied are present. In addition, in the present disclosure, a "signal path" includes, for example, one or more signal lines through which signals flow. A part of the "signal path" may be a signal line included in the 1 st circuit and/or the 2 nd circuit described later.
In the 2 nd aspect of the present disclosure, for example, in the imaging apparatus of the 1 st aspect,
the 1 st voltage may also be a supply voltage,
the 2 nd voltage may be a ground voltage.
The technique of claim 2 can contribute to noise reduction when a voltage line to which a power supply voltage is applied and a voltage line to which a ground voltage is applied are present.
In the 3 rd aspect of the present disclosure, for example, in the imaging device of the 1 st or 2 nd aspect,
the plurality of pixels may also form a pixel array having at least one row and a plurality of columns,
the column to which the 1 st pixel in the pixel array belongs and the column to which the 2 nd pixel in the pixel array belongs may also be adjacent to each other.
The layout of the 3 rd embodiment is a specific example of the layout of the imaging device.
In the 4 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 1 st to 3 rd aspects,
the one or more 1 st voltage lines, the one or more 2 nd voltage lines, the 1 st extension portion, and the 2 nd extension portion may also extend parallel to each other in the planar view.
The parallel layout of the 4 th mode is advantageous from the viewpoint of miniaturization. On the other hand, the parallel layout is not necessarily advantageous for reducing noise. Therefore, in this parallel layout, the above-described noise reduction can easily exhibit its effect.
In the 5 th aspect of the present disclosure, for example, any of the imaging devices of the 1 st to 4 th aspects may include a plurality of wiring layers including a 1 st wiring layer and a 2 nd wiring layer different from the 1 st wiring layer,
the 1 st wiring layer may include the 1 st intersection,
the 2 nd wiring layer may include the 2 nd intersection.
According to the 5 th aspect, the 1 st signal path and the 2 nd signal path intersect in a planar view.
In the 6 th aspect of the present disclosure, for example, in any one of the 1 st to 5 th aspects of the image pickup apparatus,
under the plane view, the liquid crystal display device is provided with a liquid crystal display panel,
the 1 st signal path may further comprise a 1 st connection point and a 2 nd connection point,
the 2 nd signal path may also contain a 3 rd connection point and a 4 th connection point,
in the flow of the signal of the 1 st pixel, the 1 st connection point may be located upstream of the 1 st intersection, the 2 nd connection point may be located between the 1 st intersection and the 1 st extension,
in the flow of the signal of the 2 nd pixel, the 3 rd connection point may be located upstream of the 2 nd intersection, the 4 th connection point may be located between the 2 nd intersection and the 2 nd extension,
the camera device may also be provided with a selector,
the selector may also include:
a 1 st switch connected between the 1 st connection point and the 4 th connection point;
a 2 nd switch connected between the 1 st connection point and the 2 nd connection point;
a 3 rd switch connected between the 3 rd connection point and the 4 th connection point; and
a 4 th switch connected between the 3 rd connection point and the 2 nd connection point.
According to the 6 th aspect, the path of the signal of the pixel can be switched.
In the 7 th aspect of the present disclosure, for example, any of the image pickup apparatuses of the 1 st to 6 th aspects may further include a 2 nd circuit including a 3 rd wiring portion and a 4 th wiring portion, the 3 rd wiring portion including one or more voltage lines, the 4 th wiring portion including a plurality of voltage lines,
the one or more voltage lines of the 3 rd wiring part may also include a 3 rd voltage line,
the plurality of voltage lines of the 4 th wiring part may also include a 4 th voltage line and a 5 th voltage line adjacent to the 3 rd voltage line,
the 3 rd voltage line may also be between the 4 th voltage line and the 5 th voltage line,
under the plane view, the liquid crystal display device is provided with a liquid crystal display panel,
the pitches of the 4 th voltage line, the 3 rd voltage line and the 5 th voltage line may be different from the pitches of the one or more 1 st voltage lines and the one or more 2 nd voltage lines,
when a region between the 3 rd voltage line and the 4 th voltage line is defined as a 1 st pitch region, and a region between the 3 rd voltage line and the 5 th voltage line is defined as a 2 nd pitch region,
the 1 st signal path may further include: a 1 st pitch portion extending within the 1 st pitch region,
the 2 nd signal path may further include: a 2 nd pitch portion extending within the 2 nd pitch region,
in the flow of the signal of the 1 st pixel, the 1 st pitch part may be located upstream of the 1 st intersection,
in the flow of the signal of the 2 nd pixel, the 2 nd pitch part may be located upstream of the 2 nd intersection.
The case where the pitch is different in the 7 th aspect is an example of a case where the layout with the intersection can contribute to noise reduction.
In the 8 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 1 st to 7 th aspects,
the 1 st circuit may further include a 1 st transistor of a 1 st conductivity type and a 2 nd transistor of a 2 nd conductivity type different from the 1 st conductivity type,
the 1 st transistor may also be connected to any of the one or more 1 st voltage lines,
the 2 nd transistor may also be connected to any of the one or more 2 nd voltage lines.
According to the 8 th aspect, the 1 st transistor can be operated by the 1 st voltage on the 1 st voltage line. The 2 nd transistor can be operated by the 2 nd voltage on the 2 nd voltage line.
In the 9 th aspect of the present disclosure, for example, any one of the imaging devices of the 1 st to 6 th aspects may further include a 2 nd circuit,
the 1 st circuit may further include a 1 st transistor of a 1 st conductivity type and a 2 nd transistor of a 2 nd conductivity type different from the 1 st conductivity type,
the 2 nd circuit may include a 3 rd transistor of the 1 st conductivity type and a 4 th transistor of the 2 nd conductivity type,
when the center of gravity of the gate of the 1 st transistor and the gate of the 2 nd transistor is defined as a 1 st center of gravity and the center of gravity of the gate of the 3 rd transistor and the gate of the 4 th transistor is defined as a 2 nd center of gravity, in the plan view,
the arrangement direction of the 1 st transistor and the 2 nd transistor may be different from the arrangement direction of the 3 rd transistor and the 4 th transistor,
the 1 st signal path may include a portion closest to the 2 nd centroid and a portion closest to the 1 st centroid,
the 2 nd signal path may also include a portion closest to the 2 nd center of gravity and a portion closest to the 1 st center of gravity,
in the flow of the signal of the 1 st pixel, the portion closest to the 2 nd barycenter may be located upstream of the portion closest to the 1 st barycenter,
in the flow of the signal of the 2 nd pixel, the portion closest to the 2 nd centroid may be located upstream of the portion closest to the 1 st centroid.
The case of the 9 th aspect in which the arrangement directions of the transistors are different is an example of a case in which the layout with the intersection described above can contribute to noise reduction.
In the 10 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 1 st to 9 th aspects,
the plurality of pixels may also include a 1 st OB pixel that is an optical black pixel,
the image pickup apparatus may further include a signal processing circuit and a 1OB path through which a signal of the 1OB pixel flows,
in the plan view, the 1 st OB path may include: a 1 st OB extension extending within the 2 nd region,
the signal processing circuit may also perform optical black correction using the signal of the 1 st pixel via the 1 st OB extension with respect to the signal of the 1 st pixel via the 1 st extension.
The 10 th mode is suitable for reducing a noise component superimposed on the signal of the 1 st pixel in the 2 nd region. In addition, in the present disclosure, the "OB path" includes, for example, one or more signal lines through which signals flow. A part of the "OB path" may be a signal line included in the 1 st circuit and/or the 2 nd circuit described later.
In the 11 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 1 st to 9 th aspects,
the plurality of pixels may also include a 3 rd pixel,
the image pickup device may further include a 3 rd signal path through which a signal of the 3 rd pixel flows,
in the plan view, the 3 rd signal path may also include: a 3 rd extension extending within the 2 nd region.
The 11 th aspect facilitates correction for reducing noise in the 1 st pixel signal and the 3 rd pixel signal.
In the 12 th aspect of the present disclosure, for example, in the imaging apparatus of the 11 th aspect,
the plurality of pixels may also include a 4 th pixel,
the image pickup device may further include a 4 th signal path through which a signal of the 4 th pixel flows,
in the plan view, the 4 th signal path may also include: a 4 th extension extending within the 1 st region.
The 12 th aspect facilitates correction for reducing noise in the signal of the 2 nd pixel and the signal of the 4 th pixel.
In the 13 th aspect of the present disclosure, for example, in the imaging apparatus of the 12 th aspect,
under the plane view, the liquid crystal display device is provided with a liquid crystal display panel,
the 3 rd signal path may also include a portion extending from the 3 rd pixel to the 2 nd region,
the 4 th signal path may also include a portion extending from the 4 th pixel to the 1 st region,
the portion extending from the 3 rd pixel to the 2 nd region may not intersect the portion extending from the 4 th pixel to the 1 st region.
The layout of the 13 th aspect is an example of the layout of the imaging apparatus.
In the 14 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 11 th to 13 th aspects,
the 1 st pixel may also include a 1 st color filter,
the 2 nd pixel may also include a 2 nd color filter,
the 3 rd pixel may also include a 3 rd color filter,
the 1 st color filter and the 3 rd color filter may be color filters of 1 st color,
the 2 nd color filter may be a 2 nd color filter different from the 1 st color.
The 14 th mode is suitable for reducing noise of signals of the 1 st pixel and the 3 rd pixel, which are pixels including the color filter of the 1 st color, under the same correction condition.
In the 15 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 11 th to 13 th aspects,
the 1 st pixel and the 3 rd pixel may be 1 st type pixels selected from 4 types of R pixels, B pixels, Gr pixels, and Gb pixels,
the 2 nd pixel may be a 2 nd pixel selected from 4 of an R pixel, a B pixel, a Gr pixel, and a Gb pixel,
the 1 st pixel and the 2 nd pixel may be different from each other.
The 15 th mode is suitable for reducing noise of signals of the 1 st pixel and the 3 rd pixel which are the 1 st type pixels under the same correction condition.
In the 16 th aspect of the present disclosure, for example, any one of the imaging devices according to the 11 th to 15 th aspects may further include a signal processing circuit,
the signal processing circuit may perform correction to reduce a noise component superimposed in the 2 nd region for both the signal of the 1 st pixel via the 1 st extension portion and the signal of the 3 rd pixel via the 3 rd extension portion.
According to the 16 th aspect, the same correction conditions can be easily applied to the correction of the signal of the 1 st pixel and the correction of the signal of the 3 rd pixel.
In the 17 th aspect of the present disclosure, for example, in any one of the imaging apparatuses of the 11 th to 15 th aspects,
the plurality of pixels may also include a 1 st OB pixel that is an optical black pixel,
the image pickup apparatus may further include a signal processing circuit and a 1OB path through which a signal of the 1OB pixel flows,
in the plan view, the 1 st OB path may include: a 1 st OB extension extending within the 2 nd region,
the signal processing circuit may also perform optical black correction using the signal of the 1 st pixel via the 1 st OB extension with respect to the signal of the 1 st pixel via the 1 st extension.
The 17 th mode is suitable for reducing a noise component superimposed on the signal of the 1 st pixel in the 2 nd region.
An imaging system according to claim 18 of the present disclosure includes:
any one of the imaging devices according to the 1 st to 9 th aspects and the 11 th to 15 th aspects; and
a signal processing device disposed outside the image pickup device,
the plurality of pixels includes a 1 st OB pixel which is an optical black pixel,
the image pickup apparatus further includes a 1OB path through which a signal of the 1OB pixel flows,
in the plan view, the 1 st OB path includes: a 1 st OB extension extending within the 2 nd region,
the signal processing device performs optical black correction on the signal of the 1 st pixel via the 1 st extension portion using the signal of the 1 st pixel via the 1 st extension portion.
The 18 nd mode is suitable for reducing a noise component superimposed on the signal of the 1 st pixel in the 2 nd region.
An imaging system according to claim 19 of the present disclosure includes:
any one of the imaging devices according to the 11 th to 15 th aspects; and
a signal processing device disposed outside the image pickup device,
the signal processing device performs correction to reduce a noise component superimposed in the 2 nd region for both the signal of the 1 st pixel via the 1 st extension portion and the signal of the 3 rd pixel via the 3 rd extension portion.
According to the 19 th aspect, the same correction conditions can be easily applied to the correction of the signal of the 1 st pixel and the correction of the signal of the 3 rd pixel.
An imaging device according to a 20 th aspect of the present disclosure includes:
a plurality of pixels including a 1 st pixel, a 2 nd pixel, a 3 rd pixel, and a 4 th pixel;
a 1 st circuit including a 1 st wiring part and a 2 nd wiring part, the 1 st wiring part including one or more 1 st voltage lines to which a 1 st voltage is applied, the 2 nd wiring part including one or more 2 nd voltage lines to which a 2 nd voltage different from the 1 st voltage is applied;
a 1 st signal path through which a signal of the 1 st pixel flows;
a 2 nd signal path through which a signal of the 2 nd pixel flows;
a 3 rd signal path through which a signal of the 3 rd pixel flows; and
a 4 th signal path through which a signal of the 4 th pixel flows,
in a plan view, when a region closer to each of the one or more 1 st voltage lines than any of the one or more 2 nd voltage lines is defined as a 1 st region, and a region closer to each of the one or more 2 nd voltage lines than any of the one or more 1 st voltage lines is defined as a 2 nd region,
under the plane view, the liquid crystal display device is provided with a liquid crystal display panel,
the 1 st signal path includes: a 1 st extension extending within the 2 nd region,
the 2 nd signal path includes: a 2 nd extension extending within the 1 st region,
the 3 rd signal path includes: a 3 rd extension extending within said 2 nd region,
the 4 th signal path includes: a 4 th extension extending within the 1 st region.
In the 21 st aspect of the present disclosure, for example, in the imaging apparatus of the 20 th aspect,
the 1 st pixel may also include a 1 st color filter,
the 2 nd pixel may also include a 2 nd color filter,
the 3 rd pixel may also include a 3 rd color filter,
the 4 th pixel may also include a 4 th color filter,
the 1 st color filter and the 3 rd color filter may be color filters of 1 st color,
the 2 nd color filter and the 4 th color filter may be color filters of a 2 nd color different from the 1 st color.
In the 22 nd aspect of the present disclosure, for example, in the imaging apparatus of the 20 th aspect,
the 1 st pixel and the 3 rd pixel may be 1 st type pixels selected from 4 types of R pixels, B pixels, Gr pixels, and Gb pixels,
the 2 nd pixel and the 4 th pixel may be 2 nd pixels selected from 4 types of R pixels, B pixels, Gr pixels, and Gb pixels,
the 1 st pixel and the 2 nd pixel may be different from each other.
In the 23 rd aspect of the present disclosure, for example, any one of the imaging devices of the 20 th to 22 th aspects may further include a signal processing circuit,
the signal processing circuit may perform correction to reduce a noise component superimposed in the 2 nd region for both a signal of the 1 st pixel via the 1 st extension portion and a signal of the 3 rd pixel via the 3 rd extension portion,
the signal processing circuit may perform correction to reduce a noise component superimposed in the 1 st region for both the signal of the 2 nd pixel via the 2 nd extending portion and the signal of the 4 th pixel via the 4 th extending portion.
An imaging system according to a 24 th aspect of the present disclosure includes:
the imaging device according to any one of claims 20 to 23; and
a signal processing device disposed outside the image pickup device,
the signal processing device may perform correction to reduce a noise component superimposed in the 2 nd region for both the signal of the 1 st pixel via the 1 st extension portion and the signal of the 3 rd pixel via the 3 rd extension portion,
the signal processing device may perform correction to reduce a noise component superimposed in the 1 st region for both the signal of the 2 nd pixel via the 2 nd extending portion and the signal of the 4 th pixel via the 4 th extending portion.
In the 20 th to 24 th aspects, the techniques of the 1 st to 19 th aspects can be applied.
Hereinafter, an image pickup apparatus according to an embodiment will be described with reference to the drawings.
Detailed description beyond necessity is sometimes omitted. For example, detailed descriptions of well-known items and repetitive descriptions of substantially the same configurations may be omitted. This is to avoid unnecessarily lengthy descriptions that follow, which will be readily understood by those skilled in the art. In addition, the drawings and the following description are for those skilled in the art to fully understand the technology of the present disclosure, and are not intended to limit the subject matter described in the claims.
In the drawings, elements showing substantially the same configuration, operation, and effect are given the same reference numerals. Note that all the numerical values described below are examples for specifically describing the technique of the present disclosure, and the technique of the present disclosure is not limited to the exemplified numerical values. The connection relationship between the constituent elements is exemplified for specifically describing the technique of the present disclosure, and the connection relationship for realizing the function of the technique of the present disclosure is not limited to this.
In this specification, ordinal numbers of 1 st, 2 nd and 3 rd 3 … are sometimes used. When ordinal numbers are added to certain elements, the same kind of elements with lower numbers do not always exist. The ordinal number can be changed as necessary.
(embodiment 1)
Fig. 1 shows an image pickup apparatus 100 according to the present embodiment. The imaging device 100 is, for example, an image sensor chip shown in fig. 2.
The imaging apparatus 100 shown in fig. 1 includes a pixel array 1 and an electric circuit 47. The pixel array indicates that the number of columns may be one or more, and the number of rows may be one or more. In the example of fig. 1, the electrical circuit 47 is a peripheral circuit.
The pixel array 1 includes a plurality of pixels. Fig. 3 shows an example of the pixel array 1. In the example of fig. 3, the pixels in the pixel array 1 are arranged in a matrix on the semiconductor substrate. The region in which these pixels are provided functions as an imaging region. Each pixel generates charge by photoelectrically converting incident light, and outputs a pixel signal obtained thereby (an example of a signal of the 1 st to 4 th pixels of the present disclosure). The pixel signal is an electric signal corresponding to the electric charge.
In fig. 3, "Row" means a Row of the pixel array 1. "Col" means a column of the pixel array 1. In FIG. 3, line 0, line 1, line 2, and line 3 are depicted. In fig. 3, "Col 0" indicates column 0, and "Col 1" indicates column 1.
In the example of fig. 3, a bayer array is employed in the pixel array 1. Specifically, for example, in even-numbered lines such as the 0 th line and the 2 nd line, the Gr pixels and the R pixels are alternately and repeatedly arranged. In odd-numbered lines such as the 1 st line and the 3 rd line, B pixels and Gb pixels are alternately and repeatedly arranged. In even columns such as the 0 th column, Gr pixels and B pixels are alternately and repeatedly arranged. In odd columns such as the 1 st column, R pixels and Gb pixels are alternately and repeatedly arranged.
The R pixel is a red pixel. The B pixel is a blue pixel. The Gr pixel and the Gb pixel are green pixels.
Specifically, for example, the R pixel includes an R color filter. The R filter is a red filter. The B pixel includes a B color filter. The B color filter is a blue color filter. The Gr pixel includes a Gr color filter. The Gb pixels include Gb color filters. The Gr color filter and the Gb color filter are green color filters.
In the example of fig. 3, the pixels are color pixels. Specifically, in the example of fig. 3, the pixels are primary color pixels. However, the pixels may be complementary color pixels. In the example of fig. 3, the pixel array is formed by pixels of different colors. Specifically, in the example of fig. 3, the plurality of colors is 3 colors. However, the plurality of colors may be 4 colors. The plurality of colors may also include white. Further, the pixels may be black and white pixels without a color filter. This point is also the same in the embodiment described later.
In the example of fig. 3, one pixel is connected to one signal line, and there are a plurality of groups of such combinations of pixels and signal lines. In fig. 3, each signal line extends vertically. In the example of fig. 3, the 0 th column is associated with a plurality of signal lines, and the 1 st column is associated with a plurality of signal lines. These signal lines constitute a part or all of signal paths through which signals of the pixels flow. In fig. 5 and the like described later, a part of these signal lines or signal paths may be omitted from illustration. In addition, a plurality of signal lines associated with one column may be collected in the middle to reduce the number of signal lines. The number of signal lines associated with one column may also be 1.
In the present embodiment, the center of each pixel is located at a lattice point of an imaginary square lattice. Of course, the centers of the pixels may be located at lattice points such as a virtual triangular lattice and a virtual hexagonal lattice. Further, the pixels may be arranged in 1-dimension. In this case, the image pickup apparatus 100 can be used as a line sensor.
In the example of fig. 1, the electric circuit 47 includes the 2 nd circuit 14, the 1 st circuit 6, the analog-to-digital conversion circuit 40, the signal processing circuit 43, the output circuit 44, the row scanning circuit 41, and the control circuit 42. The electric circuit 47 may be disposed on a semiconductor substrate on which the pixel array 1 is formed. A part of the electric circuit 47 may be disposed on another substrate.
The row scanning circuit 41 selects pixels of a part of rows among the plurality of pixels in the pixel array 1. Thereby, readout of the signal of the selected pixel is performed.
Fig. 4 schematically shows an example of the configuration of the 2 nd circuit 14, the 1 st circuit 6, the analog-to-digital conversion circuit 40, and the control circuit 42.
In the example of fig. 4, the 2 nd circuit 14 includes a current source circuit 50. The current source circuit 50 includes a constant current source 51. The constant current source 51 is connected to the ground 52.
The 1 st circuit 6 includes a preceding stage circuit 53 and a RAMP comparator 54. The front-stage circuit 53 includes a buffer circuit. The RAMP comparator 54 includes a 1 st input section 54a, a 2 nd input section 54b, and an output section 54 c.
The analog-to-digital conversion circuit 40 includes a counter circuit 55 and a storage circuit 56. The counter circuit 55 includes a clock for analog-to-digital conversion.
The control circuit 42 includes a digital-to-analog converter (DAC) 57. The control circuit 42 controls the 2 nd circuit 14, the 1 st circuit 6, and the analog-to-digital conversion circuit 40.
A signal of a certain column of pixels in the pixel array 1 is input to the current source circuit 50. The current source circuit 50 outputs a signal corresponding to the inputted pixel signal as an analog voltage signal by a constant current source 51. The signal of the pixel which becomes the voltage signal is input to the 1 st input portion 54a of the RAMP comparator 54 via the previous stage circuit 53.
The DAC57 outputs a reference signal RAMP. The reference signal RAMP is a voltage signal that changes with time. In one example, the reference signal RAMP is a voltage signal that increases with time. In another example, the reference signal RAMP is a voltage signal that decreases with time. The change in the voltage signal may be either monotonically increasing or monotonically decreasing. The change in the voltage signal may also be a linear change. The reference signal RAMP is input to the 2 nd input section 54b of the RAMP comparator 54.
The output unit 54c of the RAMP comparator 54 outputs a voltage as an output signal. In one example, the output unit 54c outputs a high-level voltage or a low-level voltage. The voltage level is inverted when the sign of the difference between the input voltage to the 1 st input unit 54a and the input voltage to the 2 nd input unit 54b is inverted.
The counter circuit 55 counts a period from the time when the change of the voltage signal of the RAMP comparator 54 starts to the time when the inversion is performed, by the analog-to-digital conversion clock. The longer the period obtained by counting, the larger the digital signal output from the counter circuit 55. In this way, the signal of the pixel is converted from an analog signal to a digital signal by the RAMP comparator 54 and the counter circuit 55.
The signal of the pixel after being converted into the digital signal is stored in the memory circuit 56. The signal of the pixel stored in the memory circuit 56 is subjected to signal processing by the signal processing circuit 43, and then is output from the output circuit 44 to the outside of the imaging apparatus 100.
The current source circuit 50, the RAMP comparator 54, and the analog-to-digital conversion circuit 40 are provided for each column. The current source circuit 50, the RAMP comparator 54, and the analog-to-digital conversion circuit 40 are controlled by the control circuit 42.
Hereinafter, a path along which a signal of a pixel in the pixel array 1 passes from the pixel will be described with reference to fig. 5. Hereinafter, one of the plurality of pixels may be referred to as a 1 st pixel 2. One of the plurality of pixels is sometimes referred to as a 2 nd pixel 3. The path through which the signal of the 1 st pixel 2 flows is sometimes referred to as the 1 st signal path 4. The path through which the signal of the 2 nd pixel 3 flows is sometimes referred to as a 2 nd signal path 5.
In example 1, the 1 st pixel 2 is a 1 st pixel selected from 4 types of R pixels, B pixels, Gr pixels, and Gb pixels. The 2 nd pixel 3 is a 2 nd pixel selected from 4 types of R pixel, B pixel, Gr pixel, and Gb pixel. The 1 st pixel and the 2 nd pixel are different from each other.
In example 2, the 1 st pixel 2 is a 1 st color pixel. The 2 nd pixel 3 is a 2 nd color pixel. The 1 st color and the 2 nd color are different from each other. Specifically, for example, the 1 st pixel 2 includes a color filter of the 1 st color. The 2 nd pixel 3 includes a 2 nd color filter. In example 1, the color of the 1 st pixel 2 may be different from the color of the 2 nd pixel 3.
In the example of fig. 5, the 1 st circuit 6 includes a 1 st voltage line 7 and a 2 nd voltage line 8. The 1 st voltage is applied to the 1 st voltage line 7. The 2 nd voltage line 8 is applied with the 2 nd voltage. The 1 st voltage and the 2 nd voltage are different from each other.
Hereinafter, the term "1 st wiring portion J1" may be used. The 1 st wiring portion J1 is a wiring portion to which the 1 st voltage is applied. The 1 st wiring portion J1 can correspond to one 1 st voltage line 7 or a plurality of 1 st voltage lines 7. In the example of fig. 6 described later, the 1 st wiring portion J1 corresponds to one 1 st voltage line 7.
Hereinafter, the term "2 nd wiring portion J2" may be used. The 2 nd wiring portion J2 is a wiring portion to which the 2 nd voltage is applied. The 2 nd wiring portion J2 can correspond to one 2 nd voltage line 8 or a plurality of 2 nd voltage lines 8. In the example of fig. 6 described later, the 2 nd wiring portion J2 corresponds to one 2 nd voltage line 8.
In the present embodiment, the 1 st voltage is a power supply voltage. The 2 nd voltage is the ground voltage. The 1 st voltage line 7 and the 2 nd voltage line 8 are used to operate elements in the 1 st circuit 6. In one example, the 1 st voltage line 7 and the 2 nd voltage line 8 function as a charge transfer path for operating elements in the 1 st circuit 6. For example, the voltage lines 7 and 8 are used in the buffer circuit of the previous stage circuit 53 in fig. 4. The 2 nd voltage may be a power supply voltage and the 1 st voltage may be a ground voltage.
Here, as shown in fig. 6, a region closer to the 1 st wiring portion J1 than the 2 nd wiring portion J2 is defined as the 1 st region 61 in a plan view. A region closer to the 2 nd wiring portion J2 than the 1 st wiring portion J1 is defined as the 2 nd region 62 in a plan view. At this time, in the 1 st signal path 4, the 1 st intersection 4X intersecting the 2 nd signal path 5 and the 1 st extension 4Z extending in the 2 nd region 62 are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view. That is, in the flow of the signal of the 1 st pixel 2, the 1 st intersection 4X is located upstream of the 1 st extension 4Z. In the 2 nd signal path 5, the 2 nd intersection portion 5X intersecting the 1 st signal path 4 and the 2 nd extension portion 5Z extending in the 1 st region 61 are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. That is, in the flow of the signal of the 2 nd pixel 3, the 2 nd intersection 5X is located upstream of the 2 nd extension 5Z. As described above, the 1 st wiring portion J1 is a wiring portion to which the 1 st voltage is applied. The 2 nd wiring portion J2 is a wiring portion to which the 2 nd voltage is applied. In the example of fig. 6, the 1 st wiring portion J1 corresponds to one 1 st voltage line 7. The 2 nd wiring portion J2 corresponds to one 2 nd voltage line 8. In this way, when the plurality of voltage lines 7 and 8 to which voltages different from each other are applied exist, noise can be reduced.
Specifically, for example, as shown in fig. 7, a region in which the ratio of the distance from the 1 st wiring portion J1 to the distance from the 2 nd wiring portion J2 is 1/2 or less in a plan view is defined as the first 1/2 region 71. A region in which the ratio of the distance from the 2 nd wiring portion J2 to the distance from the 1 st wiring portion J1 is 1/2 or less in plan view is defined as the second 1/2 region 72. The 1 st extension 4Z is a portion of the 1 st signal path 4 extending within the second 1/2 area 72 in plan view. The 2 nd extension 5Z is a portion of the 2 nd signal path 5 extending within the first 1/2 area 71 in plan view. In this specific example, "1/2" may be replaced with "1/3" or "1/4". This point is also the same as in the embodiment described later.
Typically, the pixel array 1 is disposed on a semiconductor substrate. The planar view means, for example, a view parallel to the thickness direction of the semiconductor substrate. In fig. 5 to 7, arrangement based on a planar view is shown.
Hereinafter, an example of the advantageous point of the above configuration in a plan view will be described.
For example, there is a limitation in the arrangement order of the 1 st voltage line 7 and the 2 nd voltage line 8 in a planar view. Such a restriction may be imposed when the 1 st voltage line 7 and the 2 nd voltage line 8 are shared by other circuits different from the 1 st circuit 6. The imaging device 100 is an image sensor chip as shown in fig. 2, and the chip has an external pad 90, and may supply the 1 st voltage to the 1 st voltage line 7 and the 2 nd voltage to the 2 nd voltage line 8 via the external pad 90. In this case, the above-described restriction may be imposed according to the arrangement order of the external pads 90.
The above-described limitations are assumed to exist. In the 2 nd circuit 14, it is necessary that the 1 st signal path 4 relatively extends to a position close to the 1 st voltage line 7 (a position on the left side in the example of fig. 5) and the 2 nd signal path 5 extends to a position close to the 2 nd voltage line 8 (a position on the right side in the example of fig. 5) in a plan view. The noise component generated on the 2 nd voltage line 8 is set to be smaller than the noise component generated on the 1 st voltage line 7. In this case, the above-described crossing effect allows the 1 st signal path 4 to be close to the 2 nd voltage line 8 and the 2 nd signal path 5 to be close to the 1 st voltage line 7 in a plan view. By the effect of the crossover, noise superimposed on the 1 st circuit 6 with respect to the signal flowing through the 1 st signal path 4 can be reduced as compared with noise superimposed on the 1 st circuit 6 with respect to the signal flowing through the 2 nd signal path 5.
The technique can be applied to various situations, in which the noise superimposed on the signal flowing through the 1 st signal path 4 in the 1 st circuit 6 can be reduced as compared with the noise superimposed on the signal flowing through the 2 nd signal path 5 in the 1 st circuit 6. For example, it can function when it is desired to reduce noise superimposed on the signal of the 1 st pixel 2 as compared with noise superimposed on the signal of the 2 nd pixel 3. The drive modes of the imaging apparatus 100 include a normal mode and a pixel addition mode. The control circuit 42 and the row scanning circuit 41 control the driving mode. Here, the normal mode is a mode in which the signal of the 1 st pixel 2 is caused to flow through the 1 st signal path 4 and the signal of the 2 nd pixel 3 is caused to flow through the 2 nd signal path 5. The pixel addition mode is a mode in which the signal of the 1 st pixel 2 is mixed with the signal of the 2 nd pixel 3 in the pixel array 1, and the resulting mixed signal is made to flow in the 1 st signal path 4. According to the above-described technique, noise superimposed on the mixed signal in the 1 st circuit 6 can be reduced in the pixel addition mode.
The illustrated pixel array 1 and the electric circuit 47 are just an example. The configurations of the pixel array 1 and the electric circuit 47 are not limited to this. It is not necessary that all of the 2 nd circuit 14, the 1 st circuit 6, the analog-to-digital conversion circuit 40, the signal processing circuit 43, the output circuit 44, the row scanning circuit 41, and the control circuit 42 exist. For example, the 2 nd circuit 14 can be omitted. These points are also the same in the embodiment described later.
The 1 st circuit 6 and/or the 2 nd circuit 14 may be an analog circuit such as a current source circuit. The 1 st circuit 6 and/or the 2 nd circuit 14 may be digital circuits operated by a clock or the like.
Fig. 8 is a sectional view of an example of the imaging apparatus 100 cut in the thickness direction. As shown in fig. 8, the image pickup apparatus 100 includes an insulating layer 91. In this example, the insulating layer 91 is provided on the semiconductor substrate 92. A plurality of wiring layers are provided at mutually different depth positions in the insulating layer 91. In the example of fig. 8, the plurality of wiring layers includes a 1 st wiring layer 81, a 2 nd wiring layer 82, a 3 rd wiring layer 83, and a 4 th wiring layer 84. One or all of the 1 st signal path 4, the 2 nd signal path 5, the 1 st voltage line 7, and the 2 nd voltage line 8 may be provided in the same wiring layer. One or all of these may be provided in different wiring layers.
In the present embodiment, the imaging device 100 includes 2 wiring layers which are mutually different layers among the multilayer wiring layers. One of the 2 wiring layers includes a 1 st intersection 4X. The other of the 2 wiring layers includes a 2 nd intersection 5X. In this way, the 1 st signal path 4 and the 2 nd signal path 5 intersect in a plan view easily. The above one of the 2 wiring layers may be any one of the wiring layers 81 to 84 of fig. 8. The above-mentioned other of the 2 wiring layers may be any one of the wiring layers 81 to 84 of fig. 8.
In the example of fig. 9, the plurality of pixels include the 1 st OB pixel 65 as an optical black pixel. The image pickup apparatus 100 includes a signal processing circuit 43 and a 1 st OB path 66 through which a signal of a 1 st OB pixel 65 flows. In the 1 st OB path 66, there is a 1 st OB extension 66Z extending within the 2 nd area 62 in plan view. The signal processing circuit 43 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st OB extension 66Z for the signal of the 1 st pixel 2 via the 1 st extension 4Z. In this way, it is suitable to reduce the noise component superimposed on the signal of the 1 st pixel 2 in the 2 nd region 62. Although not shown in fig. 9, the analog-to-digital conversion circuit 40 may be present between the signal processing circuit 43 and the 1 st circuit 6.
Specifically, for example, the 1 st OB extension 66Z is a portion extending within the second 1/2 area 72 in plan view in the 1 st OB path 66. The 1 st extension 4Z is a portion extending within the second 1/2 area 72 in plan view in the 1 st signal path 4.
In the example of fig. 10, the plurality of pixels includes the 2 nd OB pixel 67 as an optical black pixel. The image pickup apparatus 100 includes the signal processing circuit 43 and a 2OB path 68 through which a signal of the 2OB pixel 67 flows. In the 2OB path 68, there is a 2OB extension 68Z extending within the 1 st region 61 in plan view. The signal processing circuit 43 performs optical black correction using the signal of the 2 nd OB pixel 67 via the 2 nd OB extension 68Z for the signal of the 2 nd pixel 3 via the 2 nd extension 5Z. In this way, it is suitable to reduce the noise component superimposed on the signal of the 2 nd pixel 3 in the 1 st region 61.
Specifically, for example, the 2OB extension 68Z is a portion extending within the first 1/2 area 71 in a plan view in the 2OB path 68. The 2 nd extension 5Z is a portion extending within the first 1/2 area 71 in plan view in the 2 nd signal path 5.
In the present embodiment, the plurality of pixels constitute a pixel array 1 having at least one row and a plurality of columns. The column to which the 1 st pixel 2 in the pixel array 1 belongs and the column to which the 2 nd pixel 3 in the pixel array 1 belongs are adjacent to each other.
In the present embodiment, the 1 st wiring portion J1, the 2 nd wiring portion J2, the 1 st extending portion 4Z, and the 2 nd extending portion 5Z extend in parallel with each other in a plan view. Here, as described above, in the example of fig. 6, the 1 st wiring portion J1 corresponds to one 1 st voltage line 7. The 2 nd wiring portion J2 corresponds to one 2 nd voltage line 8. Such a parallel arrangement is advantageous from the viewpoint of miniaturization. On the other hand, the parallel layout is not necessarily advantageous for reducing noise. Therefore, in this parallel layout, the above-described noise reduction can easily exhibit its effect.
In the present embodiment, the 1 st wiring portion J1, the 2 nd wiring portion J2, the 1 st extending portion 4Z, and the 2 nd extending portion 5Z extend straight in a plan view.
The 1 st voltage on the 1 st voltage line 7 may be a fixed voltage or a voltage that changes with time. The same applies to the 2 nd voltage in the 2 nd voltage line 8. As the fixed voltage, a voltage of a mode signal and a voltage of a register signal are exemplified. As the voltages that change with time corresponding to the 1 st voltage and the 2 nd voltage, alternating voltages having different frequencies from each other are exemplified. As such an alternating voltage, a voltage of a clock signal is exemplified. One of the 1 st voltage and the 2 nd voltage may be a voltage of a clock signal, and the other may be a voltage of a data signal. The 1 st voltage and the 2 nd voltage may be voltages of pulse signals having mutually different timings and/or mutually different duty ratios.
In a plan view, the crossing may be performed in a region between the 1 st circuit 6 and the 2 nd circuit 14, in a region on the 1 st circuit 6, or in a region on the 2 nd circuit 14. Further, an element isolation region for electrically isolating the 1 st circuit 6 from the 2 nd circuit 14 may be provided between the 1 st circuit 6 and the 2 nd circuit 14. The crossing may be performed at a position overlapping with the element separating region in a plan view.
In the present embodiment, the 1 st intersection 4X is a portion through which the analog signal of the 1 st pixel 2 passes. The 2 nd intersection 5X is a portion through which the analog signal of the 2 nd pixel 3 passes. In the present embodiment, the 1 st extension portion 4Z is a portion through which the analog signal of the 1 st pixel 2 passes. The 2 nd extension 5Z is a portion through which the analog signal of the 2 nd pixel 3 passes. The same applies to the 1 st OB extension 66Z and the 2 nd OB extension 68Z, and corresponding analog signals pass therethrough. The 3 rd extending portion 11Z, the 3 rd extending portion 4BZ, the 4 th extending portion 5Z, and the 4 th extending portion 5BZ, which will be described later, are also the same, and are portions through which corresponding analog signals pass.
The above-described intersection in the intersection portions 4X and 5X may also be the only intersection of the 1 st signal path 4 and the 2 nd signal path 5 in a plan view. In addition to the portions 4X and 5X, the 1 st signal path 4 and the 2 nd signal path 5 may intersect again in a plan view. For example, the first circuit 6 may be further crossed downstream than the second circuit 1 in a plan view. The image pickup device 100 may be further arranged outside the downstream side of the output circuit 44 in a plan view so as to intersect with each other. Here, the downstream means downstream of the flow direction 2F of the signal of the pixel 2 and the flow direction 3F of the signal of the pixel 3.
The 2 nd circuit 14 may also include a plurality of voltage lines. Specifically, in the example of fig. 11, the plurality of voltage lines include one 3 rd voltage line 15 and 24 th voltage lines 16 (an example of the 4 th and 5 th voltage lines of the present disclosure) adjacent to the 3 rd voltage line 15. One 4 th voltage line 16, the 3 rd voltage line 15, and the other 4 th voltage line 16 are arranged in this order in a plan view. In this example, the pitch of the plurality of voltage lines 16, 15 in the 2 nd circuit 14 is different from the pitch of the voltage lines 7, 8 in the 1 st circuit 6 in a plan view. Here, the pitch of the voltage lines refers to a distance between a center line of the voltage lines extending in the longitudinal direction and a center line of the voltage lines adjacent to the voltage lines extending in the longitudinal direction.
In one specific example, the 3 rd voltage is applied to the 3 rd voltage line 15. The 4 th voltage line 16 is applied with the 4 th voltage. The 3 rd voltage and the 4 th voltage are different from each other.
The 3 rd voltage may be the same as one of the 1 st voltage and the 2 nd voltage. The 4 th voltage may be the same as the other of the 1 st voltage and the 2 nd voltage. The 3 rd voltage may be different from both the 1 st voltage and the 2 nd voltage. The 4 th voltage may be different from both the 1 st voltage and the 2 nd voltage.
In the present embodiment, the 3 rd voltage on the 3 rd voltage line 15 is a power supply voltage. The 4 th voltage of the 4 th voltage line 16 is a ground voltage. The 3 rd voltage line 15 and the 4 th voltage line 16 are used to operate elements in the 2 nd circuit 14. The voltage lines 15 and 16 are used in the current source circuit 50 of fig. 4, for example. The 4 th voltage may be a power supply voltage and the 3 rd voltage may be a ground voltage. The voltage line 15 and the voltage line 16 are connected to, for example, a transistor in the current source circuit 50, and supply a voltage to the transistor.
The 3 rd voltage may be a fixed voltage or a voltage that changes with time. The same applies to the 4 th voltage. As the fixed voltage, a voltage of a mode signal and a voltage of a register signal are exemplified. As the voltages that change with time corresponding to the 3 rd voltage and the 4 th voltage, alternating voltages having different frequencies from each other are exemplified. As such an alternating voltage, a voltage of a clock signal is exemplified. One of the 3 rd voltage and the 4 th voltage may be a voltage of a clock signal, and the other may be a voltage of a data signal. The 3 rd voltage and the 4 th voltage may be voltages of pulse signals having mutually different timings and/or mutually different duty ratios.
Hereinafter, the term "3 rd wiring portion J3" may be used. The 3 rd wiring portion J3 is a wiring portion to which the 3 rd voltage is applied. The 3 rd wiring portion J3 can correspond to one 3 rd voltage line 15 or a plurality of 3 rd voltage lines 15. In the example of fig. 11, the 3 rd wiring portion J3 corresponds to one 3 rd voltage line 15.
Hereinafter, the term "4 th wiring portion J4" may be used. The 4 th wiring portion J4 is a wiring portion to which the 4 th voltage is applied. The 4 th wiring portion J4 can correspond to one 4 th voltage line 16 or a plurality of 4 th voltage lines 16. In the example of fig. 11, the 4 th wiring portion J4 corresponds to the 24 th voltage lines 16.
In the example of fig. 11, the imaging apparatus 100 includes the 2 nd circuit 14 including the 3 rd wiring portion J3 and the 4 th wiring portion J4. In a plan view, the pitch of the 1 st wiring portion J1 and the 2 nd wiring portion J2 and the pitch of the 3 rd wiring portion J3 and the 4 th wiring portion J4 are different from each other. A region between the 3 rd wiring portion J3 and the 4 th wiring portion J4 in a plan view is defined as a pitch region 14P. At this time, in the 1 st signal path 4, the portion extending in the pitch region 14P, the 1 st intersection 4X, and the 1 st extension 4Z are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view. In the 2 nd signal path 5, the portion extending within the pitch region 14P, the 2 nd intersection 5X, and the 2 nd extension 5Z are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. In this example, the 1 st wiring portion J1 corresponds to one 1 st voltage line 7. The 2 nd wiring portion J2 corresponds to one 2 nd voltage line 8. The 3 rd wiring portion J3 corresponds to one 3 rd voltage line 15. The 4 th wiring portion J4 corresponds to the 24 th voltage lines 16. In the case where the pitches are different as described above, the layout with the intersections described above is an example of a case where noise can be reduced. Specifically, for example, when the pitch is different between the 1 st circuit 6 and the 2 nd circuit 14, if the signal paths 4 and 5 are extended straight in a plan view, the possibility that the signal paths cannot approach the desired voltage lines is higher than when the pitch is the same. However, with the above-described crossing, the desired voltage line is easily accessible.
In the example of fig. 11, specifically, the pitch between the 1 st wiring portion J1 and the 2 nd wiring portion J2 is the pitch between the 1 st voltage line 7 and the 2 nd voltage line 8. A distance between the 3 rd wiring portion J3 and the 4 th wiring portion J4 is a distance between the 3 rd voltage line 15 and the 4 th voltage line 16. The pitch region 14P is a region between the 3 rd voltage line 15 and the 4 th voltage line 16.
As described above, in the example of fig. 11, the pitches of the plurality of voltage lines 15 and 16 in the 2 nd circuit 14 and the pitches of the voltage lines 7 and 8 in the 1 st circuit 6 are different from each other in a plan view. Specifically, for example, the pitch of the plurality of voltage lines 15 and 16 in the 2 nd circuit 14 is the same as the pitch of the columns of the pixels (hereinafter, may be referred to as 1 column pitch). The pitch of the voltage lines 7, 8 in the 1 st circuit 6 is different from the 1 column pitch. The voltage lines 7 and 8 have a pitch 2 times the pitch of the columns of the pixels (hereinafter, may be referred to as a 2-column pitch).
As shown in fig. 12, the pitch of the plurality of voltage lines 15 and 16 in the 2 nd circuit 14 may be the same as the pitch of the voltage lines 7 and 8 in the 1 st circuit 6 in a plan view.
The signals of the pixels may also be input to the 1 st circuit 6 via signal paths. The signal of the pixel may not be input to the 1 st circuit 6.
Signals for the pixels may also be input to the 2 nd circuit 14 via signal paths. The signal of the pixel may not be input to the 2 nd circuit 14.
(embodiment 2)
Hereinafter, embodiment 2 will be described. In embodiment 2, the same contents as those in embodiment 1 are denoted by the same reference numerals and description thereof may be omitted.
Fig. 13 shows the pixel array 1, the 2 nd circuit 14, and the 1 st circuit 6 in embodiment 2.
In the example of fig. 13, the pixel array 1 includes a plurality of pixels. One of the plurality of pixels is sometimes referred to as a 3 rd pixel 9. One of the plurality of pixels is sometimes referred to as a 4 th pixel 10. The path through which the signal of the 3 rd pixel 9 flows is sometimes referred to as a 3 rd signal path 11. The path through which the signal of the 4 th pixel 10 flows is sometimes referred to as a 4 th signal path 12.
In the example of fig. 13, the 1 st circuit 6 includes a plurality of 1 st voltage lines 7 and a plurality of 2 nd voltage lines 8. The 1 st voltage line 7 and the 2 nd voltage line 8 are alternately and repeatedly arranged in a planar view.
In the example of fig. 13, the number of the 1 st voltage lines 7 is plural, and the number of the 2 nd voltage lines 8 is plural. Fig. 14 shows the 1 st region 61 and the 2 nd region 62 in this case. In the 1 st signal path 4, the 1 st intersection 4X intersecting the 2 nd signal path 5 and the 1 st extension 4Z extending in the 2 nd region 62 are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view. In the 2 nd signal path 5, the 2 nd intersection 5X intersecting the 1 st signal path 4 and the 2 nd extending portion extending in the 1 st region 61 are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. Here, the 1 st wiring portion J1 is a wiring portion to which the 1 st voltage is applied. The 2 nd wiring portion J2 is a wiring portion to which the 2 nd voltage is applied. In the example of fig. 13, the 1 st wiring portion J1 corresponds to the plurality of 1 st voltage lines 7. The 2 nd wiring portion J2 corresponds to the plurality of 2 nd voltage lines 8.
Specifically, for example, as shown in fig. 15, the 1 st extension portion 4Z is a portion of the 1 st signal path 4 extending within the second 1/2 area 72 in plan view. The 2 nd extension 5Z is a portion of the 2 nd signal path 5 extending within the first 1/2 area 71 in plan view.
In the example of fig. 13, the plurality of voltage lines in the 2 nd circuit 14 includes a plurality of 3 rd voltage lines 15 and a plurality of 4 th voltage lines 16. The 3 rd voltage line 15 and the 4 th voltage line 16 are alternately and repeatedly arranged in a planar view. In this example, the pitch of the plurality of voltage lines 15 and 16 in the 2 nd circuit 14 is different from the pitch of the voltage lines 7 and 8 in the 1 st circuit 6 in a plan view.
In the example of fig. 13, the plurality of voltage lines 15, 16 in the 2 nd circuit 14 have a 1 column pitch. The voltage lines 7, 8 in the 1 st circuit 6 have a pitch different from the 1 column pitch. Specifically, for example, the voltage lines 7, 8 have a 2-column pitch.
In the example of fig. 13, the imaging apparatus 100 includes the 2 nd circuit 14 including the 3 rd wiring portion J3 and the 4 th wiring portion J4. In a plan view, the pitch of the 1 st wiring portion J1 and the 2 nd wiring portion J2 and the pitch of the 3 rd wiring portion J3 and the 4 th wiring portion J4 are different from each other. A region between the 3 rd wiring portion J3 and the 4 th wiring portion J4 in a plan view is defined as a pitch region 14P. At this time, in the 1 st signal path 4, a portion extending in the pitch region 14P (an example of the 1 st pitch portion of the present disclosure), the 1 st intersection 4X, and the 1 st extension 4Z are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view. In the 2 nd signal path 5, a portion extending in the pitch region 14P (an example of the 2 nd pitch portion of the present disclosure), the 2 nd intersection portion 5X, and the 2 nd extension portion 5Z are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in a plan view. In the example of fig. 13, the 1 st wiring portion J1 corresponds to the plurality of 1 st voltage lines 7. The 2 nd wiring portion J2 corresponds to the plurality of 2 nd voltage lines 8. The 3 rd wiring portion J3 corresponds to the plurality of 3 rd voltage lines 15. The 4 th wiring portion J4 corresponds to the plurality of 4 th voltage lines 16.
In the example of fig. 13, specifically, the pitch between the 1 st wiring portion J1 and the 2 nd wiring portion J2 is the pitch between the 1 st voltage line 7 and the 2 nd voltage line 8. A distance between the 3 rd wiring portion J3 and the 4 th wiring portion J4 is a distance between the 3 rd voltage line 15 and the 4 th voltage line 16. The pitch region 14P is a region between the 3 rd voltage line 15 and the 4 th voltage line 16.
Fig. 16 shows a detailed example of the 2 nd circuit 14 and the 1 st circuit 6. Specifically, fig. 16 shows the 2 nd circuit 14 and the 1 st circuit 6 in a plan view. In fig. 16, a part of the signal path is omitted. The same applies to fig. 19A and 19B described later.
In addition, unlike fig. 13, in fig. 16, the 1 st signal path 4 and the 2 nd signal path 5 intersect in the region on the 1 st circuit 6 in a plan view. As described above, the intersection may be performed in the area between the 1 st circuit 6 and the 2 nd circuit 14, in the area on the 1 st circuit 6, or in the area on the 2 nd circuit 14 in a plan view. The intersection may be performed at a position overlapping the element isolation region in a plan view.
In a plan view, a pitch direction in which the voltage lines 7 and 8 in the 1 st circuit 6 are arranged is defined as a 1 st horizontal direction HD1, and a direction orthogonal to the 1 st horizontal direction HD1 is defined as a 1 st vertical direction VD 1. In the 1 st circuit 6, the 1 st transistor TG1 and the 2 nd transistor TG2 are arranged in the 1 st horizontal direction HD1 between the adjacent voltage lines 7, 8 in plan view.
In the example of fig. 16, the 1 st transistor TG1 is a transistor of the 1 st conductivity type. The 2 nd transistor TG2 is a transistor of the 2 nd conductivity type. The 1 st conductivity type and the 2 nd conductivity type are different from each other. In the example of fig. 16, specifically, the 1 st conductivity type is P type. The 2 nd conductivity type is N type. More specifically, for example, the 1 st transistor TG1 is a P-channel FET, and the 2 nd transistor TG2 is an N-channel FET. Alternatively, the 1 st transistor TG1 may be an N-channel FET, and the 2 nd transistor TG2 may be a P-channel FET. In this case, the arrangement of the voltage lines 7 and 8 is reversed from the example of fig. 16.
The 1 st transistor TG1 is connected to a 1 st voltage line 7. The 2 nd transistor TG2 is connected to the 2 nd voltage line 8.
In a plan view, a pitch direction in which the voltage lines 15, 16 in the 2 nd circuit 14 are arranged is defined as a 2 nd lateral direction HD2, and a direction orthogonal to the 2 nd lateral direction HD2 is defined as a 2 nd longitudinal direction VD 2. In the 2 nd circuit 14, between the adjacent voltage lines 15, 16, the 3 rd transistor TG3 and the 4 th transistor TG4 are arranged in the 2 nd vertical direction VD2 in plan view.
In the example of fig. 16, the 3 rd transistor TG3 is a transistor of the 1 st conductivity type. The 4 th transistor TG4 is a transistor of the 2 nd conductivity type. Specifically, for example, the 3 rd transistor TG3 is a P-channel FET, and the 4 th transistor TG4 is an N-channel FET. Alternatively, the 3 rd transistor TG3 may be an N-channel FET, and the 4 th transistor TG4 may be a P-channel FET.
The 3 rd transistor TG3 is connected to a 3 rd voltage line 15. The 4 th transistor TG4 is connected to the 4 th voltage line 16.
In the example of fig. 16, signals of pixels are output from the 2 nd circuit 14 at each column pitch in a plan view.
Thus, in the example of fig. 16, the imaging device includes the 2 nd circuit 14. The 1 st circuit 6 includes a 1 st transistor TG1 of a 1 st conductivity type and a 2 nd transistor TG2 of a 2 nd conductivity type different from the 1 st conductivity type. The 2 nd circuit 14 includes a 3 rd transistor TG3 of the 1 st conductivity type and a 4 th transistor TG4 of the 2 nd conductivity type. The center of gravity of the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG2 is defined as the 1 st center of gravity. The center of gravity of the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG4 is defined as the 2 nd center of gravity. In a plan view, the arrangement direction HD1 of the 1 st transistor TG1 and the 2 nd transistor TG2 is different from the arrangement direction VD2 of the 3 rd transistor TG3 and the 4 th transistor TG 4. At this time, in the 1 st signal path 4, the portion closest to the 2 nd barycenter and the portion closest to the 1 st barycenter are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view. Here, in the 1 st signal path 4, a portion closest to the 2 nd center of gravity may be included in a portion extending in the pitch region 14P, and a portion closest to the 1 st center of gravity may be included in the 1 st extending portion 4Z. In the 2 nd signal path 5, a portion closest to the 2 nd center of gravity may be included in a portion extending in the pitch region 14P, and a portion closest to the 1 st center of gravity may be included in the 2 nd extending portion 5Z.
In the 2 nd signal path 5, the portion closest to the 2 nd center of gravity and the portion closest to the 1 st center of gravity are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. In this way, the 1 st circuit 6 can be easily reduced in the arrangement direction VD1 in plan view. The 2 nd circuit 14 can be easily reduced in the arrangement direction HD2 in plan view. Therefore, by providing such a difference in arrangement of transistors, the shape in plan view can be easily changed in both circuits 6 and 14. Which can be an effective countermeasure against space restrictions of the circuit arrangement. However, the difference in arrangement of the transistors may cause a limitation in the layout of the 1 st signal path 4 and the 2 nd signal path 5 in the 1 st circuit 6 and the 2 nd circuit 14. For example, when the arrangement of the transistors is different, the above-described difference in the pitch of the voltage lines between the two circuits 6 and 14 is likely to occur in order to apply a voltage from the voltage lines to the transistors. Therefore, in the example of fig. 16, the layout with the intersection described above can contribute to noise reduction.
In one example, the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG2 are a common electrode. In this case, "the center of gravity of the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG 2" is the center of gravity of the common electrode. In other examples, the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG2 are independent electrodes. In this case, "the center of gravity of the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG 2" is the center of gravity of these 2 electrodes.
In one example, the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG4 are a common electrode. In this case, "the center of gravity of the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG 4" is the center of gravity of the common electrode. In other examples, the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG4 are independent electrodes. In this case, "the center of gravity of the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG 4" is the center of gravity of these 2 electrodes.
As is known, the center of gravity refers to the point of action of the resultant of the gravitational forces experienced by various parts of an object. The region in which at least one of the electrodes constituting the gate of the 1 st transistor TG1 and the gate of the 2 nd transistor TG2 is extended is measured by a measuring instrument such as a SEM (scanning electron Microscope), and the 1 st barycenter can be specified from the measured region. Similarly, by measuring a region in which at least one of the electrodes constituting the gate of the 3 rd transistor TG3 and the gate of the 4 th transistor TG4 is extended with a measuring instrument such as an SEM, the 2 nd gravity center can be specified from the measured region.
In the example of fig. 16, the 1 st circuit 6 includes a 1 st transistor TG1 of the 1 st conductivity type and a 2 nd transistor TG2 of the 2 nd conductivity type different from the 1 st conductivity type. The 1 st voltage line 7 of the 1 st wiring portion J1 is connected to the 1 st transistor TG 1. The 2 nd voltage line 8 of the 2 nd wiring portion J2 is connected to the 2 nd transistor TG 2. In this way, the 1 st transistor TG1 can be operated by the 1 st voltage of the 1 st wiring portion J1. The 2 nd transistor TG2 can be operated by the 2 nd voltage of the 2 nd wiring portion J2.
The technique related to the transistor described above can be applied to other embodiments such as embodiment 1.
In the example of fig. 13, the plurality of pixels includes the 3 rd pixel 9. The imaging device 100 includes a 3 rd signal path 11 through which a signal of the 3 rd pixel 9 flows. As shown in fig. 14, in the 3 rd signal path 11, there is a 3 rd extending portion 11Z extending within the 2 nd area 62 in a plan view. Such a layout facilitates correction for reducing noise of the 1 st pixel 2 signal and the 3 rd pixel 9 signal. Specifically, for example, according to such a layout, it is less likely that a difference in noise components superimposed on the signal of the 1 st pixel 2 and the signal of the 3 rd pixel 9 in the 1 st circuit 6 occurs, as compared with a case where one of the 1 st signal path 4 and the 3 rd signal path 11 extends in the 2 nd region 62 and the other extends in the 1 st region 61. Therefore, such an arrangement is suitable for reducing the noise of these signals by correction of the same correction conditions.
Specifically, for example, as shown in fig. 15, the 3 rd extending portion 11Z is a portion extending in the second 1/2 area 72 in plan view.
In the example of fig. 13, the plurality of pixels includes the 4 th pixel 10. The image pickup device 100 includes a 4 th signal path 12 through which a signal of the 4 th pixel 10 flows. As shown in fig. 14, in the 4 th signal path 12, there is a 4 th extension 12Z extending within the 1 st region 61 in plan view. Such a layout facilitates correction for reducing noise of the signal of the 2 nd pixel 3 and the signal of the 4 th pixel 10. Specifically, according to such a layout, it is less likely that a difference in noise components superimposed on the signals of the 2 nd pixel 3 and the 4 th pixel 10 in the 1 st circuit 6 occurs, as compared with a case where one of the 2 nd signal path 5 and the 4 th signal path 12 extends in the 1 st region 61 and the other extends in the 2 nd region 62. Therefore, such an arrangement is suitable for reducing the noise of these signals by correction of the same correction conditions.
Specifically, for example, as shown in fig. 15, the 4 th extension 12Z is a portion extending in the first 1/2 area 71 in plan view.
An example of a correction method for reducing noise is described below.
In the example of fig. 17, the imaging apparatus 100 includes a signal processing circuit 43. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the 2 nd area 62 for both the signal of the 1 st pixel 2 via the 1 st extension 4Z and the signal of the 3 rd pixel 9 via the 3 rd extension 11Z. According to this example, the same correction conditions can be easily applied to the correction of the signal of the 1 st pixel 2 and the correction of the signal of the 3 rd pixel 9.
Specifically, for example, the 1 st extension 4Z is a portion extending within the second 1/2 area 72 in plan view in the 1 st signal path 4. The 3 rd extension 11Z is a portion extending within the second 1/2 area 72 in plan view in the 3 rd signal path 11. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the second 1/2 region 72 for both the signal of the 1 st pixel 2 via the 1 st extension 4Z and the signal of the 3 rd pixel 9 via the 3 rd extension 11Z.
In one embodiment, the correction is an optical black correction. In this specific example, the 1 st OB pixel 65 and the 1 st OB path 66 described above are used. The signal processing circuit 43 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st OB extension portion 66Z for both the signal of the 1 st pixel 2 via the 1 st extension portion 4Z and the signal of the 3 rd pixel 9 via the 3 rd extension portion 11Z.
In the example of fig. 18, the imaging device 100 includes a signal processing circuit 43. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the 1 st region 61 for both the signal of the 2 nd pixel 3 via the 2 nd extending portion 5Z and the signal of the 4 th pixel 10 via the 4 th extending portion 12Z. According to this example, the same correction conditions can be easily applied to the correction of the signal of the 2 nd pixel 3 and the correction of the signal of the 4 th pixel 10.
Specifically, for example, the 2 nd extension portion 5Z is a portion extending within the first 1/2 area 71 in a plan view in the 2 nd signal path 5. The 4 th extension 12Z is a portion extending within the first 1/2 area 71 in plan view in the 4 th signal path 12. The imaging apparatus 100 performs correction to reduce the noise component superimposed in the first 1/2 region 71 for both the signal of the 2 nd pixel 3 via the 2 nd extending part 5Z and the signal of the 4 th pixel 10 via the 4 th extending part 12Z.
In one embodiment, the correction is an optical black correction. In this specific example, the 2 nd OB pixel 67 and the 2 nd OB path 68 described above are used. The signal processing circuit 43 performs optical black correction using the signal of the 2 nd OB pixel 67 via the 2 nd OB extension portion 68Z for both the signal of the 2 nd pixel 3 via the 2 nd extension portion 5Z and the signal of the 4 th pixel 10 via the 4 th extension portion 12Z.
In the example of fig. 13, in a plan view, a portion of the 3 rd signal path 11 extending from the 3 rd pixel 9 to the 2 nd region 62 and a portion of the 4 th signal path 12 extending from the 4 th pixel 10 to the 1 st region 61 do not intersect.
Specifically, for example, in a plan view, a portion of the 3 rd signal path 11 extending from the 3 rd pixel 9 to the second 1/2 region 72 and a portion of the 4 th signal path 12 extending from the 4 th pixel 10 to the first 1/2 region 71 do not intersect.
In example 1, the 1 st pixel 2 and the 3 rd pixel 9 are 1 st type pixels selected from 4 types of R pixels, B pixels, Gr pixels, and Gb pixels. The 2 nd pixel 3 is a 2 nd pixel selected from 4 types of R pixel, B pixel, Gr pixel, and Gb pixel. The 1 st pixel and the 2 nd pixel are different from each other. The 1 st example is adapted to reduce signal noise of the 1 st pixel 2 and the 3 rd pixel 9 as the 1 st type pixels by correction of the same correction condition.
The 4 th pixel 10 may be the 2 nd pixel. This example is suitable for reducing the signal noise of the 2 nd pixel 3 and the 4 th pixel 10 as the 2 nd type pixels by the correction of the same correction condition.
In the specific example of example 1, all paths of signals of the 1 st pixel have a portion extending in the 1 st region 61 in a plan view. All paths of the signals of the type 2 pixels have a portion extending within the type 2 region 62 in plan view.
More specifically, for example, the entire path of the signal of the 1 st pixel has a portion extending within the first 1/2 area 71 in plan view. The entire path of the signal of the type 2 pixel has a portion extending within the second 1/2 area 72 in plan view.
In example 2, the 1 st pixel 2 includes a 1 st color filter. The 2 nd pixel 3 includes a 2 nd color filter. The 3 rd pixel 9 includes a 3 rd color filter. The 1 st color filter and the 3 rd color filter are color filters of the 1 st color. The 2 nd color filter is a 2 nd color filter different from the 1 st color. The 2 nd example is adapted to reduce signal noise of the 1 st pixel 2 and the 3 rd pixel 9 as pixels including the color filter of the 1 st color by correction of the same correction condition.
The 4 th pixel 10 may include a 4 th color filter of the 2 nd color. This example is suitable for reducing signal noise of the 2 nd pixel 3 and the 4 th pixel 10, which are pixels including a color filter of the 2 nd color, by correction of the same correction condition.
In the specific example of example 2, all paths of signals of pixels including the color filter of the 1 st color have a portion extending in the 2 nd region 62 in a plan view. All paths of signals of pixels including the 2 nd color filter have a portion extending in the 1 st region 61 in a plan view.
More specifically, for example, all paths of signals of pixels including the color filter of the 1 st color have a portion extending within the second 1/2 area 72 in plan view. All paths of signals of pixels including the color filter of the 2 nd color have a portion extending within the first 1/2 area 71 in plan view.
In the example of fig. 16, the 2 nd signal path 5 and the 4 th signal path 12 extend in a portion based on the 1 st voltage line 7 different from each other in the 1 st region 61 (specifically, in the first 1/2 region 71) in a plan view. However, the 2 nd signal path 5 and the 4 th signal path 12 may extend in a portion based on the same 1 st voltage line 7 in the 1 st region 61 (specifically, in the first 1/2 region 71) in a plan view.
In the example of fig. 16, the 1 st signal path 4 and the 3 rd signal path 11 extend in a portion based on the same 2 nd voltage line 8 in the 2 nd region 62 (specifically, in the second 1/2 region 72) in plan view. However, the 1 st signal path 4 and the 3 rd signal path 11 may extend in a portion based on the 2 nd voltage lines 8 different from each other in the 2 nd region 62 (specifically, in the second 1/2 region 72) in a plan view.
In the specific example of fig. 16, the 1 st voltage on the 1 st voltage line 7 is the power supply voltage. The 2 nd voltage of the 2 nd voltage line 8 is a ground voltage. In fig. 16, "VDD" represents a power supply voltage. "GND" denotes a ground voltage. The 2 nd voltage may be a power supply voltage and the 1 st voltage may be a ground voltage.
As a measure against noise, it is known to provide a shield line or to increase the distance between signal paths. However, these countermeasures lead to an increase in layout area. In contrast, in embodiment 2, a part of the signal paths are provided in the 1 st region 61, and another part of the signal paths are provided in the 2 nd region 62, thereby realizing measures against noise. That is, in embodiment 2, by disposing a part of the signal path close to the 1 st voltage line 7 and another part of the signal path close to the 2 nd voltage line 8, a noise countermeasure is achieved. Thus, an increase in layout area can be suppressed.
By using a plurality of signal paths provided in one pixel column pitch, it is possible to achieve high speed by parallel processing or low noise by feedback to the pixel array 1. Such high speed and low noise are performed in, for example, an image sensor having a stacked structure. According to the noise countermeasure described above, such high speed and low noise can be achieved while suppressing an increase in layout area.
In the case where the 1 st signal path 4 has a feedback path to the pixel array 1, the feedback path may have a portion extending in the 2 nd area 62 in a plan view. In the case where the 2 nd signal path 5 has a feedback path for feeding back to the pixel array 1, the feedback path may have a portion extending in the 1 st region 61 in a plan view. In the case where the 3 rd signal path 11 has a feedback path to the pixel array 1, the feedback path may have a portion extending in the 2 nd area 62 in a plan view. In the case where the 4 th signal path 12 has a feedback path for feeding back to the pixel array 1, the feedback path may have a portion extending in the 1 st region 61 in a plan view.
Specifically, in the case where the 1 st signal path 4 has a feedback path for feeding back to the pixel array 1, the feedback path may have a portion extending in the second 1/2 region 72 in a plan view. In the case where the 2 nd signal path 5 has a feedback path to the pixel array 1, the feedback path may have a portion extending in the first 1/2 area 71 in a plan view. In the case where the 3 rd signal path 11 has a feedback path to the pixel array 1, the feedback path may also have a portion extending within the second 1/2 area 72 in plan view. In the case where the 4 th signal path 12 has a feedback path for feeding back to the pixel array 1, the feedback path may have a portion extending in the first 1/2 area 71 in plan view.
In fig. 13, the 2 nd voltage line 8, the 1 st voltage line 7, the 2 nd voltage line 8, and the 1 st voltage line 7 are arranged in this order in a plan view. Here, consider a case where the 1 st circuit 6 is expanded and the 2 nd voltage line 8 is further provided at the position of the broken line D. In this case, the layout of the 1 st signal path 4 may be changed so that the 1 st signal path 4 extends in the 2 nd region 62 (specifically, the second 1/2 region 72) in a portion of the 2 nd voltage line 8 based on the position of the broken line D in a plan view. In general, the 1 st signal path 4 may extend in a portion based on an arbitrary 2 nd voltage line 8 in the 2 nd region 62 (specifically, the second 1/2 region 72) in a plan view. Likewise, the 2 nd signal path 5 may extend within a portion based on any 1 st voltage line 7 in the 1 st region 61 (specifically, the first 1/2 region 71). The same applies to the other signal paths.
As described above, in the example of fig. 16, the pitches of the plurality of voltage lines 15, 16 in the 2 nd circuit 14 and the pitches of the voltage lines 7, 8 in the 1 st circuit 6 are different from each other in a plan view. Specifically, for example, the plurality of voltage lines 15, 16 in the 2 nd circuit 14 have a 1 column pitch. The voltage lines 7, 8 in the 1 st circuit 6 have a 2 column pitch instead of a 1 column pitch.
The pitch of the plurality of voltage lines 15 and 16 in the 2 nd circuit 14 may be the same as the pitch of the voltage lines 7 and 8 in the 1 st circuit 6 in a plan view.
When the pitch of the voltage lines 15 and 16 is the same as the pitch of the voltage lines 7 and 8, a description will be given of how the technique according to embodiment 2 is advantageous with reference to fig. 19A and 19B.
In the example of fig. 19A, the imaging device includes another circuit 94 different from the 1 st circuit 6 and the 2 nd circuit 14. The circuit 94 is supplied with a voltage via a plurality of voltage lines 95 and 96. The voltage lines 95 and 96 are power supply lines used in the other circuit 94, but may be noise sources for the signal paths 97 and 98.
In this example, the voltage of the voltage line 95 is the power supply voltage. The voltage of the voltage line 96 is the ground voltage. In fig. 19A, "VDD 2" represents a power supply voltage. "GND 2" represents the ground voltage. The voltage on the voltage line 96 may be a power supply voltage, and the voltage on the voltage line 95 may be a ground voltage.
In the example of fig. 19A, signal paths 97 for signals of Gr pixels and signal paths 98 for signals of Gb pixels are alternately and repeatedly arranged in a plan view. In plan view, the spacing of the signal paths 97, 98 from the voltage lines 95, 96 is ensured. This suppresses the signals from the voltage lines 95 and 96 to the signal paths 97 and 98 from being superimposed with noise.
In order to further reduce noise, as shown in fig. 19B, in a plan view, the signal path 97s and the signal path 98s intersect each other in the region M1, so that the signal path 97s can be extended to a position close to the 2 nd voltage line 8 and the signal path 98s can be extended to a position close to the 1 st voltage line 7. In the region M2, the signal path 97t and the signal path 98t intersect with each other in plan view, so that the signal path 97t can be extended to a position close to the 2 nd voltage line 8 and the signal path 98t can be extended to a position close to the 1 st voltage line 7. In this way, in a plan view, all the signal paths 97 can be extended to a position close to the 2 nd voltage line 8, and all the signal paths 98 can be extended to a position close to the 1 st voltage line 7. In this way, by performing correction to reduce noise originating from the 2 nd voltage line 8 for the signals of the plurality of signal paths 97, noise of these signals can be appropriately reduced. By performing correction to reduce noise originating from the 1 st voltage line 7 for the signals of the plurality of signal paths 98, the noise of these signals can be appropriately reduced. For this reason, also in the case where the pitch of the voltage lines 15, 16 is the same as the pitch of the voltage lines 7, 8, the technique according to embodiment 2 can obtain an advantage. Here, a position close to the 1 st voltage line 7 in a plan view corresponds to the 1 st region 61, specifically, for example, corresponds to the first 1/2 region 71. A position close to the 2 nd voltage line 8 in a plan view corresponds to the 2 nd region 62, specifically, for example, the second 1/2 region 72.
In the example of fig. 19B, in the 2 nd circuit 14, a certain signal path 97 extends to a position close to the 3 rd voltage line 15, and the other signal path 97 extends to a position close to the 4 th voltage line 16. In the 2 nd circuit 14, a certain signal path 98 extends to a position close to the 3 rd voltage line 15, and the other signal paths 98 extend to a position close to the 4 th voltage line 16. Which is not necessarily a problem in noise countermeasure. For example, in the case where the length of the 2 nd circuit 14 is short, the influence of superposition of noise in the 2 nd circuit 14 is limited. When the distance in parallel between the signal paths 97 and 98 to be noise-suppressed and the voltage lines 15 and 16 as noise sources is short, the influence of the superimposition of noise in the 2 nd circuit 14 is also limited. In addition, the 2 nd circuit 14 can suppress the influence of the superposition of noise by other means such as masking.
(embodiment 3)
Hereinafter, embodiment 3 will be described. In embodiment 3, the same contents as those in embodiment 2 are denoted by the same reference numerals and description thereof may be omitted.
As shown in fig. 20, in embodiment 3, in the 1 st signal path 4, a portion 4X intersecting the 2 nd signal path 5, a portion intersecting the 3 rd signal path 11, a portion intersecting a straight line 8L including the 2 nd voltage line 8, and a portion 4Z extending in the 2 nd area 62 are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view.
Specifically, for example, in the 1 st signal path 4, a portion 4X intersecting the 2 nd signal path 5, a portion intersecting the 3 rd signal path 11, a portion intersecting a straight line 8L including the 2 nd voltage line 8, and a portion 4Z extending in the second 1/2 region 72 are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view.
In the 3 rd signal path 11, a portion intersecting with the straight line 8L including the 2 nd voltage line 8, a portion intersecting with the 1 st signal path 4, and a portion extending in the 2 nd region 62 are arranged in this order in the flow direction of the signal of the 3 rd pixel 9 in plan view.
Specifically, for example, in the 3 rd signal path 11, a portion intersecting with the straight line 8L including the 2 nd voltage line 8, a portion intersecting with the 1 st signal path 4, and a portion extending in the second 1/2 area 72 are arranged in this order in the flow direction of the signal of the 3 rd pixel 9 in plan view.
In the example of fig. 20, in the output portion from the pixel array 1, the 1 st signal path 4, the 2 nd signal path 5, the 3 rd signal path 11, and the 4 th signal path 12 are arranged in this order in plan view. In the region closer to the 1 st circuit 6 than the intersections 4X and 5X, the 2 nd signal path 5, the 3 rd signal path 11, the 1 st signal path 4, and the 4 th signal path 12 are arranged in this order in plan view.
In embodiment 3, a portion 4X intersecting with the 2 nd signal path 5 and a portion intersecting with the 3 rd signal path 11 are arranged in the 1 st signal path 4 in a plan view. In the 1 st signal path 4, the signal path may further intersect with other signal paths in plan view. In other words, the number of intersections with other signal paths in the 1 st signal path 4 may be 2 or 3 or more in plan view.
In embodiment 3, in the 1 st signal path 4, there is a portion that intersects a straight line 8L including one 2 nd voltage line 8 in a plan view. In the 1 st signal path 4, a straight line including another voltage line may further intersect in a plan view. In other words, the number of intersections with the straight line including the voltage line in the 1 st signal path 4 may be 1 or 2 or more in plan view.
(embodiment 4)
Hereinafter, embodiment 4 will be described. In embodiment 4, the same contents as those in embodiment 1 are denoted by the same reference numerals and description thereof may be omitted.
In embodiment 1 and the like, correction for reducing noise is performed inside the imaging apparatus 100. However, correction for reducing noise may be performed outside the imaging apparatus 100. Hereinafter, embodiment 4 will be described with reference to fig. 21A to 21C. Although not shown in fig. 21A, the analog-to-digital conversion circuit 40 and the like may be provided between the 1 st circuit 6 and the output circuit 44.
As the correction, for example, optical black correction can be employed. The technique using the 1 st OB pixel 65 and the 1 st OB path 66 described above can be used for the optical black correction. For the optical black correction, the already described technique using the 2 nd OB pixel 67 and the 2 nd OB path 68 can be utilized.
In one specific example, the imaging system 200 shown in fig. 21A to 21C includes an imaging device 100 and a signal processing device 18 provided outside the imaging device 100. The plurality of pixels include the 1 st OB pixel 65 as an optical black pixel. The image pickup apparatus 100 includes a 1 st OB path 66 through which a signal of a 1 st OB pixel 65 flows. In plan view, there is a 1 st OB extension 66Z extending within the 2 nd area 62 in the 1 st OB path 66. The signal processing device 18 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st OB extension 66Z for the signal of the 1 st pixel 2 via the 1 st extension 4Z.
Specifically, for example, the 1 st OB extension 66Z is a portion extending within the second 1/2 area 72 in plan view in the 1 st OB path 66. The 1 st extension 4Z is a portion extending within the second 1/2 area 72 in plan view in the 1 st signal path 4.
In one specific example, the imaging system 200 shown in fig. 21A to 21C includes an imaging device 100 and a signal processing device 18 provided outside the imaging device 100. The plurality of pixels includes the 2 nd OB pixel 67 as an optical black pixel. The image pickup apparatus 100 includes a 2OB path 68 through which a signal of the 2OB pixel 67 flows. In a plan view, there is a 2OB extension 68Z extending within the 1 st region 61 in the 2OB path 68. The signal processing device 18 performs optical black correction using the signal of the 2 nd OB pixel 67 via the 2 nd OB extension 68Z for the signal of the 2 nd pixel 3 via the 2 nd extension 5Z.
Specifically, for example, the 2OB extension 68Z is a portion extending within the first 1/2 area 71 in a plan view in the 2OB path 68. The 2 nd extension 5Z is a portion extending within the first 1/2 area 71 in plan view in the 2 nd signal path 5.
The correction described in embodiment 2 may be performed outside the imaging apparatus 100. Fig. 22A to 22C show an image pickup system 200 suitable for the case of performing such correction. The imaging system 200 of fig. 22A to 22C includes the imaging device 100 and the signal processing device 18 provided outside the imaging device 100. The signal processing device 18 performs correction to reduce the noise component superimposed in the 2 nd area 62 for both the 1 st pixel 2 signal passing through the 1 st extension 4Z and the 3 rd pixel 9 signal passing through the 3 rd extension 11Z.
Specifically, for example, the 1 st extension 4Z is a portion extending within the second 1/2 area 72 in plan view in the 1 st signal path 4. The 3 rd extension 11Z is a portion extending within the second 1/2 area 72 in plan view in the 3 rd signal path 11. The signal processing device 18 performs correction to reduce the noise component superimposed in the second 1/2 region 72 for both the signal of the 1 st pixel 2 via the 1 st extension 4Z and the signal of the 3 rd pixel 9 via the 3 rd extension 11Z.
In one embodiment, the correction is an optical black correction. In this specific example, the 1 st OB pixel 65 and the 1 st OB path 66 described above are used. The signal processing device 18 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st OB extension 66Z for both the signal of the 1 st pixel 2 via the 1 st extension 4Z and the signal of the 3 rd pixel 9 via the 3 rd extension 11Z.
In one example, the signal processing device 18 performs correction to reduce the noise component superimposed in the 1 st region 61 for both the signal of the 2 nd pixel 3 via the 2 nd extending portion 5Z and the signal of the 4 th pixel 10 via the 4 th extending portion 12Z.
Specifically, for example, the 2 nd extension portion 5Z is a portion extending within the first 1/2 area 71 in a plan view in the 2 nd signal path 5. The 4 th extension 12Z is a portion extending within the first 1/2 area 71 in plan view in the 4 th signal path 12. The signal processing device 18 performs correction to reduce the noise component superimposed in the first 1/2 region 71 for both the signal of the 2 nd pixel 3 via the 2 nd extension 5Z and the signal of the 4 th pixel 10 via the 4 th extension 12Z.
In one embodiment, the correction is an optical black correction. In this specific example, the 2 nd OB pixel 67 and the 2 nd OB path 68 described above are used. The signal processing device 18 performs optical black correction using the signal of the 2 nd OB pixel 67 via the 2 nd OB extension 68Z for both the signal of the 2 nd pixel 3 via the 2 nd extension 5Z and the signal of the 4 th pixel 10 via the 4 th extension 12Z.
The technique of performing correction outside the imaging apparatus 100 can be applied to other embodiments.
(embodiment 5)
Hereinafter, embodiment 5 will be described. In embodiment 5, the same contents as those in embodiment 1 are denoted by the same reference numerals and description thereof may be omitted.
Fig. 23 shows the pixel array 1 and the 1 st circuit 6 in embodiment 5.
As shown in fig. 23, in the pixel array 1 according to embodiment 5, the plurality of pixels includes not only the 1 st pixel 2 and the 2 nd pixel 3 but also the 3 rd pixel 21 and the 4 th pixel 22.
In the example of fig. 23, the 1 st pixel 2 and the 3 rd pixel 21 belong to the same column in the pixel array 1. The 2 nd pixel 3 and the 4 th pixel 22 belong to the same column in the pixel array 1. The 1 st pixel 2 and the 3 rd pixel 21 belong to columns adjacent to the 2 nd pixel 3 and the 4 th pixel 22.
In example 1, the 1 st pixel 2 and the 3 rd pixel 21 are 1 st type pixels selected from 4 types of R pixels, B pixels, Gr pixels, and Gb pixels. The 2 nd pixel 3 and the 4 th pixel 22 are 2 nd pixels selected from 4 types of R pixels, B pixels, Gr pixels, and Gb pixels. Specifically, for example, the 1 st pixel 2 and the 3 rd pixel 21 are Gr pixels. The 2 nd pixel 3 and the 4 th pixel 22 are Gb pixels.
In example 2, the 1 st pixel 2 and the 3 rd pixel 21 are pixels of the 1 st color. The 2 nd pixel 3 and the 4 th pixel 22 are pixels of the 2 nd color. Specifically, for example, the 1 st pixel 2 and the 3 rd pixel 21 include color filters of the 1 st color. The 2 nd pixel 3 and the 4 th pixel 22 include color filters of the 2 nd color.
Hereinafter, a path through which a signal of the 3 rd pixel 21 flows may be referred to as a 3 rd signal path 4B. The path through which the signal of the 4 th pixel 22 flows is sometimes referred to as a 4 th signal path 5B.
In the example of fig. 23, from the output portion of the pixel array 1, the 1 st signal path 4, the 3 rd signal path 4B, the 4 th signal path 5B, and the 2 nd signal path 5 are arranged in this order in plan view. In the region closer to the 1 st circuit 6 than the intersections 4X and 5X, the 4 th signal path 5B, the 2 nd signal path 5, the 1 st signal path 4, and the 3 rd signal path 4B are arranged in this order in plan view.
In the example of fig. 23, in the 1 st signal path 4, the intersection 4X intersecting the 2 nd signal path 5 and the 1 st extension 4Z extending in the 2 nd region 62 are arranged in this order in the flow direction 2F of the signal of the 1 st pixel 2 in plan view. In the 3 rd signal path 4B, an intersection portion intersecting with the 4 th signal path 5B and the 3 rd extending portion 4BZ extending in the 2 nd region 62 are arranged in this order in the flow direction 21F of the signal of the 3 rd pixel 21 in plan view. Such a layout facilitates correction for reducing noise of the 1 st pixel 2 signal and the 3 rd pixel 21 signal. Specifically, according to such a layout, it is less likely that a difference in noise components superimposed on the signal of the 1 st pixel 2 and the signal of the 3 rd pixel 21 in the 1 st circuit 6 occurs, as compared with a case where one of the 1 st signal path 4 and the 3 rd signal path 4B extends in the 2 nd region 62 and the other extends in the 1 st region 61. Therefore, such an arrangement is suitable for reducing these signal noises by correction of the same correction conditions.
In the example of fig. 23, in the 2 nd signal path 5, the intersection portion 5X intersecting the 1 st signal path 4 and the 2 nd extending portion 5Z extending in the 1 st region 61 are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. In the 4 th signal path 5B, an intersection intersecting the 3 rd signal path 4B and a 4 th extending portion 5BZ extending in the 1 st region 61 are arranged in this order in the signal flow direction 22F of the 4 th pixel 22 in plan view. Such a layout facilitates correction for reducing noise of the signals of the 2 nd pixel 3 and the 4 th pixel 22. Specifically, according to such a layout, it is less likely that a difference in noise components superimposed on the signals of the 2 nd pixel 3 and the 4 th pixel 22 in the 1 st circuit 6 occurs, as compared with a case where one of the 2 nd signal path 5 and the 4 th signal path 5B extends in the 1 st region 61 and the other extends in the 2 nd region 62. Therefore, such an arrangement is suitable for reducing these signal noises at the correction of the same correction condition.
Specifically, for example, the 1 st extension 4Z is a portion of the 1 st signal path 4 extending within the second 1/2 area 72 in plan view. The 3 rd extension 4BZ is a portion of the 3 rd signal path 4B extending within the second 1/2 area 72 in plan view. The 2 nd extension 5Z is a portion of the 2 nd signal path 5 extending within the first 1/2 area 71 in plan view. The 4 th extension 5BZ is a portion of the 4 th signal path 5B extending within the first 1/2 area 71 in plan view.
An example of a method of correction for reducing noise is described. In the example of fig. 23, the signal processing circuit 43 performs correction to reduce the noise component superimposed in the 2 nd area 62 for both the signal of the 1 st pixel 2 via the 1 st extension portion 4Z and the signal of the 3 rd pixel 21 via the 3 rd extension portion 4 BZ. According to this example, the same correction conditions are easily applied to the correction of the signal of the 1 st pixel 2 and the correction of the signal of the 3 rd pixel 21.
Specifically, for example, the 1 st extension 4Z is a portion extending within the second 1/2 area 72 in plan view in the 1 st signal path 4. The 3 rd extension 4BZ is a portion extending within the second 1/2 area 72 in plan view in the 3 rd signal path 4B. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the second 1/2 region 72 for both the signal of the 1 st pixel 2 via the 1 st extension 4Z and the signal of the 3 rd pixel 21 via the 3 rd extension 4 BZ.
In one embodiment, the correction is an optical black correction. In this specific example, the 1 st OB pixel 65 and the 1 st OB path 66 described above are used. The signal processing circuit 43 performs optical black correction using the signal of the 1 st OB pixel 65 via the 1 st OB extension portion 66Z for both the signal of the 1 st pixel 2 via the 1 st extension portion 4Z and the signal of the 3 rd pixel 21 via the 3 rd extension portion 4 BZ.
In the example of fig. 23, the signal processing circuit 43 performs correction to reduce the noise component superimposed in the 1 st region 61 for both the signal of the 2 nd pixel 3 via the 2 nd extending portion 5Z and the signal of the 4 th pixel 22 via the 4 th extending portion 5 BZ. According to this example, the same correction conditions are easily applied to the correction of the signal of the 2 nd pixel 3 and the correction of the signal of the 4 th pixel 22.
Specifically, for example, the 2 nd extension portion 5Z is a portion extending within the first 1/2 area 71 in a plan view in the 2 nd signal path 5. The 4 th extension 5BZ is a portion extending within the first 1/2 area 71 in plan view in the 4 th signal path 5B. The signal processing circuit 43 performs correction to reduce the noise component superimposed in the first 1/2 region 71 for both the signal of the 2 nd pixel 3 via the 2 nd extension 5Z and the signal of the 4 th pixel 22 via the 4 th extension 5 BZ.
In one embodiment, the correction is an optical black correction. In this specific example, the 2 nd OB pixel 67 and the 2 nd OB path 68 described above are used. The signal processing circuit 43 performs optical black correction using the signal of the 2 nd OB pixel 67 via the 2 nd OB extension portion 68Z for both the signal of the 2 nd pixel 3 via the 2 nd extension portion 5Z and the signal of the 4 th pixel 22 via the 4 th extension portion 5 BZ.
The 1 st example is suitable for reducing noise of signals of the 1 st pixel 2 and the 3 rd pixel 21 which are the 1 st type pixels by correction of the same correction condition. The 1 st example is suitable for reducing noise of signals of the 2 nd pixel 3 and the 4 th pixel 22 as the 2 nd type pixels by correction of the same correction condition.
The 2 nd example is adapted to reduce noise of signals of the 1 st pixel 2 and the 3 rd pixel 21, which are pixels including the color filter of the 1 st color, by correction of the same correction condition. The 2 nd example is adapted to reduce noise of signals of the 2 nd pixel 3 and the 4 th pixel 22, which are pixels including the color filter of the 2 nd color, by correction of the same correction condition.
As shown in fig. 24, a 1 st voltage line 7B may be added. The 1 st voltage is applied to the 1 st voltage line 7B, similarly to the 1 st voltage line 7. In the example of fig. 24, the 1 st voltage line 7, the 4 th signal path 5B, the 2 nd signal path 5, and the 1 st voltage line 7B are arranged in this order in a plan view. In plan view, the distance between the 1 st voltage line 7 and the 4 th signal path 5B is the same as the distance between the 2 nd signal path 5 and the 1 st voltage line 7B. Thus, the difference between the noise superimposed on the signal of the 4 th signal path 5B in the 1 st region 61 and the noise superimposed on the signal of the 2 nd signal path 5 in the 1 st region 61 becomes small. Therefore, the example of fig. 24 is suitable for reducing the noise of the signals of the 2 nd pixel 3 and the 4 th pixel 22 by the correction of the same correction condition.
As shown in fig. 24, a 2 nd voltage line 8B may be added. The 2 nd voltage line 8B is applied with the 2 nd voltage, as with the 2 nd voltage line 8. In the example of fig. 24, the 2 nd voltage line 8B, the 1 st signal path 4, the 3 rd signal path 4B, and the 2 nd voltage line 8 are arranged in this order in a plan view. In plan view, the distance between the 2 nd voltage line 8B and the 1 st signal path 4 is the same as the distance between the 3 rd signal path 4B and the 2 nd voltage line 8. Thus, the difference between the noise superimposed on the signal of the 1 st signal path 4 in the 2 nd area 62 and the noise superimposed on the signal of the 3 rd signal path 4B in the 2 nd area 62 becomes small. Therefore, the example of fig. 24 is suitable for reducing the noise of the signals of the 1 st pixel 2 and the 3 rd pixel 21 by the correction under the same correction condition.
As shown in fig. 25, the 1 st signal path 4 and the 3 rd signal path 4B may intersect at an intermediate point of the length of the 2 nd voltage line 8 in a plan view. Here, the intermediate point is, for example, an intermediate portion obtained by equally dividing the length by 3, specifically, for example, a position obtained by equally dividing the length by 2. Thus, the difference between the coupling capacitance between the 1 st signal path 4 and the 2 nd voltage line 8 and the coupling capacitance between the 3 rd signal path 4B and the 2 nd voltage line 8 can be reduced. Thus, the difference between the noise superimposed on the signal of the 1 st signal path 4 in the 2 nd area 62 and the noise superimposed on the signal of the 3 rd signal path 4B in the 2 nd area 62 becomes small. Therefore, the example of fig. 25 is suitable for reducing the noise of the signals of the 1 st pixel 2 and the 3 rd pixel 21 by the correction under the same correction condition.
As shown in fig. 25, the 2 nd signal path 5 and the 4 th signal path 5B may intersect at an intermediate point of the length of the 1 st voltage line 7 in a plan view. Here, the intermediate point is, for example, an intermediate portion obtained by equally dividing the length by 3, specifically, for example, a position obtained by equally dividing the length by 2. Thus, the difference between the coupling capacitance between the 2 nd signal path 5 and the 1 st voltage line 7 and the coupling capacitance between the 4 th signal path 5B and the 1 st voltage line 7 can be reduced. Thus, the difference between the noise superimposed on the signal of the 2 nd signal path 5 in the 1 st region 61 and the noise superimposed on the signal of the 4 th signal path 5B in the 1 st region 61 becomes small. Therefore, the example of fig. 25 is suitable for reducing the noise of the signals of the 2 nd pixel 3 and the 4 th pixel 22 by the correction of the same correction condition.
(embodiment 6)
Hereinafter, embodiment 6 will be described. In embodiment 6, the same contents as those in embodiment 2 are denoted by the same reference numerals and description thereof may be omitted.
Fig. 26 shows the pixel array 1 and the 1 st circuit 6 in embodiment 6.
As shown in fig. 26, in the pixel array 1 of embodiment 6, the plurality of pixels includes the 1 st pixel 23, the 2 nd pixel 24, the 3 rd pixel 25, the 4 th pixel 26, the 5 th pixel 23C, the 6 th pixel 24C, the 7 th pixel 25C, and the 8 th pixel 26C.
Hereinafter, a path through which a signal of the 1 st pixel 23 flows may be referred to as a 1 st signal path 4. The path through which the signal of the 2 nd pixel 24 flows is sometimes referred to as the 2 nd signal path 5. The path through which the signal of the 3 rd pixel 25 flows is sometimes referred to as a 3 rd signal path 11. The path through which the signal of the 4 th pixel 26 flows is sometimes referred to as the 4 th signal path 12. A path through which a signal of the 5 th pixel 23C flows is sometimes referred to as a 5 th signal path 4C. A path through which a signal of the 6 th pixel 24C flows is sometimes referred to as a 6 th signal path 5C. A path through which a signal of the 7 th pixel 25C flows is sometimes referred to as a 7 th signal path 11C. The path through which the signal of the 8 th pixel 26C flows is sometimes referred to as an 8 th signal path 12C.
The 1 st, 2 nd, 3 rd, and 4 th signal paths 4, 5, 11, and 12 can have the same features as the 2 nd embodiment. For example, the 1 st signal path 4 intersects the 2 nd signal path 5 in plan view.
In plan view, there is a portion extending within the 1 st region 61 in the 5 th signal path 4C. In plan view, there is a portion extending within the 2 nd region 62 in the 6 th signal path 5C. In plan view, there is a portion extending within the 1 st region 61 in the 7 th signal path 11C. In plan view, there is a portion of the 8 th signal path 12C that extends within the 2 nd region 62.
Specifically, for example, in the 5 th signal path 4C, there is a portion extending in the first 1/2 area 71 in a plan view. In plan view, there is a portion in the 6 th signal path 5C that extends within the second 1/2 area 72. In plan view, there is a portion extending within the first 1/2 area 71 in the 7 th signal path 11C. In plan view, there is a portion in the 8 th signal path 12C that extends within the second 1/2 area 72.
In this example, in a plan view, there are portions extending in the 1 st region 61 in the 2 nd signal path 5, the 4 th signal path 12, the 5 th signal path 4C, and the 7 th signal path 11C. Specifically, for example, in a plan view, there are portions extending in the first 1/2 region 71 in the 2 nd signal path 5, the 4 th signal path 12, the 5 th signal path 4C, and the 7 th signal path 11C. Therefore, in the 2 nd signal path 5, the 4 th signal path 12, the 5 th signal path 4C, and the 7 th signal path 11C, a difference in noise components superimposed on the signal in the 1 st circuit 6 is less likely to occur. Therefore, this example is suitable for reducing the noise of these signals in the correction of the same correction condition. For these signals, the above-described correction to reduce the noise component superimposed in the 1 st region 61 can be performed. Specifically, for example, the above-described correction for reducing the noise component superimposed in the first 1/2 area 71 can be performed for these signals.
In this example, in a plan view, there are portions extending in the 2 nd region 62 in the 1 st signal path 4, the 3 rd signal path 11, the 6 th signal path 5C, and the 8 th signal path 12C. Specifically, for example, in plan view, there are portions extending in the second 1/2 region 72 in the 1 st signal path 4, the 3 rd signal path 11, the 6 th signal path 5C, and the 8 th signal path 12C. Therefore, in the 1 st signal path 4, the 3 rd signal path 11, the 6 th signal path 5C, and the 8 th signal path 12C, a difference in noise components superimposed on the signal in the 1 st circuit 6 is less likely to occur. Therefore, this example is suitable for reducing the noise of these signals in the correction of the same correction condition. For these signals, the above-described correction to reduce the noise component superimposed in the 2 nd region 62 can be performed. Specifically, for these signals, the above-described correction to reduce the noise component superimposed in the second 1/2 area 72 can be performed.
In the example of fig. 26, in the output portion from the pixel array 1, the 1 st signal path 4, the 5 th signal path 4C, the 6 th signal path 5C, the 2 nd signal path 5, the 3 rd signal path 11, the 7 th signal path 11C, the 8 th signal path 12C, and the 4 th signal path 12 are arranged in this order in plan view. In the region closer to the 1 st circuit 6 than the intersections 4X and 5X, the 5 th signal path 4C, the 2 nd signal path 5, the 1 st signal path 4, the 6 th signal path 5C, the 3 rd signal path 11, the 8 th signal path 12C, the 7 th signal path 11C, and the 4 th signal path 12 are arranged in this order in plan view.
In a plan view, intersections between the paths are made so that the arrangement of the paths changes between the output portion from the pixel array 1 and the region close to the 1 st circuit 6. Specifically, for example, the 1 st signal path 4 and the 5 th signal path 4C intersect between the output portion of the pixel array 1 and the region close to the 1 st circuit 6 in a plan view. In between, the 2 nd signal path 5 crosses the 6 th signal path 5C. In between, the 1 st signal path 4 crosses the 2 nd signal path 5. In between, the 7 th signal path 11C crosses the 8 th signal path 12C.
In the example of fig. 26, the 1 st pixel 23 and the 5 th pixel 23C belong to the same column in the pixel array 1. The 2 nd pixel 24 and the 6 th pixel 24C belong to the same column in the pixel array 1. The 3 rd pixel 25 and the 7 th pixel 25C belong to the same column in the pixel array 1. The 4 th pixel 26 and the 8 th pixel 26C belong to the same column in the pixel array 1. The 4 columns are arranged adjacently in the order illustrated.
In example 1, the 1 st pixel 23 and the 3 rd pixel 25 are 1 st type pixels selected from 4 types of R pixels, B pixels, Gr pixels, and Gb pixels. The 2 nd pixel 24 and the 4 th pixel 26 are the 2 nd type pixels selected from the 4 types. The 5 th pixel 23C and the 7 th pixel 25C are the 3 rd type pixels selected from the 4 types. The 6 th pixel 24C and the 8 th pixel 26C are the 4 th pixel selected from the 4 kinds. The 1 st pixel, the 2 nd pixel, the 3 rd pixel, and the 4 th pixel are different from each other.
Specifically, for example, the 1 st pixel 23 and the 3 rd pixel 25 are Gr pixels. The 2 nd pixel 24 and the 4 th pixel 26 are R pixels. The 5 th pixel 23C and the 7 th pixel 25C are B pixels. The 6 th pixel 24C and the 8 th pixel 26C are Gb pixels.
In example 2, the 1 st pixel 23 and the 3 rd pixel 25 are pixels of the 1 st color. The 2 nd pixel 24 and the 4 th pixel 26 are pixels of the 2 nd color. The 5 th pixel 23C and the 7 th pixel 25C are pixels of the 3 rd color. The 6 th pixel 24C and the 8 th pixel 26C are pixels of the 4 th color. The 1 st color, the 2 nd color, the 3 rd color, and the 4 th color are different from each other.
Specifically, for example, the 1 st pixel 23 and the 3 rd pixel 25 include a color filter of the 1 st color. The 2 nd pixel 24 and the 4 th pixel 26 include color filters of the 2 nd color. The 5 th pixel 23C and the 7 th pixel 25C include a color filter of the 3 rd color. The 6 th pixel 24C and the 8 th pixel 26C include color filters of the 4 th color.
The readout order of the pixels is not particularly limited. The 5 th pixel 23C, the 6 th pixel 24C, the 7 th pixel 25C, and the 8 th pixel 26C may be read out after the 1 st pixel 23, the 2 nd pixel 24, the 3 rd pixel 25, and the 4 th pixel 26 are read out. The 1 st pixel 23, the 2 nd pixel 24, the 3 rd pixel 25, the 4 th pixel 26, the 5 th pixel 23C, the 6 th pixel 24C, the 7 th pixel 25C, and the 8 th pixel 26C may be simultaneously read out.
(7 th embodiment)
Hereinafter, embodiment 7 will be described. In embodiment 7, the same contents as those in embodiment 1 are denoted by the same reference numerals and description thereof may be omitted.
As shown in fig. 27, the imaging apparatus according to embodiment 7 includes a selector 27. In embodiment 7, a part of the 1 st signal path 4 is formed by the selector 27. A part of the 2 nd signal path 5 is constituted by a selector 27. Fig. 28 shows the structure of the selector 27.
In embodiment 7, in the 1 st signal path 4, the 1 st connection point 29A, the 1 st intersection 4X, the 2 nd connection point 29B, and the 1 st extension portion 4Z are arranged in this order in the flow direction 2F of the 1 st pixel 2 signal in a plan view. In the 2 nd signal path 5, the 3 rd connection point 29C, the 2 nd intersection 5X, the 4 th connection point 29D, and the 2 nd extension portion 5Z are arranged in this order in the flow direction 3F of the signal of the 2 nd pixel 3 in plan view. The imaging device includes a selector 27. The selector 27 includes a 1 st switch 28A, a 2 nd switch 28B, a 3 rd switch 28C, and a 4 th switch 28D. The 1 st switch 28A electrically connects the 1 st connection point 29A and the 4 th connection point 29D. The 2 nd switch 28B electrically connects the 1 st connection point 29A and the 2 nd connection point 29B. The 3 rd switch 28C electrically connects the 3 rd connection point 29C and the 4 th connection point 29D. The 4 th switch 28D electrically connects the 3 rd connection point 29C and the 2 nd connection point 29B. The selector 27 can switch the path of the signal of the pixel.
In other words, the 1 st switch 28A is connected between the 1 st connection point 29A and the 4 th connection point 29D. The 2 nd switch 28B is connected between the 1 st connection point 29A and the 2 nd connection point 29B. The 3 rd switch 28C is connected between the 3 rd connection point 29C and the 4 th connection point 29D. The 4 th switch 28D is connected between the 3 rd connection point 29C and the 2 nd connection point 29B.
The 2 nd switch 28B is disposed on the 1 st signal path 4. The 3 rd switch 28C is disposed on the 2 nd signal path 5.
In this example, the selector 27 includes a 1 st connection point 29A, a 2 nd connection point 29B, a 3 rd connection point 29C, and a 4 th connection point 29D.
The 1 st switch 28A, the 2 nd switch 28B, the 3 rd switch 28C, and the 4 th switch 28D may be configured to be switchable between a closed (ON) state and an Open (OFF) state by electrical control. These switches may also be fixed in a closed state or an open state. The control circuit 42 may control switching between the closed state and the open state of the 1 st to 4 th switches 28A to 28D.
When the 1 st switch 28A and the 4 th switch 28D are in the off state and the 2 nd switch 28B and the 3 rd switch 28C are in the on state, the signal of the 1 st pixel 2 and the signal of the 2 nd pixel 3 flow as in the embodiment 1.
The method of using the selector 27 will be further described below.
For example, the noise component in the 2 nd voltage line 8 is set to be smaller than the noise component in the 1 st voltage line 7. In this case, the pixels may be read out every 1 line. Specifically, after reading the 1 st pixel 2, the 2 nd pixel 3 may be read. In this case, the 1 st pixel 2 can be read by first setting the 2 nd switch 28B to the closed state and the 1 st switch 28A, the 3 rd switch 28C, and the 4 th switch 28D to the open state. After that, the 4 th switch 28D is set to the closed state, and the 1 st switch 28A, the 2 nd switch 28B, and the 3 rd switch 28C are set to the open state, whereby the 2 nd pixel 3 can be read. In this way, both the signal of the 1 st pixel 2 and the signal of the 2 nd pixel 3 can be transmitted through the vicinity of the 2 nd voltage line 8 having a relatively small noise component. This enables the 1 st pixel 2 and the 2 nd pixel 3 to be read out with low noise. The readout of these images is controlled by, for example, the line scanning circuit 41 and the control circuit 42.
After the imaging device is configured, the 1 st switch 28A, the 2 nd switch 28B, the 3 rd switch 28C, and the 4 th switch 28D may be switched on/off by electric control. For example, after the imaging device is configured, the noise on the voltage lines 7 and 8 may be actually measured, and whether the signal of the pixel passes through the vicinity of the voltage line 8 or the vicinity of the voltage line 7 may be selected based on the result of the actual measurement. In this way, noise can be reduced by only electrically controlling the selector 27 without reconfiguring the imaging device.
(specific example of imaging System)
A specific example of the imaging system will be described below. The imaging system of this specific example can be used for a smartphone, a video camera, a digital camera, a surveillance camera, an in-vehicle camera, and the like.
Fig. 29 shows an imaging system 200 as a specific example. The system 200 includes a lens 110, an imaging device 100, a signal processing unit 120, and a system controller 130.
The lens 110 is an optical element for introducing incident light into the pixel array 1 included in the imaging device 100.
The imaging device 100 converts image light formed on an imaging surface by the lens 110 into an electric signal on a pixel-by-pixel basis, and outputs the resulting image signal. The image signal is a set of signals of a plurality of pixels in the above-described embodiment. The imaging device of the above-described embodiment can be used as the imaging device 100. The imaging device according to the above-described embodiment can contribute to forming an image with less noise.
The signal processing unit 120 is a circuit that performs various kinds of processing on the image signal generated in the image pickup apparatus 100. In one example, the image signal processed by the signal processing unit 120 is recorded in a recording medium such as a memory as a still image or a moving image. In another example, the image signal is displayed as a moving image on a monitor such as a liquid crystal display. The signal processing section 120 may include the signal processing device 18 of fig. 21.
The system controller 130 is a control unit that drives the image pickup apparatus 100 and the signal processing unit 120.
The imaging device and the imaging system according to the embodiments of the present disclosure have been described above, but the present disclosure is not limited to the embodiments.
For example, division of functional blocks in the block diagrams is an example, and a plurality of functional blocks may be implemented as one functional block, one functional block may be divided into a plurality of functional blocks, or some functions may be transferred to another functional block.
Each processing unit included in each device of the above embodiments is typically realized as an LSI which is an integrated circuit. The processing units may be independently integrated into a single chip, or may be integrated into a single chip so as to include a part or all of them.
The integration is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing or a reconfigurable processor (reconfigurable processor) that can reconfigure connection and setting of circuit cells inside LSI may be used.
In each of the above embodiments, a part of each component may be realized by executing a software program suitable for the component. The components may be realized by a program execution unit such as a CPU or a processor reading out and executing a software program recorded in a recording medium such as a hard disk or a semiconductor memory.
The intersections in the above-described portions 4X and 5X in the plan view are not necessary. In order to solve a part or all of the above problems or achieve a part or all of the above effects, the technical features shown in the above embodiments and modifications can be appropriately replaced or combined. In addition, technical features that are not described as essential items in the present disclosure can be appropriately deleted.
Industrial applicability
The imaging device of the present disclosure can be used in various camera systems and sensor systems such as a digital camera, a medical camera, a monitoring camera, a vehicle-mounted camera, a digital single lens reflex camera, and a digital mirror-less interchangeable lens camera.

Claims (19)

1. An imaging device includes:
a plurality of pixels including a 1 st pixel and a 2 nd pixel;
a 1 st circuit including a 1 st wiring part and a 2 nd wiring part, the 1 st wiring part including one or more 1 st voltage lines to which a 1 st voltage is applied, the 2 nd wiring part including one or more 2 nd voltage lines to which a 2 nd voltage different from the 1 st voltage is applied;
a 1 st signal path through which a signal of the 1 st pixel flows; and
a 2 nd signal path through which a signal of the 2 nd pixel flows,
in a plan view, when a region closer to each of the one or more 1 st voltage lines than any of the one or more 2 nd voltage lines is defined as a 1 st region, and a region closer to each of the one or more 2 nd voltage lines than any of the one or more 1 st voltage lines is defined as a 2 nd region,
the 1 st signal path includes a 1 st intersection intersecting the 2 nd signal path and a 1 st extension extending within the 2 nd region,
the 2 nd signal path includes a 2 nd intersection intersecting the 1 st signal path and a 2 nd extension extending in the 1 st region,
in the flow of the signal of the 1 st pixel, the 1 st intersection is located upstream of the 1 st extension,
in the flow of the signal of the 2 nd pixel, the 2 nd intersection is located upstream of the 2 nd extension.
2. The image pickup apparatus as set forth in claim 1,
the 1 st voltage is a power supply voltage,
the 2 nd voltage is a ground voltage.
3. The image pickup apparatus according to claim 1 or 2,
the plurality of pixels form a pixel array having at least one row and a plurality of columns,
the column to which the 1 st pixel in the pixel array belongs and the column to which the 2 nd pixel in the pixel array belongs are adjacent to each other.
4. The image pickup apparatus according to any one of claims 1 to 3,
the one or more 1 st voltage lines, the one or more 2 nd voltage lines, the 1 st extension portion, and the 2 nd extension portion extend parallel to each other in the planar view.
5. The image pickup apparatus according to any one of claims 1 to 4,
the imaging device includes a plurality of wiring layers including a 1 st wiring layer and a 2 nd wiring layer different from the 1 st wiring layer,
the 1 st wiring layer includes the 1 st intersection,
the 2 nd wiring layer includes the 2 nd intersection.
6. The image pickup apparatus according to any one of claims 1 to 5,
under the plane view, the liquid crystal display device is provided with a liquid crystal display panel,
the 1 st signal path further comprises a 1 st connection point and a 2 nd connection point,
the 2 nd signal path further comprises a 3 rd connection point and a 4 th connection point,
in the flow of the signal of the 1 st pixel, the 1 st connection point is located upstream of the 1 st intersection, and the 2 nd connection point is located between the 1 st intersection and the 1 st extension,
in the flow of the signal of the 2 nd pixel, the 3 rd connection point is located upstream of the 2 nd intersection, the 4 th connection point is located between the 2 nd intersection and the 2 nd extension,
the image pickup apparatus is further provided with a selector,
the selector includes:
a 1 st switch connected between the 1 st connection point and the 4 th connection point;
a 2 nd switch connected between the 1 st connection point and the 2 nd connection point;
a 3 rd switch connected between the 3 rd connection point and the 4 th connection point; and
a 4 th switch connected between the 3 rd connection point and the 2 nd connection point.
7. The image pickup apparatus according to any one of claims 1 to 6,
the image pickup apparatus further includes a 2 nd circuit including a 3 rd wiring section and a 4 th wiring section, the 3 rd wiring section including one or more voltage lines, the 4 th wiring section including a plurality of voltage lines,
the one or more voltage lines of the 3 rd wiring part include a 3 rd voltage line,
the plurality of voltage lines of the 4 th wiring part include a 4 th voltage line and a 5 th voltage line adjacent to the 3 rd voltage line,
the 3 rd voltage line is between the 4 th voltage line and the 5 th voltage line,
under the plane view, the liquid crystal display device is provided with a liquid crystal display panel,
wherein pitches of the 4 th voltage line, the 3 rd voltage line, and the 5 th voltage line are different from pitches of the one or more 1 st voltage lines and the one or more 2 nd voltage lines,
when a region between the 3 rd voltage line and the 4 th voltage line is defined as a 1 st pitch region, and a region between the 3 rd voltage line and the 5 th voltage line is defined as a 2 nd pitch region,
the 1 st signal path further includes: a 1 st pitch portion extending within the 1 st pitch region,
the 2 nd signal path further includes: a 2 nd pitch portion extending within the 2 nd pitch region,
in the flow of the signal of the 1 st pixel, the 1 st pitch part is located upstream of the 1 st intersection,
the 2 nd pitch part is located upstream of the 2 nd intersection in the flow of the signal of the 2 nd pixel.
8. The image pickup apparatus according to any one of claims 1 to 7,
the 1 st circuit further includes a 1 st transistor of a 1 st conductivity type and a 2 nd transistor of a 2 nd conductivity type different from the 1 st conductivity type,
the 1 st transistor is connected to any one of the one or more 1 st voltage lines,
the 2 nd transistor is connected to any one of the one or more 2 nd voltage lines.
9. The image pickup apparatus according to any one of claims 1 to 6,
the image pickup device is also provided with a 2 nd circuit,
the 1 st circuit further includes a 1 st transistor of a 1 st conductivity type and a 2 nd transistor of a 2 nd conductivity type different from the 1 st conductivity type,
the 2 nd circuit includes a 3 rd transistor of the 1 st conductivity type and a 4 th transistor of the 2 nd conductivity type,
when the center of gravity of the gate of the 1 st transistor and the gate of the 2 nd transistor is defined as a 1 st center of gravity and the center of gravity of the gate of the 3 rd transistor and the gate of the 4 th transistor is defined as a 2 nd center of gravity, in the plan view,
the arrangement direction of the 1 st transistor and the 2 nd transistor is different from the arrangement direction of the 3 rd transistor and the 4 th transistor,
the 1 st signal path includes a portion closest to the 2 nd center of gravity and a portion closest to the 1 st center of gravity,
the 2 nd signal path includes a portion closest to the 2 nd center of gravity and a portion closest to the 1 st center of gravity,
in the flow of the signal of the 1 st pixel, the portion closest to the 2 nd barycenter is located upstream of the portion closest to the 1 st barycenter,
in the flow of the signal of the 2 nd pixel, the portion closest to the 2 nd barycenter is located upstream of the portion closest to the 1 st barycenter.
10. The image pickup apparatus according to any one of claims 1 to 9,
the plurality of pixels includes a 1 st OB pixel which is an optical black pixel,
the image pickup apparatus further includes a signal processing circuit and a 1OB path through which a signal of the 1OB pixel flows,
in the plan view, the 1 st OB path includes: a 1 st OB extension extending within the 2 nd region,
the signal processing circuit performs optical black correction on the signal of the 1 st pixel via the 1 st extension portion using the signal of the 1 st pixel via the 1 st extension portion.
11. The image pickup apparatus according to any one of claim 1 to claim 9,
the plurality of pixels includes a 3 rd pixel,
the image pickup device further includes a 3 rd signal path through which a signal of the 3 rd pixel flows,
in the plan view, the 3 rd signal path includes: a 3 rd extension extending within the 2 nd region.
12. The image pickup apparatus as set forth in claim 11,
the plurality of pixels includes a 4 th pixel,
the imaging device further includes a 4 th signal path through which a signal of the 4 th pixel flows,
in the plan view, the 4 th signal path includes: a 4 th extension extending within the 1 st region.
13. The image pickup apparatus as set forth in claim 12,
under the plane view, the liquid crystal display device is provided with a liquid crystal display panel,
the 3 rd signal path includes a portion extending from the 3 rd pixel to the 2 nd region,
the 4 th signal path includes a portion extending from the 4 th pixel to the 1 st region,
the portion extending from the 3 rd pixel to the 2 nd region does not intersect the portion extending from the 4 th pixel to the 1 st region.
14. The image pickup apparatus according to any one of claim 11 to claim 13,
the 1 st pixel includes a 1 st color filter,
the 2 nd pixel includes a 2 nd color filter,
the 3 rd pixel includes a 3 rd color filter,
the 1 st color filter and the 3 rd color filter are color filters of a 1 st color,
the 2 nd color filter is a 2 nd color filter different from the 1 st color.
15. The image pickup apparatus according to any one of claim 11 to claim 13,
the 1 st pixel and the 3 rd pixel are 1 st type pixels selected from 4 types of R pixels, B pixels, Gr pixels and Gb pixels,
the 2 nd pixel is a 2 nd pixel selected from 4 of an R pixel, a B pixel, a Gr pixel and a Gb pixel,
the 1 st pixel and the 2 nd pixel are different from each other.
16. The image pickup apparatus according to any one of claim 11 to claim 15,
the image pickup apparatus is further provided with a signal processing circuit,
the signal processing circuit performs correction to reduce a noise component superimposed in the 2 nd region for both a signal of the 1 st pixel via the 1 st extension portion and a signal of the 3 rd pixel via the 3 rd extension portion.
17. The image pickup apparatus according to any one of claims 11 to 15,
the plurality of pixels includes a 1 st OB pixel which is an optical black pixel,
the image pickup apparatus further includes a signal processing circuit and a 1OB path through which a signal of the 1OB pixel flows,
in the plan view, the 1 st OB path includes: a 1 st OB extension extending within the 2 nd region,
the signal processing circuit performs optical black correction on the signal of the 1 st pixel via the 1 st extension portion using the signal of the 1 st pixel via the 1 st extension portion.
18. An imaging system includes:
the image pickup apparatus according to any one of claim 1 to claim 9 and claim 11 to claim 15; and
a signal processing device disposed outside the image pickup device,
the plurality of pixels includes a 1 st OB pixel which is an optical black pixel,
the image pickup apparatus further includes a 1OB path through which a signal of the 1OB pixel flows,
in the plan view, the 1 st OB path includes: a 1 st OB extension extending within the 2 nd region,
the signal processing device performs optical black correction on the signal of the 1 st pixel via the 1 st extension portion using the signal of the 1 st pixel via the 1 st extension portion.
19. An imaging system includes:
the image pickup apparatus of any one of claim 11 to claim 15; and
a signal processing device disposed outside the image pickup device,
the signal processing device performs correction to reduce a noise component superimposed in the 2 nd region for both the signal of the 1 st pixel via the 1 st extension portion and the signal of the 3 rd pixel via the 3 rd extension portion.
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