JP5847870B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device.

  In recent years, solid-state imaging devices mounted on digital still cameras, video cameras, mobile phones, and the like have been actively developed. CCD (Charge Coupled Devices) sensors and CMOS (Complementary Metal Oxide Semiconductor) sensors are widely known as solid-state imaging devices. Compared with a CCD sensor, a CMOS sensor having features such as low power consumption, high-speed reading, and system-on-chip is increasing.

  The CMOS sensor includes an amplifier circuit such as a floating diffusion amplifier for each pixel. A method of reading out pixel signals by selecting one row in the pixel array portion arranged in a matrix in the row direction and the column direction, and simultaneously reading out the pixel signals of all the pixels located in the selected one row Is often used.

  The demand for higher pixels and higher speeds of solid-state imaging devices continues to increase. For example, Patent Document 1 provides high-speed reading by arranging a plurality of vertical output lines in each column and simultaneously reading a plurality of rows. To do.

JP 2005-311821 A

  However, the solid-state imaging device described in Patent Document 1 achieves high speed by arranging a plurality of vertical output lines in each column and simultaneously reading out pixel signals in a plurality of rows. The area of the conversion element is reduced. That is, it is difficult to increase the number of pixels of the solid-state imaging device in order for each pixel to obtain a predetermined aperture ratio.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device that shortens the time for reading out pixel signals of all pixels and improves the aperture ratio of the pixels.

A solid-state imaging device according to the present invention includes a plurality of pixels arranged in a matrix in a plurality of rows and a plurality of columns, each having a photoelectric conversion element and a color filter, a plurality of buffers arranged for each of the plurality of pixels, and the pixels A plurality of vertical output lines arranged in each column, and an input unit of each of the buffers is commonly connected to a plurality of pixels having different colors of the color filter, and an output unit of the plurality of buffers Are alternately connected to a plurality of vertical output lines, and pixel signals of a plurality of pixels of the same color in different rows of the same column are simultaneously read to the plurality of vertical output lines via the plurality of buffers, respectively. And is added .

  It is possible to shorten the readout time of the pixel signals of all pixels and improve the aperture ratio of the pixels.

It is the schematic which shows the structural example of the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is a figure which shows the drive method of the solid-state imaging device of the pixel structure of FIG. It is the figure which showed the pixel signal output to the vertical output line of each column in time sequence. It is the figure which showed the transition of the exposure period of the pixel of each line in FIG. It is a figure which shows the drive method of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. It is the figure which showed the pixel signal output to the vertical output line of each column in time sequence. It is the figure which showed the transition of the exposure period of the pixel of each line in FIG. 6 and FIG. It is a figure which shows the reading method of the solid-state imaging device which concerns on the 3rd Embodiment of this invention. It is the figure which showed the pixel signal input into a column read-out circuit in order of time. It is the figure which showed the cross-section of the pixel of a solid-state imaging device.

(First embodiment)
FIG. 1 is a schematic diagram illustrating a pixel layout configuration of the solid-state imaging device according to the first embodiment of the present invention, in which two adjacent columns are arranged in a pixel array unit including a plurality of rows and a plurality of columns. It is a figure which extracted and showed the pixel for 8 rows located in the 2 columns. In the pixel layout configuration of FIG. 1, the solid-state imaging device includes a pixel 3, a buffer 2 connected in common to two pixels adjacent in the row direction, and two vertical output lines 1 for each column. The two vertical output lines 1 are alternately connected to the buffer 2 in the row direction. The vertical output line 1 has vertical output lines x10, y11, x12, and y13.

  The solid-state imaging device includes a pixel array unit in which pixels 3 having photoelectric conversion elements 80, color filters 82, and a plurality of transistors shown in FIGS. 10A and 10B are arranged in a matrix in a plurality of rows and a plurality of columns. Have The solid-state imaging device includes a buffer 2 arranged for each of the plurality of pixels 3 and a plurality of vertical output lines 1 arranged for each column. The input portion of the buffer 2 is connected in common to the plurality of pixels 3, and the vertical output lines 1 are alternately connected to the output portions of the plurality of buffers 2 in the row direction.

  FIG. 2 is a diagram illustrating a pixel signal reading method when the pixel configuration of the layout of FIG. 1 is applied to a Bayer array solid-state imaging device. FIG. 2 shows two adjacent columns in the pixel array section, and is a diagram in which pixels located in the two columns are extracted from the 0th row to the 7th row. The two adjacent columns are m and m + 1, and the two vertical output lines for each column are a vertical output line x and a vertical output line y, respectively. In FIG. 2, the pixel of the red color filter is indicated by, for example, R1, the pixel of the green color filter is indicated by, for example, G11, and the pixel of the blue color filter is indicated by, for example, B1.

  In FIG. 2, first, signals of pixels located in the 0th and 2nd rows are read out. The pixel signal is output to the vertical output line via different buffers 2. At this time, the pixel signal of the pixel R1 is output to the m-th column vertical output line x10, the pixel signal of the pixel R2 is output to the m-th column vertical output line y11, and the pixel G12 is output to the m + 1-th column vertical output line x12. The pixel signal of the pixel G22 is output to the vertical output line y13 of the (m + 1) th column.

  Next, the signals of the pixels located in the first and third rows are read out. At this time, the pixel signal of the pixel G11 is output to the m-th column vertical output line x10, the pixel signal of the pixel G21 is output to the m-th column vertical output line y11, and the pixel B1 is output to the m + 1-th column vertical output line x12. The pixel signal is output to the vertical output line y13 of the (m + 1) th column, and the pixel signal of the pixel B2 is output.

  Next, the signals of the pixels located in the fourth and sixth rows are read out. At this time, the pixel signal of the pixel R3 is output to the m-th column vertical output line x10, the pixel signal of the pixel R4 is output to the m-th column vertical output line y11, and the pixel G32 is output to the m + 1-th column vertical output line x12. The pixel signal is output from the pixel G42 to the (m + 1) th column vertical output line y13.

  Next, the signals of the pixels located in the fifth and seventh rows are read out. At this time, the pixel signal of the pixel G31 is output to the m-th column vertical output line x10, the pixel signal of the pixel G41 is output to the m-th column vertical output line y11, and the pixel B3 is output to the m + 1-th column vertical output line x12. The pixel signal is output from the pixel B4 to the vertical output line y13 in the (m + 1) th column.

  FIG. 3 is a table summarizing the output relationship of the pixel signals with respect to the readout row, and is a table showing which pixel signals are output to the respective vertical output lines for the readout row. As described above, in this embodiment, pixel data of pixels located in every other row are simultaneously read out to different vertical output lines via different buffers 2, and the readout rows are sequentially shifted to the last of the pixel array unit. Read to line.

  FIG. 4 is a diagram illustrating a transition of exposure periods of pixels located in each row from the 0th row to the 7th row according to the present embodiment. The pixels in the eighth and subsequent rows are omitted.

  As described above, by using two vertical output lines, two rows can be read simultaneously, and the time for reading out data of all pixels is halved compared to the case where there is one vertical output line. . Further, by making the buffer 2 common to two pixels in the row direction, a higher aperture ratio can be expected compared with the case where the buffer 2 is provided for each pixel, and a higher pixel can be expected. Also, as shown in FIG. 3, since the signals output simultaneously to the two vertical output lines x and y for each column are the same color closest to the row direction, vertical pixel addition of the same color is easy.

  In FIG. 2, a row selection line for selecting a pixel readout row and a column readout circuit connected to the vertical output lines x and y of each column are omitted.

(Second Embodiment)
FIG. 5 is a diagram illustrating a readout method of the solid-state imaging device according to the second embodiment of the present invention, and illustrates another readout method of the solid-state imaging device having the pixel configuration in the Bayer array as in the first embodiment. In this embodiment, the 0th row of the pixel array unit is not read, but first, signals of pixels located in the 1st and 2nd rows are read. The signals of the pixels located in the first and second rows are output to the vertical output line via different buffers 2. At this time, the pixel signal of the pixel G11 is output to the m-th column vertical output line x10, the pixel signal of the pixel R2 is output to the m-th column vertical output line y11, and the pixel B1 is output to the m + 1-th column vertical output line x12. The pixel signal of the pixel G22 is output to the vertical output line y13 of the (m + 1) th column.

  Next, signals of pixels located in the third and fourth rows are read out. At this time, the pixel signal of the pixel R3 is output to the m-th column vertical output line x10, the pixel signal of the pixel G21 is output to the m-th column vertical output line y11, and the pixel G32 is output to the m + 1-th column vertical output line x12. The pixel signal is output to the vertical output line y13 of the (m + 1) th column, and the pixel signal of the pixel B2 is output.

  Next, the signals of the pixels located in the fifth and sixth rows are read out. At this time, the pixel signal of the pixel G31 is output to the m-th column vertical output line x10, the pixel signal of the pixel R4 is output to the m-th column vertical output line y11, and the pixel B3 is output to the m + 1-th column vertical output line x12. The pixel signal is output from the pixel G42 to the (m + 1) th column vertical output line y13.

  FIG. 6 is a table summarizing the output relationship of the pixel signals with respect to the readout row, and is a table showing which pixel signal is output to each vertical output line for the readout row. Note that the output of the signals of pixels located in the seventh and subsequent rows is omitted.

  Thus, in the present embodiment, the first set of pixel signals of pixels located in two rows adjacent in the row direction and having different buffers 2 are simultaneously read out to different vertical output lines via different buffers 2. The pixel signals of the second set of pixels in which the buffer 2 is located in two common rows are read out to the same vertical output line via the same buffer 2 at different timings. Two rows of readout rows are sequentially shifted to read out pixel signals for all pixels. Since two rows adjacent in the row direction are selected, the exposure period of the pixels located in each row is as shown in FIG.

  By using this embodiment, in addition to shortening the readout period and increasing the number of pixels, the exposure period can be changed in the row order as shown in FIG. Furthermore, the four pixels constituting the Bayer array can be read out simultaneously. Therefore, control of the imaging device and image processing are facilitated. In the present embodiment, the reading method in which the signal of the pixel located in the 0th row is not read is shown, but the present invention is not limited to this. First, only the signal of the pixel located in the 0th row may be read out.

  In FIG. 5, a row selection line for selecting a pixel readout row and a column readout circuit connected to the vertical output lines x and y of each column are omitted.

(Third embodiment)
8A and 8B are diagrams illustrating a readout method of the solid-state imaging device according to the third embodiment of the present invention. 8A and 8B are diagrams illustrating a configuration example having a changeover switch for each column. FIG. 8A is a diagram showing the connection between the column readout circuit and the vertical output line when reading odd numbers, and FIG. 8B shows the connection between the column readout circuit and the vertical output line when reading even numbers. FIG. The description of the same parts and operations as those in FIG. 5 is omitted.

  8A and 8B, column readout circuits for each column are designated as column readout circuits x and y. The switching element 64 is arranged between the column readout circuits x60, y61, x62, y63 of the m-th column and the (m + 1) -th column and the vertical output lines x10, y11, x12, y13 of the m-th column and the (m + 1) -th column. ing. For example, the column readout circuit x60 is selectively connected to one of the m-th column vertical output lines x10 and y11.

  The read operation is as follows. First, signals of pixels located in the first and second rows are read out. At this time, the column readout circuit x60 of the mth column is connected to the vertical output line y11 of the mth column via the switching element 64, and the column readout circuit y61 of the mth column is connected to the vertical output line x10 of the mth column. Connected through. The column read circuit x62 of the (m + 1) th column is connected to the vertical output line y13 of the (m + 1) th column via the switching element 64, and the column read circuit y63 of the (m + 1) th column via the switching element 64 is connected to the vertical output line x12 of the (m + 1) th column. Connected. The connection relationship between the vertical output lines x10, y11, x12, and y13 of each column and the column readout circuits x60, y61, x62, and y63 is as shown in FIG.

  Next, signals of pixels located in the third and fourth rows are read out. At this time, the column readout circuit x60 of the mth column is connected to the vertical output line x10 via the switching element 64, and the column readout circuit y61 of the mth column is connected to the vertical output line y11 of the mth column via the switching element 64. Is done. The column readout circuit x62 of the (m + 1) th column is connected to the vertical output line x12 via the switching element 64, and the column readout circuit y63 of the (m + 1) th column is connected to the vertical output line y13 via the switching element 64. The connection relationship between the vertical output lines x10, y11, x12, and y13 of each column and the column readout circuits x60, y61, x62, and y63 is as shown in FIG.

  Next, the signals of the pixels located in the fifth and sixth rows are read out. At this time, the column readout circuit x60 of the mth column is connected to the vertical output line y11 via the switching element 64, and the column readout circuit y61 of the mth column is connected to the vertical output line x10 of the mth column via the switching element 64. Is done. The column readout circuit x62 of the (m + 1) th column is connected to the vertical output line y13 via the switching element 64, and the column readout circuit y63 of the (m + 1) th column is connected to the vertical output line x12 via the switching element 64. The connection relationship between the vertical output lines x10, y11, x12, and y13 of each column and the column readout circuits x60, y61, x62, and y63 is as shown in FIG.

  As described above, the pixel signal readout method of this embodiment selects two rows that are adjacent to each other in the row direction and have different two-pixel shared buffers 2, and outputs signals of pixels located in the selected row. read out. Further, the connection of the vertical output lines x10, y11, x12, y13 and the column readout circuits x60, y61, x62, y63 in each column is switched between when the order of reading by the switching element 64 is odd and even. That is, each time a row from which a pixel signal is read transitions, the connection relationship between the vertical output line and the column readout circuit for each column alternately repeats the connection relationship in FIG. 8A and the connection relationship in FIG. 8B. The exposure period of the pixels located in each row is as shown in FIG. 7 as in the second embodiment because signals of pixels located in two rows adjacent in the row direction are read out simultaneously.

  FIG. 9 is a table summarizing the output relationship of the pixel signals with respect to the readout row, and is a table showing which pixel signal is input to each column readout circuit for the readout row. Note that the output of the signals of pixels located in the seventh and subsequent rows is omitted.

  When this embodiment is applied, the period for reading out the signals of all the pixels can be shortened, and the configuration can easily be adapted to increase in the number of pixels. Furthermore, the signals of the four pixels constituting the Bayer array can be read out simultaneously, and the exposure period located in each row can also be changed in the row order. As shown in FIG. 9, since the pixel signals having the same color filter are input to the column readout circuits, vertical pixel addition of the same color pixel signals is facilitated.

  In the example of FIG. 8, the column readout circuits x60, y61, x62, y63 and the switching element 64 are separated from the pixel region in the upper and lower directions, but the present invention is not limited to this. For example, the column readout circuits x60, y61, x62, y63 and the switching element 64 may be arranged only on the lower side. In FIG. 8, a row selection line for selecting a pixel readout row is omitted.

  In each of the above embodiments, the vertical output lines are arranged on both sides of the corresponding column, but the present invention is not limited to this. A configuration may be employed in which a plurality of vertical output lines corresponding to one side of the column are arranged. For example, the m-th column vertical output line x10 and the vertical output line y11 may both be arranged on the left side of the pixel.

  In each of the embodiments described above, the readout method is such that the readout rows are sequentially shifted from the first row to the last row of the pixel array unit, but the present invention is not limited to this. For example, a method of selecting and reading out only necessary rows may be used.

  In each of the above embodiments, the pixel layout configuration in which two vertical output lines are arranged for each column has been described, but the present invention is not limited to this. For example, the number of vertical output lines for each column may be three, or four or more. The number of column readout circuits for each column is preferably equal to the number of vertical output lines.

  In each of the embodiments described above, one shared buffer is provided for every two pixels, but the present invention is not limited to this. For example, one shared buffer may be used for every four pixels, or the buffer may be shared with a larger number of pixels.

  In each of the embodiments described above, the position of the shared buffer is arranged at the same position in the row direction regardless of the column, but the present invention is not limited to this. For example, the position in the row direction of the shared buffer may be changed for each column.

  In each of the above embodiments, the pixels connected to the shared buffer are pixels adjacent in the row direction, but the present invention is not limited to this. For example, the buffer may be shared by a total of four pixels, two pixels adjacent in the row direction and two pixels adjacent in the column direction.

  FIG. 10A is a diagram illustrating a cross-sectional structure of a pixel of a front-illuminated solid-state imaging device, and FIG. 10B is a diagram illustrating a cross-sectional structure of a pixel of the back-illuminated solid-state imaging device. 10A and 10B includes a photoelectric conversion element 80 formed on the substrate 83, a circuit formed on the surface of the substrate 83, and a wiring layer 81. In the surface irradiation type solid-state imaging device of FIG. 10A, the color filter 82 is formed on the upper surface of the circuit and wiring layer 81 on the substrate surface side and receives light from the substrate surface side. 10B, the color filter 82 is formed on the back surface of the substrate 83 and receives light from the back surface side of the substrate.

  In the front-illuminated solid-state imaging device shown in FIG. 10A and the back-illuminated solid-state imaging device shown in FIG. 10B, if the first to third embodiments are applied, a buffer connected to the pixel is provided. Since it can be shared with a plurality of pixels, the area of the pixel circuit can be reduced. Therefore, the first to third embodiments can be applied to both the front-illuminated solid-state imaging device and the back-illuminated solid-state imaging device.

  According to the solid-state imaging devices of the first to third embodiments, it is possible to shorten the readout time of pixel signals of all pixels and improve the aperture ratio of the pixels.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

1 Vertical output line, 2 buffers, 3 pixels

Claims (4)

A plurality of pixels arranged in a matrix in a plurality of rows and columns, and having photoelectric conversion elements and color filters;
A plurality of buffers arranged for each of a plurality of pixels;
And a plurality of vertical output lines are more arranged in each column of the pixels,
The input unit of each of the buffers is commonly connected to a plurality of pixels having different colors of the color filter,
The output portions of the plurality of buffers are alternately connected to a plurality of vertical output lines ,
Solid-state imaging , wherein pixel signals of a plurality of pixels of the same color in different rows of the same column are simultaneously read and added to the plurality of vertical output lines via the plurality of buffers, respectively. apparatus. A first set of signals of pixels adjacent in the row direction is simultaneously output to a plurality of vertical output lines via different buffers.
2. The solid-state imaging device according to claim 1, wherein signals of the second set of pixels adjacent in the row direction are output to the same vertical output line through the same buffer at different timings. The color filter of the plurality of pixels, the solid-state imaging device according to claim 1 or 2, characterized in that it is a Bayer array. The solid-state imaging device according to any one of claims 1 to 3, characterized in that a back-illuminated.

Images