JP2007258916A - Solid-state imaging element and drive method thereof, manufacturing method of solid-state imaging element, and electronic information apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element and a drive method thereof capable of easily revising the number of summated pixels in the horizontal direction and achieving a high speed frame rate at imaging of a moving picture. <P>SOLUTION: A summation section 20 being a gate region comprising m×j rows is provided to a vertical transmission section 10 toward a side of a horizontal transfer section and x sets of first transfer gate groups 21 and (j-(x-1)) sets of second transfer gate groups 22 each comprising m rows and K columns are alternately arranged in the horizontal direction to rows at the side of the horizontal transfer section from (x-1)×(m+1)th row to (x×m)th row (x is a natural number from 1 to j) relative to a pixel period K of light receiving section pixels in the horizontal direction. In the case of a summation drive mode, a first operating period wherein signal electric charges of both the transfer gate groups are vertically transferred and a second operating period wherein signal electric charges of only the second transfer gate groups are vertically transferred are combined. Since the transfer period is shorter for columns including many of the second transfer gate groups and the transfer period is longer for columns including many of the first transfer gate groups, the signal electric charges earlier transferred to the horizontal transfer section are horizontally transferred by the horizontal transfer section and the horizontal transfer section can summate the electric charges to transferred signal electric charges later. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device that speeds up signal processing by adding pixel signals read by selecting all pixels, a method for driving the solid-state imaging device, a method for manufacturing the solid-state imaging device, and imaging the solid-state imaging device The present invention relates to an electronic information device such as a digital camera having a moving image shooting mode function used in the section.

  Conventionally, a solid-state imaging device such as a CCD area sensor has a plurality of light receiving portions such as photodiodes arranged in a matrix (matrix shape), and an amount of signal charge corresponding to the amount of incident light incident from a subject is received. It is generated by photoelectric conversion. The signal charges read from each light receiving unit pixel are transferred in the column direction (vertical direction) by the vertical transfer unit made of CCD, and further transferred in the row direction (horizontal direction) by the horizontal transfer unit made of CCD to be predetermined. Are output in the horizontal period period and detected as image information.

  As a digital still camera using such a solid-state imaging device is increased in pixel count, various techniques have been proposed in order to achieve higher performance in a moving image shooting mode as an additional function. Among them, the problem of securing the frame rate at the time of moving image shooting is an important issue, and the following three types of first to third techniques are adopted for this issue.

  The first technique is a method of reading out information (signal charge) of an arbitrary pixel among pixels constituting the entire screen. In this method, by thinning out pixels, the number of pixels that are finally subjected to signal processing can be reduced, and one screen can be processed at high speed. However, since the first technique includes a problem that the resolution is deteriorated and a false color signal is generated, in most cases, the first technique is employed only as a driving mode for viewing angle monitoring.

  The second technique is a method of dividing the screen of the solid-state imaging device into arbitrary regions and reading out pixels in each region in parallel. In this method, high-speed processing can be realized by performing signal processing in parallel with a plurality of output circuits. However, the second technique has a problem in that the image quality becomes discontinuous at the boundary portion of the readout region due to the difference in the characteristics of the output circuit.

  The third technique is a method of compressing and reading information between arbitrary adjacent pixels. In this method, pixel signals that are close to each other according to a rule are added to reduce the number of readout signals, thereby realizing high-speed processing. However, this third technique has the demerits that the driving of the solid-state imaging device becomes complicated and the number of gate terminals increases.

  Of these first to third technologies, the most effective means at present is the third technology. A conventional solid-state imaging device driving method using the third technique will be described in detail below with reference to FIGS. 20 (a) to 20 (d).

  FIG. 20A is a diagram illustrating an example of the arrangement of each pixel in a conventional solid-state imaging device, and FIGS. 20B to 20D are screens on which RGB pixels shown in FIG. FIG. 5 is a diagram illustrating a combination example of addition pixels in a case where signals of two pixels are added in the horizontal direction, a signal of three pixels is added in the horizontal direction, and a signal of four pixels is added in the horizontal direction.

  As shown in the Bayer array in FIG. 20A, a row in which R pixels and G pixels are alternately arranged in the horizontal direction and a row in which G pixels and B pixels are alternately arranged in the horizontal direction are in the vertical direction. They are lined up alternately.

  20B to 20D, four pixels from the 4 × 4 region, 4 × 6 region, and 4 × 8 region are displayed on the screen in which RGB pixels are arranged as shown in FIG. 20A. An example of combination of added pixels is shown for the case where signals are added and output.

  As shown in FIG. 20B, in the lower right 4 × 4 region, the signals of the four R (red) pixels in the first row and the third row from the bottom are added to output 1 (“1” is R pixel position is shown). In addition, the signals of the four G pixels included in the first and third rows from the bottom where R pixels and G (green) pixels are alternately arranged in the horizontal direction are added to output 2 (“2” is G The pixel position is indicated), and the signals of the four G pixels included in the second and fourth rows from the bottom where the G pixel and the B pixel are alternately arranged in the horizontal direction are added and output 3 ( "3" indicates the G pixel position). Further, the signals of the four B (blue) pixels in the second and fourth rows from the bottom are added and output as output 4 (“4” indicates the pixel position of B). In this way, two horizontal pixels are added to a total of four pixels (two horizontal pixels and two vertical pixels are added) and read out as one pixel to the horizontal transfer unit, so the number of read signals can be reduced. And high-speed processing can be realized. The added value in this case remains the added value of 4 pixels, which is four times the value of a normal pixel. Compared with the thinning-out addition of the first technique, pixel information is not discarded, and high-speed processing is possible while obtaining a high resolution. In particular, the effect is remarkable in the case of a moving image.

  Next, FIG. 20C and FIG. 20D show the case where the compression rate is increased by using both 4-pixel addition and thinning-out addition.

  As shown in FIG. 20C, the signals of the four R pixels in the first and third rows from the bottom in the lower right 6 × 4 region are added and output as output 1. Also, the signals of the four G pixels in the first and third rows from the bottom are added and output as output 2, and the four G pixels in the fourth and sixth rows from the bottom are added and output as output 3 Has been. Further, four B pixels in the fourth and sixth rows from the bottom are added and output as output 4.

  As shown in FIG. 20D, four R pixels in the first row and the third row from the bottom in the lower right 8 × 4 region are added and output as output 1. Also, the four G pixels in the first and third rows from the bottom are added and output as output 2, and the four G pixels in the sixth and eighth rows from the bottom are added and output as output 3. Yes. Further, the four B pixels in the sixth and eighth rows from the bottom are added and output as output 4.

  21A and 21B show a driving procedure for adding 4 pixels from a 4 × 4 area. Hereinafter, FIG. 21 (i) to FIG. 21 (vii), which are added to one place for each color while being sequentially shifted, will be described in detail step by step.

  As shown in FIG. 21 (i), signals are read so that the added pixels are adjacent in the vertical direction. Alternatively, the signals are rearranged from the initial state of FIG. For example, in FIG. 21 (0), the first line is R11, G12, R13, G14 from the right, the second line is G21, B22, G23, B24 from the right, and the third line is R31, G32, R33, G34, 4 from the right. The rows are arranged in the order of G41, B42, G43, and B44 from the right, whereas in FIG. 21 (i), the row holding the signal charge with S (storage) is the first row. The second row is rearranged from the right to R11 and R31, G12 and G32, R13 and R33, G14 and G34, and the first and second rows are rearranged from the right to G21 and G41, B22 and B42, G23 and G43, B24 and B44, Pixels to be added are adjacent in the vertical direction.

  In FIG. 21 (ii), the third, fourth, seventh, eighth, ninth, eleventh and twelfth columns are selectively read out to the horizontal transfer unit (HCCD). Thereby, for example, R13 and R33 in the third column and G14 and G34 in the fourth column are read out to the horizontal transfer unit.

  In FIG. 21 (iii), the signals read out to the horizontal transfer unit are transferred in two rows in the horizontal direction. Thus, for example, R13 and R33 in the third column and G14 and G34 in the fourth column are transferred corresponding to the first and second columns, respectively.

  In FIG. 21 (iv), signals are transferred in the vertical direction, and the first, second, fifth, sixth, ninth, and tenth columns are read out to the horizontal transfer unit. Thereby, for example, R11 and R31 in the first column and G12 and G32 in the second column are read out to the horizontal transfer unit. R is added with signals of four pixels R13, R33, R11 and R31, and G is added with signals of four pixels G14, G34, G12 and G32.

  In FIG. 21 (v), the third column, the third column, the fourth column, the seventh column, the eighth column, the ninth column, the eleventh column, and the twelfth column are selectively read out to the horizontal transfer unit. Accordingly, for example, G23 and G43 in the third column and B24 and B44 in the fourth column are read out to the horizontal transfer unit.

  In FIG. 21 (vi), the signals read out to the horizontal transfer unit are transferred in two rows in the horizontal direction. Thus, for example, the third column G23 and G43 are transferred to the first column, and the fourth column B24 and B44 are transferred to the second column.

  In FIG. 21 (vii), signals are transferred in the vertical direction, and the first, second, fifth, sixth, ninth, and tenth columns are read out to the horizontal transfer unit. Thereby, for example, G21 and G41 in the first column and B22 and B42 in the second column are read out to the horizontal transfer unit. G is added with signals of four pixels G23, G43, G21 and G41, and B is added with signals of four pixels B24, B44, B22 and B42.

  By performing the above operation, signal charges of 4 pixels are added from the 4 × 4 region and read as one pixel, and high-speed processing is performed.

  When adding 4 pixel signals from the 4 × 4 region, 4 × 6 region, and 4 × 8 region, the signals of 4 pixels adjacent to each other in the horizontal direction are added. In this way, in order to realize the operations of FIG. 21 (i) to FIG. 21 (vii) in which the position of the signal charge is added and read out for each color while sequentially shifting the position of the signal charge, FIG. 22 shows an example of a gate configuration in which the signal charge is read out at the same time while the signal charge is read out differently with the smaller one.

  FIG. 22 is a diagram for explaining an example of the gate configuration of the vertical transfer unit and the addition unit in the case of adding signals of two adjacent pixels in each horizontal direction. Note that the adding unit 40 in FIG. 22 corresponds to S (storage) in FIG.

  In FIG. 22, the conventional solid-state imaging device is provided with an adder 40 for adding pixel signals on the horizontal transfer unit side (lower side in FIG. 22) with respect to the vertical transfer unit (normal transfer unit) 10. ing. The vertical transfer unit 10 includes a plurality of n rows of transfer gates connected in the column direction (vertical direction), and signal charges read from each light receiving unit (each pixel) (not shown) are transferred in the vertical direction. Is done. In the adder 40, vertical transfer portions 41 in which eight rows of transfer gates A1 to A8 are arranged in two columns and vertical transfer portions 42 in which four rows of transfer gates B1 to B4 are arranged in two rows are alternately arranged in the horizontal direction. Has been.

  In this conventional solid-state imaging device, since the number of transfers differs between the vertical transfer portion 41 and the vertical transfer portion 42, the transfer time to the horizontal transfer portion is different. For example, the vertical transfer portion 42 has a higher transfer speed than the vertical transfer portion 41, and the signal charge transferred to the horizontal transfer portion through the four rows of transfer gates B1 to B4 is horizontal to the bottom of the transfer gates A1 to A8. The signal charges transferred in the horizontal direction by the transfer unit and passed through the transfer gates A1 to A8 correspond to the signal charges passed from the transfer gates B1 to B4 through the horizontal transfer unit, and 1 for each color in the horizontal transfer unit. It is added as a pixel.

Examples of actually adopting the third technique in the interline CCD are disclosed in Patent Document 1 and Patent Document 2, for example.
Japanese Patent Laid-Open No. 11-54741 JP 2000-115643 A

  As described above, in the CCD area sensor, as the number of pixels increases, it takes time to read out signals from a larger number of pixels, and the frame rate decreases.

  As a method for increasing the frame rate by speeding up the signal charge reading process, if the above-described third technique is employed, for example, a horizontal signal in which pixel signals for two columns in the horizontal direction are added and mixed into a pixel packet for one column. By adding two pixels, the number of vertical lines that can be transferred in one horizontal period is twice that of the prior art.

  In order to cope with further increase in the pixel area of the CCD area sensor, a driving method in which the compression rate of the added pixel is further increased is required. For example, as horizontal three-pixel addition driving, according to horizontal three-pixel addition driving in which pixel signals for three columns in the horizontal direction are added and mixed into pixel packets for one column, the number of vertical lines that can be transferred in one horizontal period is conventionally 3 times. Further, according to the horizontal four-pixel addition driving in which pixel signals for four columns in the horizontal direction are added and mixed to pixel packets for one column, the number of vertical lines that can be transferred in one horizontal period is four times that of the conventional case.

  However, in order to change the number of pixels added in the horizontal direction, many circuit design changes, drive terminal changes, drive timing changes, and the like are required, which is very difficult.

  The present invention solves the above-described conventional problems, the number of pixels added in the horizontal direction can be changed more easily, and a solid-state imaging device capable of easily realizing a high frame rate during moving image imaging, and a driving method thereof, An object of the present invention is to provide a manufacturing method of the solid-state imaging device and an electronic information device such as a digital camera having a moving image shooting mode function using the solid-state imaging device.

  In the solid-state imaging device according to the present invention, a plurality of light receiving portions that generate signal charges corresponding to the amount of incident light by photoelectric conversion are arranged in a matrix with a pixel period in the row direction as K (K is a natural number). A solid-state imaging device having a column direction transfer unit that transfers signal charges read from the column direction in the column direction, and a row direction transfer unit that outputs the signal charges transferred by the column direction transfer unit at a predetermined period , Between the column direction transfer unit and the row direction transfer unit, a plurality of first transfer gate groups of m (m is a natural number) rows and K columns, and charge transfer is faster than the first transfer gate group. M × j (j is a natural number) rows of gate areas having a plurality of second transfer gate groups of m rows and K columns set as described above, and the gate regions are arranged on the row direction transfer section side. (X−1) × m + 1 line to x × m line (from x = 1 to j) Number x) of the first transfer gate group and j- (x-1) set of the second transfer gate group are alternately arranged in the row direction. Yes, and the above purpose is achieved.

  Preferably, in the solid-state imaging device of the present invention, j = (A−1) is set when adding signal charges of A pixels (A is a natural number) adjacent in the row direction.

  Further preferably, in the solid-state imaging device of the present invention, at least one set of m rows of third transfer gate groups is provided adjacent to each other in the column direction between the gate region and the column direction transfer unit.

  Further preferably, in the solid-state imaging device of the present invention, when adding the signal charges of the A pixel adjacent in the row direction, j = (A−1) is set, and the third transfer gate group is i (i is a natural number greater than or equal to A)-(A-1)) set, adjacent to each other in the column direction.

  Further preferably, in the solid-state imaging device of the present invention, at least one gate electrode among the gate electrodes constituting the third transfer gate group is connected to one of the gate electrodes constituting the column-direction transfer unit. ing.

  Further preferably, the gate region in the solid-state imaging device of the present invention is arranged with charge transfer columns having different combinations of the number of the first transfer gate groups and the number of the second transfer gate groups for each K columns. ing.

  Further preferably, in the solid-state imaging device of the present invention, the charge transfer speed by the second transfer gate group is set to be the first transfer gate so that the row-direction transfer unit performs a plurality of pixel addition processing as one pixel for each color. It is set faster than the charge transfer speed by the transfer gate group.

  Further preferably, the second transfer gate group in the solid-state imaging device of the present invention can apply a gate drive voltage independent of the first transfer gate group to any gate electrode in at least one row. ing.

  Further preferably, in the solid-state imaging device of the present invention, a first operation period in which both the first transfer gate group and the second transfer gate group are operated, and only the second transfer gate group is operated. Signal charge transfer control is performed in combination with the second operation period.

  Further preferably, in the solid-state imaging device of the present invention, the number of pixels added in the row direction can be changed by changing the layout of the gate electrode layers of the first transfer gate group and the second transfer gate group. It is configured.

  Further preferably, in the solid-state imaging device of the present invention, the layout of the gate electrode layers of the third transfer gate group, the first transfer gate group, and the second transfer gate group is changed to change the row direction. The number of added pixels can be changed.

  Further preferably, in the solid-state imaging device of the present invention, a plurality of gates applied to the column-direction transfer unit are provided on each gate electrode constituting each of the first transfer gate group and the second transfer gate group. Each predetermined pulse is assigned from the drive pulse.

  Further preferably, in the solid-state imaging device of the present invention, each predetermined pulse from a plurality of gate drive pulses applied to the column direction transfer unit is assigned to each gate electrode constituting the third transfer gate group. The predetermined pulses are sequentially assigned to the gate electrodes constituting the first transfer gate group and the second transfer gate group, respectively.

  An electronic information device according to the present invention uses the solid-state imaging device according to the present invention as an imaging unit, and thereby achieves the above object.

  The solid-state imaging device driving method according to the present invention is a solid-state imaging device driving method for driving the solid-state imaging device according to the present invention, in which signal charges are transmitted in the first transfer gate group and the second transfer gate group. At the same time, a first operation period in which a first operation pulse is applied in order to transfer charges in at least m rows in the column direction, and signal charges are transferred in at least m rows in the column direction only in the second transfer gate group. In order to achieve this, the row direction multi-pixel addition processing is performed in the row direction transfer unit using the second operation period in which the second operation pulse is applied, whereby the above object is achieved.

  The solid-state imaging device manufacturing method of the present invention is a manufacturing method of a solid-state imaging device for manufacturing the above-described solid-state imaging device of the present invention. As a gate electrode forming step, the first layer in the row direction is formed on the element substrate. Forming each gate electrode layer of the third transfer gate group and at least each of the common gate electrode layers of the first and second transfer gate groups side by side in the column direction; As the second layer in the row direction, at least each of the gate electrode layers of the third transfer gate group and each of the gate electrode layers of the first transfer gate group are arranged in the column direction. And a step of forming the gate electrode layers of the second transfer gate group side by side in the column direction as a third layer in the row direction, thereby achieving the above object.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, m × j rows of gate regions (adders) are provided between the column direction transfer unit (vertical transfer unit) and the row direction transfer unit (horizontal transfer unit). The pixel period K in the row direction (horizontal direction) of each light receiving unit in an area corresponding to the region between the (x−1) × m + 1th row and the x × mth row (natural number from x = 1 to j) X sets of a plurality of first transfer gate groups each consisting of m rows and K columns, and a j- (x-1) set of second transfer gate groups in which the charge transfer rate is set faster than this. They are arranged alternately in the horizontal direction. As a result, in the gate region composed of m × j rows, the number of first transfer gate groups and the number of second transfer gate groups are different for each K column.

  When the signal charges of the A pixels (A is an integer) that are adjacent in the horizontal direction are added and output to the horizontal transfer unit, a gate region of m × (A−1) rows is provided. For example, when two pixels are added in the horizontal direction, a gate region of m rows × 1 row (j = 1; one gate region of m rows) is provided, and the first transfer gate group and the second transfer gate group are provided. Transfer gate groups are provided alternately. In addition, when adding three pixels in the horizontal direction, a gate region of m × 2 rows (j = 2; two gate regions of m rows) is provided, and the first row to the m-th row are the first ones. One set of transfer gate groups and three sets of second transfer gate groups are alternately provided. In the (m + 1) th to 2 × mth rows, two sets of the first transfer gate group and the second transfer gate group Two sets are provided alternately. Further, when adding four pixels in the horizontal direction, a gate region of m × 3 rows (j = 3; three gate regions of m rows) is provided, and the first row to the m-th row are the first ones. One set of transfer gate groups and three sets of second transfer gate groups are alternately provided. In the (m + 1) th to 2 × mth rows, two sets of the first transfer gate group and the second transfer gate group Two sets are alternately provided, and from the 2 × m + 1 row to the 3 × m row, three sets of the first transfer gate group and one set of the second transfer gate group are alternately provided.

  The first transfer gate group and the second transfer gate group can apply a gate drive voltage to any gate in at least one row independently of each other, and vertically transfer the signal charges of both transfer gate groups. A first operation period and a second operation period in which signal charges of only the second transfer gate group are vertically transferred are provided. Accordingly, the transfer period to the horizontal transfer unit is shortened in a column having a large number of second transfer gate groups, and the transfer time to the horizontal transfer unit is increased in a column having a large number of first transfer gate groups. Therefore, the signal charge transferred to the horizontal transfer unit first is horizontally transferred by the horizontal transfer unit, and the signal charge transferred later to the horizontal transfer unit is added to the same color in the horizontal direction. It is possible to add the signal charges of each pixel.

  Each of the first transfer gate group and the second transfer gate group has m rows and K columns, and the number of pixels to be added in the horizontal direction can be simply changed simply by changing the transfer gate wiring or changing the drive timing. Can be changed more easily.

  Further, it is possible to provide at least one set of the third transfer gate group consisting of m rows as a connection portion adjacent to the gate region consisting of the m × j rows in the column direction. In this case, even if the number of pixels added in the horizontal direction changes and the number of sets in the column direction between the first transfer gate group and the second transfer gate group changes, the third transfer gate group The number of sets can be changed so as to cancel out the increase and decrease. If the gates constituting the third transfer gate group are connected to the gates constituting the vertical transfer unit, and the drive signals of the vertical transfer unit are used for the first to third transfer gate groups, the types of drive signals increase. There is no.

  As described above, according to the present invention, in the solid-state imaging device having the pixel addition mode, the row direction (horizontal direction) can be changed by a very simple change such as a transfer gate wiring change or a drive timing setting change by a drive signal. By changing the number of added pixels, the compression rate of the added pixels can be easily changed. Accordingly, in the development of a CCD area sensor having a pixel addition mode, it is possible to reduce the cost of model development and shorten the development period. Furthermore, when the number of added pixels in the horizontal direction is changed, the number of CCD transfer stages, the type of drive signal, the number of drive terminals, the element size, etc. do not change, so signal processing becomes very easy, and packages and pins It is not necessary to change the (terminal) layout.

  Embodiments of a solid-state imaging device and a driving method thereof according to the present invention will be described below in detail with reference to the drawings.

Before describing the embodiment of the solid-state imaging device of the present invention and the driving method thereof that enables the number of horizontal addition pixels to be changed more easily, first, the number of horizontal addition pixels (multiple pixel addition) of the solid-state imaging device of the present invention will be described. Each structural example 1-6 of (Process) is demonstrated in detail using FIGS.
(Configuration example 1)
In this configuration example 1, signal charges of two pixels adjacent in the horizontal direction are added (horizontal two-screen addition).

  FIG. 1 is a diagram illustrating a gate configuration example of the vertical transfer unit 10 and the addition unit 20 in the solid-state imaging device according to the first configuration example.

  Although not shown in FIG. 1, the solid-state imaging device of Configuration Example 1 includes a plurality of light receiving units in which a signal charge corresponding to the amount of incident light incident from a subject is generated by photoelectric conversion in a row direction ( The pixel periods K in the horizontal direction are arranged in a matrix (matrix). In the first embodiment, K = 2 is set.

  Each of the light receiving portions is arranged above the vertical transfer portion 10 (normal transfer portion) as the column direction transfer portion in FIG. 1, and the signal charges read from the light receiving portions (pixels) in an arbitrary row are arranged. Charges are transferred in the column direction (downward or vertical in FIG. 1) by the vertical transfer unit 10. In the vertical transfer unit 10, a plurality of portions having transfer gates in n rows are connected in the column direction (vertical direction).

  Further, although not shown in FIG. 1, a horizontal transfer unit is provided below the vertical transfer unit 10, and signal charges transferred from each light receiving unit by the vertical transfer unit 10 are set in a predetermined horizontal period. It is output to the horizontal transfer unit as the row direction transfer unit according to the cycle.

  As shown in FIG. 1, a plurality of first transfer gate groups 21 having m rows and K columns and the first transfer are arranged on the horizontal transfer unit side (lower side in FIG. 1) with respect to the vertical transfer unit 10. A plurality of second transfer gate groups 22 having m rows and K columns, which are faster in reading speed than the gate group 21, are provided. The first transfer gate group 21 and the second transfer gate group 22 are The gate drive voltage can be applied independently to any gate electrode (gate) in at least one row. The adding unit 20 is configured by m × j rows (j is a positive integer) of the gate regions including the first transfer gate group 21 and the second transfer gate group 22. In this configuration example 1, j = (A−1) = 1 is set in order to add the signal charges of A = 2 pixels that are adjacent in the horizontal direction.

  The gate region (adder 20) composed of m × j rows corresponds to the range from (x−1) × m + 1 to x × m rows (integers from x = 1 to j) from the horizontal transfer unit side. The first transfer gate group x set and the second transfer gate group j- (x-1) set, and the first transfer gate group x set and the second transfer gate group. Of j- (x-1) sets are alternately arranged in the horizontal direction. In the present configuration example 1, since j = 1 is set, one set of the first transfer gate group 21 and one set of the second transfer gate are arranged in the region from the first row to the m-th row from the side close to the horizontal transfer unit. The transfer gate groups 22 are alternately arranged in the horizontal direction.

With the above configuration, the first transfer gate group 21 and the second transfer gate group 22 having different reading speeds are provided in the left column and the right column, and the reading speed increases as the right column increases. The signal charge is read simultaneously as one pixel, and horizontal two-pixel addition (multiple pixel addition processing) is performed.
(Configuration example 2)
In the second configuration example, signals of three pixels adjacent in the horizontal direction are added (horizontal three-screen addition).

  FIG. 2 is a diagram illustrating a gate configuration example of the vertical transfer unit 10 and the addition unit 20 in the solid-state imaging device according to the second configuration example. In addition, about the member which show | plays the same effect as the case of the structural example 1 shown in FIG. 1, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  In FIG. 2, a plurality of first transfer gate groups 21 having m rows and K columns and a plurality of m rows and K columns are provided on the horizontal transfer portion side (lower side in FIG. 2) with respect to the vertical transfer portion 10. The second transfer gate group 22 is provided, and the first transfer gate group 21 and the second transfer gate group 22 independently apply a gate drive voltage to any one or more arbitrary gates. It is possible. The adding unit 20 is configured by m × j rows (j is an integer) of gate regions including the first transfer gate group 21 and the second transfer gate group 22. In the second configuration example, j = (3-1) = 2 is set in order to add signals of A = 3 pixels that are close to each other in the horizontal direction.

  The gate region (adder 20) composed of m × j rows corresponds to the range from (x−1) × m + 1 to x × m rows (integers from x = 1 to j) from the horizontal transfer unit side. The first transfer gate group x set and the second transfer gate group j- (x-1) set, and the first transfer gate group x set and the second transfer gate group. Of j- (x-1) sets are alternately arranged in the horizontal direction. In this configuration example 2, since j = 2 is set, one set of the first transfer gate group 21 and two sets of the second transfer gates are arranged in the region from the first row to the m-th row from the side close to the horizontal transfer unit. The transfer gate groups 22 are alternately arranged in the horizontal direction. Also, two sets of first transfer gate groups 21 and one set of second transfer gate groups 22 are alternately arranged in the horizontal direction in the area from the (m + 1) th row to the 2 × mth row from the side close to the horizontal transfer unit. Has been placed.

With the above configuration, two sets of first transfer gate groups 21, one set of first transfer gate groups 21, one set of second transfer gate groups 22, two sets of second transfer gate groups 22, Are provided from the left side column to the right side column, and the reading speed increases as the right side column increases. Therefore, the horizontal transfer unit reads the signal charge as one pixel and adds the three horizontal pixels (multiple pixel addition process).
(Configuration example 3)
In the third configuration example, signals of four pixels adjacent in the horizontal direction are added (horizontal four-screen addition).

  FIG. 3 is a diagram illustrating a gate configuration example of the vertical transfer unit 10 and the addition unit 20 in the solid-state imaging device of Configuration Example 3. In addition, about the member which show | plays the same effect as the case of the structural example 1 shown in FIG. 1, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  3, on the horizontal transfer unit side (lower side in FIG. 3) with respect to the vertical transfer unit 10, a plurality of first transfer gate groups 21 having m rows and K columns and a plurality of m rows and K columns are provided. The second transfer gate group 22 is provided, and the first transfer gate group 21 and the second transfer gate group 22 independently apply a gate drive voltage to any one or more arbitrary gates. It is possible. The adding unit 20 is configured by m × j rows (j is an integer) of gate regions including the first transfer gate group 21 and the second transfer gate group 22. In the third configuration example, j = (4-1) = 3 is set in order to add signals of A = 4 pixels that are adjacent in the horizontal direction.

  The gate region (adder 20) composed of m × j rows corresponds to the range from (x−1) × m + 1 to x × m rows (integers from x = 1 to j) from the horizontal transfer unit side. The first transfer gate group x set and the second transfer gate group j- (x-1) set, and the first transfer gate group x set and the second transfer gate group. Of j- (x-1) sets are alternately arranged in the horizontal direction. In this configuration example 3, since j = 2 is set, one set of the first transfer gate group 21 and three sets of the second transfer gates are arranged in the region from the first row to the m-th row from the side close to the horizontal transfer unit. The transfer gate groups 22 are alternately arranged in the horizontal direction. Also, two sets of first transfer gate groups 21 and two sets of second transfer gate groups 22 are alternately arranged in the horizontal direction in the area from the (m + 1) th row to the 2 × mth row from the side close to the horizontal transfer unit. Has been placed. Further, three sets of first transfer gate groups 21 and one set of second transfer gate groups 22 are arranged in the horizontal direction in the region of 2 × m + 1 row to 3 × m row from the side close to the horizontal transfer section. Alternatingly arranged.

With the above configuration, three sets of first transfer gate groups 21, two sets of first transfer gate groups 21, one set of second transfer gate groups 22, one set of second transfer gate groups 22, and Two sets of second transfer gate groups 22 and three sets of second transfer gate groups 22 are sequentially provided from the left column to the right column, and the reading speed increases as the right column increases. The signal charge is read out as a pixel, and four horizontal pixels are added.
(Configuration example 4)
In the fourth configuration example, as in the first configuration example, signals of two pixels adjacent in the horizontal direction are added (horizontal two-pixel addition).

  FIG. 4 is a diagram illustrating a gate configuration example in the case where the connection unit 30 is provided between the vertical transfer unit 10 and the addition unit 20 in the solid-state imaging device according to the fourth configuration example. In addition, about the member which show | plays the same effect as the case of the structural example 1 shown in FIG. 1, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

In FIG. 4, three sets of third transfer gate groups 31 each consisting of m rows are provided between the adder 20 consisting of m × j rows and the vertical transfer unit 10. At least one of the gates constituting the transfer gate group 31 is connected to one of the gates constituting the vertical transfer unit 10. In this configuration example 4, i = 4 is set, and the signal of A = 2 pixels that are adjacent in the horizontal direction is added, so (i− (A−1)) = 3 sets of third transfers A gate group 31 is provided.
(Embodiment 5)
In the present configuration example 5, as in the case of the configuration example 2 described above, a signal of three pixels adjacent in the horizontal direction is added (horizontal three pixel addition).

  FIG. 5 is a diagram illustrating a gate configuration example in which a connection unit 30 is provided between the vertical transfer unit 10 and the addition unit 20 in the solid-state imaging device according to Configuration Example 5. In addition, about the member which show | plays the same effect as the case of the structural example 1 shown in FIG. 1, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

In FIG. 5, two sets of third transfer gate groups 31 each having m rows are provided between the adder 20 having m × j rows and the vertical transfer unit 10. At least one of the gates constituting the third transfer gate group 31 is connected to one of the gates constituting the vertical transfer unit 10. In this configuration example 5, i = 4 is set, and signals of A = 3 pixels that are close to each other in the horizontal direction are added, so (i− (A−1)) = 2 sets of second transfers A gate group 31 is provided.
(Configuration example 6)
In the present configuration example 6, as in the case of the above configuration example 3, a signal of four pixels adjacent in the horizontal direction is added (horizontal four pixel addition).

  FIG. 6 is a diagram illustrating a gate configuration example of the vertical transfer unit 10, the addition unit 20, and the connection unit 30 in the solid-state imaging device of the configuration example 6. In addition, about the member which show | plays the same effect as the case of the structural example 1 shown in FIG. 1, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  In FIG. 6, a third transfer gate group 31 consisting of one set of m rows is provided between the adder 20 consisting of m × j rows and the vertical transfer unit 10, and the third transfer gate group At least one of the gates constituting the gate 31 is connected to one of the gates constituting the vertical transfer unit. In the sixth embodiment, i = 4 is set, and a signal of A = 4 pixels that are close to each other in the horizontal direction is added, so (i− (A−1)) = 1 set of third transfer. A gate group 31 is provided.

  Here, the configuration and the operation of the first transfer gate group 21 and the second transfer gate group 22 in the solid-state imaging devices of the respective configuration examples 1 to 6 will be described with reference to FIGS. An outline of the driving method of the solid-state imaging device of Configuration Example 2 will be described with reference to FIG.

  FIGS. 7A, 8A, and 9A are configuration examples 1 and 4 that add signal charges of two pixels in the horizontal direction, and configuration example 2 that adds signals of three pixels in the horizontal direction, respectively. , 5, and each of the solid-state imaging devices of Configuration Examples 3 and 6 that add the signals of four pixels in the horizontal direction, the first transfer gate group 21 having a slow charge transfer and the second transfer gate group having a fast charge transfer. FIG. In these drawings, the first transfer gate group 21 and the second transfer gate group 22 are surrounded by a thick line, and the first transfer gate group 21 is colored. In addition, the portion not surrounded by a thick line indicates the gate of the vertical transfer unit 10 in the configuration examples 1 to 3, and the gates of the third transfer gate group 31 in the configuration examples 4 to 6.

  In FIG. 7A, as shown in FIGS. 1 and 4, one set of the first transfer gate group 21 and one set of the first transfer gate group 21 in the region from the first row to the m-th row from the side close to the horizontal transfer section. Two transfer gate groups 22 are alternately arranged in the horizontal direction. Further, in FIG. 4, three sets of third transfer gate groups 31 are provided on the vertical transfer unit 10 side of the addition unit 20.

  In FIG. 8A, as shown in FIGS. 2 and 5, one set of the first transfer gate group 21 and two sets of the first transfer gate group 21 and the two sets of the first transfer gate group 21 in the region from the first row to the m-th row from the side close to the horizontal transfer section. The second transfer gate groups 22 are alternately arranged in the horizontal direction, and two sets of the first transfer gate groups 21 and one set of the first transfer gate groups 21 in the area of the (m + 1) th row to the 2 × mth row from the side close to the horizontal transfer unit. Two transfer gate groups 22 are alternately arranged in the horizontal direction. Further, in FIG. 5, two sets of third transfer gate groups 31 are provided on the vertical transfer unit 10 side of the addition unit 20.

  In FIG. 9A, as shown in FIGS. 3 and 6, one set of the first transfer gate group 21 and three sets of the first transfer gate group 21 in the region from the first row to the m-th row from the side close to the horizontal transfer portion. The two transfer gate groups 22 are alternately arranged in the horizontal direction, and two sets of the first transfer gate groups 21 and two sets of the first transfer gate groups 22 are arranged in an area from the (m + 1) th row to the 2 × mth row from the side near the horizontal transfer unit. The two transfer gate groups 22 are alternately arranged in the horizontal direction, and three sets of the first transfer gate groups 21 and one set are arranged in the region of the 2 × m + 1 row to the 3 × m row from the side close to the horizontal transfer unit. The second transfer gate groups 22 are alternately arranged in the horizontal direction. Further, in FIG. 6, a set of third transfer gate groups 31 is provided on the vertical transfer unit side of the adder unit 20.

  7 (b) and 7 (c), FIG. 8 (b) and FIG. 8 (c), and FIG. 9 (b) and FIG. 9 (c) are the above-described configurations for adding signals of two pixels in the horizontal direction, respectively. The first transfer gate for each of the solid-state imaging devices of Examples 1 and 4, Configuration Examples 2 and 5 for adding a signal of 3 pixels in the horizontal direction, and Configuration Examples 3 and 6 for adding a signal of 4 pixels in the horizontal direction FIG. 6 is a diagram illustrating an operation example of a group 21 and a second transfer gate group 22. In these figures, an arrow is attached to a gate group in which a signal transfer operation is performed.

  As shown in FIG. 7B, FIG. 8B, and FIG. 9B, in the first operation, the signal charges are received in both the first transfer gate group 21 and the second transfer gate group 22. Transfer m lines vertically. Further, as shown in FIGS. 7C, 8C, and 9C, during the second operation, only the second transfer gate group 22 transfers the signal charges in the m-row vertical direction. .

  By setting the vertical drive timing by combining the first operation and the second operation, the first transfer gate group 21 and the second transfer gate group 22 are included in the transfer column in the vertical direction. The order in which the signal charges are transferred to the horizontal transfer unit can be selectively controlled.

  For example, when signals of three pixels are added in the horizontal direction, as shown in FIG. 8 (a), as the transfer columns in the vertical direction, two transfer columns on the left side including two sets of first transfer gate groups 21 are provided. And two central transfer columns including one set of the first transfer gate group 21 and one set of the second transfer gate group 22, and two transfer columns on the right side including two sets of the second transfer gate group 22. There are three types of transfer trains.

  When the vertical drive timing including the first operation shown in FIG. 8B and the second operation shown in FIG. 8C is set for each of these three types of transfer trains, the second transfer gate The signal charge transfer is completed first in the transfer sequence on the right side including two sets of groups 22, and second in the central transfer sequence including one set of the first transfer gate group 21 and one set of the second transfer gate group 22. The signal charge transfer is completed, and the signal charge transfer is finally completed in the left transfer column including two sets of the first transfer gate group 21. In this way, the pixel addition operation can be realized by utilizing the fact that the signal charge transfer completion order can be selectively controlled.

  FIGS. 10 (0) to 10 (x) are diagrams for explaining an example of a method for driving the solid-state imaging device in the case of adding signals of three pixels in the horizontal direction (horizontal three-pixel addition).

  First, in the initial state of FIG. 10 (0), pixel signals are arranged in the rows y = 1 to 3. Here, the signal charges of the three pixels numbered 1 and 2 are added in the first row and the third row, respectively, and the signals of the three pixels numbered 3 and 4 are added in the second row, respectively. Is.

  In FIG. 10I, the second operation of transferring the signal charges in the m-row vertical direction only in the second transfer gate group 22 is performed. As a result, the signals of the pixels having the numbers 1 and 2 in the right two columns are transferred from the side closer to the vertical transfer unit to the side closer to the horizontal transfer unit.

  Next, in FIG. 10 (ii), the first operation of transferring the signal charges in the m-row vertical direction is performed in both the first transfer gate group 21 and the second transfer gate group 22. As a result, the signals of the pixels assigned numbers 1 and 2 in the right two columns are output to the horizontal transfer unit, and are transferred in the horizontal direction to the bottom of the central two columns of transfer columns in the horizontal transfer unit.

  In FIG. 10 (iii), the second operation of transferring the signal charges in the m-row vertical direction only in the second transfer gate group 22 is performed. As a result, the signals of the pixels assigned numbers 1 and 2 in the central two columns are output to the horizontal transfer unit, and are added to the signals transferred to that portion. Further, the signals of the pixels assigned numbers 3 and 4 in the right two columns are transferred from the side close to the vertical transfer unit to the side close to the horizontal transfer unit.

  In FIG. 10 (iv), the second operation of transferring signal charges in the m-row vertical direction only in the second transfer gate group 22 is performed. As a result, the pixel signals with numbers 3 and 4 in the right two columns are output to the horizontal transfer unit, and are transferred in the horizontal direction to the bottom of the central two columns of transfer columns in the horizontal transfer unit. Further, in the horizontal transfer unit, the addition signals for the two pixels assigned numbers 1 and 2 below the central two columns are transferred in the horizontal direction to the bottom of the left two transfer columns.

  In FIG. 10 (v), the first operation of transferring the signal charges in the m-row vertical direction is performed in both the first transfer gate group 21 and the second transfer gate group 22. As a result, the signals of the pixels assigned numbers 1 and 2 in the left two columns are output to the horizontal transfer unit, and are added to the signals for the two pixels that have been transferred to that portion.

  In FIG. 10 (vi), the second operation of transferring the signal charge in the m-row vertical direction only in the second transfer gate group 22 is performed. As a result, the signals of the pixels assigned numbers 3 and 4 in the central two columns are output to the horizontal transfer unit and added to the signal transferred to that portion. Further, the signals of the pixels assigned with numbers 1 and 2 in the right two columns are transferred from the side close to the vertical transfer unit to the side close to the horizontal transfer unit.

  In FIG. 10 (vii), the second operation for transferring the signal charge in the vertical direction of m rows is performed only in the second transfer gate group 22. As a result, the signals of the pixels assigned numbers 1 and 2 in the right two columns are output to the horizontal transfer unit, and are transferred in the horizontal direction to the bottom of the central two columns of transfer columns in the horizontal transfer unit. Further, in the horizontal transfer unit, the addition signals for two pixels assigned numbers 3 and 4 below the central two columns are transferred in the horizontal direction to the bottom of the left two transfer columns.

  In FIG. 10 (viii), the first operation of transferring the signal charges in the m-row vertical direction is performed in both the first transfer gate group 21 and the second transfer gate group 22. As a result, the signals of the pixels assigned numbers 3 and 4 in the left two columns are output to the horizontal transfer unit and added to the signals for the two pixels transferred to that portion.

  In FIG. 10 (ix), the second operation of transferring the signal charge in the m-row vertical direction only in the second transfer gate group 22 is performed. As a result, the signals of the pixels having the numbers 1 and 2 in the central two columns are output to the horizontal transfer unit and added to the signal charges transferred to the portion, and the left two transfer columns in the horizontal transfer unit. Is transferred horizontally to the bottom.

  In FIG. 10 (x), the first operation of transferring the signal charges in the m-row vertical direction is performed in both the first transfer gate group 21 and the second transfer gate group 22. As a result, the signals of the pixels assigned with the numbers 1 and 2 in the left two columns are output to the horizontal transfer unit, and are added to the signals for the two pixels that have been transferred to that portion.

  As described above, signals of three pixels are added in the horizontal direction with respect to the signal charges of the pixels of y = 1 to 3 rows. Similarly, when the signals of 2 pixels are added in the horizontal direction and when the signals of 4 pixels are added in the horizontal direction, the signals in both the first transfer gate group 21 and the second transfer gate group 22 are the same. This can be realized by combining the first operation of transferring charges in the vertical direction of m rows and the second operation of transferring signal charges in the vertical direction of m rows only in the second transfer gate group 22. .

  Next, as in the solid-state imaging devices of the first to sixth embodiments, when a signal of 2 pixels is added in the horizontal direction, a signal of 3 pixels is added in the horizontal direction, and a signal of 4 pixels is added in the horizontal direction. In the case of addition, a combination example in which addition pixels are combined will be described with reference to FIG.

  11 (b) to 11 (d) are respectively horizontal when a signal of two pixels is added in the horizontal direction on a screen in which RGB pixels are arranged as in the Bayer arrangement shown in FIG. 11 (a). It is a figure which shows the example of a combination of the addition pixel with thinning-out addition about the case where the signal of 3 pixels is added in the direction, and the case of adding the signal of 4 pixels in the horizontal direction.

  In FIG. 11A, rows in which R pixels and G pixels are alternately arranged in the horizontal direction and rows in which G pixels and B pixels are alternately arranged in the horizontal direction are alternately arranged in the vertical direction.

  In FIG. 11B, signal charges corresponding to 2 horizontal pixels × 2 vertical pixels = 4 pixels are added to one horizontal transfer packet of the horizontal transfer unit. For example, the signals of four R pixels in the first and third rows from the bottom are added and output as one pixel in one packet of the horizontal transfer unit as output 1, and 4 in the first and third rows from the bottom. The signals of two G pixels are added and output as one pixel in one packet of the horizontal transfer unit as output 2, and the signals of four G pixels in the fourth and sixth rows from the bottom are added and output as horizontal 3 It is output to one packet of the transfer unit, the signals of the four B pixels in the fourth and sixth rows from the bottom are added, and output as one output to one packet of the horizontal transfer unit.

  In FIG. 11C, signal charges of 3 horizontal pixels × 2 vertical pixels = 6 pixels are added to one horizontal packet of the horizontal transfer unit. For example, the signals of the six R pixels in the first and third rows from the bottom are added and output as one output to one packet of the horizontal transfer unit, and the six G pixels in the first and third rows from the bottom Are added to one packet of the horizontal transfer unit as output 2, and the signals of the 6 G pixels in the 4th and 6th rows from the bottom are added and output 3 to 1 packet of the horizontal transfer unit The signals of the 6 B pixels in the 4th and 6th rows from the bottom are added together and output as 4 in one packet of the horizontal transfer unit. In addition, the signals of the six R pixels in the seventh and ninth rows from the bottom are added and output to one packet of the horizontal transfer unit as an output 5, and further, the six rows in the seventh and ninth rows from the bottom. The G pixel signals are added and output as an output 6 to one packet of the horizontal transfer unit.

  In FIG. 11D, signal charges of 4 horizontal pixels × 2 vertical pixels = 8 pixels are added to one horizontal packet of the horizontal transfer unit. For example, the signals of the six R pixels in the first and third rows from the bottom are added and output as one output to one packet of the horizontal transfer unit, and the six G in the first and third rows from the bottom. The pixel signals are added and output as an output 2 to one packet of the horizontal transfer unit. The signals of the 6 G pixels in the fourth and sixth rows from the bottom are added and output 3 as the output of the horizontal transfer unit. It is output to one packet, and the signals of the six B pixels in the fourth and sixth rows from the bottom are added and output as one output to one packet of the horizontal transfer unit. In addition, the signals of the six R pixels in the seventh and ninth rows from the bottom are added and output as an output 5 to one packet of the horizontal transfer unit, and the six G in the seventh and ninth rows from the bottom. The pixel signals are added and output as an output 6 to one packet of the horizontal transfer unit. The signals of the 6 G pixels in the 10th and 12th rows from the bottom are added and output 7 as the output of the horizontal transfer unit. It is output to one packet, and the signals of the six B pixels in the 10th and 12th rows from the bottom are added together and output as an output 8 to one packet of the horizontal transfer unit.

  Next, a specific configuration of the addition unit and the connection unit in the solid-state imaging device of the configuration example 5 that adds the signals of three pixels in the horizontal direction will be described with reference to FIG. This will be described using a timing chart.

  FIG. 12 shows an adder 20 comprising a first transfer gate group 21 and a second transfer gate group 22 and a connection part comprising two sets of third transfer gate groups 31 in the solid-state imaging device of Configuration Example 5 above. It is a figure for demonstrating allocation of 30 gate structures and terminal wiring connection. In FIG. 12, the first transfer gate group 21 side is colored.

  In FIG. 12, a plurality of first transfer gate groups 21 having m = 4 rows and K = 2 columns and m = 4 rows on the horizontal transfer portion side (lower side in FIG. 12) with respect to the vertical transfer portion 10. A plurality of second transfer gate groups 22 each having K = 2 columns are provided, and the first transfer gate group 21 and the second transfer gate group 22 are arranged in the second row from the side close to the horizontal transfer unit. Gate drive voltages can be applied independently to the gates scA and scB in the sixth row and the gates saA and saB in the fourth and eighth rows close to the horizontal transfer section. Further, the same gate drive voltage is applied to the gates sd of the first and fifth rows from the side close to the horizontal transfer unit and the gates sb of the third and seventh rows close to the horizontal transfer unit. It has become. The adding unit 20 is constituted by the gate region of m = 4 × j = 2 rows composed of the first transfer gate group 21 and the second transfer gate group 22.

  The adding unit 20 includes one set of first transfer gate group 21 and two sets of second transfer in the region from the first row to the fourth row on the side closer to the horizontal transfer unit (the side closer to the horizontal transfer unit). Gate groups 22 are alternately arranged in the horizontal direction. Further, two sets of first transfer gate groups 21 and one set of second transfer gate groups 22 are arranged in the region from the fifth row to the eighth row on the side close to the horizontal transfer portion (the side far from the horizontal transfer portion). Are alternately arranged in the horizontal direction.

  Between the adder 20 and the vertical transfer unit 10, two sets of third transfer gate groups 31 including gates a to d of m = 4 rows are provided, and the vertical transfer unit 10 and the adder 20 are connected. A connecting portion 30 is provided.

  FIG. 13 is a timing chart for explaining an example of driving timing for each gate when performing the pixel addition operation in the solid-state imaging device of FIG.

  In FIG. 13, ΦH1 and ΦH2 indicate horizontal drive pulses for driving the horizontal transfer unit, and ΦsaA to Φsd indicate vertical drive pulses for driving the first transfer gate group 21 and the second transfer gate group 22.

  The vertical drive pulse ΦsaA is applied to the gate saA of the first transfer gate group 21 shown in FIG. 12, and the vertical drive pulse ΦsaB is applied to the gate saB of the second transfer gate group 22. The vertical drive pulse Φsb is applied to the gates sb of the first transfer gate group 21 and the second transfer gate group 22. Further, the vertical drive pulse ΦscA is applied to the gate scA of the first transfer gate group 21, and the vertical drive pulse ΦscB is applied to the gate scB of the second transfer gate group 22. Further, the vertical drive pulse Φsd is applied to the gates sd of the first transfer gate group 21 and the second transfer gate group 22.

  With the above configuration, first, at the timing (i) shown in FIG. 13, the vertical drive pulses ΦsaB and Φsb become low level, the vertical drive pulses ΦscB and Φsd become high level, and the vertical drive pulses ΦsaA and ΦscA do not change. As a result, the second operation of transferring the signal charges in the m-row vertical direction is performed only in the second transfer gate group 22, and as shown in FIG. The signal charges of the attached pixels are transferred from the side closer to the vertical transfer unit 10 to the side closer to the horizontal transfer unit.

  Next, at the timing (ii) shown in FIG. 13, the vertical drive pulses ΦsaA, ΦsaB, and Φsb are at a low level, and the vertical drive pulses ΦscA, ΦscB, and Φsd are at a high level. As a result, the first operation of transferring the signal charges in the m-row vertical direction is performed in both the first transfer gate group 21 and the second transfer gate group 22, and as shown in FIG. The signals of the pixels with numbers 1 and 2 in two columns are output to the horizontal transfer unit. These signals output to the horizontal transfer unit transfer charges in the horizontal direction to the bottom of the two central transfer columns by the next horizontal drive pulses ΦH1 and ΦH2.

  At the timing (iii) shown in FIG. 13, the vertical drive pulses ΦsaB and Φsb are at the low level, the vertical drive pulses ΦscB and Φsd are at the high level, and the vertical drive pulses ΦsaA and ΦscA do not change. As a result, the second operation of transferring the signal charges in the m-row vertical direction only in the second transfer gate group 22 is performed, and numbers 1 and 2 in the central two columns are assigned as shown in FIG. 10 (iii). The pixel signal is output to the horizontal transfer unit and added to the signal transferred to that portion. In addition, the signals of the pixels assigned numbers 3 and 4 in the right two columns are transferred from the side close to the vertical transfer unit to the side close to the horizontal transfer unit.

  At the timing (iv) shown in FIG. 13, the vertical drive pulses ΦsaB and Φsb are at the low level, the vertical drive pulses ΦscB and Φsd are at the high level, and the vertical drive pulses ΦsaA and ΦscA do not change. As a result, the second operation of transferring the signal charges in the m-row vertical direction only in the second transfer gate group 22 is performed, and numbers 3 and 4 in the right two columns are assigned as shown in FIG. 10 (iv). The signal charges of the pixels are output to the horizontal transfer unit. These signal charges output to the horizontal transfer section are transferred in the horizontal direction to the bottom of the two central charge transfer columns by horizontal drive pulses ΦH1 and ΦH2. Further, the addition signals for two pixels assigned numbers 1 and 2 below the central two columns are also transferred in the horizontal direction to the bottom of the two transfer columns on the left side.

  At the timing (v) shown in FIG. 13, the vertical drive pulses ΦsaA, ΦsaB, and Φsb are at a low level, and the vertical drive pulses ΦscA, ΦscB, and Φsd are at a high level. As a result, the first operation of transferring the signal charges in the m-row vertical direction is performed in both the first transfer gate group 21 and the second transfer gate group 22, and as shown in FIG. The signals of the pixels with numbers 1 and 2 in two columns are output to the horizontal transfer unit and added to the signals for the two pixels that have been transferred to that portion.

  At the timing (vi) shown in FIG. 13, the vertical drive pulses ΦsaB and Φsb become low level, the vertical drive pulses ΦscB and Φsd become high level, and the vertical drive pulses ΦsaA and ΦscA do not change. As a result, a second operation for transferring the signal charges in the m-row vertical direction is performed only in the second transfer gate group 22, and as shown in FIG. The added pixel signal is output to the horizontal transfer unit, and added to the signal transferred to that portion. In addition, the signals of the pixels assigned numbers 1 and 2 in the two right columns are transferred from the side close to the vertical transfer unit to the side close to the horizontal transfer unit.

  At timing (vii) shown in FIG. 13, the vertical drive pulses ΦsaB and Φsb are at a low level, the vertical drive pulses ΦscB and Φsd are at a high level, and the vertical drive pulses ΦsaA and ΦscA do not change. As a result, the second operation of transferring the signal charges in the m-row vertical direction only in the second transfer gate group 22 is performed, and numbers 1 and 2 in the right two columns are assigned as shown in FIG. 10 (vii). The pixel signal is output to the horizontal transfer unit. These signals output to the horizontal transfer unit are transferred in the horizontal direction to the bottom of the central two transfer columns by horizontal drive pulses ΦH1 and ΦH2. Further, the addition signals for two pixels assigned numbers 3 and 4 below the central two columns are also transferred in the horizontal direction to the bottom of the two transfer columns on the left side.

  At timing (viii) shown in FIG. 13, the vertical drive pulses ΦsaA, ΦsaB, and Φsb are at a low level, and the vertical drive pulses ΦscA, ΦscB, and Φsd are at a high level. As a result, the first operation of transferring the signal charges in the m-row vertical direction is performed in both the first transfer gate group 21 and the second transfer gate group 22, and as shown in FIG. The signals of the pixels with numbers 3 and 4 in two columns are output to the horizontal transfer unit, and added to the signals for the two pixels that have been transferred to that portion.

  At the timing (ix) shown in FIG. 13, the vertical drive pulses ΦsaB and Φsb become low level, the vertical drive pulses ΦscB and Φsd become high level, and the vertical drive pulses ΦsaA and ΦscA do not change. As a result, the second operation of transferring the signal charges in the m-row vertical direction only in the second transfer gate group 22 is performed, and numbers 1 and 2 in the center two columns are assigned as shown in FIG. The pixel signal is output to the horizontal transfer unit and added to the signal transferred to that portion. The added signals are transferred in the horizontal direction by the horizontal drive pulses ΦH1 and ΦH2 to the bottom of the left two transfer columns.

  At timing (x) shown in FIG. 13, the vertical drive pulses ΦsaA, ΦsaB, and Φsb are at a low level, and the vertical drive pulses ΦscA, ΦscB, and Φsd are at a high level. As a result, the first operation of transferring the signal charges in the m-row vertical direction is performed in both the second transfer gate group 21 and the second transfer gate group 22, and as shown in FIG. The signals of the pixels with numbers 1 and 2 in two columns are output to the horizontal transfer unit and added to the signals for the two pixels that have been transferred to that portion.

  As described above, signals of three pixels are added in the horizontal direction. In addition, in the case of adding a signal of 2 pixels in the horizontal direction or in the case of adding a signal of 4 pixels in the horizontal direction, the signal is transmitted in both the first transfer gate group 21 and the second transfer gate group 22. This can be realized by combining the first operation for transferring charges in the m-row vertical direction and the second operation for transferring signal charges in the m-row vertical direction only in the second transfer gate group 22.

  Next, an example of signal connection between the addition unit 20 and the connection unit 30 and the vertical transfer unit 10 in the solid-state imaging device of the configuration example 5 that adds signals of three pixels in the horizontal direction will be described with reference to FIG.

  FIG. 14 is a diagram illustrating a movement state of the signal charge at the time of normal transfer in the solid-state imaging device of the configuration example 5 described above.

  In FIG. 14, between the addition unit 20 including the first transfer gate group 21 and the second transfer gate group 22 and the vertical transfer unit 10 that transfers the signal charges read from the light receiving unit pixels in the column direction. 2, two sets of the third transfer gate group 31 composed of m rows having the same number of rows are arranged to constitute the connection unit 30.

  The vertical transfer unit 10 is configured by a 10-phase drive gate (n = 10), and the third transfer gate group 31 is configured by a 4-phase drive gate (m = 4).

  Furthermore, four types of pulses are selected and assigned to the gates a to d constituting the third transfer gate group 31 from the ten types of gate drive pulses ΦV1 to ΦV10 applied to the vertical transfer unit 10. ing.

  For example, in the example of FIG. 14, ΦV2 is assigned to the gates a of the fourth row and the eighth row from the side closer to the horizontal transfer unit, and ΦV3 is assigned to the gates b of the third row and the seventh row from the side closer to the horizontal transfer unit. ΦV7 is assigned to the gates c of the second and sixth rows from the side closer to the horizontal transfer unit, and ΦV8 is assigned to the gates d of the first and fifth rows from the side closer to the horizontal transfer unit. .

  Further, the number of gates (m = 4) of the third transfer gate group 31 is set to be equal to the first transfer gate group 21 and the second transfer gate group 22 constituting the adder 20. ΦV2 is assigned to the gates saA and saB in the fourth and eighth rows from the side closer to the horizontal transfer unit, and ΦV3 is assigned to the gates sb in the third and seventh rows from the side closer to the horizontal transfer unit, ΦV7 is assigned to the gates scA and scB in the second and sixth rows from the side closer to the horizontal transfer unit, and ΦV8 is assigned to the gates sd in the first and fifth rows from the side closer to the horizontal transfer unit.

  In the diagram of FIG. 14, the barrier state in the vertical transfer channel is shown as a white circle and the accumulation state is shown as a black circle, and is shown over one cycle period [1T to 20T] according to the time series.

  As shown in this diagram, the transfer channel packets of the first transfer gate group 21, the second transfer gate group 22, and the third transfer gate group 31 are linked to the gate drive in the vertical transfer unit 10 and continuously. Thus, the signal charge transfer operation is completed. Therefore, according to this configuration, the third transfer gate group has the same number of gate rows as the first and second transfer gate groups, and the adder unit 20 and the connection unit 30 have compatibility. The element layout design corresponding to various numbers of horizontal addition pixels can be easily performed while keeping the same kind of drive pulse, the number of drive terminals, and the chip size.

  In this case, at the time of pixel addition, a pulse as shown in FIG. 13 is applied to the first transfer gate group and the second transfer gate group.

  The solid-state imaging devices of the above configuration examples 4 to 6 shown in FIGS. 4 to 6 respectively add 2 pixel signals in the horizontal direction, add 3 pixel signals in the horizontal direction, and 4 in the horizontal direction. This corresponds to the case where the pixel signals are added, but the change from the configuration of adding the signals of 2 pixels in the horizontal direction shown in FIG. 4 to the configuration of adding the signals of 3 pixels in the horizontal direction shown in FIG. This can be realized by distributing one set of the third transfer gate group 31 to the gate regions constituting the first transfer gate group 21 and the second transfer gate group 22 to form the adder 20 in FIG. The reverse change is also the same.

  In addition, the change from the configuration in which the signal of 2 pixels is added in the horizontal direction shown in FIG. 4 to the configuration in which the signal of 4 pixels is added in the horizontal direction shown in FIG. This can be realized by assigning to the gate regions constituting the first transfer gate group 21 and the second transfer gate group 22 to be the adder 20 of FIG. The reverse change is also the same.

  Furthermore, the change from the configuration in which the signal of 3 pixels is added in the horizontal direction shown in FIG. 5 to the configuration in which the signal of 4 pixels is added in the horizontal direction shown in FIG. This can be realized by assigning to the gate regions constituting the first transfer gate group 21 and the second transfer gate group 22 to be the adder 20 of FIG. The reverse change is also the same.

  Furthermore, the change from the configuration in which the signals of two pixels are added in the horizontal direction shown in FIG. 4 to the configuration in which the signals of five or more pixels are added in the horizontal direction also changes the third transfer gate group 31 to three or more sets. This can be realized by allocating to the gate regions constituting one transfer gate group 21 and the second transfer gate group 22.

  In addition, the setting in the adding unit 20 and the connecting unit 30 may be performed by simply changing the assignment of the first transfer gate group 21 and the second transfer gate group 22, and it is not necessary to newly provide a drive pulse or a gate structure. Absent. Therefore, it is possible to change the compression ratio of the added pixels by changing the number of added pixels in the horizontal direction by a very simple method such as changing the wiring of the transfer gate or changing the setting of the drive timing.

  FIG. 15 is a gate arrangement diagram in the case of horizontal three-pixel addition, and FIGS. 16A and 16B are plan views showing gate wiring layers corresponding to the gate arrangement diagram of FIG. FIG. 17 is a gate arrangement diagram in the case of horizontal two-pixel addition. FIGS. 18A and 18B are plan views showing gate wiring layers corresponding to the gate arrangement diagram of FIG.

  For example, when changing between the case of the horizontal three-pixel addition and the case of the horizontal two-pixel addition, as shown in FIGS. 15 to 18, the gate wirings that are the second and third gate electrode layers It is possible to easily change the number of added pixels by changing the layer layout.

  Next, the manufacturing method of the solid-state image sensor of this invention is demonstrated.

  On the element substrate, as the first layer in the row direction, at least the gate electrode layers of the third transfer gate group 31 and the common gate electrode layers of the first and second transfer gate groups 21 and 22 The step of forming the common gate electrode layers in the column direction and the second layer in the row direction include the gate electrode layers of the third transfer gate group 31 and the gate electrode layers of the first transfer gate group 21 as the second layer in the row direction. A step of arranging at least the gate electrode layers in the column direction, and a step of forming the gate electrode layers of the second transfer gate group 22 in the column direction as a third layer in the row direction. .

  Specifically, the horizontal two-pixel addition will be described. As shown in FIGS. 17 and 18, as the gate electrode formation step, the first gate electrode layers b, d, b in the row direction are formed on the solid-state imaging device substrate. , D, sb and sd are arranged in the column direction, the second gate electrode layers a, c, a, c, saA and scA in the row direction are arranged in the column direction, and the row direction And forming a third gate electrode layer saB and scB side by side in the column direction.

  The horizontal three-pixel addition will be described. As shown in FIGS. 15 and 16, as the gate electrode formation step, the first gate electrode layers b, d, sb, sd, a step of forming sb and sd side by side in the column direction, a step of forming second gate electrode layers a, c, saA, scA, saA, and scA in the column direction side by side, and a third in the row direction A step of forming the gate electrode layers saB, scB, saB, and scB of the upper layer in the column direction.

  The horizontal four-pixel addition will be described. As the gate electrode formation step, the first gate electrode layers sb, sd, sb, sd, sb, and sd in the row direction are formed side by side in the column direction on the solid-state imaging device substrate. A step, a step of forming the second gate electrode layers saA, scA, saA, scA, saA and scA in the column direction side by side in the column direction, and a third gate electrode layer saB, scB, in the row direction and saB, scB, saB, and scB are formed side by side in the column direction.

  As described above, according to the solid-state imaging device of the present invention, the addition unit 20 that is a gate region of m × j rows is provided on the horizontal transfer unit side of the vertical transfer unit 10, and (x−1) × on the horizontal transfer unit side. From the (m + 1) -th row to the x × m-th row (natural number from x = 1 to j), the m-th row K (horizontal pixel cycle of the light-receiving unit) column according to the horizontal pixel cycle K of the light-receiving unit pixels. The x set of one transfer gate group 21 and the j- (x-1) set of the second transfer gate group 22 are alternately arranged in the horizontal direction. In the addition drive mode, the first operation period in which the signal charges of both transfer gate groups 21 and 22 are vertically transferred and the second operation period in which the signal charges of only the second transfer gate group 22 are vertically transferred are combined. . The column with many second transfer gate groups 22 has a short transfer period (the charge transfer rate becomes fast), and the column with many first transfer gate groups 21 has a long transfer time (the charge transfer rate becomes slow). The signal charge previously transferred to the horizontal transfer unit can be horizontally transferred by the horizontal transfer unit, and the signal charge transferred later can be added by the horizontal transfer unit. In this case, the third transfer gate group has the same number of gate rows as the first and second transfer gate groups, and the adder unit 20 and the connection unit 30 have compatibility, and the layout of each predetermined gate wiring layer is determined. By simply changing it, it is possible to easily perform element layout design corresponding to various numbers of horizontally added pixels while maintaining the same number of transfer stages, types of drive pulses, number of drive terminals and chip size, and horizontal addition. The number of pixels can be changed more easily, and the frame rate at the time of moving image capturing can be easily increased.

  When changing the number of pixels to be added in the vertical direction in a conventional CCD element capable of pixel addition driving, it is not necessary to change the structure of the adding unit, but to change the number of pixels to be added in the horizontal direction. However, since the addition part structure needs to be significantly changed, a product with a changed number of added pixels needs to be developed as a different model. On the other hand, in the above embodiment, as shown in FIG. 19, one or a plurality of groups N of the normal transfer unit (vertical transfer unit 10 in FIG. 12) composed of n stages of gates and an addition gate (addition unit 20). 1 or a plurality of groups L forming a connection group 30 having the same number of stages (rows) as the number of stages of the group L, and a gate group of the group M is provided. As an example of the configuration in which the group is connected to one of the group N gate groups, the horizontal three-pixel addition configuration (corresponding to FIG. 19B) has been described with reference to FIG. FIG. 19A shows the addition configuration, and FIG. 19C shows the horizontal 4-pixel addition configuration. As a result, when the number of pixels to be added in the horizontal direction is changed, the number of pixels to be added in the horizontal direction is changed by switching the number of added pixels with a switch means or the like as shown in FIGS. 19 (a) to 19 (c). Alternatively, as described above, it is possible to change the predetermined electrode wirings at the design stage (change the layout of the predetermined gate wiring layers) and change the entire electrode wiring layout substantially without changing the entire electrode wiring layout. The number of added pixels in the horizontal direction can be changed more easily by the size.

  In the above-described embodiment, a plurality of first transfer gate groups 21 of m (m is a natural number) rows and K columns between the vertical transfer units 10 and the horizontal transfer units, and more charges than the first transfer gate groups 21. An adder 20 of m × j (j is a natural number) rows having a plurality of second transfer gate groups 22 of m rows and K columns set so as to be transferred earlier is provided. Although the description has been given of the case where the third transfer gate group 31 of m rows is provided between the transfer units 10 in any one of the first to third sets in the column direction, the third transfer gate is not limited to this. Even when there is no group 31, the effects of the present invention can be obtained to some extent. In this case, it is necessary to shift the positions of the horizontal transfer unit and the data output unit of the sense amplifier in terms of layout, but otherwise the first transfer gate group 21 and the second transfer gate group 22 as described above. The number of added pixels in the row direction can be changed simply by changing the layout of each gate wiring layer. Also at this time, as described above, each gate constituting each of the first transfer gate group 21 and the second transfer gate group 22 has a predetermined number of gate drive pulses applied to the vertical transfer unit 10. Each pulse may be assigned.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a solid-state imaging device that speeds up signal processing by adding pixel signals read out by selecting all pixels, a driving method thereof, a manufacturing method of the solid-state imaging device, and a solid-state imaging device. In the field of electronic information devices such as digital cameras that use the moving image shooting mode function, pixels that are added in the horizontal direction by changing the transfer gate wiring or changing the drive timing setting using the drive signal By changing the number, the compression rate of the added pixels can be easily changed. Accordingly, in the development of a CCD area sensor having a pixel addition mode, it is possible to reduce the cost of model development and shorten the development period. Furthermore, when the number of added pixels in the horizontal direction is changed, the number of CCD transfer stages, the type of drive signal, the number of drive terminals, the element size, etc. do not change, so signal processing becomes very easy, and packages and pins It is not necessary to change the (terminal) layout.

It is a figure which shows the gate structure of the vertical transfer part and the addition part in the solid-state image sensor which concerns on the structural example 1 of this invention. It is a figure which shows the gate structure of the vertical transfer part and the addition part in the solid-state image sensor which concerns on the structural example 2 of this invention. It is a figure which shows the gate structure of the vertical transfer part and the addition part in the solid-state image sensor which concerns on the structural example 3 of this invention. It is a figure which shows the gate structure of the vertical transfer part in the solid-state image sensor which concerns on the example 4 of this invention, an addition part, and a connection part. It is a figure which shows the gate structure of the vertical transfer part in the solid-state image sensor which concerns on the example 5 of this invention, an addition part, and a connection part. It is a figure which shows the gate structure of the vertical transfer part in the solid-state image sensor which concerns on the example 6 of this invention, an addition part, and a connection part. (A) is a figure which shows the example of arrangement | positioning of a 1st transfer gate group and a 2nd transfer gate group about the solid-state image sensor of the structural examples 1 and 4 which add the signal of 2 pixels in a horizontal direction, (b) (C) and (c) are diagrams showing an operation example of the first transfer gate group and the second transfer gate group. (A) is a figure which shows the example of arrangement | positioning of a 1st transfer gate group and a 2nd transfer gate group about the solid-state image sensor of the structural examples 2 and 5 which add the signal of 3 pixels in a horizontal direction, (b) (C) and (c) are diagrams showing an operation example of the first transfer gate group and the second transfer gate group. (A) is a figure which shows the example of arrangement | positioning of the 1st transfer gate group and the 2nd transfer gate group about the solid-state image sensor of the structural examples 3 and 5 which add the signal of 4 pixels to a horizontal direction, (b) (C) and (c) are diagrams showing an operation example of the first transfer gate group and the second transfer gate group. It is a figure for demonstrating the example in the case of adding the signal of 3 pixels in a horizontal direction in the drive method of the solid-state image sensor concerning embodiment of this invention. (A) is a figure which shows the example of an arrangement | sequence of a pixel about the solid-state image sensor which concerns on embodiment of this invention, (b)-(d) is each arrange | positioning each pixel of RGB as shown to (a). FIG. 6 is a diagram illustrating a combination example of addition pixels in a case where a signal of 2 pixels is added in the horizontal direction, a signal of 3 pixels is added in the horizontal direction, and a signal of 4 pixels is added in the horizontal direction on the screen. is there. In the solid-state imaging device according to Configuration Example 5 of the present invention, the gate structure and the terminal wiring connection of the addition unit including the first transfer gate group and the second transfer gate group, and the connection unit including the third transfer gate group It is a figure for demonstrating allocation. 13 is a timing chart for explaining an example of drive timing when performing a pixel addition operation in the solid-state imaging device of FIG. 12. It is a figure which shows the movement state of the signal charge at the time of normal transfer about the solid-state image sensor which concerns on the structural example 5 of this invention. It is a gate arrangement diagram in the case of horizontal three-pixel addition. FIG. 16 is a plan view showing each gate wiring layer (No. 1) corresponding to the gate arrangement diagram of FIG. 15. FIG. 16 is a plan view showing each gate wiring layer (No. 2) corresponding to the gate arrangement diagram of FIG. 15. It is a gate arrangement diagram in the case of horizontal two-pixel addition. FIG. 18 is a plan view showing gate wiring layers (No. 1) corresponding to the gate arrangement diagram of FIG. 17. FIG. 18 is a plan view showing each gate wiring layer (No. 2) corresponding to the gate arrangement diagram of FIG. 17. (A) is the gate structure of the addition part which consists of a 1st transfer gate group and a 2nd transfer gate group, and the connection part which consists of a 3rd transfer gate group in the solid-state image sensor which concerns on the structural example 4 of this invention. FIG. 6B is a diagram for explaining the assignment of terminal wiring connections; FIG. 5B is a diagram illustrating an addition unit including a first transfer gate group and a second transfer gate group in the solid-state imaging device according to Configuration Example 5 of the present invention; The figure for demonstrating allocation of the gate structure and terminal wiring connection of a connection part which consists of 3rd transfer gate groups, (c) is the 1st transfer gate group in the solid-state image sensor which concerns on the structural example 6 of this invention. FIG. 10 is a diagram for explaining the assignment of the gate structure and the terminal wiring connection of the addition unit composed of the second transfer gate group and the connection unit composed of the third transfer gate group. (A) is a figure which shows the example of an arrangement | sequence of a pixel about the conventional solid-state image sensor, (b)-(d) is respectively horizontal on the screen on which each pixel of RGB was arranged as shown to (a). It is a figure which shows the example of a combination of an addition pixel about the case where the signal of 2 pixels is added in the direction, the case of adding the signal of 3 pixels in the horizontal direction, and the case of adding the signal of 4 pixels in the horizontal direction. It is a figure which shows the drive procedure at the time of adding 4 pixels from a 4 * 4 area | region about the drive method of the conventional solid-state image sensor (the 1). It is a figure which shows the drive procedure at the time of adding 4 pixels from a 4 * 4 area | region about the drive method of the conventional solid-state image sensor (the 2). In the conventional solid-state image sensor, it is a figure for demonstrating the example of a gate structure of a vertical transfer part and an addition part about the case where the signal charge of 2 pixels adjacent to a horizontal direction is added.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Vertical transfer part 20 Adder part 21 1st transfer gate group 22 2nd transfer gate group 30 Connection part 31 3rd transfer gate group

Claims (16)

A plurality of light receiving units that generate signal charges corresponding to the amount of incident light by photoelectric conversion are arranged in a matrix with the pixel period in the row direction being K (K is a natural number), and the signal charges read from each light receiving unit are In a solid-state imaging device having a column direction transfer unit that transfers charges in the column direction, and a row direction transfer unit that outputs signal charges transferred by the column direction transfer unit in a predetermined period period,
Between the column-direction transfer unit and the row-direction transfer unit, a plurality of first transfer gate groups of m (m is a natural number) rows and K columns, and charge transfer is faster than the first transfer gate groups. A gate region of m × j (j is a natural number) rows having a plurality of second transfer gate groups of m rows and K columns set;
The gate region is transferred to the region corresponding to the region between the (x−1) × m + 1 row and the x × m row (natural number from x = 1 to j) on the row direction transfer unit side. A solid-state imaging device in which x sets of gate groups and j- (x-1) sets of the second transfer gate groups are alternately arranged in the row direction.   2. The solid-state imaging device according to claim 1, wherein j = (A−1) is set when adding signal charges of A pixels (A is a natural number) adjacent in the row direction.   3. The solid-state imaging device according to claim 1, wherein at least one set of m rows of third transfer gate groups is provided adjacent to each other in the column direction between the gate region and the column direction transfer unit.   When adding the signal charges of the A pixels adjacent in the row direction, j = (A−1) is set, and the third transfer gate group is i (i is a natural number greater than or equal to A) − (A− 1)) The solid-state imaging device according to claim 3, wherein the solid-state imaging device is provided adjacent to the set in the column direction.   4. The solid-state imaging device according to claim 1, wherein at least one gate electrode among the gate electrodes constituting the third transfer gate group is connected to any one of the gate electrodes constituting the column direction transfer unit. 5. .   2. The solid-state imaging device according to claim 1, wherein in the gate region, charge transfer columns having different combinations of the number of the first transfer gate groups and the number of the second transfer gate groups are arranged for each K column. .   The charge transfer rate by the second transfer gate group is set faster than the charge transfer rate by the first transfer gate group so that a plurality of pixel addition processing is performed with one pixel for each color in the row direction transfer unit. The solid-state imaging device according to claim 1 or 6.   8. The solid state according to claim 1, wherein the second transfer gate group is capable of applying a gate drive voltage independent of the first transfer gate group to at least one row of arbitrary gate electrodes. Image sensor.   Transfer of signal charges by a combination of a first operation period in which both the first transfer gate group and the second transfer gate group are operated and a second operation period in which only the second transfer gate group is operated The solid-state imaging device according to claim 8, wherein control is performed.   2. The solid-state imaging device according to claim 1, wherein the number of pixels added in a row direction can be changed by changing a layout of each gate electrode layer of the first transfer gate group and the second transfer gate group. .   The number of added pixels in the row direction can be changed by changing a layout of each gate electrode layer of the third transfer gate group, the first transfer gate group, and the second transfer gate group. 3. The solid-state imaging device according to 3.   Each of the gate electrodes constituting each of the first transfer gate group and the second transfer gate group is assigned predetermined pulses from a plurality of gate drive pulses applied to the column direction transfer unit. Item 2. The solid-state imaging device according to Item 1.   Each gate electrode constituting the third transfer gate group is assigned a predetermined pulse from a plurality of gate drive pulses applied to the column direction transfer unit, and the first transfer gate group and the second transfer gate group 6. The solid-state imaging device according to claim 3, wherein the predetermined pulses are sequentially assigned to the gate electrodes respectively constituting the transfer gate groups.   An electronic information device using the solid-state imaging device according to claim 1 for an imaging unit. A method for driving a solid-state imaging device for driving the solid-state imaging device according to claim 1,
A first operation period in which a first operation pulse is applied in order to simultaneously transfer at least m rows of signal charges in the column direction in the first transfer gate group and the second transfer gate group; A plurality of pixels in the row direction in the row direction transfer unit using a second operation period in which a second operation pulse is applied to transfer signal charges in at least m rows in the column direction only in the two transfer gate groups. A method for driving a solid-state imaging device that performs addition processing. A method for manufacturing a solid-state imaging device for manufacturing the solid-state imaging device according to claim 1,
As a gate electrode formation process,
On the element substrate, as a first layer in the row direction, at least each of the gate electrode layers of the third transfer gate group and the common gate electrode layers of the first and second transfer gate groups is common. A step of forming the gate electrode layers side by side in the column direction, and a second layer in the row direction, including the gate electrode layers of the third transfer gate group and the gate electrode layers of the first transfer gate group. Solid-state imaging comprising: a step of forming at least the gate electrode layers side by side in the column direction; and a step of forming the gate electrode layers of the second transfer gate group in the column direction as a third layer in the row direction. Device manufacturing method.

Images