JP7326913B2 - semiconductor integrated circuit - Google Patents

Description

The present disclosure relates to a semiconductor integrated circuit and a test method for the semiconductor integrated circuit.

In a device with redundant interfaces, for example, two interfaces having the same configuration, a basic interface and a redundant interface, are provided. Between semiconductor integrated circuits that communicate via these two interfaces, for example, by transmitting and receiving exactly the same signal in duplicate, even if one communication path fails, communication via the other communication path is possible. By being able to do so, the reliability of communication can be ensured. The redundant configuration interface may be used in any manner. For example, two interfaces may be used for transmitting and receiving different signals to double the signal transmission width.

When checking the operation of each circuit and connection path for a device on which N semiconductor integrated circuits are mounted, each of which has a redundantly configured interface, N test devices are applied to each of the N semiconductor integrated circuits. A test method of connecting and executing tests in parallel is conceivable. Alternatively, a test method can be considered in which one test apparatus is sequentially connected to N semiconductor integrated circuits to sequentially perform tests N times.

For parallel testing, it is necessary to prepare N test devices. In addition, operations for the number of test devices are required, which is time-consuming. In the case of sequential testing, the test is performed N times while switching the test equipment, which takes N times as long.

JP 2007-187489 A JP 2011-179881 A

In view of the above, a circuit configuration capable of efficiently testing a plurality of semiconductor integrated circuits having redundantly configured interfaces is desired.

A semiconductor integrated circuit includes an internal circuit, a first signal path for transmitting/receiving a signal between the outside and the internal circuit, a second signal path for transmitting/receiving a signal between the outside and the internal circuit, and the a first command detection circuit that detects a command received from the outside on a first signal path; and a register that stores a command detection result by the command detection circuit, wherein the command detection result of the register is received from the outside. When a test operation is indicated in response to a setting command , a transfer operation is performed to transmit the setting command and a signal received from the outside on the first signal path to the outside from the second signal path, and the command is stored in the register. If the detection result does not indicate a test operation, the first signal path and the second signal path are operated independently of each other without executing the transfer operation.

According to at least one embodiment, multiple semiconductor integrated circuits having redundant interfaces can be efficiently tested.

It is a figure which shows an example of a structure of a test system. It is a figure which shows an example of a structure of a test apparatus. 1 is a diagram showing an example of a configuration of a semiconductor integrated circuit; FIG. FIG. 4 is a diagram showing an example of a command sequence exchanged between the testing device and the device under test during test operation; 2 is a flow chart showing an example of test operation by the test system shown in FIG. 1; FIG. 4 is a diagram showing an example of the configuration of a setting command; FIG. FIG. 10 is a diagram showing another example of the configuration of a setting command; FIG. FIG. 4 is a diagram showing an example of the configuration of an information command; FIG. FIG. 9 is a diagram showing the input/output relationship of the selection circuit. FIG. 10 is a diagram showing a table defining operations of an input selection circuit; FIG. 10 is a diagram showing a table defining operations of an output selection circuit;

Embodiments of the invention are described in detail below with reference to the accompanying drawings. In the accompanying drawings, the same or corresponding components are referred to by the same or corresponding numbers, and descriptions thereof are omitted as appropriate.

FIG. 1 is a diagram showing an example of the configuration of a test system. The test system shown in FIG. 1 includes a test device 10 and an evaluated device 20 . The test apparatus 10 includes a semiconductor integrated circuit (LSI) 13 mounted on a printed circuit board (PCB) 12, a basic interface connector 11-1, and a redundant interface connector 11-2. The device under test 20 includes semiconductor integrated circuits 23-1 and 23-2 mounted on a printed circuit board 22-1, basic interface connectors 21-1 and 21-3, and redundant interface connectors 21-2 and 21-4. include. The device under test 20 further includes semiconductor integrated circuits 23-3 and 23-4 mounted on the printed circuit board 22-2, basic interface connectors 21-5 and 21-7, and redundant interface connectors 21-6 and 21-8. including.

The device under evaluation 20 is connected to an error information management device 26 and a shared memory 25 . The semiconductor integrated circuits 23-1 to 23-4 mounted on the device under evaluation 20 may be, for example, memory controllers that manage data reading and writing with respect to the shared memory 25. FIG. In the following description, the test system will be described assuming that the semiconductor integrated circuits 23-1 to 23-4 are circuits that read and write data to and from the shared memory 25. FIG. However, in the test system shown in FIG. 1, the functions of the semiconductor integrated circuits 23-1 to 23-4 to be tested are not particularly limited.

The device under test 20 shown in FIG. 1 includes four semiconductor integrated circuits 23-1 to 23-4, but the number of semiconductor integrated circuits is not limited to a specific number, and a plurality of semiconductor integrated circuits are tested. It is sufficient if it is provided. In addition, the semiconductor integrated circuits to be tested do not have to be provided in one device (device to be evaluated 20), and a plurality of semiconductor integrated circuits provided as separate devices may be tested by the test device 10. .

Each of the semiconductor integrated circuits 23-1 to 23-4 has a first signal path (P1 in FIG. 3) for transmitting and receiving signals between an external circuit and an internal circuit, and a signal path for transmitting signals between the external circuit and the internal circuit. and a second signal path (P2 in FIG. 3) for transmission and reception. Each of the semiconductor integrated circuits 23-1 to 23-4 is capable of selectively transmitting a signal received from the outside on the first signal path (basic interface side) to the outside from the second signal path (redundant interface side). Can be set to operating mode. First signal paths of semiconductor integrated circuits 23-1, 23-2, 23-3 and 23-4 are connected to basic interface connectors 21-1, 21-3, 21-5 and 21-7, respectively. . Second signal paths of semiconductor integrated circuits 23-1, 23-2, 23-3 and 23-4 are connected to redundant interface connectors 21-2, 21-4, 21-6 and 21-8, respectively. . A semiconductor integrated circuit 13 of the test apparatus 10 is connected to a basic interface connector 11-1 and a redundant interface connector 11-2.

In FIG. 1, each signal line may be a serial signal line capable of transmitting and receiving signals in both directions. For example, the transmitting side is provided with a pair of two signal lines for differential signal transmission, and the receiving side is also provided with a pair of two signal lines for differential signal transmission. , may transmit and receive signals serially. In this case, the devices on the transmitting and receiving sides have a function of signal conversion between parallel data and serial data, and may transmit the serial data signal via the signal line.

A basic interface and a redundant interface are two interfaces having the same configuration. For example, the same signal may be transmitted and received twice between semiconductor integrated circuits communicating via these two interfaces. In this configuration, even when one communication path fails, communication can be performed via the other communication path, thereby ensuring the reliability of communication. For example, when a processor or the like is connected to the device under evaluation 20 and the semiconductor integrated circuits 23-1 to 23-4 are configured to normally operate as memory controllers, the basic interface and the redundant interface have the same configuration. can be used as a signal path for

In the test system shown in FIG. 1, signal lines such as cables are used to connect the basic interface and the redundant interface between the adjacent semiconductor integrated circuits 23-1 to 23-4 in order to efficiently perform the test. to connect. This forms one propagation path in which the semiconductor integrated circuits 23-1 to 23-4 are cascaded. The four semiconductor integrated circuits 23 - 1 to 23 - 4 chained in this manner are connected to two input/output points of the semiconductor integrated circuit 13 .

Specifically, among the four semiconductor integrated circuits 23-1 to 23-4, the second signal path (redundant interface side) and the (i+1)-th and the first signal path (basic interface side) in the semiconductor integrated circuit. Thus, four semiconductor integrated circuits 23-1 to 23-4 are cascaded to form one propagation path. A first signal path of the first semiconductor integrated circuit 23-1 is connected to the semiconductor integrated circuit 13 on the side of the test apparatus 10 via basic interface connectors 21-1 and 11-1. The second signal path of the fourth semiconductor integrated circuit 23-4 is connected to the semiconductor integrated circuit 13 on the test apparatus 10 side via redundant interface connectors 21-8 and 11-2.

In the above connected state configuration, the test apparatus 10 performs the operation test of the semiconductor integrated circuits 23-1 to 23-4 together with the connection test of the basic interface connector and the redundant interface connector. First, by using the test apparatus 10 to sequentially propagate a setting command from one end (21-1) of one propagation path to four semiconductor integrated circuits 23-1 to 23-4 via one propagation path, Four semiconductor integrated circuits 23-1 to 23-4 are set to the test operation mode.

As described above, the test operation mode means that in each of the semiconductor integrated circuits 23-1 to 23-4, a signal received from the outside on the first signal path is selectively sent to the outside from the second signal path. It is an operation mode in which a transfer operation to send can be executed. Specifically, when the setting command is supplied to the first signal path (basic interface side) of the i-th semiconductor integrated circuit, the semiconductor integrated circuit is set to the test operation mode. By setting the i-th semiconductor integrated circuit to the test operation mode, the setting command is transferred from the first signal path (basic interface side) to the second signal path (redundant interface side) and output. The next (i+1)-th semiconductor integrated circuit receives the setting command transferred from the redundant interface side of the i-th semiconductor integrated circuit on the basic interface side, and is set to the test operation mode like the i-th semiconductor integrated circuit. and transfer the setting command to the next stage.

After the above setting, the test apparatus 10 sequentially propagates the operation command from the one end (21-1) to the four semiconductor integrated circuits 23-1 to 23-4 via one propagation path. As a result, each of the four semiconductor integrated circuits 23-1 to 23-4 is caused to operate the internal circuit based on the operation command. In each of the four semiconductor integrated circuits 23-1 to 23-4, data corresponding to the operation of the internal circuit executed based on the operation command is propagated through one propagation path. is taken into the test apparatus 10 from the other end (21-8). By executing the above operations, the semiconductor integrated circuits 23-1 to 23-4 can be tested.

If data indicating operation completion is not loaded into the test apparatus 10 as the data, or if data indicating an error is loaded into the test apparatus 10 as the data, the test apparatus 10 collects information about the failure from the device under evaluation 20. perform the action to be performed. Specifically, information indicating the status of the four semiconductor integrated circuits 23-1 to 23-4 is propagated through one propagation path, and the information is collected into the test apparatus 10. FIG. As a result, it is possible to collect detailed information indicating the location of the failure, the type of failure, and the like, and appropriately use the collected information to identify and solve the problem.

The test operation outlined above will be described in detail later.

FIG. 2 is a diagram showing an example of the configuration of the test apparatus 10. As shown in FIG. In FIG. 2 and subsequent similar figures, the boundaries between each functional block and other functional blocks indicated by each box basically indicate functional boundaries, such as separation of physical positions, electrical It does not necessarily correspond to logical signal separation, control logical separation, and the like. The illustrated device may have a hardware configuration realized by combining electronic circuit blocks having the functions of each functional block, or software that realizes the functions of each functional block by executing software in a general-purpose processor, which is an electronic circuit. may be configured. In the case of hardware, each functional block may be a single hardware module physically separated from other blocks to some extent, or may be a hardware module physically integrated with other blocks. It may represent one function. In the case of software, each functional block may be a single software module logically separated to some extent from other blocks, or a single function within a soft module logically integrated with other blocks. may be shown.

The semiconductor integrated circuit 13 includes a write/read circuit 14 , an information command transmission/reception circuit 15 , a setting command transmission circuit 16 and a selection circuit 17 . The setting command transmission circuit 16 transmits setting commands for test operations of the semiconductor integrated circuits 23-1 to 23-4. Setting commands are supplied to the semiconductor integrated circuits 23-1 to 23-4 via the selection circuit 17 from the basic interface connector 11-1 or the redundant interface connector 11-2. The setting command sets the four semiconductor integrated circuits 23-1 to 23-4 to the test operation mode.

The direction in which the above setting commands are propagated to the semiconductor integrated circuits 23-1 to 23-4 has been explained as being the direction from the basic interface connector 21-1 to the redundant interface connector 21-8 (forward direction). As for the signal propagation direction, as will be described later, in addition to the forward direction, the signal may be similarly propagated in the reverse direction from the redundant interface connector 21-8 to the basic interface connector 21-1. By allowing signals to propagate in both directions for testing, more reliable testing can be performed.

The write/read circuit 14 is a circuit that performs write and read operations on the semiconductor integrated circuits 23-1 to 23-4 in order to test the semiconductor integrated circuits 23-1 to 23-4. The write and read circuit 14 receives an operation command instructing a write operation or a read operation from the basic interface connector 11-1 or the redundant interface connector 11-2 via the selection circuit 17 to the semiconductor integrated circuits 23-1 to 23-4. Send to This operation command corresponds to an SREQ command, which will be described later. The write/read circuit 14 also reads read data read from the semiconductor integrated circuits 23 - 1 to 23 - 4 via the basic interface connector 11 - 1 or the redundant interface connector 11 - 2 and the selection circuit 17 .

In each of the four semiconductor integrated circuits 23-1 to 23-4 provided on the side of the device under evaluation 20, the internal circuit executes an operation based on the operation command. When the semiconductor integrated circuits 23-1 to 23-4 are circuits that read/write data from/to the shared memory 25, this operation consists of writing data to the shared memory 25 according to the first instruction, and writing data to the shared memory 25 according to the next instruction. It may be an operation of reading the data from the shared memory 25 in response to the request. By comparing written data and read data in the write/read circuit 14, the operation of the semiconductor integrated circuits 23-1 to 23-4 can be confirmed. The write/read circuit 14 may supply the detected error information to the information command transmission/reception circuit 15 .

The information command transmitting/receiving circuit 15 transmits an information command in order to collect information about failures from the device under evaluation 20 . Information commands are supplied to the semiconductor integrated circuits 23-1 through 23-4 via the selection circuit 17 from the basic interface connector 11-1 or the redundant interface connector 11-2. By operating the semiconductor integrated circuits 23-1 to 23-4 in response to this information command, error information indicating the status of failures, etc., is propagated through the propagation path of the chain connection and captured by the test apparatus 10. be Error information or the like may be received by the information command transmission/reception circuit 15 as an information response command.

An operator can manually read data such as error information from the information command transmission/reception circuit 15 and set a setting command to the setting command transmission circuit 16 from outside the test apparatus 10 . At this time, data may be read and written (set) by a method such as JTAG (Joint Test Action Group).

FIG. 3 is a diagram showing an example of the configuration of a semiconductor integrated circuit. Although FIG. 3 shows the configuration of the semiconductor integrated circuit 23-1 as a representative, the semiconductor integrated circuits 23-2 to 23-4 may also have the same configuration.

The semiconductor integrated circuit 23 - 1 includes a command detection circuit 30 , an input selection circuit 31 , an output selection circuit 32 , a command detection circuit 33 , an input selection circuit 34 , an output selection circuit 35 , an internal circuit 36 and a selection circuit 37 . The semiconductor integrated circuit 23-1 further includes a plurality of registers (flags). These registers are TEST-MODE register 38-1, TEST-RVS register 38-2, TEST-FIRST register 38-3, TEST-LAST register 38-4, output flag register 38-5, and error information register 38- including 6.

The internal circuit 36 is a circuit having various functions to be executed by the semiconductor integrated circuit 23-1 during normal operation. The first signal path P1 transmits and receives signals between the outside (the side of the basic interface connector 21-1) and the internal circuit . The second signal path P2 transmits and receives signals between the outside (redundant interface connector 21-2 side) and the internal circuit . When the semiconductor integrated circuit 23-1 is a memory controller, the internal circuit 36 performs data write operation and data read operation with respect to the shared memory 25 as a memory controller. During normal operation, the first signal path P 1 and the second signal path P 2 may be used to duplicate the same data between the external and internal circuitry 36 . During the test operation, the input selection circuit 31, the output selection circuit 32, the input selection circuit 34, and the output selection circuit 35 pass data from one of the first signal path P1 and the second signal path P2 to the other. Data can be transferred without going through the internal circuit 36 .

The command detection circuit 30 detects a command received from the outside through the basic interface connector 21-1 on the first signal path P1. The command detection circuit 30 appropriately sets data in the registers 38-1 to 38-4 according to the decoding result of the received command. That is, the registers 38-1 to 38-4 store command detection results (decode results) by the command detection circuit 30. FIG.

Specifically, when the command detection circuit 30 receives a setting command for setting the test operation, a value (for example, "1") designating the test operation is set in the TEST-MODE register 38-1. A value of "1" in the TEST-MODE register 38-1 indicates test operation, and a value of "0" indicates normal operation. When the test operation is performed in the reverse direction, when the command detection circuit 30 receives a setting command or the like indicating it, a value (for example, "1") designating the reverse direction is also set in the TEST-RVS register 38-2. . Here, the opposite direction means the direction from the redundant interface connector 21-8 to the basic interface connector 21-1 in FIG. 1, as described above. When the test operation is carried out by propagating signals in the forward direction (the direction from the basic interface connector 21-1 to the redundant interface connector 21-8 in FIG. 1), the TEST-RVS register 38-2 contains the value "0". may be set.

The selection circuit 37 outputs a signal S-TF indicating a forward test and a signal S-TR indicating a reverse test according to the values of the TEST-MODE register 38-1 and the TEST-RVS register 38-2. . As shown in FIG. 9, when the value of the TEST-MODE register 38-1 is "0" (normal operation), both the signal S-TF and the signal S-TR are "0". When the TEST-MODE register 38-1 is "1" and the TEST-RVS register 38-2 is "0", the signals S-TF and S-TR are "1" and "0". When the TEST-MODE register 38-1 is "1" and the TEST-RVS register 38-2 is "1", the signals S-TF and S-TR are "0" and "1".

In the following, a case in which a signal is propagated in the forward direction and a test is performed will be described.

When the command detection results of the registers 38-1 and 38-2 indicate the test operation (forward direction), the input selection circuit 31 and the output selection circuit 32 select the signal received from the outside on the first signal path P1 as the second signal. A transfer operation is executed to transmit to the outside from the signal path P2. A signal S-TF indicating a forward test is input to the input selection circuit 31 and the output selection circuit 32, and based on the value of this signal S-TF, an operation corresponding to the command detection result is executed. The input selection circuit 31 and the output selection circuit 32 do not perform the above transfer operation when the command detection result of the registers 38-1 and 38-2 does not indicate test operation (that is, during normal operation). Therefore, during normal operation, the first signal path P1 and the second signal path P2 operate independently of each other between the external circuit and the internal circuit 36. FIG.

The input selection circuit 31 selectively inputs a signal received from the outside on the first signal path P1 to the internal circuit 36 according to the command detection results of the registers 38-1 and 38-2, and selectively inputs it to the internal circuit 36. 2 signal path P2. Specifically, during test operation, the received signal is supplied to the internal circuit 36 and transferred to the second signal path P2, and during normal operation, the received signal is supplied to the internal circuit 36 and transferred to the second signal path P2. Do not forward. As will be described later, during the test operation, instead of supplying all the received signals (commands and data) to the internal circuit 36, some of the received signals (commands and data) are selectively supplied to the internal circuit 36. You can

The output selection circuit 32 selectively transmits the signal output from the internal circuit 36 to the outside according to the command detection result of the registers 38-1 and 38-2 on the second signal path P2, and selects the input signal. It selectively transmits the signal transferred from the circuit 31 to the outside. Specifically, during the test operation, the signal output from the internal circuit 36 is selectively transmitted to the outside and the signal transferred from the input selection circuit 31 is selectively transmitted to the outside, and during the normal operation, the internal circuit The signal output from 36 is transmitted to the outside.

The command detection circuit 33, the input selection circuit 34, and the output selection circuit 35 are arranged in the above-described command detection circuit 30, input selection circuit 31, and output selection circuit when the test operation is performed by propagating signals in the reverse direction. 32, respectively. In order to improve reliability, the circuit and signal path for the test operation including the command detection circuit 30, the input selection circuit 31, the output selection circuit 32, the command detection circuit 33, the input selection circuit 34, and the output selection circuit 35 are A redundant configuration (configuration provided in duplicate) may be employed.

The TEST-FIRST register 38-3 and the TEST-LAST register 38-4 are registers whose values are set according to where the semiconductor integrated circuit is positioned in one chain-connected propagation path. The TEST-FIRST register 38-3 of the first semiconductor integrated circuit 23-1 in the order of arrangement on the chain connection is set to a value (for example, "1") indicating that it is the first. The TEST-LAST register 38-4 of the semiconductor integrated circuit 23-4 at the end of the chain connection is set to a value (for example, "1") indicating the end. The TEST-LAST register 38-4 is set to the value "0" in the semiconductor integrated circuit 23-1, and the TEST-FIRST register 38-3 is set to the value "0" in the semiconductor integrated circuit 23-4. In other semiconductor integrated circuits 23-2 and 23-3, both the TEST-FIRST register 38-3 and the TEST-LAST register 38-4 are set to the value "0". How to set these register values and control based on these register values will be described later in detail.

FIG. 4 is a diagram showing an example of a command sequence exchanged between the testing apparatus 10 and the device under evaluation 20 during test operation. First, the write operation shown in FIG. 4(a) is performed, and then the read operation shown in FIG. 4(b) is performed.

As shown in FIG. 4A, first, a setting command (CMD (setting) shown in the drawing) is transmitted from the testing apparatus 10 to the device under evaluation 20 . After completing the setting, the test apparatus 10 issues a START-REQUEST command (CMD (SREQ) shown in the figure). In the write operation, the test apparatus 10 transmits the write data (DATA (write)) following the SREQ command, and after transmitting all the write data, transmits the LAST-DATA-FLAG command (CMD (LDF) shown in the figure). issue. After writing the received write data to the shared memory 25, the device under evaluation 20 transmits a TERM command (CMD (TERM) shown in the figure) indicating the completion of the write operation. Upon receiving the TERM command, the test apparatus 10 determines the end of the write command, and then executes the read operation.

As shown in FIG. 4(b), when the test device 10 issues an SREQ command (CMD (SREQ) shown in the figure) specifying a read operation, the device under test 20 responds to this with read data ( DATA (read) shown in the drawing is transmitted to the test apparatus 10 . After transmitting the read data, the device under evaluation 20 issues a TERM command (CMD (TERM) shown in the figure) indicating completion of the read operation. The test apparatus 10 determines whether there is a failure by comparing the write data and the read data. When determining that there is a failure, the test apparatus 10 transmits an information command (CMD (information) shown in the diagram) to the evaluated apparatus 20 . In response to the information command, the device under evaluation 20 returns error information indicating the status and details of the failure to the test device 10 as an information command (CMD (information response) shown in the figure). The test device 10 and the operator can evaluate the state of the device under evaluation 20 based on the error information.

FIG. 5 is a flow chart showing an example of test operation by the test system shown in FIG. In FIG. 5, the execution order of each step described in the flowchart is merely an example, and the technical scope intended by the present application is not limited to the described execution order. For example, even if the application describes step B as being performed after step A, it is possible not only to perform step B after step A, but also to perform step A after step B. It may be physically and logically possible to do so. In this case, if all the results affecting the processing of the flowchart are the same regardless of the order in which the steps are executed, then for the purpose of the technology disclosed in the present application, step B is followed by step A. may be performed. Even if the present application describes that step B is executed after step A, it is not intended to exclude obvious cases such as the above from the intended technical scope of the present application. If it is obvious, it naturally falls within the technical scope intended by the present application.

In step S1, the operator inputs a setting command to the semiconductor integrated circuit 13 of the test apparatus 10 using a JTAG command or the like. The setting command is a TEST-MODE register 38-1, a TEST-RVS register 38-2, a TEST-FIRST register 38-3, and a TEST-LAST register 38-4 for the semiconductor integrated circuits 23-1 to 23-4. It is for setting such as.

At step S2, the test apparatus 10 starts a test operation procedure. At step S3, the test apparatus 10 first issues a setting command. Upon receiving the setting command, the semiconductor integrated circuit 23-1 performs settings related to the test operation for each register according to the command detection result (decoding result), and also sends the setting command to the next-stage semiconductor integrated circuit 23-2. Forward. The semiconductor integrated circuits 23-2 to 23-4 in the subsequent stages repeat the same operation as the semiconductor integrated circuit 23-1. The setting command sets the TEST-MODE register 38-1 and the TEST-RVS register 38-2 to the same value (for example, a value indicating forward test operation) in all semiconductor integrated circuits. In the semiconductor integrated circuit 23-1, the TEST-FIRST register 38-3 is set to a value "1" indicating that it is at the beginning, and in the semiconductor integrated circuit 23-4, the TEST-LAST register 38-4 is at the end. is set to a value "1" indicating that

FIG. 6 is a diagram showing an example of the configuration of a setting command. In this configuration command example, the configuration command is transmitted in a packet format having a header, payload, and tail. In the header part, a header code, a code indicating that the packet is a setting command, an instruction to set a test operation (TEST-MODE), an instruction to set a reverse test (RVS), and a head LSI are set. and an instruction (FIRST) to do so. The tail portion also includes a tail code indicating the end position of the packet.

In each of the semiconductor integrated circuits 23-1 to 23-4, the value "1" is set in the TEST-MODE register 38-1 according to the instruction (TEST-MODE) for setting the test operation contained in the header portion. good. Further, when the reverse direction test setting instruction (RVS) included in the header portion has the value "1", each of the semiconductor integrated circuits 23-1 to 23-4 stores the value "1" in the TEST-RVS register 38-2. ” can be set. When the reverse direction test setting instruction (RVS) has the value "0", each of the semiconductor integrated circuits 23-1 to 23-4 may set the value "0" in the TEST-RVS register 38-2. .

Each of the semiconductor integrated circuits 23-1 to 23-4 determines whether it is the leading semiconductor integrated circuit based on the instruction (FIRST) for setting the leading LSI included in the header portion. As an instruction (FIRST) to set the leading LSI, for example, a bit at a predetermined position in the header may be set to the value "1". The semiconductor integrated circuit 23-1 that first received the setting command sets the value "1" in the TEST-FIRST register 38-3 in response to the instruction to set the leading LSI, and at the same time puts the TEST-FIRST register 38-3 at the predetermined position in the header. Modify the value of a bit to "0". The semiconductor integrated circuit 23-1 transfers the corrected setting command to the semiconductor integrated circuits 23-2 to 23-4 in the subsequent stages. In the semiconductor integrated circuits 23-2 to 23-4 in the subsequent stages, since the value of the bit corresponding to the instruction to set the leading LSI in the received setting command is "0", they themselves are not the leading LSI. I can judge.

In the payload portion, the value "1" indicating the end semiconductor integrated circuit is set at the position corresponding to the LSI-ID of the semiconductor integrated circuit 23-4 at the end, and the other bit positions A value of "0" is set. In the example of the test system shown in FIG. 1, it is assumed that the semiconductor integrated circuits 23-1 to 23-4 are given LSI-IDs "1", "2", "3" and "4", respectively. In the payload portion, the value "1" indicating the end is set at the fourth bit position corresponding to the LSI-ID "4" of the semiconductor integrated circuit 23-4 at the end. Thereby, each of the semiconductor integrated circuits 23-1 to 23-4 can determine whether it is the last semiconductor integrated circuit.

FIG. 7 is a diagram showing another example of the configuration of the setting command. In this configuration command example, the configuration command is transmitted in a packet format having a header, payload, and tail. The header portion includes a header code, a code indicating that the packet is a setting command, an instruction to set a reverse direction test (RVS), and an instruction to set the top LSI (FIRST). The tail portion also includes a tail code indicating the end position of the packet.

For the TEST-RVS register 38-2 and the TEST-FIRST register 38-3, similarly to the setting command example shown in FIG. It may be set based on the instruction (FIRST).

The setting command example in FIG. 7 may be performed based on an instruction to set the leading LSI. The first 32 bits (32 bits in the first row) in the payload portion serve as TEST-MODE setting bits. In the setting command transmitted by the test apparatus 10, only the first bit of the TEST-MODE setting bits (first 32 bits) in the payload portion is set to the value "1" as shown in FIG. When the semiconductor integrated circuit 23-1 that has received this setting command detects the value "1" in any of the TEST-MODE setting bits, it sets the value "1" to the TEST-MODE register 38-1, Shift the TEST-MODE setting bit to the right by 1 bit. In the setting command received by the second semiconductor integrated circuit 23-2, only the second bit of the TEST-MODE setting bit in the payload portion is "1". When the semiconductor integrated circuit 23-2 that has received this setting command detects the value "1" in any of the TEST-MODE setting bits, it sets the value "1" to the TEST-MODE register 38-1, Shift the TEST-MODE setting bit to the right by 1 bit. In this manner, the positions of bits having a value of "1" in the TEST-MODE setting bits are sequentially shifted to the right.

The 32 bits in the second row in the payload portion serve as TEST-LAST setting bits. In each of the semiconductor integrated circuits 23-1 to 23-4, the position of the bit having the value "1" in the TEST-MODE setting bit matches the position of the bit having the value "1" in the TEST-LAST setting bit. When it receives a setting command, it determines that it is the last one. In the example shown in FIG. 7, since the fourth bit position in the TEST-LAST setting bit has a value of "1", only the semiconductor integrated circuit 23-4 determines that it is the last, A value of "1" is set in the LAST register 38-4.

Returning to FIG. 5, in step S4, the test apparatus 10 executes the write operation. Specifically, the test apparatus 10 issues an SREQ command for instructing writing to the semiconductor integrated circuits 23-1 to 23-4, write data, and an LDF command (LAST-DATA-FLAG command). In the semiconductor integrated circuits 23-1 to 23-4, the input selection circuit 31, the output selection circuit 32, the input selection circuit 34, and the output selection circuit 35 operating based on the set values of the registers 38-1 to 38-4 , command and data input and transfer operations are controlled.

FIG. 10 shows a table defining the operations of the input selection circuits 31 and 34. In FIG. By operating the input selection circuits 31 and 34 as shown in FIG. 10, each command and data are input to the internal circuit 36 of the semiconductor integrated circuits 23-1 to 23-4, and the semiconductor integrated circuit 23- 1 to 23-4. A signal S-TF and a signal S-TR shown in FIG. 10 are output from the selection circuit 37 as shown in FIG. 3, and are signals indicating the test operation mode and the test operation direction as described above. A signal S-INF and a signal S-TRF are signals output from the input selection circuit 31, and are an input signal to the internal circuit 36 and a transfer signal to the second signal path P2, respectively. A signal S-INR and a signal S-TRR are signals output from the input selection circuit 34, and are input signals to the internal circuit 36 and transfer signals to the first signal path P1, respectively.

As defined in FIG. 10, when both the signal S-TF and the signal S-TR are at the value "0", the normal operation mode is entered, so all commands and data received by the input selection circuit 31 are is input to the internal circuit 36 as an input signal S-INF or S-INR. At this time, the transfer signals S-TRF and S-TRR between the first signal path P1 and the second signal path P2 are suppressed.

In the test operation mode, for the first semiconductor integrated circuit (LSI1 shown in FIG. 10), all commands and data are input to the internal circuit 36 as S-INF or S-INR, and S-TRF or It is forwarded to the opposite signal path as S-TRR. Commands and data from the test apparatus 10 are input to the internal circuit 36 as S-INF or S-INR for semiconductor integrated circuits other than the top (LSI2 to LSI4 shown in FIG. 10). All commands and data are also transferred to the opposite signal path as S-TRF or S-TRR.

FIG. 11 shows a table defining the operation of output selection circuit 32. Referring to FIG. The operation of the output selection circuit 35 is the same. By operating the output selection circuit 32 as shown in FIG. 11, each command and data are transferred between the semiconductor integrated circuits 23-1 to 23-4, and the output data from the internal circuit 36 is transferred to the external circuit. sent to. The meanings of signals S-TF, S-TR, and S-TRF are as described above. The signal S-OUT is a signal output from the internal circuit 36 and input to the output selection circuit 32, as shown in FIG.

Note that, as shown in FIGS. 10 and 11, the command and data supply destinations are determined based on the position in the arrangement order of the semiconductor integrated circuits 23-1 to 23-4 (the position at the beginning or the end, etc.). The selective signal supply operation is realized by making the presence or absence of supply, etc. different. This avoids inputting unnecessary information and transferring unnecessary information, and realizes efficient and appropriate test operation.

In step S4 of FIG. 5, when the test device 10 executes a write operation, the semiconductor integrated circuits 23-1 to 23-4 receive an operation command instructing a write operation and write data from the test device 10. FIG. In the leading semiconductor integrated circuit 23-1, the signal S-TF and the TEST-FIRST register 38-3 are "1", so the received command and write data are sent to the internal circuit 36 as shown in FIG. It is input and transferred to the output selection circuit 32 on the side of the second signal path P2. The internal circuit 36 operates based on the input command and writes the write data to the shared memory 25 .

In the semiconductor integrated circuit 23-1, the TEST-FIRST register 38-3 has the value "1" and the TEST-LAST register 38-4 has the value "0". Therefore, in the output selection circuit 32 of the semiconductor integrated circuit 23-1, as shown in FIG. 11, the command and write data received as the signal S-TRF and the internal circuit 36 received as the signal S-OUT are output. Send the TERM command to the outside. When the TERM command is output, the output flag register 38-5 shown in FIG. 3 is set to "1". Also, when the internal circuit 36 generates error information, the error information is stored in the error information register 38-6.

The semiconductor integrated circuit 23-2 receives commands and write data from the semiconductor integrated circuit 23-1. In the semiconductor integrated circuit 23-2, the signal S-TF has the value "1" and the TEST-FIRST register 38-3 has the value "0". Therefore, as shown in FIG. 10, only commands and write data received from the test apparatus 10 are input to the internal circuit 36, and all received commands and write data are output selected on the side of the second signal path P2. Transferred to circuit 32 . The internal circuit 36 operates based on the input command and writes the write data to the shared memory 25 .

In the semiconductor integrated circuit 23-2, the TEST-FIRST register 38-3 has the value "0" and the TEST-LAST register 38-4 has the value "0". Therefore, in the output selection circuit 32 of the semiconductor integrated circuit 23-2, as shown in FIG. 11, the SREQ command, the LDF command, and the write data received as the signal S-TRF are transmitted to the outside. Also, the TERM command from the preceding stage semiconductor integrated circuit received as signal S-TRF is temporarily held and compared with the TERM command received from internal circuit 36 as signal S-OUT. Send the TERM command to the outside. If any one of the compared TERM commands contains error information, the TERM command including the error information is transmitted to the outside. When the TERM command is output, the output flag register 38-5 shown in FIG. 3 is set to "1". Also, when the internal circuit 36 generates error information, the error information is stored in the error information register 38-6.

The semiconductor integrated circuit 23-3 receives commands and write data from the semiconductor integrated circuit 23-2. The operation of the semiconductor integrated circuit 23-3 is the same as that of the semiconductor integrated circuit 23-2.

The semiconductor integrated circuit 23-4 receives commands and write data from the semiconductor integrated circuit 23-3. In the semiconductor integrated circuit 23-4, the signal S-TF has the value "1" and the TEST-FIRST register 38-3 has the value "0". Therefore, as shown in FIG. 10, only commands and write data received from the test apparatus 10 are input to the internal circuit 36, and all received commands and write data are output selected on the side of the second signal path P2. Transferred to circuit 32 . The internal circuit 36 operates based on the input command and writes the write data to the shared memory 25 .

In the semiconductor integrated circuit 23-4, the TEST-FIRST register 38-3 has the value "0" and the TEST-LAST register 38-4 has the value "1". Therefore, in the output selection circuit 32 of the semiconductor integrated circuit 23-4, as shown in FIG. 11, the SREQ command and the LDF command received as the signal S-TRF are transmitted to the outside. Discard the data. Also, the TERM command from the preceding stage semiconductor integrated circuit received as signal S-TRF is temporarily held and compared with the TERM command received from internal circuit 36 as signal S-OUT. Send the TERM command to the outside. If any one of the compared TERM commands contains error information, the TERM command including the error information is transmitted to the outside. When the TERM command is output, the output flag register 38-5 shown in FIG. 3 is set to the value "1". Also, when the internal circuit 36 generates error information, the error information is stored in the error information register 38-6.

At step S5 in FIG. 5, the test apparatus 10 determines whether or not the TERM command has been received. The test apparatus 10 repeats the TERM reception determination process of step S5 until the TERM command is received. Upon receiving the TERM command, the test apparatus 10 determines that the write command has been completed, and advances the process to step S6. Note that the SREQ command and LDF command sent from the device under evaluation 20 may be discarded in the test device 10 .

In step S6, the test apparatus 10 determines whether or not the TERM command contains error information. If no error information is included, it is determined that the write command has been completed normally, and the process proceeds to step S7.

In step S7, the test apparatus 10 issues an SREQ command instructing the device under test 20 to perform a read operation. In the leading semiconductor integrated circuit 23-1, the signal S-TF and the TEST-FIRST register 38-3 are "1", so the received command is input to the internal circuit 36 as shown in FIG. together with it is transferred to the output selection circuit 32 on the side of the second signal path P2. The internal circuit 36 operates based on the input command and reads data from the shared memory 25 .

In the semiconductor integrated circuit 23-1, the TEST-FIRST register 38-3 has the value "1" and the TEST-LAST register 38-4 has the value "0". Therefore, as shown in FIG. 11, the output selection circuit 32 of the semiconductor integrated circuit 23-1 selects the command received as the signal S-TRF and the TERM command output from the internal circuit 36 received as the signal S-OUT. Send externally. Also, the read data output from the internal circuit 36 received as the signal S-OUT is discarded. When the TERM command is output, the output flag register 38-5 shown in FIG. 3 is set to the value "1". Also, when the internal circuit 36 generates error information, the error information is stored in the error information register 38-6.

The read data is discarded because each of the semiconductor integrated circuits 23-1 to 23-4 reads data from the same address in the shared memory 25, and the data read by each is the same. The data read from the semiconductor integrated circuit 23-4 at the end of the chain connection should be sent to the test apparatus 10, and the data read from the other semiconductor integrated circuits 23-1 to 23-3 are discarded. You can put it away. However, the TERM command indicating whether or not the read data has been normally completed is transmitted to the test apparatus 10 after collation among the semiconductor integrated circuits 23-1 to 23-4. Therefore, based on this TERM command, it can be determined whether or not there is a problem in the read operation in the semiconductor integrated circuits 23-1 to 23-3 other than the end.

The semiconductor integrated circuit 23-2 receives commands from the semiconductor integrated circuit 23-1. In the semiconductor integrated circuit 23-2, the signal S-TF has the value "1" and the TEST-FIRST register 38-3 has the value "0". Therefore, as shown in FIG. 10, only commands received from the test apparatus 10 are input to the internal circuit 36, and all received commands are transferred to the output selection circuit 32 on the side of the second signal path P2. . The internal circuit 36 operates based on the input command and reads data from the shared memory 25 .

In the semiconductor integrated circuit 23-2, the TEST-FIRST register 38-3 has the value "0" and the TEST-LAST register 38-4 has the value "0". Therefore, in the output selection circuit 32 of the semiconductor integrated circuit 23-2, as shown in FIG. 11, the SREQ command received as the signal S-TRF is transmitted to the outside. Also, the TERM command from the preceding stage semiconductor integrated circuit received as signal S-TRF is temporarily held and compared with the TERM command received from internal circuit 36 as signal S-OUT. Send the TERM command to the outside. If any one of the compared TERM commands contains error information, the TERM command including the error information is transmitted to the outside. Also, the read data output from the internal circuit 36 received as the signal S-OUT is discarded. When the TERM command is output, the output flag register 38-5 shown in FIG. 3 is set to the value "1". Also, when the internal circuit 36 generates error information, the error information is stored in the error information register 38-6.

The semiconductor integrated circuit 23-3 receives commands from the semiconductor integrated circuit 23-2. The operation of the semiconductor integrated circuit 23-3 is the same as that of the semiconductor integrated circuit 23-2.

The semiconductor integrated circuit 23-4 receives commands from the semiconductor integrated circuit 23-3. In the semiconductor integrated circuit 23-4, the signal S-TF has the value "1" and the TEST-FIRST register 38-3 has the value "0". Therefore, as shown in FIG. 10, only commands received from the test apparatus 10 are input to the internal circuit 36, and all received commands are transferred to the output selection circuit 32 on the side of the second signal path P2. . The internal circuit 36 operates based on the input command and reads data from the shared memory 25 .

In the semiconductor integrated circuit 23-4, the TEST-FIRST register 38-3 has the value "0" and the TEST-LAST register 38-4 has the value "1". Therefore, in the output selection circuit 32 of the semiconductor integrated circuit 23-4, as shown in FIG. 11, the SREQ command received as the signal S-TRF is transmitted to the outside. Also, the TERM command from the preceding stage semiconductor integrated circuit received as signal S-TRF is temporarily held and compared with the TERM command received from internal circuit 36 as signal S-OUT. Send the TERM command to the outside. If any one of the compared TERM commands contains error information, the TERM command including the error information is transmitted to the outside. The read data output from the internal circuit 36 received as the signal S-OUT is transmitted to the outside. When the TERM command is output, the output flag register 38-5 shown in FIG. 3 is set to the value "1". Also, when the internal circuit 36 generates error information, the error information is stored in the error information register 38-6.

At step S8 in FIG. 5, the test apparatus 10 determines whether or not the TERM command has been received. The test apparatus 10 repeats the TERM reception determination process of step S8 until the TERM command is received. Upon receiving the TERM command, the test apparatus 10 determines that the read command is completed, and advances the process to step S9. Note that the SREQ command sent from the device under evaluation 20 may be discarded in the test device 10 .

In step S9, the test apparatus 10 determines whether or not the TERM command contains error information. If no error information is included, it is determined that the read command has been completed normally, and the process proceeds to step S10.

In step S10, the test apparatus 10 compares write data and read data. In step S11, the test apparatus 10 determines whether the comparison result indicates data match. If data match is indicated, it is determined that there is no problem with the device under evaluation 20, and the test operation ends in step S12. If data mismatch is indicated, the operator investigates the fault occurring in the device under evaluation 20 in step S13.

In step S14, the test apparatus 10 monitors whether or not the TERM command indicating the execution result of the write operation has been received. If the TERM command is not received after the predetermined time has passed, the process proceeds to step S16. If it is detected in step S6 that the TERM command contains error information, the process also proceeds to step S16.

Similarly, in step S15, the test apparatus 10 monitors whether or not a TERM command indicating the execution result of the read operation has been received. If the TERM command is not received after the predetermined time has passed, the process proceeds to step S16. If it is detected in step S9 that the TERM command contains error information, the process also proceeds to step S16.

In step S16, the test apparatus 10 determines whether or not error information has been detected (that is, whether error information detection or time overrun has occurred). If the time has expired, the process proceeds to step S17. In the case of error information detection, the process skips step S17 and proceeds to step S18.

In step S17, the test apparatus 10 changes the direction of propagating the information command for collecting information about the failure status of the semiconductor integrated circuits 23-1 to 23-4 to the previously executed test operation (set operation, write operation). operation, read operation). Specifically, the test apparatus 10 issues to the device under evaluation 20 a setting command for setting the test operation in the reverse direction (a command in which RVS is set to "1" in FIG. 6).

When the TERM command including the error information is received and the error information is detected, it is guaranteed that at least the signal propagation path is normally propagating the signal. On the other hand, if the TERM command is not received within the predetermined time and the time is exceeded, there is a possibility that there is a problem in the signal propagation path and the signal is not normally transmitted. In this case, even if an attempt is made to collect information about the failure using the signal lines in the same direction, the information may not be collected and the time may run out again. If it is determined that the time is exceeded, the direction of signal propagation is reversed for the information gathering operation as described above, and the forward signal line used in the previous test operation, for example, is used. Information gathering operation is performed using the signal line. As a result, it is possible to increase the possibility that the information gathering operation will be successful.

In step S<b>18 , the test device 10 issues an information command to the device under evaluation 20 . The direction in which this information command propagates through the semiconductor integrated circuits 23-1 to 23-4 is the forward direction when time overrun does not occur, and is the forward direction when time overrun occurs, as described above. in the opposite direction.

FIG. 8 is a diagram showing an example of the configuration of an information command. In this information command example, the configuration command is transmitted in a packet format having a header, payload, and tail. The header portion includes a header code and a code indicating that the packet is an information command. The tail portion also includes a tail code indicating the end position of the packet.

The payload portion includes information collection areas E1 to E16 for copying and storing the stored values of the output flag register 38-5 and the error information register 38-6 in each of the semiconductor integrated circuits 23-1 to 23-4. is provided. Each of the information collection areas E1 to E16 is a 2-bit width area. For example, the information collection area E1 stores the value of the output flag register 38-5 and the value of the error information register 38-6 in the first semiconductor integrated circuit (23-1 or 23-4) in the information collection direction. The values of the output flag register 38-5 and the value of the error information register 38-6 in each semiconductor integrated circuit are sequentially stored in the information collection areas E1 to E16. In the case of the configuration example shown in FIG. 1, the value of the output flag register 38-5 and the error information register 38 in the last semiconductor integrated circuit (23-1 or 23-4) in the information gathering direction are stored in the information gathering area E4. A value of -6 is stored. When 16 information collection areas E1 to E16 are provided, information can be collected for 16 semiconductor integrated circuits.

As described above, the information command in which the output flag value and the error information value are stored in the information collection areas E1 to E16 is returned to the test apparatus 10 as an information response command. The test apparatus 10 can obtain information about the failure of the device under evaluation 20 by examining the values stored in the information collection areas E1 to E16 in the information response command.

For example, assume that a command issued by the test apparatus 10 cannot be completed due to an interface failure between the semiconductor integrated circuits 23-1 and 23-2. In this case, since the semiconductor integrated circuit 23-1 normally outputs the command, the value of the output flag register 38-5 is "1". However, in the semiconductor integrated circuit 23-2, since the output selection circuit 32 has not received the command, the value of the output flag register 38-5 is "0". In this state, by reading the value of each output flag register 38-5 with the information command, it can be found that there is a fault in the interface between the semiconductor integrated circuit 23-1 and the semiconductor integrated circuit 23-2.

Although the present invention has been described above based on the embodiments, the present invention is not limited to the above embodiments, and various modifications are possible within the scope of the claims.

10 Test device 20 Evaluated device 25 Shared memory 26 Error information management device 30 Command detection circuit 31 Input selection circuit 32 Output selection circuit 33 Command detection circuit 34 Input selection circuit 35 Output selection circuit 36 Internal circuit 37 Selection circuit

Claims (4)

an internal circuit;
a first signal path for transmitting and receiving signals between the outside and the internal circuit;
a second signal path for transmitting and receiving signals between the outside and the internal circuit;
a first command detection circuit for detecting an externally received command on the first signal path;
a register for storing a command detection result by the first command detection circuit;
including
When the command detection result of the register indicates a test operation in response to a setting command received from the outside , the setting command and the signal received from the outside on the first signal path are transmitted to the outside from the second signal path. and if the command detection result of the register does not indicate the test operation, the first signal path and the second signal path are operated independently of each other without performing the transfer operation. Semiconductor integrated circuit. a signal externally received on the first signal path is selectively input to the internal circuit and selectively transferred to the second signal path according to the command detection result of the register; an input selection circuit;
In the second signal path, according to the command detection result of the register, the signal output from the internal circuit is selectively transmitted to the outside, and the signal transferred from the first input selection circuit is transmitted to the outside. a first output selection circuit that selectively transmits to the outside, and performs the transfer operation by transferring a signal between the first input selection circuit and the first output selection circuit; 2. The semiconductor integrated circuit according to claim 1. It further includes a second command detection circuit that detects a command received from the outside on the second signal path, the register can store a command detection result by the second command detection circuit, and the command in the register can be stored. 3. The device according to claim 1 or 2, wherein, when the detection result indicates a reverse test operation, a reverse transfer operation is performed to transmit a signal received from the outside on the second signal path to the outside from the first signal path. Semiconductor integrated circuit. a signal externally received on the second signal path is selectively input to the internal circuit and selectively transferred to the first signal path according to the command detection result of the register; an input selection circuit;
In the first signal path, according to the command detection result of the register, the signal output from the internal circuit is selectively transmitted to the outside, and the signal transferred from the second input selection circuit is transmitted to the outside. and a second output selection circuit for selectively transmitting to the outside, and executing the backward transfer operation by transferring a signal between the second input selection circuit and the second output selection circuit. 4. The semiconductor integrated circuit according to claim 3, wherein:

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