JP7315667B2 - 量子コンピューティング・デバイスのフリップ・チップ・アセンブリ - Google Patents
量子コンピューティング・デバイスのフリップ・チップ・アセンブリ Download PDFInfo
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- JP7315667B2 JP7315667B2 JP2021518131A JP2021518131A JP7315667B2 JP 7315667 B2 JP7315667 B2 JP 7315667B2 JP 2021518131 A JP2021518131 A JP 2021518131A JP 2021518131 A JP2021518131 A JP 2021518131A JP 7315667 B2 JP7315667 B2 JP 7315667B2
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Description
Claims (18)
- 量子デバイスであって、
1組のビアを含むインターポーザ層と、
前記インターポーザ層の第1の側に形成された誘電体層であって、前記1組のビアに通信可能に結合された1組の伝送線を含む、前記誘電体層と、
前記インターポーザ層の反対側に結合された複数のキュービット・チップであって、各キュービット・チップが、
前記キュービット・チップの第1の側の複数のキュービット、および
前記キュービット・チップの第2の側の複数の突起を含む、前記複数のキュービット・チップと、
前記複数のキュービット・チップに熱的に結合された第1のヒート・シンクであって、前記複数のキュービット・チップの前記複数の突起に位置合わせされた複数の凹部を含む、前記第1のヒート・シンクと、
前記1組の伝送線に通信可能に結合された信号コネクタと、
前記誘電体層に結合された第2のヒート・シンクを含み、
前記第2のヒート・シンクは、前記信号コネクタと前記誘電体層との間に配置され、
前記信号コネクタは、1組の締め具によって前記第1のヒート・シンクに結合されている、量子デバイス。 - 前記複数の突起の形状は、前記複数の突起が前記複数の凹部と自己整合するように構成されている、請求項1に記載の量子デバイス。
- 前記複数の突起はピラミッド形状を有する、請求項1ないし2のいずれかに記載の量子デバイス。
- 各パッドが対応するキュービットに接続された、前記複数のキュービット・チップ上の第1の組のパッドと、
前記インターポーザ層上の第2の組のパッドであって、前記ビアに形成された、前記第2の組のパッドとをさらに含む、請求項1ないし3のいずれかに記載の量子デバイス。 - 前記第2の組のパッド上に配置された第1の層と、
前記第1の層上に配置され、前記第1の組のパッドと前記第2の組のパッドとを接着するように構成された1組のはんだバンプとをさらに含む、請求項4に記載の量子デバイス。 - 前記1組のはんだバンプは、インジウムと、スズと、ビスマスとを含む組から選択された少なくとも1つの要素からなる、請求項5に記載の量子デバイス。
- 前記複数のキュービット・チップの前記複数の突起上に配置された第1の層と、
前記第1のヒート・シンクの前記複数の凹部に配置された第2の層とをさらに含む、請求項1ないし3のいずれかに記載の量子デバイス。 - 前記第1の層は、チタンと、銀と、銅と、プラチナと、金とを含む組から選択された少なくとも1つの要素からなる、請求項7に記載の量子デバイス。
- 前記第2の層は、チタンと、銀と、銅と、プラチナと、金とを含む組から選択された少なくとも1つの要素からなる、請求項7または8に記載の量子デバイス。
- 方法であって、
1組のビアを含むインターポーザ層を形成することと、
前記インターポーザ層の第1の側に形成される誘電体層を形成することであって、前記誘電体層が前記1組のビアに通信可能に結合された1組の伝送線を含む、前記誘電体層を形成することと、
複数のキュービット・チップ上に複数の突起を形成することと、
前記インターポーザ層の反対側に前記複数のキュービット・チップを結合することと、
第1のヒート・シンクに複数の凹部を形成することと、
前記複数の凹部が前記複数の突起と位置合わせさるように、前記複数のキュービット・チップを前記第1のヒート・シンクに結合することと、
前記誘電体層に第2のヒート・シンクを結合することと、
前記1組の伝送線に信号コネクタを通信可能に結合し、前記第2のヒート・シンクを前記信号コネクタと前記誘電体層との間に配置することと、
1組の締め具によって前記信号コネクタを前記第1のヒート・シンクに結合することを含む、方法。 - 前記複数の突起の形状は、前記複数の突起が前記複数の凹部と自己整合するように構成される、請求項10に記載の方法。
- 接着剤を使用して前記誘電体層にハンドラを取り付けることと、
前記インターポーザ層の反対側において前記1組のビアを露出させるように前記インターポーザ層の厚さを薄くすることとをさらに含む、請求項10または11に記載の方法。 - 前記複数のキュービット・チップを前記インターポーザ層に結合した後で、前記インターポーザ層から前記ハンドラを取り去ることをさらに含む、請求項12に記載の方法。
- 前記複数のキュービット・チップ上に第1の組のパッドを堆積させることと、
前記インターポーザ層上に第2の組のパッドを堆積させることであって、前記第2の組のパッドがビア上に堆積される、前記第2の組のパッドを堆積させることとをさらに含む、請求項10ないし13のいずれかに記載の方法。 - 前記第2の組のパッド上に第1の層を堆積させることと、
前記第1の層上に1組のはんだバンプを堆積させることであって、前記1組のはんだバンプは前記第1の組のパッドと前記第2の組のパッドとを接着するように構成される、前記1組のはんだバンプを堆積させることとをさらに含む、請求項14に記載の方法。 - 前記複数のキュービット・チップの前記複数の突起上に第1の層を堆積させることと、
前記第1のヒート・シンクの前記複数の凹部に第2の層を堆積させることとをさらに含む、請求項10ないし15のいずれかに記載の方法。 - 前記第1の層は、チタンと、銀と、銅と、プラチナと、金とを含む組から選択された少なくとも1つの要素からなる、請求項16に記載の方法。
- 前記第2の層は、チタンと、銀と、銅と、プラチナと、金とを含む組から選択された少なくとも1つの要素からなる、請求項16または17に記載の方法。
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US16/188,466 US10692795B2 (en) | 2018-11-13 | 2018-11-13 | Flip chip assembly of quantum computing devices |
US16/188,466 | 2018-11-13 | ||
PCT/EP2019/080173 WO2020099171A1 (en) | 2018-11-13 | 2019-11-05 | Quantum computing device coupled to an interposer and a heat sink |
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TW202038266A (zh) * | 2018-11-26 | 2020-10-16 | 瑞典商斯莫勒科技公司 | 具有離散的能量儲存構件之半導體組件 |
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US11158781B2 (en) * | 2019-11-27 | 2021-10-26 | International Business Machines Corporation | Permanent wafer handlers with through silicon vias for thermalization and qubit modification |
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JP7456304B2 (ja) * | 2020-06-19 | 2024-03-27 | 日本電気株式会社 | 量子デバイス |
JP7552091B2 (ja) * | 2020-06-19 | 2024-09-18 | 日本電気株式会社 | 量子デバイス |
JP7528557B2 (ja) * | 2020-06-19 | 2024-08-06 | 日本電気株式会社 | 量子デバイス及びその製造方法 |
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US20230163080A1 (en) * | 2021-11-22 | 2023-05-25 | International Business Machines Corporation | Processor die alignment guides |
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WO2023152961A1 (ja) | 2022-02-14 | 2023-08-17 | 富士通株式会社 | 電子装置及び電子装置の製造方法 |
WO2024054693A2 (en) * | 2022-02-23 | 2024-03-14 | Rigetti & Co, Llc | Modular quantum processor configurations and module integration plate with inter-module connections for the same |
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