WO2018057024A1

WO2018057024A1 - Sintered silver heat exchanger for qubits

Info

Publication number: WO2018057024A1
Application number: PCT/US2016/053637
Authority: WO
Inventors: Ravi Pillarisetty; Hubert C. GEORGE; Jeanette M. Roberts; Nicole K. THOMAS; James S. Clarke
Original assignee: Intel Corporation
Priority date: 2016-09-26
Filing date: 2016-09-26
Publication date: 2018-03-29

Abstract

Described herein are qubit device packages which incorporate portions of electrical connections for supporting transport of charge carriers to/from the qubits. An exemplary package includes a die and a package substrate. The die includes a qubit device and has a first face with a plurality of conductive contacts. An opposing second face of the die is mechanically attached to a first face of the package substrate. The package further includes qubit level interconnects, i.e. conductive pathways provided within the same package as qubits of the qubit device of the die, electrically coupling conductive contacts at the first face of the die with associated conductive contacts at the first face of the package substrate. Providing qubit level interconnects ensures that these interconnects are kept at the same temperature level as the qubits of the die, advantageously allowing cooling of the charge carriers injected into the qubit device.

Description

SINTERED SILVER HEAT EXCHANGER FOR QUBITS

Technical Field

[0001] This disclosure relates generally to the field of quantum computing, and more specifically, to a sintered silver heat exchanger in quantum circuits.

Background

[0002] Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices.

Brief Description of the Drawings

[0003] To provide a more complete understanding of the present disclosure and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying figures, wherein like reference numerals represent like parts, in which:

[0004] FIGS. 1-3 are cross-sectional views of an exemplary device implementing quantum dot qubits, according to some embodiments of the present disclosure.

[0005] FIGS. 4-6 are cross-sectional views of various examples of quantum well stacks that may be used in a quantum dot device, according to some embodiments of the present disclosure.

[0006] FIGS. 7-13 illustrate example base/fin arrangements that may be used in a quantum dot device, according to some embodiments of the present disclosure.

[0007] FIG. 14 provides a schematic illustration of an exemplary device implementing superconducting qubits, according to some embodiments of the present disclosure.

[0008] FIG. 15 provides a schematic illustration of an exemplary physical layout of a device implementing superconducting qubits, according to some embodiments of the present disclosure.

[0009] FIG. 16 provides a schematic illustration of a conventional cooling assembly in which qubits operate.

[0010] FIG. 17 provides a schematic illustration of an exemplary qubit device package with integrated qubit level interconnects for cooling charge carriers, according to some embodiments of the present disclosure.

[0011] FIG. 18 provides a schematic illustration of a cooling assembly in which the qubit device package of FIG. 17 may be used, according to some embodiments of the present disclosure.

[0012] FIG. 19 provides a flow chart of an exemplary method for fabricating a qubit device package with integrated qubit level interconnects, according to some embodiments of the present disclosure. [0013] FIG. 20 provides a schematic illustration of an exemplary quantum computing device that may include a qubit package with integrated qubit level interconnects for cooling charge carriers as described herein, according to some embodiments of the present disclosure.

Detailed Description

Overview

[0014] As previously described herein, quantum computing, or quantum information processing, refers to the field of research related to computation systems that use quantum-mechanical phenomena to manipulate data. One example of quantum-mechanical phenomena is the principle of quantum superposition, which asserts that any two or more quantum states can be added together, i.e.

superposed, to produce another valid quantum state, and that any quantum state can be represented as a sum of two or more other distinct states. Quantum entanglement is another example of quantum- mechanical phenomena. Entanglement refers to groups of particles being generated or interacting in such a way that the state of one particle becomes intertwined with that of the others. Furthermore, the quantum state of each particle cannot be described independently. Instead, the quantum state is given for the group of entangled particles as a whole. Yet another example of quantum-mechanical phenomena is sometimes described as a "collapse" because it asserts that when we observe (measure) particles, we unavoidably change their properties in that, once observed, the particles cease to be in a state of superposition or entanglement (i.e. by trying to ascertain anything about the particles, we collapse their state).

[0015] Put simply, superposition postulates that a given particle can be simultaneously in two states, entanglement postulates that two particles can be related in that they are able to instantly coordinate their states irrespective of the distance between them in space and time, and collapse postulates that when one observes a particle, one unavoidably changes the state of the particle and its' entanglement with other particles. These unique phenomena make manipulation of data in quantum computers significantly different from that of classical computers (i.e. computers that use phenomena of classical physics). Classical computers encode data into binary values, commonly referred to as bits. At any given time, a bit is always in only one of two states - it is either 0 or 1. Quantum computers use so- called quantum bits, referred to as qubits (both terms "bits" and "qubits" often interchangeably refer to the values that they hold as well as to the actual devices that store the values). Similar to a bit of a classical computer, at any given time, a qubit can be either 0 or 1. However, in contrast to a bit of a classical computer, a qubit can also be 0 and 1 at the same time, which is a result of superposition of quantum states. Entanglement also contributes to the unique nature of qubits in that input data to a quantum processor can be spread out among entangled qubits, allowing manipulation of that data to be spread out as well: providing input data to one qubit results in that data being shared to other qubits with which the first qubit is entangled. [0016] Compared to well-established and thoroughly researched classical computers, quantum computing is still in its infancy, with the highest number of qubits in a solid-state quantum processor currently being about 10. One of the main challenges resides in protecting qubits from decoherence so that they can stay in their information-holding states long enough to perform the necessary calculations and read out the results. Also for the reason of protection from decoherence, qubits are often operated at cryogenic temperatures, typically just a few degrees Kelvin or even just a few milliKelvin above absolute zero, because at cryogenic temperatures thermal energy is low enough to not cause spurious excitations, which is thought to help minimize qubit decoherence.

[0017] None of the challenges described above ever had to be addressed for classical computers, and these challenges are not easy. In particular, continuously cooling the qubits to keep them at cryogenic temperatures during operation is a difficult task to begin with, further complicated by the fact that cooling efforts are hindered by various sources of temperature increase due to the overall configuration of an assembly in which qubits are operating. One such source is that, while the qubits themselves are kept in a helium mixing chamber of a dilution refrigerator in order to be kept at milliKelvin

temperatures during their operation, electrical connections providing charge carriers to qubits are mainly outside of this mixing chamber. As a result, charge carriers provided to qubits may be at much higher temperatures.

[0018] Embodiments of the present disclosure provide qubit device packages which incorporate portions of electrical connections for supporting transport of charge carriers (electrons or holes) to/from the qubits within a package. An exemplary qubit device package includes a die and a package substrate. The die includes a qubit device and has a first face with a plurality of conductive contacts and an opposing second face, the second face of the die mechanically attached to a first face of the package substrate. The package further includes qubit level interconnects, i.e. conductive pathways provided within the same package as qubits of the qubit device of the die, electrically coupling conductive contacts at the first face of the die with associated conductive contacts at the first face of the package substrate. Providing qubit level interconnects ensures that these interconnects are kept at the same temperature level as the qubits of the die, i.e. if the qubits are kept at milliKelvin temperature during operation, than the qubit level interconnects are also at that temperature, advantageously allowing cooling of the charge carriers injected into the qubit device. To provide an even more efficient cooling, the qubit level interconnects may include, or be enclosed by, sintered silver. Sintered silver has a large surface area which provides increased thermal conductivity, thus effectively serving as a heat exchanger for cooling the charge carriers injected into the qubit device.

[0019] For the purposes of the present disclosure, the terms such as "upper," "lower," "over," "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0020] The phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation "A/B/C" means (A), (B), and/or (C).

[0021] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale.

[0022] As used herein, terms indicating what may be considered an idealized behavior, such as e.g. "superconducting" or "lossless", are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss, either in terms of non-zero electrical resistance or non-zero amount of spurious two-level systems (TLS's) may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms. Specific values associated with an acceptable level of loss are expected to change over time as fabrication precision will improve and as fault-tolerant schemes may become more tolerant of higher losses, all of which are within the scope of the present disclosure.

[0023] Furthermore, while the present disclosure may include references to microwave signals, this is done only because current qubits are designed to work with such signals because the energy in the microwave range is higher than thermal excitations at the temperature that qubits are operated at. In addition, techniques for the control and measurement of microwaves are well known. For these reasons, typical frequencies of qubits are in 5-10 gigahertz (GHz) range, in order to be higher than thermal excitations, but low enough for ease of microwave engineering. However, advantageously, because excitation energy of qubits is controlled by the circuit elements, qubits can be designed to have any frequency. Therefore, in general, qubits could be designed to operate with signals in other ranges of electromagnetic spectrum and embodiments of the present disclosure could be modified accordingly. All of these alternative implementations are within the scope of the present disclosure. [0024] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0025] Furthermore, in the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well- known features are omitted or simplified in order not to obscure the illustrative implementations.

[0026] Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment(s). Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

Qubit level interconnects integrated with various gubit devices

[0027] The ability to manipulate and read out quantum states, making quantum-mechanical phenomena visible and traceable, and the ability to deal with and improve on the fragility of quantum states of a qubit present unique challenges not found in classical computers. These challenges explain why so many current efforts of the industry and the academics continue to focus on a search for new and improved physical systems whose functionality could approach that expected of theoretically designed qubits. Physical systems for implementing qubits that have been explored until now include e.g. quantum dot devices, superconducting qubit devices, single trapped ion devices, photon polarization devices, etc. To indicate that these devices implement qubits, sometimes these devices are referred to as qubits, e.g. quantum dot qubits, superconducting qubits, etc.

[0028] The type of qubits used in a qubit device implemented in a die would affect what kind of electrical connectivity qubit level interconnects described herein would be configured to provide. Below, two exemplary qubit devices are described - one incorporating quantum dot qubits (FIGs. 1-13) and one incorporating superconducting qubits (FIGs. 14-15). However, integration of qubit level interconnects in the same package with a die housing qubits, as described herein, is applicable to qubit devices which include any type of qubits, all of which are within the scope of the present disclosure. Exemplary qubit devices with Quantum dot qubits

[0029] Qubit devices implemented as quantum dot devices may enable the formation of quantum dots to serve as quantum bits (i.e. as qubits) in a quantum computing device. One type of quantum dot devices includes devices having a base, a fin extending away from the base, where the fin includes a quantum well layer, and one or more gates disposed on the fin. A quantum dot formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Unlike previous approaches to quantum dot formation and manipulation, quantum dot devices with fins provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices. Therefore, this is the type of quantum dot device that is described as a first exemplary qubit device that may be integrated in a single package with qubit level interconnects according to embodiments of the present disclosure.

[0030] FIGS. 1-3 are cross-sectional views of an exemplary quantum dot device 100 implementing quantum dot qubits, in accordance with various embodiments. In particular, FIG. 2 illustrates the quantum dot device 100 taken along the section A-A of FIG. 1 (while FIG. 1 illustrates the quantum dot device 100 taken along the section C-C of FIG. 2), and FIG. 3 illustrates the quantum dot device 100 taken along the section B-B of FIG. 1 (while FIG. 1 illustrates a quantum dot device 100 taken along the section D-D of FIG. 3). Although FIG. 1 indicates that the cross-section illustrated in FIG. 2 is taken through the fin 104-1, an analogous cross section taken through the fin 104-2 may be identical, and thus the discussion of FIGs. 1-3 refers generally to the "fin 104."

[0031] A qubit device integrated in a single package with qubit level interconnects as described herein may include one or more of the quantum dot devices 100.

[0032] As shown in FIGs. 1-3, the quantum dot device 100 may include a base 102 and multiple fins 104 extending away from the base 102. The base 102 and the fins 104 may include a semiconductor substrate and a quantum well stack (not shown in FIGS. 1-3, but discussed below with reference to the semiconductor substrate 144 and the quantum well stack 146), distributed in any of a number of ways between the base 102 and the fins 104. The base 102 may include at least some of the semiconductor substrate, and the fins 104 may each include a quantum well layer of the quantum well stack (discussed below with reference to the quantum well layer 152 of FIGs. 4-6). Examples of base/fin arrangements are discussed below with reference to the base fin arrangements 158 of FIGS. 7-13. [0033] Although only two fins, 104-1 and 104-2, are shown in FIGS. 1-3, this is simply for ease of illustration, and more than two fins 104 may be included in the quantum dot device 100. In some embodiments, the total number of fins 104 included in the quantum dot device 100 is an even number, with the fins 104 organized into pairs including one active fin 104 and one read fin 104, as discussed in detail below. When the quantum dot device 100 includes more than two fins 104, the fins 104 may be arranged in pairs in a line (e.g., 2N fins total may be arranged in a lx2N line, or a 2xN line) or in pairs in a larger array (e.g., 2N fins total may be arranged as a 4xN/2 array, a 6xN/3 array, etc.). The discussion herein will largely focus on a single pair of fins 104 for ease of illustration, but all the teachings of the present disclosure apply to quantum dot devices 100 with more fins 104.

[0034] As noted above, each of the fins 104 may include a quantum well layer (not shown in FIGS. 1-3, but discussed below with reference to the quantum well layer 152). The quantum well layer included in the fins 104 may be arranged normal to the z-direction, and may provide a layer in which a two- dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the quantum dot device 100, as discussed in further detail below. The quantum well layer itself may provide a geometric constraint on the z-location of quantum dots in the fins 104, and the limited extent of the fins 104 (and therefore the quantum well layer) in the y-direction may provide a geometric constraint on the y-location of quantum dots in the fins 104. To control the x-location of quantum dots in the fins 104, voltages may be applied to gates disposed on the fins 104 to adjust the energy profile along the fins 104 in the x-direction and thereby constrain the x-location of quantum dots within quantum wells (discussed in detail below with reference to the gates 106/108). The dimensions of the fins 104 may take any suitable values. For example, in some embodiments, the fins 104 may each have a width 162 between 10 and 30 nanometers. In some embodiments, the fins 104 may each have a height 164 between 200 and 400 nanometers (e.g., between 250 and 350 nanometers, or equal to 300 nanometers).

[0035] The fins 104 may be arranged in parallel, as illustrated in FIGS. 1 and 3, and may be spaced apart by an insulating material 128, which may be disposed on opposite faces of the fins 104. The insulating material 128 may be a dielectric material, such as silicon oxide. For example, in some embodiments, the fins 104 may be spaced apart by a distance 160 between 100 and 250 microns.

[0036] Multiple gates may be disposed on each of the fins 104. In the embodiment illustrated in FIG. 2, three gates 106 and two gates 108 are shown as distributed on the top of the fin 104. This particular number of gates is simply illustrative, and any suitable number of gates may be used. Additionally, multiple groups of gates like the gates illustrated in FIG. 2 may be disposed on the fin 104.

[0037] As shown in FIG. 2, the gate 108-1 may be disposed between the gates 106-1 and 106-2, and the gate 108-2 may be disposed between the gates 106-2 and 106-3. Each of the gates 106/108 may include a gate dielectric 114. In the embodiment illustrated in FIG. 2, the gate dielectric 114 for all of the gates 106/108 is provided by a common layer of gate dielectric material. In other embodiments, the gate dielectric 114 for each of the gates 106/108 may be provided by separate portions of gate dielectric 114. In some embodiments, the gate dielectric 114 may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin 104 and the corresponding gate metal). The gate dielectric 114 may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric 114 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the gate dielectric 114 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric 114 to improve the quality of the gate dielectric 114.

[0038] Each of the gates 106 may include a gate metal 110 and a hardmask 116. The hardmask 116 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 110 may be disposed between the hardmask 116 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 110 and the fin 104. Only one portion of the hardmask 116 is labeled in FIG. 2 for ease of illustration. In some embodiments, the gate metal 110 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. In some embodiments, the hardmask 116 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 116 may be removed during processing, as discussed below). The sides of the gate metal 110 may be substantially parallel, as shown in FIG. 2, and insulating spacers 134 may be disposed on the sides of the gate metal 110 and the hardmask 116. As illustrated in FIG. 2, the spacers 134 may be thicker closer to the fin 104 and thinner farther away from the fin 104. In some embodiments, the spacers 134 may have a convex shape. The spacers 134 may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride). The gate metal 110 may be any suitable metal, such as titanium nitride.

[0039] Each of the gates 108 may include a gate metal 112 and a hardmask 118. The hardmask 118 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 112 may be disposed between the hardmask 118 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 112 and the fin 104. In the embodiment illustrated in FIG. 2, the hardmask 118 may extend over the hardmask 116 (and over the gate metal 110 of the gates 106), while in other embodiments, the hardmask 118 may not extend over the gate metal 110 (e.g., as discussed below with reference to FIG. 45). In some embodiments, the gate metal 112 may be a different metal from the gate metal 110; in other embodiments, the gate metal 112 and the gate metal 110 may have the same material composition. In some embodiments, the gate metal 112 may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or niobium titanium nitride. In some embodiments, the hardmask 118 may not be present in the quantum dot device 100 (e.g., a hardmask like the hardmask 118 may be removed during processing, as discussed below).

[0040] The gate 108 may extend between the proximate spacers 134 on the sides of the gate 106-1 and the gate 106-3, as shown in FIG. 2. In some embodiments, the gate metal 112 may extend between the spacers 134 on the sides of the gate 106-1 and the gate 106-3. Thus, the gate metal 112 may have a shape that is substantially complementary to the shape of the spacers 134, as shown. In some embodiments in which the gate dielectric 114 is not a layer shared commonly between the gates 108 and 106, but instead is separately deposited on the fin 104 between the spacers 134 (e.g., as discussed below with reference to FIGS. 40-44), the gate dielectric 114 may extend at least partially up the sides of the spacers 134, and the gate metal 112 may extend between the portions of gate dielectric 114 on the spacers 134. The gate metal 112, like the gate metal 110, may be any suitable metal, such as titanium nitride.

[0041] The dimensions of the gates 106/108 may take any suitable values. For example, in some embodiments, the z-height 166 of the gate metal 110 may be between 40 and 75 nanometers (e.g., approximately 50 nanometers); the z-height of the gate metal 112 may be in the same range. In embodiments like the ones illustrated in FIG. 2, the z-height of the gate metal 112 may be greater than the z-height of the gate metal 110. In some embodiments, the length 168 of the gate metal 110 (i.e., in the x-direction) may be between 20 and 40 nanometers (e.g., 30 nanometers). In some embodiments, the distance 170 between adjacent ones of the gates 106 (e.g., as measured from the gate metal 110 of one gate 106 to the gate metal 110 of an adjacent gate 106 in the x-direction, as illustrated in FIG. 2) may be between 40 and 60 nanometers (e.g., 50 nanometers). In some embodiments, the thickness 172 of the spacers 134 may be between 1 and 10 nanometers (e.g., between 3 and 5 nanometers, between 4 and 6 nanometers, or between 4 and 7 nanometers). The length of the gate metal 112 (i.e., in the x-direction) may depend on the dimensions of the gates 106 and the spacers 134, as illustrated in FIG. 2. As indicated in FIG. 1, the gates 106/108 on one fin 104 may extend over the insulating material 128 beyond their respective fins 104 and towards the other fin 104, but may be isolated from their counterpart gates by the intervening insulating material 130.

[0042] As shown in FIG. 2, the gates 106 and 108 may be alternatingly arranged along the fin 104 in the x-direction. During operation of the quantum dot device 100, voltages may be applied to the gates 106/108 to adjust the potential energy in the quantum well layer (not shown) in the fin 104 to create quantum wells of varying depths in which quantum dots 142 may form. Only one quantum dot 142 is labeled with a reference numeral in FIGS. 2 and 3 for ease of illustration, but five are indicated as dotted circles in each fin 104, forming what may be referred to as a "quantum dot array." The location of the quantum dots 142 in FIG. 2 is not intended to indicate a particular geometric positioning of the quantum dots 142. The spacers 134 may themselves provide "passive" barriers between quantum wells under the gates 106/108 in the quantum well layer, and the voltages applied to different ones of the gates 106/108 may adjust the potential energy under the gates 106/108 in the quantum well layer; decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers.

[0043] The fins 104 may include doped regions 140 that may serve as a reservoir of charge carriers for the quantum dot device 100. For example, an n-type doped region 140 may supply electrons for electron-type quantum dots 142, and a p-type doped region 140 may supply holes for hole-type quantum dots 142. In some embodiments, an interface material 141 may be disposed at a surface of a doped region 140, as shown. The interface material 141 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 136, as discussed below) and the doped region 140. The interface material 141 may be any suitable material; for example, in embodiments in which the doped region 140 includes silicon, the interface material 141 may include nickel silicide.

[0044] The quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots 142. Note that the polarity of the voltages applied to the gates 106/108 to form quantum wells/barriers depend on the charge carriers used in the quantum dot device 100. In embodiments in which the charge carriers are electrons (and thus the quantum dots 142 are electron- type quantum dots), amply negative voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108, and amply positive voltages applied to a gate 106/108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in which an electron- type quantum dot 142 may form). In embodiments in which the charge carriers are holes (and thus the quantum dots 142 are hole-type quantum dots), amply positive voltages applied to a gate 106/108 may increase the potential barrier under the gate 106/108, and amply negative voltages applied to a gate 106 and 108 may decrease the potential barrier under the gate 106/108 (thereby forming a potential well in which a hole-type quantum dot 142 may form). The quantum dot devices 100 disclosed herein may be used to form electron-type or hole-type quantum dots.

[0045] Voltages may be applied to each of the gates 106 and 108 separately to adjust the potential energy in the quantum well layer under the gates 106 and 108, and thereby control the formation of quantum dots 142 under each of the gates 106 and 108. Additionally, the relative potential energy profiles under different ones of the gates 106 and 108 allow the quantum dot device 100 to tune the potential interaction between quantum dots 142 under adjacent gates. For example, if two adjacent quantum dots 142 (e.g., one quantum dot 142 under a gate 106 and another quantum dot 142 under a gate 108) are separated by only a short potential barrier, the two quantum dots 142 may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate 106/108 may be adjusted by adjusting the voltages on the respective gates 106/108, the differences in potential between adjacent gates 106/108 may be adjusted, and thus the interaction tuned.

[0046] In some applications, the gates 108 may be used as plunger gates to enable the formation of quantum dots 142 under the gates 108, while the gates 106 may be used as barrier gates to adjust the potential barrier between quantum dots 142 formed under adjacent gates 108. In other applications, the gates 108 may be used as barrier gates, while the gates 106 are used as plunger gates. In other applications, quantum dots 142 may be formed under all of the gates 106 and 108, or under any desired subset of the gates 106 and 108.

[0047] Conductive vias and lines may make contact with the gates 106/108, and to the doped regions 140, to enable electrical connection to the gates 106/108 and the doped regions 140 to be made in desired locations. As shown in FIGS. 1-3, the gates 106 may extend away from the fins 104, and conductive vias 120 may contact the gates 106 (and are drawn in dashed lines in FIG. 2 to indicate their location behind the plane of the drawing). The conductive vias 120 may extend through the hardmask 116 and the hardmask 118 to contact the gate metal 110 of the gates 106. The gates 108 may extend away from the fins 104, and conductive vias 122 may contact the gates 108 (also drawn in dashed lines in FIG. 2 to indicate their location behind the plane of the drawing). The conductive vias 122 may extend through the hardmask 118 to contact the gate metal 112 of the gates 108. Conductive vias 136 may contact the interface material 141 and may thereby make electrical contact with the doped regions 140. The quantum dot device 100 may include further conductive vias and/or lines (not shown) to make electrical contact to the gates 106/108 and/or the doped regions 140, as desired.

[0048] During operation, a bias voltage may be applied to the doped regions 140 (e.g., via the conductive vias 136 and the interface material 141) to cause current to flow through the doped regions 140. When the doped regions 140 are doped with an n-type material, this voltage may be positive; when the doped regions 140 are doped with a p-type material, this voltage may be negative. The magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts).

[0049] The conductive vias 120, 122, and 136 may be electrically isolated from each other by an insulating material 130. The insulating material 130 may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material 130 may include silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride. As known in the art of integrated circuit manufacturing, conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other. In some embodiments, the conductive vias 120/122/136 may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some embodiments, conductive lines (not shown) included in the quantum dot device 100 may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater. The particular arrangement of conductive vias shown in FIGS. 1-3 is simply illustrative, and any electrical routing arrangement may be implemented.

[0050] As discussed above, the structure of the fin 104-1 may be the same as the structure of the fin 104-2; similarly, the construction of gates 106/108 on the fin 104-1 may be the same as the construction of gates 106/108 on the fin 104-2. The gates 106/108 on the fin 104-1 may be mirrored by corresponding gates 106/108 on the parallel fin 104-2, and the insulating material 130 may separate the gates 106/108 on the different fins 104-1 and 104-2. In particular, quantum dots 142 formed in the fin 104-1 (under the gates 106/108) may have counterpart quantum dots 142 in the fin 104-2 (under the corresponding gates 106/108). In some embodiments, the quantum dots 142 in the fin 104-1 may be used as "active" quantum dots in the sense that these quantum dots 142 act as qubits and are controlled (e.g., by voltages applied to the gates 106/108 of the fin 104-1) to perform quantum computations. The quantum dots 142 in the fin 104-2 may be used as "read" quantum dots in the sense that these quantum dots 142 may sense the quantum state of the quantum dots 142 in the fin 104-1 by detecting the electric field generated by the charge in the quantum dots 142 in the fin 104-1, and may convert the quantum state of the quantum dots 142 in the fin 104-1 into electrical signals that may be detected by the gates 106/108 on the fin 104-2. Each quantum dot 142 in the fin 104-1 may be read by its corresponding quantum dot 142 in the fin 104-2. Thus, the quantum dot device 100 enables both quantum computation and the ability to read the results of a quantum computation.

[0051] Although not specifically shown in FIGs. 1-3, the quantum dot device 100 may further include one or more accumulation gates used to form a 2DEG in the quantum well area between the area with the quantum dots and the reservoir such as e.g. the doped regions 140 which, as previously described, may serve as a reservoir of charge carriers for the quantum dot device 100. Using such accumulation gates may allow to reduce the number of charge carriers in the area adjacent to the area in which quantum dots are to be formed, so that single charge carriers can be transferred from the reservoir into the quantum dot array. In various embodiments, an accumulation gate may be implemented on either side of an area where a quantum dot is to be formed.

[0052] Although also not specifically shown in FIGs. 1-3, some implementations of the quantum dot device 100 further include or are coupled to a magnetic field source used for spin manipulation of the charge carriers in the quantum dots. In various embodiments, e.g. a microwave transmission line or one or more magnets with pulsed gates may be used as a magnetic field source. Once a quantum dot array is initialized by ensuring that a desired number of charge carriers are present in each quantum dot and ensuring the initial spins of these charge carriers, spin manipulation may be carried out with either a single spin or pairs of spin or possibly larger numbers of spins. In some embodiments, single spins may be manipulated using electron spin resonance with a rotating magnetic field (perpendicular to its static field) and on resonance with the transition energy at which the spin flips.

[0053] As discussed above, the base 102 and the fin 104 of a quantum dot device 100 may be formed from a semiconductor substrate 144 and a quantum well stack 146 disposed on the semiconductor substrate 144. The quantum well stack 146 may include a quantum well layer in which a 2DEG may form during operation of the quantum dot device 100. The quantum well stack 146 may take any of a number of forms, several of which are illustrated in FIGS. 4-6. The various layers in the quantum well stacks 146 discussed below may be grown on the semiconductor substrate 144 (e.g., using epitaxial processes).

[0054] FIG. 4 is a cross-sectional view of a quantum well stack 146 including only a quantum well layer 152. The quantum well layer 152 may be disposed on the semiconductor substrate 144, and may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152 proximate to the upper surface of the quantum well layer 152. The gate dielectric 114 of the gates 106/108 may be disposed on the upper surface of the quantum well layer 152. In some embodiments, the quantum well layer 152 of FIG. 4 may be formed of intrinsic silicon, and the gate dielectric 114 may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device 100, a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the silicon oxide. In some such embodiments, the intrinsic silicon may be strained, while in other embodiments, the intrinsic silicon may not be strained. The thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 4 may take any suitable values. For example, in some embodiments, the thickness of the quantum well layer 152 (e.g., intrinsic silicon) may be between 0.8 and 1.2 microns.

[0055] FIG. 5 is a cross-sectional view of a quantum well stack 146 including a quantum well layer 152 and a barrier layer 154. The quantum well stack 146 may be disposed on a semiconductor substrate 144 such that the barrier layer 154 is disposed between the quantum well layer 152 and the semiconductor substrate 144. The barrier layer 154 may provide a potential barrier between the quantum well layer 152 and the semiconductor substrate 144. As discussed above with reference to FIG. 4, the quantum well layer 152 of FIG. 5 may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152 proximate to the upper surface of the quantum well layer 152. For example, in some embodiments in which the semiconductor substrate 144 is formed of silicon, the quantum well layer 152 of FIG. 5 may be formed of silicon, and the barrier layer 154 may be formed of silicon germanium. The germanium content of this silicon germanium may be 20-80% (e.g., 30%). The thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 5 may take any suitable values. For example, in some embodiments, the thickness of the barrier layer 154 (e.g., silicon germanium) may be between 0 and 400 nanometers. In some embodiments, the thickness of the quantum well layer 152 (e.g., silicon) may be between 5 and 30 nanometers.

[0056] FIG. 6 is a cross-sectional view of a quantum well stack 146 including a quantum well layer 152 and a barrier layer 154-1, as well as a buffer layer 176 and an additional barrier layer 154-2. The quantum well stack 146 may be disposed on the semiconductor substrate 144 such that the buffer layer 176 is disposed between the barrier layer 154-1 and the semiconductor substrate 144. The buffer layer 176 may be formed of the same material as the barrier layer 154, and may be present to trap defects that form in this material as it is grown on the semiconductor substrate 144. In some embodiments, the buffer layer 176 may be grown under different conditions (e.g., deposition temperature or growth rate) from the barrier layer 154-1. In particular, the barrier layer 154-1 may be grown under conditions that achieve fewer defects than the buffer layer 176. In some embodiments in which the buffer layer 176 includes silicon germanium, the silicon germanium of the buffer layer 176 may have a germanium content that varies from the semiconductor substrate 144 to the barrier layer 154-1. For example, the silicon germanium of the buffer layer 176 may have a germanium content that varies from zero percent at the silicon semiconductor substrate 144 to a nonzero percent (e.g., 30%) at the barrier layer 154-1. The thicknesses (i.e., z-heights) of the layers in the quantum well stack 146 of FIG. 6 may take any suitable values. For example, in some embodiments, the thickness of the buffer layer 176 (e.g., silicon germanium) may be between 0.3 and 4 microns (e.g., 0.3-2 microns, or 0.5 microns). In some embodiments, the thickness of the barrier layer 154-1 (e.g., silicon germanium) may be between 0 and 400 nanometers. In some embodiments, the thickness of the quantum well layer 152 (e.g., silicon) may be between 5 and 30 nanometers (e.g., 10 nanometers). In some embodiments, the thickness of the barrier layer 154-2 (e.g., silicon germanium) may be between 25 and 75 nanometers (e.g., 32 nanometers).

[0057] As discussed above with reference to FIG. 5, the quantum well layer 152 of FIG. 6 may be formed of a material such that, during operation of the quantum dot device 100, a 2DEG may form in the quantum well layer 152 proximate to the upper surface of the quantum well layer 152. For example, in some embodiments in which the semiconductor substrate 144 is formed of silicon, the quantum well layer 152 of FIG. 6 may be formed of silicon, and the barrier layer 154-1 and the buffer layer 176 may be formed of silicon germanium. In some such embodiments, the silicon germanium of the buffer layer 176 may have a germanium content that varies from the semiconductor substrate 144 to the barrier layer 154-1. For example, the silicon germanium of the buffer layer 176 may have a germanium content that varies from zero percent at the silicon semiconductor substrate 144 to a nonzero percent (e.g., 30%) at the barrier layer 154-1. The barrier layer 154-1 may in turn have a germanium content equal to the nonzero percent. In other embodiments, the buffer layer 176 may have a germanium content equal to the germanium content of the barrier layer 154-1, but may be thicker than the barrier layer 154-1 so as to absorb the defects that may arise during growth. The barrier layer 154-2, like the barrier layer 154-1, may provide a potential energy barrier around the quantum well layer 152, and may take the form of any of the embodiments of the barrier layer 154-1. In some embodiments of the quantum well stack 146 of FIG. 6, the buffer layer 176 and/or the barrier layer 154-2 may be omitted.

[0058] The semiconductor substrate 144 and the quantum well stack 146 may be distributed between the base 102 and the fins 104 of the quantum dot device 100, as discussed above. This distribution may occur in any of a number of ways. For example, FIGS. 7-13 illustrate example base/fin arrangements 158 that may be used in a quantum dot device 100, in accordance with various embodiments.

[0059] In the base/fin arrangement 158 of FIG. 7, the quantum well stack 146 may be included in the fins 104, but not in the base 102. The semiconductor substrate 144 may be included in the base 102, but not in the fins 104. Manufacturing of the base/fin arrangement 158 of FIG. 7 may include fin etching through the quantum well stack 146, stopping when the semiconductor substrate 144 is reached.

[0060] In the base/fin arrangement 158 of FIG. 8, the quantum well stack 146 may be included in the fins 104, as well as in a portion of the base 102. A semiconductor substrate 144 may be included in the base 102 as well, but not in the fins 104. Manufacturing of the base/fin arrangement 158 of FIG. 8 may include fin etching that etches partially through the quantum well stack 146, and stops before the semiconductor substrate 144 is reached. FIG. 9 illustrates a particular embodiment of the base/fin arrangement 158 of FIG. 8. In the embodiment of FIG. 9, the quantum well stack 146 of FIG. 6 is used; the fins 104 include the barrier layer 154-1, the quantum well layer 152, and the barrier layer 154-2, while the base 102 includes the buffer layer 176 and the semiconductor substrate 144.

[0061] In the base/fin arrangement 158 of FIG. 10, the quantum well stack 146 may be included in the fins 104, but not the base 102. The semiconductor substrate 144 may be partially included in the fins 104, as well as in the base 102. Manufacturing the base/fin arrangement 158 of FIG. 10 may include fin etching that etchs through the quantum well stack 146 and into the semiconductor substrate 144 before stopping. FIG. 11 illustrates a particular embodiment of the base/fin arrangement 158 of FIG. 10. In the embodiment of FIG. 11, the quantum well stack 146 of FIG. 6 is used; the fins 104 include the quantum well stack 146 and a portion of the semiconductor substrate 144, while the base 102 includes the remainder of the semiconductor substrate 144.

[0062] Although the fins 104 have been illustrated in many of the preceding figures as substantially rectangular with parallel sidewalls, this is simply for ease of illustration, and the fins 104 may have any suitable shape (e.g., shape appropriate to the manufacturing processes used to form the fins 104). For example, as illustrated in the base/fin arrangement 158 of FIG. 12, in some embodiments, the fins 104 may be tapered. In some embodiments, the fins 104 may taper by 3-10 nanometers in x-width for every 100 nanometers in z-height (e.g., 5 nanometers in x-width for every 100 nanometers in z-height). When the fins 104 are tapered, the wider end of the fins 104 may be the end closest to the base 102, as illustrated in FIG. 12. FIG. 13 illustrates a particular embodiment of the base/fin arrangement 158 of FIG. 12. In FIG. 13, the quantum well stack 146 is included in the tapered fins 104 while a portion of the semiconductor substrate 144 is included in the tapered fins and a portion of the semiconductor substrate 144 provides the base 102.

[0063] In the embodiment of the quantum dot device 100 illustrated in FIG. 2, the z-height of the gate metal 112 of the gates 108 may be approximately equal to the sum of the z-height of the gate metal 110 and the z-height of the hardmask 116, as shown. Also in the embodiment of FIG. 2, the gate metal 112 of the gates 108 may not extend in the x-direction beyond the adjacent spacers 134. In other embodiments, the z-height of the gate metal 112 of the gates 108 may be greater than the sum of the z-height of the gate metal 110 and the z-height of the hardmask 116, and in some such embodiments, the gate metal 112 of the gates may extend beyond the spacers 134 in the x-direction.

Exemplary pubit devices with superconducting qubits

[0064] Qubit devices implementing superconducting qubits are also promising candidates for building a quantum computer. Therefore, these are the types of qubits that may be used in a second exemplary qubit device that may be integrated in a single package with qubit level interconnects according to embodiments of the present disclosure.

[0065] All of superconducting qubits operate based on the Josephson effect, which refers to a macroscopic quantum phenomenon of supercurrent, i.e. a current that, due to zero electrical resistance, flows indefinitely long without any voltage applied, across a device known as a Josephson Junction. Josephson Junctions are integral building blocks in superconducting quantum circuits where they form the basis of quantum circuit elements that can approximate functionality of theoretically designed qubits.

[0066] Within superconducting qubit implementations, three classes are typically distinguished: charge qubits, flux qubits, and phase qubits. Transmons, a type of charge qubits with the name being an abbreviation of "transmission line shunted plasma oscillation qubits", are particularly encouraging because they exhibit reduced sensitivity to charge noise.

[0067] In implementations when superconducting qubits are implemented as transmon qubits, two basic elements of superconducting quantum circuits are inductors and capacitors. However, circuits made using only these two elements cannot make a system with two energy levels because, due to the even spacing between the system's energy levels, such circuits will produce harmonic oscillators with a ladder of equivalent states. A nonlinear element is needed to have an effective two-level quantum state system, or qubit. Josephson Junction is an example of such non-linear, non-dissipative circuit element. [0068] Josephson Junctions may form the central circuit elements of a quantum computer based on superconducting qubits. A Josephson Junction may include a thin layer of an insulating material, typically referred to as a barrier or a tunnel barrier, sandwiched between two layers of superconductor. The Josephson Junction acts as a superconducting tunnel junction. Cooper pairs tunnel across the barrier from one superconducting layer to the other. The electrical characteristics of this tunneling are governed by so-called Josephson relations which provide the basic equations governing the dynamics of the Josephson effect:

I = I_c sin (p (1)

ν = Τ_β Φ (2)

[0069] In these equations, ψ is the phase difference in the superconducting wave function across the junction, Ic (the critical current) is the maximum current that can tunnel through the junction, which depends on the barrier thickness and the area of the junction, V is the voltage across the Josephson Junction, I is the current flowing through the Josephson Junction, h is the reduced Planck's constant, and e is electron's charge. Equations (1) and (2) can be combined to give an equation (3):

V =— -— / (3)

2el_ccosq>

[0070] Equation (3) looks like the equation for an inductor with inductance L:

L = ^{^}^- (4)

2eI_ccos<p

[0071] Since inductance is a function of q>, which itself is a function of I, the inductance of a Josephson Junction is non-linear, which makes an LC circuit formed using a Josephson Junction as the inductor have uneven spacing between its energy states.

[0072] The foregoing provides an illustration of using a Josephson Junction in a transmon, which is one class of superconducting qubit. In other classes of superconducting qubits, Josephson Junctions combined with other circuit elements have similar functionality of providing the non-linearity necessary for forming an effective two-level quantum state, or qubit. In other words, when implemented in combination with other circuit elements (e.g. capacitors in transmons or superconducting loops in flux qubits), one or more Josephson Junctions allow realizing a quantum circuit element which has uneven spacing between its energy levels resulting in a unique ground and excited state system for the qubit. This is illustrated in FIG. 14, providing a schematic illustration of a superconducting quantum circuit 200, according to some embodiments of the present disclosure. As shown in FIG. 14, an exemplary superconducting quantum circuit 200 includes two or more qubits: 202-1 and 202-2. Qubits 202-1 and 202-2 may be identical and thus the discussion of FIG. 14 refers generally to the "qubit 202," and the same applies to referring to Josephson Junctions 204-1 and 204-2 generally as "Josephson Junctions 204" and referring to circuit elements 206-1 and 206-2 generally as "circuit elements 206." As shown in FIG. 14, each of the superconducting qubits 202 may include one or more Josephson Junctions 204 connected to one or more other circuit elements 206, which, in combination with the Josephson Junction(s) 204, form a non-linear circuit providing a unique two-level quantum state for the qubit. The circuit elements 206 could be e.g. capacitors in transmons or superconducting loops in flux qubits.

[0073] As also shown in FIG. 14, an exemplary superconducting quantum circuit 200 typically includes means 208 for providing external control of qubits 202 and means 210 for providing internal control of qubits 202. In this context, "external control" refers to controlling the qubits 202 from outside of, e.g, an integrated circuit (IC) chip comprising the qubits, including control by a user of a quantum computer, while "internal control" refers to controlling the qubits 202 within the IC chip. For example, if qubits 202 are transmon qubits, external control may be implemented by means of flux bias lines (also known as "flux lines" and "flux coil lines") and by means of readout and drive lines (also known as "microwave lines" since qubits are typically designed to operate with microwave signals), described in greater detail below. On the other hand, internal control lines for such qubits may be implemented by means of resonators, e.g., coupling and readout resonators, also described in greater detail below.

[0074] Any one of the qubits 202, the external control means 208, and the external control means 210 of the quantum circuit 200 may be provided on, over, or at least partially embedded in a substrate (not shown in FIG. 14).

[0075] FIG. 15 provides a schematic illustration of an exemplary physical layout of a superconducting quantum circuit 211 where qubits are implemented as transmons, according to some embodiments of the present disclosure.

[0076] Similar to FIG. 14, FIG. 15 illustrates two qubits 202. In addition, FIG. 15 illustrates flux bias lines 212, microwave lines 214, a coupling resonator 216, a readout resonator 218, and conductive contacts, e.g. wirebonding pads, 220 and 222. The flux bias lines 212 and the microwave lines 214 may be viewed as examples of the external control means 208 shown in FIG. 14. The coupling resonator 216 and the readout resonator 218 may be viewed as examples of the internal control means 210 shown in FIG. 14.

[0077] Running a current through the flux bias lines 212, provided from the conductive contacts 220, allows tuning (i.e. changing) the frequency of the corresponding qubits 202 to which each line 212 is connected. In general, it operates in the following manner. As a result of running the current in a particular flux bias line 212, magnetic field is created around the line. If such a magnetic field is in sufficient proximity to the qubit 202, e.g. by a portion of the flux bias line 212 being provided next to the qubit 202, the magnetic field couples to the qubit, thereby changing the spacing between the energy levels of the qubit. This, in turn, changes the frequency of the qubit since the frequency is directly related to the spacing between the energy levels via Planck's equation. The Planck's equation is E=hv, where E is the energy (in this case the energy difference between energy levels of a qubit), h is the Planck's constant and v is the frequency (in this case the frequency of the qubit). As this equation illustrates, if E changes, then v changes. Provided there is sufficient multiplexing, different currents can be sent down each of the flux lines allowing for independent tuning of the various qubits.

[0078] Typically, the qubit frequency may be controlled in order to bring the frequency either closer to or further away from another resonant item, for example a coupling resonator such as 216 shown in FIG. 15 that connects two or more qubits together, as may be desired in a particular setting.

[0079] For example, if it is desirable that a first qubit 202 (e.g. the qubit 202 shown on the left side of FIG. 15) and a second qubit 202 (e.g. the qubit 202 shown on the right side of FIG. 15) interact, via the coupling resonator 216 connecting these qubits, then both qubits 202 may need to be tuned to be at nearly the same frequency. One way in which such two qubits could interact is that, if the frequency of the first qubit 202 is tuned very close to the resonant frequency of the coupling resonator 216, the first qubit can, when in the excited state, relax back down to the ground state by emitting a photon (similar to how an excited atom would relax) that would resonate within the coupling resonator 216. If the second qubit 202 is also at this energy (i.e. if the frequency of the second qubit is also tuned very close to the resonant frequency of the coupling resonator 216), then it can absorb the photon emitted from the first qubit, via the coupling resonator 216, and be excited from it's ground state to an excited state. Thus, the two qubits interact in that a state of one qubit is controlled by the state of another qubit. In other scenarios, two qubits could interact via a coupling resonator at specific frequencies, but these three elements do not have to be tuned to be at nearly the same frequency with one another. In general, two or more qubits could be configured to interact with one another by tuning their frequencies to specific values or ranges.

[0080] On the other hand, it may sometimes be desirable that two qubits coupled by a coupling resonator do not interact, i.e. the qubits are independent. In this case, by applying magnetic flux, by means of controlling the current in the appropriate flux bias line, to one qubit it is possible to cause the frequency of the qubit to change enough so that the photon it could emit no longer has the right frequency to resonate on the coupling resonator. If there is nowhere for such a frequency-detuned photon to go, the qubit will be better isolated from its surroundings and will live longer in its current state. Thus, in general, two or more qubits could be configured to avoid or eliminate interactions with one another by tuning their frequencies to specific values or ranges.

[0081] The state(s) of each qubit 202 may be read by way of its corresponding readout resonator 218. As explained below, the qubit 202 induces a resonant frequency in the readout resonator 218. This resonant frequency is then passed to the microwave lines 214 and communicated to the conductive contacts 222.

[0082] To that end, a readout resonator 218 may be provided for each qubit. The readout resonator 218 may be a transmission line that includes a capacitive connection to ground on one side and is either shorted to the ground on the other side (for a quarter wavelength resonator) or has a capacitive connection to ground (for a half wavelength resonator), which results in oscillations within the transmission line (resonance), with the resonant frequency of the oscillations being close to the frequency of the qubit. The readout resonator 218 is coupled to the qubit by being in sufficient proximity to the qubit 202, more specifically in sufficient proximity to the capacitor of the qubit 202, when the qubit is implemented as a transmon, either through capacitive or inductive coupling. Due to a coupling between the readout resonator 218 and the qubit 202, changes in the state of the qubit 202 result in changes of the resonant frequency of the readout resonator 218. In turn, because the readout resonator 218 is in sufficient proximity to the microwave line 214, changes in the resonant frequency of the readout resonator 218 induce changes in the current in the microwave line 214, and that current can be read externally via the conductive contacts 222.

[0083] The coupling resonator 216 allows coupling different qubits together, e.g. as described above, in order to realize quantum logic gates. The coupling resonator 216 is similar to the readout resonator 218 in that it is a transmission line that includes capacitive connections to ground on both sides (i.e. a half wavelength resonator), which also results in oscillations within the coupling resonator 216. Each side of the coupling resonator 216 is coupled (again, either capacitively or inductively) to a respective qubit by being in sufficient proximity to the qubit, namely in sufficient proximity to the capacitor of the qubit, when the qubit is implemented as a transmon. Because each side of the coupling resonator 216 has coupling with a respective different qubit, the two qubits are coupled together through the coupling resonator 216. In this manner, state of one qubit depends on the state of the other qubit, and the other way around. Thus, coupling resonators may be employed in order to use a state of one qubit to control a state of another qubit.

[0084] In some implementations, the microwave line 214 may be used to not only readout the state of the qubits as described above, but also to control the state of the qubits. When a single microwave line is used for this purpose, the line operates in a half-duplex mode where, at some times, it is configured to readout the state of the qubits, and, at other times, it is configured to control the state of the qubits. In other implementations, microwave lines such as the line 214 shown in FIG. 15 may be used to only readout the state of the qubits as described above, while separate drive lines such as e.g. drive lines 224 shown in FIG. 15, may be used to control the state of the qubits. In such implementations, the microwave lines used for readout may be referred to as readout lines (e.g. readout line 214), while microwave lines used for controlling the state of the qubits may be referred to as drive lines (e.g. drive lines 224). The drive lines 224 may control the state of their respective qubits 202 by providing, using e.g. wirebonding pads 226 as shown in FIG. 15, a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the states of the qubit. By varying the length of this pulse, a partial transition can be stimulated, giving a superposition of the states of the qubit. [0085] Flux bias lines, microwave lines, coupling resonators, drive lines, and readout resonators, such as e.g. those described above, together form interconnects for supporting propagation of microwave signals. Further, any other connections for providing direct electrical interconnection between different quantum circuit elements and components, such as e.g. connections from electrodes of Josephson Junctions to plates of the capacitors or to superconducting loops of superconducting quantum interference devices (SQUIDS) or connections between two ground lines of a particular transmission line for equalizing electrostatic potential on the two ground lines, are also referred to herein as interconnects. Still further, the term "interconnect" may also be used to refer to elements providing electrical interconnections between quantum circuit elements and components and non-quantum circuit elements, which may also be provided in a quantum circuit, as well as to electrical

interconnections between various non-quantum circuit elements provided in a quantum circuit.

Examples of non-quantum circuit elements which may be provided in a quantum circuit may include various analog and/or digital systems, e.g. analog to digital converters, mixers, multiplexers, amplifiers, etc.

[0086] In various embodiments, the interconnects as shown in FIG. 15 could have different shapes and layouts. For example, some interconnects may comprise more curves and turns while other interconnects may comprise less curves and turns, and some interconnects may comprise substantially straight lines. In some embodiments, various interconnects may intersect one another, in such a manner that they don't make an electrical connection, which can be done by using e.g. a bridge, bridging one interconnect over the other. As long as these interconnects operate in accordance with use of these interconnects as known in the art for which some exemplary principles were described above, quantum circuits with different shapes and layouts of the interconnects than those illustrated in FIG. 15 are all within the scope of the present disclosure.

[0087] Coupling resonators and readout resonators may be configured for capacitive coupling to other circuit elements at one or both ends in order to have resonant oscillations, whereas flux bias lines and microwave lines may be similar to conventional microwave transmission lines because there is no resonance in these lines. Each one of these interconnects may be implemented as any suitable architecture of a microwave transmission line, such as e.g. a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line. Typical materials to make the interconnects include aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), molybdenum rhenium (MoRe), and niobium titanium nitride (NbTiN), all of which are particular types of superconductors. However, in various embodiments, other suitable superconductors and alloys of superconductors may be used as well.

[0088] While FIGs. 14 and 15 illustrate examples of qubit devices comprising only two qubits 202, embodiments with any larger number of qubits are possible and are within the scope of the present disclosure. Furthermore, while FIGs. 14 and 15 illustrate embodiments specific to transmons, subject matter disclosed herein is not limited in this regard and may include other embodiments of qubit devices implementing other types of superconducting qubits that would also utilize Josephson Junctions as described herein, all of which are within the scope of the present disclosure.

Conventional cooling assembly

[0089] FIG. 16 provides a schematic illustration of a conventional assembly 300 in which qubits operate. As shown, such an assembly includes several levels of cooling, each providing cooling of the components to a certain temperature. At the lowest level of cooling, i.e. at a level where the temperatures are the lowest, is a mixing chamber 302 of a dilution refrigerator, e.g. filled with helium. A qubit device package 304 is placed into this chamber in order to keep the qubit device provided in the package at temperatures suitable for qubit operation. For example, the temperatures in the mixing chamber may be below 0.7 Kelvin.

[0090] Conventionally, the qubit device package 304 includes a package substrate 306 on which a qubit die 308 is provided. The die 308 includes a qubit device 310.

[0091] The qubit device package 304 may be placed inside a cooling apparatus, e.g. a dilution refrigerator, which may keep the qubits of the qubit device 310 at sufficiently low temperatures during qubit operation. In some embodiments, a ³He/ He dilution refrigerator may be used. A ³He/ He dilution refrigerator is a cryogenic device that can provide continuous cooling to temperatures as low as 2 milliKelvin. The cooling power is provided by the heat of mixing of the Helium-3 (³He) and Helium-4 (⁴He) isotopes. The mixing may take place in a mixing chamber 302, shown in FIG. 16. When the qubit device package 304 is placed inside the mixing chamber 302, conductive contacts 312 on the qubit die 310 connect the die to circuitry external to the mixing chamber, e.g. to conductive pathways enclosed in heat exchangers 314 outside of the mixing chamber 302. The heat exchangers 314 may include e.g. one or more low thermal conductivity metals or alloys of metals. The heat exchangers 314 ensure that charge carriers injected into the qubit device 310 are at temperatures achieved by the next stage of cooling, a pre-cooling device 316 may comprise a still. The temperatures achieved by the pre-cooling device 316 may be in the range of 0.7 to 1 Kelvin. Additional stages of pre-cooling may also be possible, as shown in FIG. 16 with a pre-cooling device 320, which provides cooling to temperatures in the range of a few Kelvin, e.g. around 4.2 Kelvin. The pre-cooling device 320 may provide charge carriers to the pre-cooling device 316 through conductive pathways enclosed in heat exchangers 318. Similar to the heat eaxhcangers 314, the heat exchangers 318 may also include e.g. one or more low thermal conductivity metals or alloys of metals.

Qubit level interconnects integrated in a single package with a qubit device die

[0092] As described above, inventors of the present disclosure realized that conventional assemblies such as the assembly 300 shown in FIG. 16 are not the most optimal in terms of sufficiently cooling the charge carriers injected into the qubit devices. FIG. 17 provides a schematic illustration of an exemplary qubit device package 404 with integrated qubit level interconnects for cooling charge carriers, according to some embodiments of the present disclosure.

[0093] As shown in FIG. 17, the qubit device package 404 may include a package substrate 406 on which a qubit die 408 is provided. The die 408 includes a qubit device 410. The qubit device 410 may be any component that includes a plurality of qubits which may be used to perform quantum processing operations. For example, the qubit device 410 may include one or more quantum dot devices 100 or one or more devices 200 or 211 implementing superconducting qubits. However, in general, the qubit device 410 may include any type of qubits, all of which are within the scope of the present disclosure.

[0094] The package substrate 406 may be or may otherwise include a silicon interposer. Silicon may have a desirably low coefficient of thermal expansion compared with other dielectric materials and thus may limit the degree to which the package substrate 406 expands and contracts during temperature changes relative to other materials (e.g. polymers having higher coefficients of thermal expansion). Limiting differential thermal expansion and contraction may help preserve the mechanical and electrical integrity of the qubit device package 404 as the qubit device package 404 is fabricated (and exposed to higher temperatures) and used in a cooled environment (and exposed to lower temperatures).

[0095] The die 408 includes a first face 422 and an opposing second face 424. Conductive contacts 412 are disposed on the first face 422 of the die 408. The second face 424 of the die is mechanically attached to a first face 426 of the package substrate using any suitable means. For example, an underfill material (not specifically shown in FIG. 17) may be provisioned between the second face of the die 408 and the first face of the package substrate 406. After the underfill material is provisioned between the second face of the die 408 and the first face of the package substrate 406, it may be cured to allow it to set for a period of time, or by exposing it to heat or another energy source. The underfill material may be, for example, an epoxy-based material, a conductive silver paste, or any other material that has limited thermal expansion (for the reasons described above).

[0096] In contrast to the conventional qubit device package shown in FIG. 16, the conductive contacts 412 of the die 408 are not electrically coupled to the external circuitry directly. Instead, a second set of conductive contacts is provided within the package 404, namely a set of conductive contacts 428 disposed on the first face of the package substrate 406 at a distance D from the qubit die 408, as illustrated in FIG. 17. In various embodiments, the distance D may be in the range between 50 micrometers and 50 millimeters, e.g. around 1 millimeter. The conductive contacts 412 of the die are electrically coupled to the associated conductive contacts 428 of the package substrate 406 through corresponding qubit level interconnects 430. [0097] The qubit level interconnects 430 may include any type of interconnects suitable for enabling control of the operation of the qubit device 410. For example, the qubit level interconnects 430 may include electrically conductive structures that would allow application of appropriate voltages to any of the plunger, barrier, and/or accumulation gates of one or more quantum dot arrays that may be realized in the qubit device 410. In some embodiments, the qubit level interconnects 430 may include electrically conductive structures that support direct currents. In some embodiments, the qubit level interconnects 430 may include electrically conductive structures that support microwave currents or pulsed currents at microwave frequencies. Such interconnects may be implemented as microwave transmission lines using various transmission line architectures, such as e.g. a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line. In some embodiments, the qubit level interconnects 430 may be made from superconducting materials, such as, but not limited to, aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN), and niobium titanium nitride (NbTiN), as well as other suitable superconductors and/or their alloys.

[0098] As illustrated in FIG. 17 with the qubit level interconnects 430 being shown with somewhat random shapes, in some embodiments, the qubit level interconnects 430 may be encompassed by or may be formed of sintered silver materials. Sintered silver materials have relatively large surface area which may provide large thermal conductivity. Therefore, such materials may be efficiently used as heat exchangers integrated into the qubit device package 404, to efficiently cool the charge carriers injected into the qubit device 410.

[0099] As described above, in some embodiments, the qubit level interconnects 430 may be formed of one or more superconducting materials. Such superconducting qubit level interconnects may additionally be encompassed by a sintered silver heat exchanger in order to more efficiently cool off the charge carriers provided to the qubit device 410. A combination of superconducting qubit level interconnects with sintered silver heat exchangers may advantageously ensure having substantially lossless electrical connectivity while also benefiting from the efficient cooling provided by the large surface area of sintered silver materials.

[00100] In various embodiments, the qubit level interconnects 430 as shown in FIG. 17 could have different shapes and layouts. For example, some qubit level interconnects 430 may comprise curves and turns while other interconnects may comprise substantially straight lines. In some embodiments, various qubit level interconnects 430 may intersect one another, in such a manner that they do not make an electrical connection. As long as these conductive pathways operate in accordance with the exemplary principles as described herein, qubit device packages with qubit level interconnects having different shapes and layouts than those illustrated in FIG. 17 with the qubit level interconnects 430 are all within the scope of the present disclosure. [00101] In some embodiments, the qubit level interconnects 430 may be suspended over the package substrate 406, e.g. at a height H as shown in FIG. 17. In various embodiments, the height H may be in the range between 1 and 1000 micrometers, e.g. around 50 micrometers.

[00102]The distance D and/or the height H may be selected as to ensure that charge carriers injected into the qubit device 410 are sufficiently cooled by travelling through the qubit level interconnects 430. In various embodiments, distances D as measured from different sides of the qubit die 408 may be different. Similarly, in various embodiments, heights H as measured from different points of the package substrate 406 to the qubit level interconnects 430 may be different. Furthermore, while the qubit device package 404 illustrates an example with two conductive contacts 412 on the first face 422 of the die 408 and two conductive contacts 428 on the first face 426 of the package substrate 406, in various embodiments, any number of conductive contacts may be provided on the die 408 and on the package substrate 406, interconnected with any number of the qubit level interconnects 430, as required for a particular design. Furthermore, in some embodiments, the conductive contacts 412 may be provided on the sides 432 of the die 408 instead of on the first face 422 of the die (such

embodiments not specifically shown in FIG. 17).

[00103]The qubit level interconnects 430 may be provided using any suitable techniques, e.g. standard solder techniques.

[00104] In some embodiments, the structures and materials in the qubit device 410 may be damaged if the qubit device 410 is exposed to high temperatures which are common in conventional integrated circuit processing (e.g. greater than 100 degrees Celsius, or greater than 200 degrees Celsius). This may affect the choice of materials used to form at least the conductive contacts 412 on the die 408. In some embodiments, such materials may include any variety of solders. In some further embodiments, the solder used for the conductive contacts 412 may be a low-temperature solder (e.g. a solder having a melting point below 100 degrees Celsius) so that it can be melted to couple the conductive contacts 412 and the qubit level interconnects 430 without having to expose the die 408 to higher temperatures and risk damaging the qubit device 410. Examples of solders that may be suitable include indium-based solders (e.g. solders including indium alloys).

[00105] In some embodiments, the same considerations as described above for the conductive contacts 412 may be used in deciding which materials to use in forming the conductive contacts 428 on the package substrate 406. Thus, a material for the conductive contacts 428 may be selected from the materials listed above for the conductive contacts 412. In various embodiments, the conductive contacts 412 and the conductive contacts 428 may be formed from the same or different materials.

[00106] However, since the conductive contacts 428 may be provided on the package substrate 406 prior to attaching the qubit die 408 to the substrate 406, the conductive contacts 428 may also include materials which may require higher temperature processing. [00107] In some embodiments, the qubit device package 404 may be used with conventional cooling assemblies such as e.g. the one shown in FIG. 16. This is shown with an assembly 500 in FIG. 18 illustrating components of FIG. 16 except that the device package 304 shown in FIG. 16 is replaced with the device package 404 as shown in FIG. 17. Descriptions of elements with reference numerals shown in FIGs. 16 and 17 are applicable to elements with the same reference numerals shown in FIG. 18. Therefore, in the interests of brevity, these descriptions are not repeated here.

[00108] In other embodiments, the implementation of the integrated qubit level interconnects 430 in the qubit device package 404 as described herein may allow eliminating one or more of the pre-cooling stages (and their associated heat exchangers) shown in the assembly of FIG. 18, such as e.g. eliminating the pre-cooling device 316 and the heat exchangers 314.

[00109] In some embodiments, the qubit device package 404 may be implemented in or may be used to implement a quantum processing device 2026 described below with reference to FIG. 20.

[00110] During operation of the qubit device 410, electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the qubit device 410 through the qubit level interconnects 430. Exactly which signals are routed/supported by the qubit level interconnects 430 would depend on the type of qubits that the qubit device 410 uses.

[00111] For example, if the qubit device 410 uses quantum dot qubits, the qubit level interconnects 430 could be configured to support application of appropriate voltages to any one of plunger, barrier gates, and/or accumulation gates in order to initialize and manipulate the quantum dots. Some examples of controlling the voltages on these gates are explained above with reference to the quantum dot device 100. In the interests of brevity, these explanations are not repeated in detail here.

[00112] In general, the term "plunger gate" is used to describe a gate under which an electro-static quantum dot is formed. By supporting the voltage applied to a plunger gate, the qubit level interconnects 430 enable modulation of the electric field underneath that gate to create an energy valley (assuming electron-based quantum dot qubits) between the tunnel barriers created by the barrier gates.

[00113] In general, the term "barrier gate" is used to describe a gate used to set a tunnel barrier (i.e. a potential barrier) between either two plunger gates (i.e. controlling tunneling of charge carrier(s), e.g. electrons, from one quantum dot to an adjacent quantum dot) or a plunger gate and an accumulation gate. When the qubit level interconnects 430 support change in the voltage applied to a barrier gate, the height of the tunnel barrier changes. When a barrier gate is used to set a tunnel barrier between two plunger gates, the barrier gate may be used to transfer charge carriers between quantum dots that may be formed under these plunger gates. When a barrier gate is used to set a tunnel barrier between a plunger gate and an accumulation gate, the barrier gate may be used to transfer charge carriers in and out of the quantum dot array via the accumulation gate. [00114] In general, the term "accumulation gate" is used to describe a gate used to form a 2DEG in an area that is between the area where the quantum dots may be formed and a charge carrier reservoir. Supporting the change in voltage applied to the accumulation gate allows the qubit level interconnects 430 to enable control of the number of charge carriers in the area under the accumulation gate. For example, changing the voltage applied to the accumulation gate allows reducing the number of charge carriers in the area under the gate so that single charge carriers can be transferred from the reservoir into the quantum dot array, and vice versa.

[00115]The qubit level interconnects 430 may further be configured to enable control of spins of charge carriers in quantum dots of the one or more qubits by controlling a magnetic field generated by the magnetic field generator. In this manner, the qubit level interconnects 430 may be able to support initialization and manipulation of spins of the charge carriers in the quantum dots to implement qubit operations. Typically, the magnetic field generator generates a microwave magnetic field of a frequency matching that of the qubit. If the magnetic field for the qubits of the qubit device 410 is generated by a microwave transmission line, then the qubit level interconnects 430 may support setting/manipulating the spins of the charge carriers by supporting applications of appropriate pulse sequences to manipulate spin precession.

[00116] In another example, if the qubit device 410 uses superconducting qubits, the qubit level interconnects 430 could be configured to support provision of appropriate currents in any of flux bias lines, microwave lines, and/or drive lines in order to initialize and manipulate the superconducting dots. Some examples of controlling the currents in these lines are explained above with reference to the devices 200 and 211. In the interests of brevity, these explanations are not repeated in detail here.

[00117] In some embodiments of superconducting qubits, the qubit level interconnects 430 may be configured to support current(s) in microwave line(s). For example, operation of the qubit device 410 may be based on the current(s) detected in the microwave line(s) by reading the current(s) in the qubit level interconnects 430. By supporting current in a microwave line, the qubit level interconnects 430 supports a control logic to assess/detect the state of the corresponding qubit(s) to which the line is coupled. In some further embodiments, the qubit level interconnects 430 may further be configured to also apply current(s) in microwave line(s). By supporting provision of the current to a microwave line, the qubit level interconnect 430 assists in controlling (e.g. changing) the state of the corresponding qubit(s) to which the line is coupled. In such further embodiments, operation of the microwave lines may be switched between providing the current in the microwave lines to control states of the qubit(s) and detecting the current in the microwave lines to detect the states of the qubit(s). Thus, the qubit level interconnects 430 can operate, along with the microwave lines, in a half-duplex mode where the microwave lines are either used for readout or for setting the state(s) of the corresponding qubits. [00118] In some embodiments of superconducting qubits, the qubit level interconnects 430 may be configured to support provision of current(s) to one or more drive lines. By supporting provision of current to a drive line, the qubit level interconnects 430 assist in controlling (e.g. changing) the state of the corresponding qubit(s) to which the line is coupled. When drive lines are used for setting the state(s) of the qubits, microwave lines may be used for readout of the state(s) of the corresponding qubits, which would be an alternative to the half-duplex mode implementation described above. For example, the qubit level interconnects 430 may be configured to support provision of current to one or more drive lines by supporting provision of one or more pulses of the current at a frequency of the one or more qubits. In this manner, the qubit level interconnects 430 can provide a microwave pulse at the qubit frequency, which in turn stimulates (i.e. triggers) a transition between the states of the corresponding qubit. Varying the length/duration of the pulse(s) can stimulate a partial transition between the states of the corresponding qubit, giving a superposition of the states of the qubit.

[00119] As noted above, any suitable techniques may be used to manufacture the qubit device package 404 disclosed herein. FIG. 19 provides a flow chart of an exemplary illustrative method 1000 for fabricating a qubit device package with integrated qubit level interconnects, according to some embodiments of the present disclosure. Although the operations discussed below with reference to the method 1000 are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g. in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method 1000 may be illustrated with reference to one or more of the embodiments described above, but the method 1000 may be used to manufacture any suitable qubit device package, including any suitable ones of the embodiments described herein.

[00120] At 1002, a package substrate may be fabricated, using any suitable technique. A set of conductive contacts such as e.g. the contacts 428 discussed above may be provided on the first face of the package substrate.

[00121] At 1004, a die may be fabricated, the die including a qubit device implementing any type of qubits, such as e.g. quantum dot qubits or superconducting qubits discussed above. A set of conductive contacts such as e.g. the contacts 412 discussed above may be provided on the first face of the die.

[00122] At 1006, a second face of the die may be mechanically attached to the first face of the package substrate, at a distance from the conductive contacts provided on the first face of the package substrate.

[00123] At 1008, the conductive contacts provided at the first face of the die may be electrically coupled to the conductive contacts provided at the first face of the package substrate through corresponding qubit level interconnects, such as e.g. the qubit level interconnects 430 described herein. [00124]The qubit level interconnects provided at 1008 may include or be encompassed by sintered silver. In some embodiments, sintered silver may be prepared from a powder of silver nanoparticles, e.g. with a diameter between 50 nanometers and 100 micrometers. The powder may then be heated to a temperature between 600 to 1000 degrees Celsius, to sinter the nanoparticles into a solid structure with a large surface area.

Exemplary quantum computing device

[00125] In various embodiments, qubit package with integrated heat exchanger for cooling charge carriers as described herein may be used to implement components associated with a quantum integrated circuit (IC). Such components may include those that are mounted on or embedded in a quantum IC, or those connected to a quantum IC. The quantum IC may be either analog or digital and may be used in a number of applications within or associated with quantum systems, such as e.g. quantum processors, quantum amplifiers, quantum sensors, etc., depending on the components associated with the integrated circuit. The integrated circuit may be employed as part of a chipset for executing one or more related functions in a quantum system.

[00126] FIG. 20 provides a schematic illustration of an exemplary quantum computing device 2000 that may include a qubit package with integrated qubit level interconnects/heat exchanger for cooling charge carriers as described herein, according to some embodiments of the present disclosure.

[00127] A number of components are illustrated in FIG. 20 as included in the quantum computing device 2000, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device 2000 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on-a- chip (SoC) die. Additionally, in various embodiments, the quantum computing device 2000 may not include one or more of the components illustrated in FIG. 20, but the quantum computing device 2000 may include interface circuitry for coupling to the one or more components. For example, the quantum computing device 2000 may not include a display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 2006 may be coupled. In another set of examples, the quantum computing device 2000 may not include an audio input device 2018 or an audio output device 2008, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 2018 or audio output device 2008 may be coupled.

[00128]The quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2002 may include a quantum processing device 2026 (e.g., one or more quantum processing devices), and a non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). The quantum processing device 2026 may include one or more of the quantum circuit components included within a qubit package with integrated qubit level interconnects/heat exchanger for cooling charge carriers disclosed herein. The quantum processing device 2026 may include any of the qubit devices disclosed herein, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits, and monitoring the result of those operations. For example, different qubits may be allowed to interact, the quantum states of different qubits may be set or transformed, and the quantum states of qubits may be read (e.g., by another qubit via a coupling resonator or externally via a readout resonator). The quantum processing device 2026 may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device 2026 may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device 2026 may also include support circuitry to support the processing capability of the quantum processing device 2026, such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to- digital converters.

[00129] As noted above, the processing device 2002 may include a non-quantum processing device 2028. In some embodiments, the non-quantum processing device 2028 may provide peripheral logic to support the operation of the quantum processing device 2026, e.g. the control logic described above. For example, the non-quantum processing device 2028 may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device 2026. For example, the non-quantum processing device 2028 may interface with one or more of the other components of the quantum computing device 2000 (e.g., the communication chip 2012 discussed below, the display device 2006 discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device 2026 and conventional components. The non-quantum processing device 2028 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), crypto processors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

[00130]The quantum computing device 2000 may include a memory 2004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device 2026 may be read and stored in the memory 2004. In some embodiments, the memory 2004 may include memory that shares a die with the non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[00131]The quantum computing device 2000 may include a cooling apparatus 2024. The cooling apparatus 2024 may maintain the quantum processing device 2026 at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device 2026. This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 degrees Kelvin or less. In some embodiments, the non-quantum processing device 2028 (and various other components of the quantum computing device 2000) may not be cooled by the cooling apparatus 2024, and may instead operate at room temperature. The cooling apparatus 2024 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator. In some embodiments, during qubit operation, the qubit package with integrated heat exchanger for cooling charge carriers as described herein may be kept within the cooling apparatus 2024.

[00132] In some embodiments, the quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured for managing wireless communications for the transfer of data to and from the quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[00133]The communication chip 2012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 1402.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 1402.16 standards. The communication chip 2012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA ( E-HSPA), or LTE network. The communication chip 2012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2012 may operate in accordance with other wireless protocols in other embodiments. The quantum computing device 2000 may include an antenna 2022 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[00134] In some embodiments, the communication chip 2012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2012 may include multiple communication chips. For instance, a first communication chip 2012 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2012 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some

embodiments, a first communication chip 2012 may be dedicated to wireless communications, and a second communication chip 2012 may be dedicated to wired communications.

[00135] The quantum computing device 2000 may include battery/power circuitry 2014. The battery/power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device 2000 to an energy source separate from the quantum computing device 2000 (e.g., AC line power).

[00136] The quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). The display device 2006 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[00137]The quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). The audio output device 2008 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[00138]The quantum computing device 2000 may include an audio input device 2018 (or corresponding interface circuitry, as discussed above). The audio input device 2018 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[00139]The quantum computing device 2000 may include a global positioning system (GPS) device 2016 (or corresponding interface circuitry, as discussed above). The GPS device 2016 may be in communication with a satellite-based system and may receive a location of the quantum computing device 2000, as known in the art.

[00140] The quantum computing device 2000 may include an other output device 2010 (or

corresponding interface circuitry, as discussed above). Examples of the other output device 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[00141] The quantum computing device 2000 may include an other input device 2020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[00142] The quantum computing device 2000, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

Selected Examples

[00143] Some Examples in accordance with various embodiments of the present disclosure are now described.

[00144] Example 1 provides a qubit device package, including a die, a package substrate, and qubit level interconnects. The die has a first face and an opposing second face and includes a qubit device including a plurality of conductive contacts at the first face of the die. The qubit device also includes a plurality of qubits, such as e.g. quantum dot qubits, superconducting qubits, or any other type of qubits. The package substrate has a first face and an opposing second face. The second face of the die is mechanically attached to the first face of the package substrate. Conductive contacts are disposed at the first face of the package substrate at a distance from a place of attachment of the second face of the die to the first face of the package substrate. The qubit level interconnects electrically couple the conductive contacts at the first face of the die with associated conductive contacts at the first face of the package substrate.

[00145] Example 2 provides the qubit device package according to Example 1, where the qubit level interconnects include sintered silver interconnects (i.e. the qubit level interconnects are formed of sintered silver) or are encompassed by sinter silver which acts as a heat exchanger. [00146] Example 3 provides the qubit device package according to Example 1, where the qubit level interconnects include a superconducting material. In some further Examples, such qubit level interconnects may advantageously be encompassed by sintered silver.

[00147] Example 4 provides the qubit device package according to Example 1, where the conductive contacts at the first face of the die are formed of solder.

[00148] Example 5 provides the qubit device package according to Example 1, where the distance is between 50 micrometers and 50 millimeters.

[00149] Example 6 provides the qubit device package according to Example 1, where the qubit level interconnects are suspended over the package substrate.

[00150] Example 7 provides the qubit device package according to Example 1, where the package substrate includes a silicon interposer.

[00151] Example 8 provides the qubit device package according to any one of Examples 1-7, where the qubit device is a quantum dot device and where the qubit device further includes a quantum well stack, a plurality of gates adjacent to the quantum well stack, and a plurality of conductive pathways coupled between associated ones of the plurality of gates and conductive contacts at the first face of the die.

[00152] Example 9 provides the qubit device package according to Example 8, where the quantum well stack is included in a fin that extends away from a base.

[00153] Example 10 provides the qubit device package according to Example 9, where the quantum well stack is a first quantum well stack, the fin is a first fin, the plurality of gates is a first plurality of gates, the plurality of conductive pathways if a first plurality of conductive pathways, and the quantum dot device further includes a second quantum well stack included in a second fin, a second plurality of gates adjacent to the second quantum well stack, and a second plurality of conductive pathways coupled between associated ones of the second plurality of gates and conductive contacts at the first face of the die.

[00154] Example 11 provides the qubit device package according to Example 10, where the first and second fins are spaced apart by an insulating material.

[00155] Example 12 provides the qubit device package according to Example 8, where the plurality of gates includes one or more plunger gates for controlling formation of quantum dots in the quantum dot device, one or more barrier gates for controlling a potential barrier between two adjacent plunger gates or between a plunger gate and an adjacent accumulation gate, and/or one or more accumulation gates for controlling a number of charge carriers in an area between an area where the quantum dots are formed and a charge carrier reservoir.

[00156] Example 13 provides the qubit device package according to any one of Examples 1-7, where the qubit device is a superconducting qubit device including a plurality of superconducting qubits and a plurality of conductive pathways electrically coupled between associated ones of the plurality of superconducting qubits and conductive contacts at the first face of the die.

[00157] Example 14 provides the qubit device package according to Example 13, where the plurality of conductive pathways include a plurality of flux bias lines associated with the plurality of

superconducting qubits, and the qubit level interconnects are configured to support provision of current to the plurality of flux bias lines.

[00158] Example 15 provides the qubit device package according to Example 13, where the plurality of conductive pathways include a plurality of microwave lines associated with the plurality of superconducting qubits, and the qubit level interconnects are configured to support detection of current in the plurality of microwave lines.

[00159] Example 16 provides the qubit device package according to Example 13, where the plurality of conductive pathways include a plurality of microwave lines associated with the plurality of superconducting qubits, and the qubit level interconnects are configured to support provision of current to the plurality of microwave lines.

[00160] Example 17 provides the qubit device package according to Example 13, where the plurality of conductive pathways include a plurality of drive lines associated with the plurality of superconducting qubits, and the qubit level interconnects are configured to support provision of current to the plurality of drive lines.

[00161] Example 18 provides the qubit device package according to Example 17, where the current provided to the plurality of drive lines includes pulsed current having a frequency equal to that of the associated superconducting qubits.

[00162] Example 19 provides a method of manufacturing a qubit device package, the method including attaching a second face of a die, the die having a first face and the opposing second face, to a first face of a package substrate; and coupling conductive contacts disposed on the first face of the die to conductive contacts disposed on the first face of the package substrate through qubit level interconnects.

[00163] Example 20 provides the method according to Example 19, where the qubit level interconnects include sintered silver interconnects and where the coupling includes providing powdered silver at locations where the qubit level interconnects are to be provides, and heating the powdered silver to form the sintered silver.

[00164] Example 21 provides the method according to Example 19, where the qubit level interconnects are suspended over the package substrate.

[00165] Example 22 provides the method according to any one of Examples 19-21, further including manufacturing the package substrate. [00166] Example 23 provides a quantum computing device, including a quantum processing device, a non-quantum processing device, and a memory device. The quantum processing device includes a die having a first face and an opposing second face. The die includes a qubit device including a plurality of conductive contacts at the first face of the die. The second face of the die is attached to a first face of a package substrate which also includes conductive contacts, at the first face of the package substrate. The conductive conducts of the package substrate are coupled to the conductive contacts at the first face of the die through qubit level interconnects. The non-quantum processing device is coupled to the quantum processing device at least partially via the package substrate, and is configured to control electrical signals applied to the qubit device applied through the qubit level interconnects. The memory device is configured to store data generated during operation of the qubit device.

[00167] Example 24 provides the quantum computing device according to Example 23, further including a cooling apparatus configured to maintain a temperature of the qubit device and of the qubit level interconnects below 0.7 degrees Kelvin.

[00168] Example 25 provides the quantum computing device according to Examples 23 or 24, where the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

[00169] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[00170] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

Claims:

1. A qubit device package, comprising:

a die having a first face and an opposing second face, wherein the die includes a qubit device including a plurality of conductive contacts at the first face of the die;

a package substrate having a first face and an opposing second face, wherein the second face of the die is attached to the first face of the package substrate and wherein conductive contacts are disposed at the first face of the package substrate at a distance from a place of attachment of the second face of the die to the first face of the package substrate; and

qubit level interconnects electrically coupling the conductive contacts at the first face of the die with associated conductive contacts at the first face of the package substrate.

2. The qubit device package according to claim 1, wherein the qubit level interconnects comprise sintered silver.

3. The qubit device package according to claim 1, wherein the qubit level interconnects comprise a superconducting material.

4. The qubit device package according to claim 1, wherein the conductive contacts at the first face of the die are formed of solder.

5. The qubit device package according to claim 1, wherein the distance is between 50 micrometers and 50 millimeters.

6. The qubit device package according to claim 1, wherein the qubit level interconnects are suspended over the package substrate.

7. The qubit device package according to claim 1, wherein the package substrate includes a silicon interposer.

8. The qubit device package according to any one of claims 1-7, wherein the qubit device is a quantum dot device and wherein the qubit device further includes:

a quantum well stack,

a plurality of gates adjacent to the quantum well stack, and

a plurality of conductive pathways coupled between associated ones of the plurality of gates and conductive contacts at the first face of the die.

9. The qubit device package according to claim 8, wherein the quantum well stack is included in a fin that extends away from a base.

10. The qubit device package according to claim 9, wherein the quantum well stack is a first quantum well stack, the fin is a first fin, the plurality of gates is a first plurality of gates, the plurality of conductive pathways if a first plurality of conductive pathways, and the quantum dot device further includes:

a second quantum well stack included in a second fin, a second plurality of gates adjacent to the second quantum well stack, and a second plurality of conductive pathways coupled between associated ones of the second plurality of gates and conductive contacts at the first face of the die.

11. The qubit device package according to claim 10, wherein the first and second fins are spaced apart by an insulating material.

12. The qubit device package according to claim 8, wherein the plurality of gates comprises: one or more plunger gates for controlling formation of quantum dots in the quantum dot device,

one or more barrier gates for controlling a potential barrier between two adjacent plunger gates or between a plunger gate and an adjacent accumulation gate, and

one or more accumulation gates for controlling a number of charge carriers in an area between an area where the quantum dots are formed and a charge carrier reservoir.

13. The qubit device package according to any one of claims 1-7, wherein:

the qubit device is a superconducting qubit device comprising a plurality of superconducting qubits and a plurality of conductive pathways electrically coupled between associated ones of the plurality of superconducting qubits and conductive contacts at the first face of the die.

14. The qubit device package according to claim 13, wherein the plurality of conductive pathways include a plurality of flux bias lines associated with the plurality of superconducting qubits, and the qubit level interconnects are configured to support provision of current to the plurality of flux bias lines.

15. The qubit device package according to claim 13, wherein the plurality of conductive pathways include a plurality of microwave lines associated with the plurality of superconducting qubits, and the qubit level interconnects are configured to support detection of current in the plurality of microwave lines.

16. The qubit device package according to claim 13, wherein the plurality of conductive pathways include a plurality of microwave lines associated with the plurality of superconducting qubits, and the qubit level interconnects are configured to support provision of current to the plurality of microwave lines.

17. The qubit device package according to claim 13, wherein the plurality of conductive pathways include a plurality of drive lines associated with the plurality of superconducting qubits, and the qubit level interconnects are configured to support provision of current to the plurality of drive lines.

18. The qubit device package according to claim 17, wherein the current provided to the plurality of drive lines comprises pulsed current having a frequency equal to that of the associated superconducting qubits.

19. A method of manufacturing a qubit device package, the method comprising:

attaching a second face of a die, the die having a first face and the opposing second face, to a first face of a package substrate; and

coupling conductive contacts disposed on the first face of the die to conductive contacts disposed on the first face of the package substrate through qubit level interconnects.

20. The method according to claim 19, wherein the qubit level interconnects comprise sintered silver interconnects and wherein the coupling comprises:

providing powdered silver at locations where the qubit level interconnects are to be provides, and

heating the powdered silver to form the sintered silver interconnects.

21. The method according to claim 19, wherein the qubit level interconnects are suspended over the package substrate.

22. The method according to any one of claims 19-21, further comprising:

manufacturing the package substrate.

23. A quantum computing device, comprising:

a quantum processing device, wherein:

the quantum processing device includes a die having a first face and an opposing second face,

the die includes a qubit device including a plurality of conductive contacts at the first face of the die,

the second face of the die is attached to a first face of a package substrate, and conductive contacts at the first face of the package substrate are coupled to the plurality of conductive contacts at the first face of the die through qubit level interconnects; a non-quantum processing device, coupled to the quantum processing device at least partially via the package substrate, to control electrical signals applied to the qubit device applied through the qubit level interconnects; and

a memory device to store data generated during operation of the qubit device.

24. The quantum computing device according to claim 23, further comprising a cooling apparatus configured to maintain a temperature of the qubit device and of the qubit level interconnects below 0.7 degrees Kelvin.

25. The quantum computing device according to claims 23 or 24, wherein the memory device is configured to store instructions for a quantum computing algorithm to be executed by the quantum processing device.