JP7310910B2 - 情報処理回路および情報処理回路の設計方法 - Google Patents

情報処理回路および情報処理回路の設計方法 Download PDF

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JP7310910B2
JP7310910B2 JP2021554008A JP2021554008A JP7310910B2 JP 7310910 B2 JP7310910 B2 JP 7310910B2 JP 2021554008 A JP2021554008 A JP 2021554008A JP 2021554008 A JP2021554008 A JP 2021554008A JP 7310910 B2 JP7310910 B2 JP 7310910B2
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circuit
information processing
processing circuit
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parameter
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JPWO2021084717A5 (https=
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崇 竹中
浩明 井上
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NEC Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks

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  • Data Mining & Analysis (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
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JP2021554008A 2019-10-31 2019-10-31 情報処理回路および情報処理回路の設計方法 Active JP7310910B2 (ja)

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JP7310910B2 true JP7310910B2 (ja) 2023-07-19

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US (1) US20220413806A1 (https=)
JP (1) JP7310910B2 (https=)
TW (1) TWI830940B (https=)
WO (1) WO2021084717A1 (https=)

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JP7456501B2 (ja) * 2020-05-26 2024-03-27 日本電気株式会社 情報処理回路および情報処理回路の設計方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004086374A (ja) 2002-08-23 2004-03-18 Ricoh Co Ltd 半導体装置
JP2018124754A (ja) 2017-01-31 2018-08-09 日本電信電話株式会社 多層ニューラルネットの大局構造抽出装置、方法、及びプログラム
JP2018132830A (ja) 2017-02-13 2018-08-23 ＬｅａｐＭｉｎｄ株式会社 ニューラルネットワーク構築方法、ニューラルネットワーク装置及びニューラルネットワーク装置更新方法

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US10552732B2 (en) * 2016-08-22 2020-02-04 Kneron Inc. Multi-layer neural network
US11586907B2 (en) * 2018-02-27 2023-02-21 Stmicroelectronics S.R.L. Arithmetic unit for deep learning acceleration
JP2019168851A (ja) * 2018-03-22 2019-10-03 東芝メモリ株式会社 演算装置及び演算方法
CN108764467B (zh) * 2018-04-04 2021-08-17 北京大学深圳研究生院 用于卷积神经网络卷积运算和全连接运算电路
WO2020095140A1 (ja) * 2018-11-08 2020-05-14 株式会社半導体エネルギー研究所 半導体装置、及び電子機器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004086374A (ja) 2002-08-23 2004-03-18 Ricoh Co Ltd 半導体装置
JP2018124754A (ja) 2017-01-31 2018-08-09 日本電信電話株式会社 多層ニューラルネットの大局構造抽出装置、方法、及びプログラム
JP2018132830A (ja) 2017-02-13 2018-08-23 ＬｅａｐＭｉｎｄ株式会社 ニューラルネットワーク構築方法、ニューラルネットワーク装置及びニューラルネットワーク装置更新方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WHATMOUGH Paul N. et al.，FIXYNN: EFFICIENT HARDWARE FOR MOBILE COMPUTER VISION VIA TRANSFER LEARNING，arXiv.org [online]，米国，Cornell University Library，2019年02月27日，[検索日 2023.03.14], インターネット:<URL: https://arxiv.org/pdf/1902.11128.pdf>

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TWI830940B (zh) 2024-02-01
JPWO2021084717A1 (https=) 2021-05-06
US20220413806A1 (en) 2022-12-29
TW202119256A (zh) 2021-05-16
WO2021084717A1 (ja) 2021-05-06

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