JP7307585B2 - Time synchronization measurement system - Google Patents

Description

The present invention relates to a time-synchronized measurement system for measuring multiple points of measurement targets at the same timing by one master device and a plurality of slave devices interconnected via a communication network.

2. Description of the Related Art Conventionally, there has been known a time synchronization system in which a large number of nodes are connected via a communication network and predetermined processing is executed while maintaining time synchronization between the nodes. Methods of time synchronization in a time synchronization system include a wired method, a wireless method, and a combination of wired and wireless methods. For example, a time synchronization system using GPS radio signals has been proposed (see Patent Document 1). Further, for example, a time synchronization system has been proposed that performs accurate time synchronization using time stamps between a master device and a slave device via a wireless LAN (see Patent Document 2). It should be noted that IEEE 1588 is also defined in relation to the time synchronization system.

JP-A-11-191919 Japanese Patent No. 5243786

In general, when applying the conventional time synchronization method described above and building a time synchronization measurement system consisting of a master device that generates a reference time and a plurality of slave devices that use time synchronized with the reference time, sounds, vibrations, etc. In order to measure the state of high-speed propagation, it is assumed that a sensor is installed at each of a plurality of measurement points. In this case, it is necessary to provide AD converters connected to the respective sensors, and to start sampling by synchronizing the timings of the respective AD converters with high accuracy. However, according to the conventional time synchronization method, even if time synchronization is maintained between the master device and a plurality of slave devices, it is difficult to synchronize the sampling start of the AD converters with high accuracy.

In order to solve the above problems, the present invention provides a time synchronization measurement system in which one master device (10) and at least one slave device (11) are interconnected via a communication network (NW), wherein the master a reference time generator (20, 21) for generating a reference time (T0) based on a reference clock (C0); a first communication unit (30) for transmitting information including the reference time to the slave device; ), the slave device includes a second communication unit (52) that receives information including the reference time from the master device, an internal time (T1) generated based on an internal clock (C1), and the A time synchronization unit (40, 41, 42) for time-synchronizing the slave device with the master device by controlling the frequency of the internal clock based on the error (E ) between the reference time and a predetermined physical quantity. A sensor unit (51) for measuring and extracting an analog signal, an AD converter (47) for sampling the analog signal and converting it to a digital signal, and a sampling clock (47) used in the AD converter based on the internal clock. SC1), a reset signal generator (46) for generating a reset signal (R1) for initializing the operation of the sampling clock generator, and a controller connected to the communication network. a device (13) , wherein the control device sets a sampling start time for the slave device and the master device when the slave device is in a time synchronization state with the master device by the time synchronization unit; The reset signal generator supplies the reset signal to the sampling clock generator at the timing when the sampling start time arrives.

According to the present invention, when the master device and the slave device are in the time synchronization state, when the predetermined sampling start time arrives, the sampling of the AD converter is started at the timing of the reset signal. At this time, since the sampling operations of all the slave devices are defined by the reference time, they have the same timing on the order of nanoseconds. Therefore, when measuring sound or vibration propagating at high speed, it is possible to perform highly accurate measurement using sensors installed at multiple points while synchronizing the time with high accuracy.

As with the slave device, the master device of the present invention includes a sensor unit, an AD conversion unit, a master device side sampling clock generation unit that generates a sampling clock used in the AD conversion unit of the master device based on a reference clock, and a master device side A master machine side reset signal generating section for generating a reset signal for initializing the operation of the sampling clock generating section can be provided. In this case, similarly to the slave device, the reset signal of the master device can be supplied to the sampling clock generator on the master device side at the timing when the sampling start time arrives when the master device and the slave devices are in the time synchronization state. As a result, for example, one master device and N slave devices can be used to install a large number of sensor units at multiple points for measurement. N is 1 or more if the master machine has a measurement function, and N is 2 or more if it does not. The maximum value of N depends on the network environment.

In the present invention, the control device can set the sampling start time for all of the master device and the plurality of slave devices when the master device and the plurality of slave devices are all in the time synchronization state. As such a control device, for example, a personal computer capable of executing a program related to time control can be used.

The time synchronization unit of the slave device includes an error detection unit that calculates the error between the internal time and the reference time and outputs it as an error signal, a voltage controlled oscillator that outputs an internal clock whose oscillation frequency is controlled according to the control voltage, It can be configured to include a PI control section that controls the control voltage based on the error signal. In this case, when controlling the control voltage, the direct control mode in which the PI control unit does not intervene and the PI control mode by the PI control unit may be switched in this order. Further, in the PI control mode, it may be possible to selectively set a plurality of stages of parameter groups with different time synchronization states according to the magnitude of the error signal. As described above, the time synchronization unit of the slave device can finely adjust the control method and parameters according to the synchronization state, environmental conditions, and the like.

A delta-sigma AD converter using delta-sigma modulation technology can be used as the AD converter of the present invention. As a result, the sampling clock of the present invention can be supplied to the MCLK (master clock) of a delta-sigma AD converter that requires sufficiently small jitter, and stabilization can be achieved. In this case, each of the plurality of slave devices further includes a down-sampling section for down-sampling the digital signal output from the AD conversion section, and generates a sampling clock for the reset signal of the slave device at the timing when the sampling start time arrives. In addition to the section, it may be supplied to the downsampling section. Further, a waveform storage section may be further provided for holding waveform data composed of digital signals output from the down-sampling section within a predetermined time range from the sampling start time.

In the present invention, the communication network can be a wireless network, and each of the first communication unit and the second communication unit can be wireless units that transmit and receive data via the wireless network. In this case, the wireless network may be a wireless LAN conforming to a predetermined standard, and a configuration may be adopted in which transmission and reception are performed between the master device and a plurality of slave devices via wireless LAN access points.

According to the present invention, it is possible to achieve high-precision time synchronization between a master device and a plurality of slave devices, and to match the sampling start timings of the AD converters used in the respective sensor units with high precision. It is possible to realize a time-synchronized measurement system suitable for simultaneous measurement of sound, vibration, etc. at a large number of measurement points.

1 is a block diagram showing a schematic configuration of a time synchronization measurement system according to this embodiment; FIG. 3 is a diagram showing the configuration of the master machine 10. FIG. 3 is a diagram showing the configuration of a slave device 11; FIG. 4 is a diagram showing a specific configuration example of a PI control unit 41; FIG. 4 is a flow chart showing the flow of operations related to time synchronization between the master device 10 and the slave device 11 in the time synchronization measurement system of this embodiment.

Preferred embodiments of the present invention will be described below with reference to the drawings. However, the embodiment described below is an example of a form to which the technical idea of the present invention is applied, and the present invention is not limited by the content of the present embodiment. In this embodiment, a case will be described in which the present invention is applied to a time-synchronized measurement system for measuring physical quantities such as sound and vibration in an object to be measured.

FIG. 1 is a block diagram showing a schematic configuration of a time synchronization measurement system (hereinafter simply referred to as "measurement system") of this embodiment. As shown in FIG. 1, the measurement system of this embodiment is interconnected via a communication network NW, and includes one master device 10, N slave devices 11(1) to 11(N), and one It comprises an access point 12 and one control device 13 . In the following description, the N slave devices 11(1) to 11(N) are simply referred to as slave device 11 without distinguishing between them.

In FIG. 1, the communication network NW is, for example, a wireless LAN conforming to a predetermined standard, and in this case the access point 12 functions as a wireless LAN access point, and each master device 10, slave device 11, control device It has the role of relaying data transmission and reception between 13. The control device 13 is, for example, a general personal computer, and stores and saves a program to be executed when performing time control, which will be described later. One master device 10 and N slave devices 11 are installed in respective parts of the object to be measured, and have the role of measuring physical quantities such as sound and vibration at common timing synchronized with each other. By performing measurements in a time-synchronized state with high accuracy, it is possible to measure the state of propagation of physical quantities with high accuracy, so that more detailed structural analysis and abnormality diagnosis can be performed.

Here, with reference to FIGS. 2 and 3, the configuration and operation of mainly the master device 10 and the slave device 11 in the measurement system of FIG. 1 will be specifically described. Although only one slave device 11 is shown in FIG. 3, the configuration of the other N−1 slave devices 11 is omitted because they have the same configuration.

As shown in FIG. 2, the master device 10 includes a crystal oscillator 20, a clock section 21, a time stamper 22, a sampling clock generation section 23, a reset signal generation section 24, an AD conversion section 25, an AAF (Anti -Aliasing Filter) section 26 , downsampling section 27 , waveform storage section 28 , sensor section 29 and radio section 30 . Although not shown in FIG. 2, the master device 10 has a control section for controlling operations.

In the master device 10, the crystal oscillator 20 is an oscillation circuit using a crystal oscillator, and generates a reference clock C0 having a predetermined oscillation frequency as a timing reference. The clock unit 21 functions as clocking means of the master device 10, counts the reference clock C0 output from the crystal oscillator 20, and outputs the count value as the reference time T0. The reference time T0 is not an absolute time. For example, it can start from 0 after the power of the master device 10 is turned on and can be incremented one by one like 1, 2, 3. In FIG. 2 , the crystal oscillator 20 and the clock section 21 function as a reference time generation section in the master device 10 .

In this embodiment, the reference time T0 is the reference for time synchronization of all the slave devices 11, which will be described later in detail. The reference time T0 by the clock unit 21 is, for example, in increments of 1 nanosecond, and its accuracy depends on the oscillation frequency of the crystal oscillator 20 . Each clock of the crystal oscillator 20 counts up the reference time T0 by a predetermined nanosecond.

The time stamper 22 recognizes a beacon received from the access point 12 via the radio section 30 and generates a time stamp TS0 including the reference time T0 input from the clock section 21 at that time. A beacon periodically transmitted by the access point 12 is added with a TSF (Timing Synchronization Function) value as an identifier, and a beacon having the same TSF value is received by both the master device 10 and the slave device 11. be. In the time stamper 22, the received beacon with TSF value and the reference time T0 at that time are paired and listed. Also, the time stamp TS0 generated by the time stamper 22 is transmitted from the wireless unit 30 to the slave device 11 via the access point 12, and the operation at that time will be described later.

The sampling clock generator 23 divides the frequency of the reference clock C0 output from the crystal oscillator 20 to generate the sampling clock SC0 used for the operation of the AD converter 25 . For example, when the frequency of the reference clock C0 is 50 MHz and the sampling clock generator 23 divides the frequency of the reference clock C0 by 8, the frequency of the sampling clock SC0 is 6.25 MHz. Note that the actual frequency of the sampling clock SC0 is appropriately determined according to the specifications of the AD converter 25, which will be described later.

The reset signal generation unit 24 generates a reset signal R0 for initializing the operation of each of the sampling clock generation unit 23 and the downsampling unit 27 when a later-described sampling start time set by the control device 13 arrives. That is, the reset signal generation unit 24 outputs the reset signal R0 at the timing when the reference time T0 output from the clock unit 21 coincides with the preset sampling start time. By initialization, the operation of the sampling clock generation unit 23 and the downsampling unit 27 is started at the sampling start time that coincides with the reset signal R0, and the phases of the other slave devices 11 are aligned on the order of nanoseconds at the same timing. be started. Also, the sampling start time may be set separately as the first sampling start time for the sampling clock generator 23 and the second sampling start time for the down-sampling unit 27 . In that case, the first sampling start time and the second sampling start time may be the same, or the second sampling start time may be set a predetermined time after the first sampling start time.

The AD conversion section 25 uses the sampling clock SC0 generated by the sampling clock generation section 23 to convert the analog signal output from the sensor section 29 into a digital signal. As the AD converter 25, a delta-sigma AD converter that converts an analog signal into a digital signal using a so-called delta-sigma modulation technique can be used. When the aforementioned sampling clock SC0 is supplied as MCLK (master clock), it is required to use MCLK with high stability and extremely small jitter.

The AAF section 26 is a filter that removes aliasing (aliasing noise) that occurs during sampling of the digital signal output from the AD conversion section 25 . Further, the down-sampling unit 27 thins out the digital signal by sampling the digital signal output from the AAF unit 26 using a frequency lower than the sampling clock SC0. Therefore, the down-sampling section 27 outputs a digital signal at a data rate with a frequency lower than that of the sampling clock SC0. As described above, the operation of the downsampling section 27 is started in response to the reset signal R0. Therefore, the start timing can be synchronized on the order of nanoseconds.

The waveform storage unit 28 is storage means for holding waveform data composed of digital signals output from the down-sampling unit 27 within a predetermined time range from the sampling start time. The waveform data held in the waveform storage section 28 corresponds to the waveform pattern of the analog signal of the sensor section 29 within the aforementioned time range. As the waveform storage unit 28, an internal storage device of the master device 10 may be used, but an external storage device connectable to the master device 10 directly or via a wireless network may also be used.

The sensor unit 29 is a sensor that is attached to an object to be measured and detects a predetermined physical quantity. The measurement system of the present embodiment aims at measuring physical quantities with high transmission speeds at the same timing from a large number of measurement points on the measurement object, instead of constantly monitoring the measurement object. Therefore, as the sensor unit 29, for example, an acceleration sensor, a microphone, or the like for measuring vibration of each part of a building or sound at each position in a predetermined space can be used.

The wireless unit 30 (first communication unit of the present invention) is a module that wirelessly transmits and receives data within the network NW. As already explained, the radio unit 30 transmits the time stamp TS0 to all the slave devices 11 via the access point 12 and receives control signals (including the sampling start time) from the control device 13 .

Next, as shown in FIG. 3, the slave device 11 includes an error detector 40, a PI controller 41, a VC-TCXO (Voltage-Controlled Temperature Compensated Crystal Oscillator) 42 which is a voltage-controlled oscillator of the present invention, and a clock. section 43, time stamper 44, sampling clock generation section 45, reset signal generation section 46, AD conversion section 47, AAF section 48, down-sampling section 49, waveform storage section 50, sensor section 51 , and a radio unit 52 . Although not shown in FIG. 3, like the master device 10, the slave device 11 has a control section for controlling its operation.

In the slave device 11, the error detection unit 40 receives the aforementioned time stamp TS0 generated by the time stamper 22 of the master device 10 via the access point 12 and the radio unit 52, and the time stamper 44 of the slave device 11. A later-described time stamp TS1 generated in 1 is input, and an error signal E indicating an error between the reference time T0 and the later-described internal time T1 is detected. Specifically, in the error detection unit 40, by subtracting the internal time T1 of the slave device 11 from the reference time T0 of the master device 10 at the same TSF value of the time stamps TS0 and TS1, the error signal E (=T0- T1) is calculated.

The PI control section 41 controls the control voltage Vc supplied to the VC-TCXO 42, which will be described later, based on the error signal E output from the error detection section 40. FIG. In this embodiment, when adjusting the time, it is possible to switch between a direct control mode in which the PI control unit 41 does not intervene and a PI control mode by the PI control unit 41 according to the synchronization state of the slave device 11 . Of these modes, the direct control mode is a method of forcibly adding or subtracting a time difference to or from the internal time T0 when the error signal E at the beginning of the operation is large (e.g., equivalent to 1 second). On the other hand, when the error signal E is relatively small, the PI control section 41 operates to shift to the PI control mode.

Here, FIG. 4 shows a specific configuration example of the PI control unit 41. As shown in FIG. The PI control unit 41 shown in FIG. 4 includes a multiplier 60 that multiplies the error signal E by the P gain, an integrator 61 that integrates the error signal E, a multiplier 62 that multiplies the output of the integrator 61 by the I gain, 2 It includes an adder 63 that adds the outputs of the two multipliers 60 and 62 and a limiter 64 that limits the output level of the adder 63 . The output of the limiter 64 is directly supplied to the VC-TCXO 42 as the control voltage Vc.

The PI control unit 41 in FIG. 4 can implement feedback control for the oscillation frequency of the VC-TCXO 42 among the entire configuration of the slave device 11 . Further, by providing a limiter 64 at the final stage to limit the upper and lower limits of the output level of the adder 63, the control voltage Vc can be limited within an appropriate range even when the synchronous state is deviated. The internal clock C1 output from the TCXO 42 can be stabilized within an appropriate frequency range. Therefore, even if the sampling clock SC0 supplied to the AD converter 25 is out of synchronous state, it is limited within an appropriate range. can continue to operate. The P gain and I gain in FIG. 4 can be changed according to the time synchronization state of the slave device 11 . Note that FIG. 4 is an example, and the PI control unit 41 can be replaced with various control circuits that can implement similar feedback control.

Returning to FIG. 3, the VC-TCXO 42 is a temperature-compensated crystal oscillator whose oscillation frequency can be controlled according to the control voltage Vc supplied from the PI control section 41, and generates an internal clock C1. The frequency of the internal clock C1 speeds up or slows down the progress of the time of the clock section 43. FIG. When the error signal E is within the allowable range, the internal clock C1 has a phase shift from the reference clock C0 of the master device 10 within the allowable range.

The respective functions of the clock section 43 and the time stamper 44 are generally the same as those of the clock section 21 and the time stamper 22 of the master device 10, so detailed description thereof will be omitted. Note that, as shown in FIG. 3, the clock unit 43 outputs an internal time T1 based on the internal clock C1, and the time stamper 44 outputs a time stamp TS1 including the internal time T1. Like the reference time T0, the internal time T1 can start from 0 after the power of the slave device 11 is turned on and can be incremented one by one like 1, 2, and 3, for example. In this case, when time synchronization is established between the master device 10 and the slave device 11, the internal time T1 coincides with the reference time T0. Note that the time stamper 44 receives the above-described beacon via the access point 12 and the wireless unit 52 in the same manner as the time stamper 22 of the master device 10 . In FIG. 3, the error detection section 40, the PI control section 41, the VC-TCXO 42, and the clock section 43 function as a time synchronization section in the slave device 11. FIG.

Also, a sampling clock generation unit 45, a reset signal generation unit 46, an AD conversion unit 47, an AAF unit 48, a downsampling unit 49, a waveform storage unit 50, a sensor unit 51, and a radio unit 52 (second communication unit of the present invention) also have functions common to the sampling clock generation unit 23, reset signal generation unit 24, AD conversion unit 25, AAF unit 26, down-sampling unit 27, waveform storage unit 28, sensor unit 29, and radio unit 30 of the master device 10, respectively. , the description is omitted. Note that, as shown in FIG. 3, the sampling clock generator 45 outputs a sampling clock SC1 based on the internal clock C1, and the reset signal generator 46 outputs a reset signal R1. The sampling clock SC1 and reset signal R1 change in the same manner as the sampling clock SC0 and reset signal R0 of the master device 10 if the master device 10 and slave device 11 are time-synchronized.

In this embodiment, the master device 10 includes the sensor section 29 and related components, but the master device 10 that does not include the sensor section 29 and the like may be used. Specifically, a configuration may be adopted in which only the crystal oscillator 20, the clock unit 21, the time stamper 22, and the radio unit 30 are provided in the master device 10, and other components are not provided. In this case, the master device 10 does not function as measuring means using the sensor section 29, and has only the reference time generating function. Also, a configuration in which the master machine 10 is integrated with the control device 13 may be adopted.

2 and 3, a configuration without the AAF units 26 and 48 and the down-sampling units 27 and 49 may be employed. For example, if the AD converters 25 and 47 sufficiently cover the low frequency range, downsampling of the digital signal can be omitted. The communication network NW in FIG. 1 is not limited to a wireless LAN, and may be of a different wireless system. In this case, the time stampers 22 and 44 may not be provided. As the communication network NW, a wired network or a network combining wired and wireless may be adopted. In this case, the radio units 30 and 52 may be replaced with radio units or communication units compatible with the communication system of the network NW.

Hereinafter, the time synchronization operation of the master device 10 of FIG. 2 and the slave device 11 of FIG. 3 in the measurement system of this embodiment will be described with reference to FIG. FIG. 5 is a flowchart mainly showing a flow related to time synchronization between the master device 10 and the slave device 11. As shown in FIG. In the following description, the operation of the slave machine 11 is common to all of the N slave machines 11. FIG. First, as shown in FIG. 5, the master device 10 and the slave device 11 are activated by power-on (steps S10 and S20). Subsequently, the wireless unit 30 of the master device 10 and the wireless unit 52 of the slave device 11 operate to establish a wireless LAN connection within the network NW including the master device 10 and the slave device 11 (steps S11, S21).

Next, transmission of the time stamp TS0 from the master device 10 to the slave device 11 is started (step S12), and at the same time detection of the error signal E by the error detector 40 of the slave device 11 is started (step S22). Immediately after step S22, the slave device 11 is asynchronous with the master device 10 and the error signal E has a large value. In the direct control mode, the slave device 11 is in a time synchronization state with low precision, but when the error signal E falls within the allowable range, the direct control mode is switched to the PI control mode by the PI control unit 41 (step S22a). When switching in step S22a, in addition to the value of the error signal E, the state of wireless communication, the output state of the PI control unit 41, and the like are taken into consideration.

After a certain period of time has elapsed from steps S12 and S22, the error signal E becomes sufficiently small, and the master device 10 and the slave device 11 shift to highly accurate time synchronization (steps S13 and S23). At this point in time, the reference clock C0 of the master device 10 and the internal clock C1 of the slave device 11 are in phase with each other, and the reference time T0 of the master device 10 and the internal time T1 of the slave device 11 coincide on the order of nanoseconds. It is in. When each of the N slave devices 11 transitions to a high-precision time synchronization state and maintains the high-precision time synchronization state for a predetermined period of time, it is determined that the time synchronization is stable, and a notification signal is sent. Send to the control device 13 .

Next, when the control device 13 receives this notification signal from all the slave devices 11, it sets the aforementioned sampling start times for the master device 10 and the slave devices 11 (step S30). When it is difficult for all the slave devices 11 to be time-synchronized due to the situation at the measurement site, the sampling start time may be set by receiving notification signals from some of the slave devices 11 . At this time, a highly accurate time synchronization state is maintained between the master device 10 and the slave device 11 . Thereafter, the master device 10 and the slave device 11 continue to wait until the sampling start time arrives (steps S14, S24).

After that, when the sampling start time arrives in the master device 10 and the slave device 11 (step S14: YES, S24: YES), reset signals R0 and R1 are output from the respective reset signal generators 24 and 46 (step S15). , S25). As a result, the sampling clock generators 23, 45 and down-sampling units 27, 49 of the master device 10 and the slave device 11 are initialized at the same timing. Then, in the master device 10 and the slave device 11, the sampling operation is continued until a predetermined time (preset sampling number) has passed from steps S15 and S25 (steps S16 and S26). After that, the sampling operation is terminated, and the waveform data during that period is held in the waveform storage units 28 and 50 of the master device 10 and the slave device 11, completing the series of operations in FIG.

Here, the PI control mode of step S22a by the slave device 11 will be specifically described. As described with reference to FIG. 4, the control voltage Vc supplied to the VC-TCXO 42 changes differently depending on the P gain and I gain in the PI control section 41 . Therefore, it is desirable to set a plurality of stages of parameter groups consisting of different combinations of P gain and I gain in advance so that desired parameters in the PI control mode can be selectively set. In this case, the response speed of the control voltage Vc by the PI control unit 41 differs depending on the P gain and the I gain. It may be switchable.

For example, in the PI control mode, the parameter with the slowest response speed of the control voltage Vc is set as the first stage, the response speed becomes faster in order from the second stage to the third stage, and the parameter with the fastest response speed is set as the fourth stage. can do. Thus, in the PI control mode, the first stage parameters are used when the error signal E is large, and the fourth stage parameters are used when the error signal E is sufficiently small. Initially, it is efficient to set parameters for the second or third stage.

As described above, the measurement system of the present embodiment realizes highly accurate time synchronization between the master device 10 and the plurality of slave devices 11, and at the same time, the AD converters 25 and 47 are controlled by the reset signals R0 and R1. Sampling operations can be started at the same timing. In this case, in the conventional time synchronization method, even if time synchronization is achieved, the possibility that the respective sampling clocks may deviate cannot be ruled out. Since the reference time T0 is synchronized with the internal time T1, and the phase of the reference clock C0 is synchronized with the phase of the internal clock C1, it is possible to reliably match the sampling start times based on the reset signals R0 and R1. can.

A delta-sigma type AD converter is used for the AD converters 25 and 47 of this embodiment. AD converters are generally used in the field of measurement. If jitter occurs in the AD converter's master clock (sampling clocks SC0 and SC1 in this embodiment), sampling may stop due to malfunction or stoppage of operation. In the field of measurement, there is a demand to continue taking data until the end of the measurement even if the measurement becomes asynchronous. Therefore, in this embodiment, even if some of the slave devices 11 change from the time-synchronized state to the non-time-synchronized state due to a communication failure or the like, the limiter 64 of the PI control unit 41 keeps the control voltage Vc within an appropriate range. made it possible to maintain Therefore, since the frequency of the internal clock C1 output from the VC-TCXO 42 can be maintained within an appropriate range, it is possible to avoid the occurrence of jitter in the sampling clock SC1 generated based on the internal clock C1. The operation state of the AD converters 25 and 47 using AD converters can be maintained, and sampling can be continued until a predetermined measurement time has elapsed.

The measurement system of this embodiment is not limited to the configuration and operation shown in FIGS. 1 to 5, and various modifications can be envisaged. For example, among the configurations shown in FIGS. 2 and 3, a configuration in which the AAF units 26 and 48 of the master device 10 and slave device 11 are replaced with effective value processing units, respectively, may be employed. In this case, the effective value processing unit calculates and outputs the effective value of the digital signal obtained by the AD conversion units 25 and 47, and the waveform storage units 28 and 50 store the sensor output level (effective value) instead of the waveform data. value).

Reference Signs List 10 Master device 11 Slave device 12 Access point 13 Control device 20 Crystal oscillators 21, 43 Clock units 22, 44 Time stampers 23, 45 Sampling clock generation units 24, 46 Reset signal generation unit 25, 47 AD conversion units 26, 48 AAF units 27, 49 Down sampling units 28, 50 Waveform storage units 29, 51 Sensor units 30, 52 Radio unit 40 Error detection unit 41 PI control unit 42 VC -TCXO
60, 62 Multiplier 61 Integrator 63 Adder 64 Limiter NW Communication network

Claims (7)

In a time synchronous measurement system in which one master device and at least one slave device are interconnected via a communication network,
The master machine
a reference time generator that generates a reference time based on a reference clock;
a first communication unit that transmits information including the reference time to the slave device;
with
The slave machine
a second communication unit that receives information including the reference time from the master device;
a time synchronization unit that time-synchronizes the slave device with the master device by controlling the frequency of the internal clock based on the error between the internal time generated based on the internal clock and the reference time;
a sensor unit that measures a predetermined physical quantity and extracts an analog signal;
an AD converter that samples the analog signal and converts it into a digital signal;
a sampling clock generation unit that generates a sampling clock used in the AD conversion unit based on the internal clock;
a reset signal generator that generates a reset signal that initializes the operation of the sampling clock generator;
a control device connected to the communication network ;
with
The control device sets a sampling start time for the slave device and the master device when the slave device is in a time synchronization state with the master device by the time synchronization unit,
The time synchronous measurement system , wherein the reset signal generator supplies the reset signal to the sampling clock generator at the timing when the sampling start time arrives. The master machine further
the sensor unit;
the AD conversion unit;
a master device side sampling clock generation unit that generates a sampling clock used in the AD conversion unit of the master device based on the reference clock;
a master device-side reset signal generation unit that generates a reset signal that initializes the operation of the master device-side sampling clock generation unit;
with
The reset signal of the master device is supplied to the master device side sampling clock generation unit at the timing when the sampling start time arrives when the master device and the slave device are in the time synchronization state. The time synchronous measurement system according to claim 1. comprising a plurality of said slave machines,
The control device sets the sampling start time to all of the master device and the plurality of slave devices when the master device and the plurality of slave devices are all in a state of time synchronization. The time synchronous measurement system according to claim 1 or 2. The AD converter is a delta-sigma AD converter that uses the sampling clock as a master clock,
The time synchronization is
a voltage controlled oscillator that increases or decreases the frequency of the internal clock by a control voltage based on the error between the internal time and the reference time and outputs the frequency;
Having a limiter that limits the maximum value of the control voltage,
In a predetermined time range from the sampling start time, the frequency of the sampling clock is maintained within a predetermined range even if the slave device is out of the time synchronization state, and the delta-sigma AD converter does not perform sampling. 4. The time-synchronized measurement system according to claim 3, characterized in that it continues. The slave device further comprises a downsampling unit that downsamples the digital signal,
5. The time-synchronized measurement according to claim 4, wherein the reset signal of the slave device is supplied to the down-sampling section in addition to the sampling clock generating section at the timing when the sampling start time arrives. system. 6. The time-synchronized measurement system according to claim 5, further comprising a waveform storage unit that holds waveform data composed of digital signals output from the down-sampling unit within a predetermined time range from the sampling start time. . the communication network is a wireless network;
each of the first communication unit and the second communication unit is a wireless unit that transmits and receives data via the wireless network;
2. The wireless network is a wireless LAN conforming to a predetermined standard, and transmission and reception are performed between the master device and the slave device via an access point of the wireless LAN. 7. The time synchronous measurement system according to any one of 6.

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