JP7304322B2 - power converter - Google Patents

Description

TECHNICAL FIELD Embodiments of the present invention relate to power converters.

Modular multi-level converter (MMC) type power converters, in which a plurality of unit converters are connected in series, can easily achieve a high withstand voltage, and are being used for DC power transmission, frequency converters, and the like.

By bypassing unit converters connected in series (see, for example, Patent Document 1), redundant operation of the converters is facilitated, which can contribute to improving the availability of the power system.

Since the unit converter uses a half-bridge or full-bridge type, there is a mode in which current flows through the reverse conducting diode. If the unit converter performs a bypass operation at the timing when current flows through the reverse conducting diode, an excessive voltage may be applied to the reverse conducting diode. Reverse recovery operation of the reverse conducting diode and application of overvoltage may damage the reverse conducting diode.

There is a demand for a power converter that can safely continue operation without damaging the reverse conducting diodes regardless of the timing of the bypass operation of the unit converter.

JP 2017-175740 A

An object of the embodiment is to provide a power converter that can safely perform a bypass operation.

A power conversion device according to an embodiment includes a power conversion section including a plurality of unit converters connected in series, and a control device that controls the power conversion section. The plurality of unit converters include a first switching element, a second switching element connected in series with the first switching element, a first diode connected in anti-parallel with the first switching element, and the first A second diode connected in anti-parallel to two switching elements, and a capacitor connected in parallel to a series circuit of the first switching element and the second switching element, respectively. Each of the plurality of unit converters changes the voltage across the capacitor by the switching operations of the first switching element and the second switching element when the voltage across the capacitor is lower than a predetermined overvoltage threshold value. and turns off the first switching element and turns on the second switching element for bypass operation when the voltage value across the capacitor exceeds the overvoltage threshold value. . di/dt of the current flowing through the second switching element when the second switching element is turned on during the bypass operation is It is set smaller than di/dt of the flowing current.

The present embodiment provides a power conversion device that can safely perform a bypass operation.

1 is a schematic block diagram illustrating a power converter according to an embodiment; FIG. FIGS. 2(a) and 2(b) are schematic block diagrams illustrating a part of the power converter according to the embodiment. It is a typical block diagram which illustrates a part of power converter of an embodiment. 4(a) and 4(b) are schematic circuit diagrams for explaining the operation of the power converter of the embodiment. FIG. 4 is a schematic operation waveform diagram for explaining the operation of the power conversion device of the embodiment;

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each portion, the size ratio between portions, and the like are not necessarily the same as the actual ones. Also, even when the same parts are shown, the dimensions and ratios may be different depending on the drawing.
In addition, in the present specification and each figure, the same reference numerals are given to the same elements as those described above with respect to the already-appearing figures, and detailed description thereof will be omitted as appropriate.

FIG. 1 is a schematic block diagram illustrating a power conversion device according to an embodiment.
As shown in FIG. 1 , the power conversion device 10 includes a power conversion section 20 and a control device 50 . Power converter 20 includes terminals 21a to 21c. The power converter 20 is connected to the AC circuit 1 via terminals 21a to 21c. As in this example, the power converter 20 may be connected to the AC circuit 1 via the transformer 2 . The AC circuit 1 can include, for example, an AC power source, an AC load, a transmission line, and the like. The AC circuit 1 is, for example, a three-phase AC power system.

Power converter 20 includes terminals 21d and 21e. The power converter 20 is connected to the DC circuit 3 via terminals 21d and 21e. The DC circuit 3 can include, for example, a DC power supply, a DC load, a DC transmission line, and the like. The DC circuit 3 is, for example, a DC power system.

The power conversion device 10 of the embodiment is connected between the AC circuit 1 and the DC circuit 3, and performs power conversion between AC and DC bidirectionally or in either direction.

Power converter 20 includes a plurality of unit converters 30 . A plurality of unit converters 30 are connected in series. The n unit converters 30 are connected in series to form an arm 22 . Arms 22 are connected in series via reactors 24 . A series circuit of the arm 22 and the reactor 24 is called a leg. In this example, three legs are provided so as to correspond to each phase of the three-phase alternating current. The three legs are connected in parallel between terminals 21d and 21e.

The control device 50 is connected to the power converter 20 . Control device 50 and power converter 20 are connected, for example, by an optical fiber cable. This optical fiber cable is provided for transmitting control data including control signals for operating each unit converter.

By bypassing the failed unit converter 30, the MMC removes that unit converter from the arm 22 and allows the entire arm 22 to continue operating. Thereby, the power conversion device 10 can continue to operate.

FIGS. 2(a) and 2(b) are schematic block diagrams illustrating a part of the power converter according to the embodiment.
2(a) and 2(b) show the circuit configuration of the unit converter 30. FIG. FIG. 2(a) shows an example of a half-bridge type main circuit, and FIG. 2(b) shows an example of a full-bridge type main circuit.
As shown in FIG. 2(a), the unit converter 30 includes switching elements 31a and 31b, reverse conduction diodes 32a and 32b, and a capacitor 33. As shown in FIG. The switching elements 31a and 31b are connected in series. In the series circuit of the switching elements 31a and 31b, the switching element 31a (first switching element) is connected to the high potential side, and the switching element 31b (second switching element) is connected to the low potential side. The switching elements 31a and 31b are, for example, IGBTs (Insulated Gate Bipolar Transistors). Even in the case of a full-bridge type main circuit, which will be described later, the switching elements may be voltage-driven switching elements, and may be MOSFETs instead of IGBTs.

A reverse conducting diode 32a (first diode) is connected in anti-parallel to the switching element 31a. A reverse conducting diode 32b (second diode) is connected in antiparallel to the switching element 31b. The capacitor 33 is connected in parallel with the series circuit of the switching elements 31a and 31b.

Unit converter 30 includes terminals 30a and 30b. The terminal 30a is connected to a connection node of the switching elements 31a and 31b. The terminal 30b is connected to the main terminal on the low potential side of the switching element 31b. In this example, the switching elements 31a and 31b are IGBTs, and the main terminal on the low potential side of the switching element 31b is the emitter terminal. The unit converter 30 is connected in series to other unit converters 30 via terminals 30a and 30b.

The switching elements 31a and 31b are turned on and off by complementary gate drive signals during normal operation of the power converter 10, thereby charging and discharging the voltage across the capacitor 33 to a desired value.

In bypass operation, the switching elements 31a and 31b turn off the switching element 31a and turn on the switching element 31b by complementary gate drive signals. This shorts the terminals 30a and 30b and removes the unit converter 30 from the arm 22 on which the bypassed unit converter 30 is mounted.

Bypass operation is performed in response to several failure modes in unit converter 30 . In the power converter 10 of the present embodiment, the conditions for the bypass operation include the detection of an overvoltage in which the voltage across the capacitor 33 of the unit converter 30 becomes higher than the rated voltage. An appropriate value can be arbitrarily set as the overvoltage detection voltage. In addition to overvoltage protection, bypass operation conditions can be low voltage protection when the voltage across the capacitor 33 is lower than the rated voltage, when there is an abnormality in the unit converter 30, and the like.

In the power converter 10 of the embodiment, the ON time of the switching element 31b in the bypass operation is set in advance so as to be later than the ON time of the switching element 31b in normal operation. In the switching element 31b, the surge voltage (recovery surge) generated across the reverse conducting diode 32a when the switching element 31b is turned off can be suppressed by setting the on-time speed during the bypass operation to be slow. By suppressing the surge voltage across the reverse conducting diode 32a, the reverse conducting diode 32a is less likely to be damaged. It should be noted that the ON time of the switching element 31b means the rising time of the current flowing through the switching element.

As shown in FIG. 2(b), the unit converter 130 includes switching elements 31a-31d, reverse conducting diodes 32a-32d, and a capacitor 33. As shown in FIG. The switching elements 31a and 31b are connected in series. The switching elements 31c and 31d are connected in series. The reverse conducting diodes 32a-32d are connected in anti-parallel to the switching elements 31a-31d, respectively. The capacitor 33 is connected in parallel to the series circuit of the switching elements 31a and 31b and the series circuit of the switching elements 31c and 31d.

In the bypass operation of the full-bridge unit converter 130, the switching elements 31b and 31d are turned on and the switching elements 31a and 31c are turned off. When the switching elements 31b and 31d are turned on, the on time is set to be later than in the case of normal switching operation. Even if one of the reverse-conducting diodes 32a and 32c causes a reverse recovery phenomenon, the surge voltage generated across the reverse-conducting diodes 32a and 32c by the switching elements 31b and 31d set to a slow ON time is Suppressed.

In the full-bridge type unit converter 130, the bypass operation is not limited to the case described above, and the switching elements 31a and 31c may be turned on and the switching elements 31b and 31d may be turned off. Even in this case, the on-time of the switching elements 31a and 31c is set later than the on-time in the normal switching operation. Thereby, the surge voltage applied across the reverse conducting diodes 32b and 32d can be suppressed.

FIG. 3 is a schematic block diagram illustrating part of the power conversion device of the embodiment.
FIG. 3 schematically shows part of the drive circuit 35 for the switching element 31b. FIG. 3 is a diagram for explaining the concept of the operation of the drive circuit 35, and the configuration of the level shift circuit and the like in the drive circuit 35 is omitted.
As shown in FIG. 3, the drive circuit 35 includes inverters 351 and 353, AND circuits 352a and 352b, drive transistors 354a and 354b, and a bypass drive transistor 356 in this example.

An input of the drive circuit 35 is connected to a control circuit (not shown). The control circuit generates an ON command and an overvoltage protection ON command and supplies them to the drive circuit 35 . The ON command is a command for generating a gate drive signal for normal switching operation of the switching element 31b. In this example, the switching element 31b is turned on when the ON command is at high level, and the switching element 31b is turned off when the ON command is at low level. The ON command is supplied to drive circuit 35 when unit converter 30 operates normally.

The overvoltage protection ON command is generated and supplied to the drive circuit 35 when the unit converter 30 is bypassed. In this example, when the overvoltage protection ON command is at high level, the ON command is invalidated and the switching element 31b is turned ON. Therefore, ON/OFF operation is performed.

The output of drive circuit 35 is connected to the gate and emitter of switching element 31b. The switching element 31b outputs a gate drive signal to drive the switching element 31b based on the ON command and the overvoltage protection ON command.

The switching element 31b is turned off by applying a voltage lower than the threshold voltage between the gate and the emitter. The switching element 31b applies a voltage sufficiently lower than the threshold voltage between the gate and the emitter in order to speed up the turn-off speed. In this example, a negative voltage is applied between the gate and emitter of the switching element 31b when turned off. Power sources 34 a and 34 b are connected to the drive circuit 35 . The power supply 34a supplies a positive voltage between the gate and the emitter for turning on the switching element 31b, and the power supply 34b supplies a negative voltage between the gate and the emitter for turning off the switching element 31b.

The ON command is input to one input of the AND circuit 352a and input via the inverter 351 to one input of the AND circuit 352b.

The overvoltage protection ON command is input to the other inputs of AND circuits 352 a and 352 b via inverter 353 . Therefore, when the overvoltage protection ON command is high level, the ON command is disabled, and the AND circuit 352a outputs a low level signal and the AND circuit 352b outputs a high level signal regardless of the ON command.

The output of AND circuit 352a is connected to drive drive transistor 354a. The driving transistor 354a turns on when the output of the AND circuit 352a is at high level, and turns off when the output of the AND circuit 352a is at low level.

The output of AND circuit 352b is connected to drive drive transistor 354b. The driving transistor 354b turns on when the output of the AND circuit 352b is at high level, and turns off when the output of the AND circuit 352b is at low level.

The input of the drive transistor 356 during bypass is connected to the control circuit, and an overvoltage protection ON command is input. The bypass drive transistor 356 turns on when the overvoltage protection on command is at high level, and turns off when the overvoltage protection on command is at low level.

The output of drive transistor 354a is connected to the gate of switching element 31b through resistor 355a. The output of drive transistor 354b is connected to the gate of switching element 31b through resistor 355b.

The output of the bypass drive transistor 356 is connected via a resistor 357 to the gate of the switching element 31b.

The resistance values of resistors 355a and 355b are set so that switching element 31b can switch at a sufficiently high speed during normal operation.

The resistance value of resistor 357 is set to a value greater than the resistance value of resistor 355a. Since the resistance value of the resistor 357 is larger than the resistance value of the resistor 355a, the current charging the gate of the switching element 31b when the overvoltage protection ON command is high level is charged when the ON command is high level. Since it is smaller than the current, the ON time of the switching element 31b becomes longer than the normal ON time. Therefore, di/dt of the current flowing through the switching element 31b can be reduced when the switching element 31b is turned on.

When the switching element 31b is turned on by an overvoltage protection ON command while a forward current is flowing through the reverse conducting diode 32a, the current flowing through the reverse conducting diode 32a is commutated to the switching element 31b. Therefore, the absolute value of the current di/dt flowing through the reverse conducting diode 32a is substantially equal to the current di/dt flowing through the switching element 31b. Since the surge voltage generated across the reverse conducting diode 32a is proportional to di/dt, the smaller the di/dt, the more the magnitude of the surge voltage can be suppressed. Therefore, the reverse conducting diode 32a is prevented from being damaged by the surge voltage applied across it.

In the drive circuit 35 of FIG. 3, the resistance value of the resistor 357 is adjusted so that the ON time of the switching element 31b during bypass operation is sufficiently delayed, but the present invention is not limited to this example. Other circuit configurations may be used as long as di/dt of the current flowing through the switching element 31b during bypass operation can be reduced without affecting the switching operation during normal operation. For example, in place of the drive transistor 356 and the resistor 357 during bypass, a constant current circuit or the like capable of suppressing the charging current to the gate of the switching element 31b may be used, or another circuit configuration or the like may be used. Of course, the overvoltage protection ON command may be generated by the control device 50 instead of the control circuit in the unit converter.

The operation of the power converter 10 of the embodiment will be described in detail.
4(a) and 4(b) are schematic circuit diagrams for explaining the operation of the power converter of the embodiment.
FIG. 4(a) shows a state in which a current flows through the reverse conducting diode 32a. The current flowing through the reverse conducting diode 32a is indicated by the arrow. FIG. 4(b) shows a state in which the switching element 31b is turned on by the bypass operation while current is flowing through the reverse conducting diode 32a. The arrows indicate that current flowing into terminal 30a is commutated from reverse conducting diode 32a to switching element 31b.

4(a), 4(b), and FIG. 5 described later, the switching element 31a and the reverse conducting diode 32a on the high potential side are referred to as the switching element S1 and the reverse conducting diode D1. Also, the switching element 31b and the reverse conducting diode 32b on the low potential side are referred to as the switching element S2 and the reverse conducting diode D2.

Let iS2 be the current flowing through the switching element S2, and vS2 be the voltage applied between the collector and the emitter of the switching element S2. Let iD1 be the current flowing through the reverse-conducting diode D1, and vD1 be the voltage applied across the reverse-conducting diode D1.

As shown in FIG. 4(a), the current flowing from the terminal 30a charges the capacitor 33 through the reverse conducting diode D1. The voltage across the capacitor 33 is detected by a voltage detector or the like (not shown) and monitored by a control circuit. When the voltage across the capacitor 33 reaches the overvoltage protection detection level, the control circuit generates an overvoltage protection ON command and supplies it to the drive circuit 35 .

As shown in FIG. 4B, the switching element 31b is turned on by the overvoltage protection ON command. The current flowing through the reverse conducting diode D1 is commutated to the switching element 31b, and the reverse conducting diode D1 is turned off.

As described with reference to FIG. 4A, a forward current flows through the reverse conducting diode D1, so even if the reverse conducting diode D1 is turned off, the minority carriers accumulated between the pn junctions do not recombine. A reverse recovery phenomenon occurs until it disappears (in the figure, the reverse recovery phenomenon occurs in the reverse conducting diode D1 circled). During the period in which the reverse-conducting diode D1 is undergoing the reverse recovery phenomenon, current continues to flow in the reverse direction of the reverse-conducting diode D1. A surge voltage is generated across the reverse conducting diode D1 according to di/dt of the current during reverse recovery.

FIG. 5 is a schematic operation waveform diagram for explaining the operation of the power conversion device of the embodiment.
With reference to FIG. 5, the operation when the switching element S2 is turned on and the reverse conducting diode D1 is turned off by the overvoltage protection ON command will be described in more detail.
As shown in FIG. 5, in a period before time t1, a current flows through the reverse conducting diode D1. In the period up to time t1, capacitor 33 is charged by iD1 and the voltage across capacitor 33 continues to rise.

At time t1, the voltage across capacitor 33 reaches the overvoltage detection level, so that an overvoltage protection ON command (denoted as S2 gate signal in the figure) is generated. The overvoltage detection level is Vov, which is higher than the voltage across the capacitor 33 during normal operation.

Since the switching element S2 is turned on by the overvoltage protection ON command, the collector-emitter voltage vS2 of the switching element S2 starts to drop. By turning on the switching element S2, the current flowing through the reverse conducting diode D1 is commutated to the switching element S2, the current iS2 increases, and the current iD1 decreases.

From time t1 to time t4, the current flowing through the reverse conducting diode D1 is commutated to the switching element S2, so di/dt of iD1 is approximately equal to the absolute value of di/dt of iS2.

At time t2, the current iD1 flowing through the reverse conducting diode D1 is all commutated to the switching element S2.

From time t2 to time t4, a reverse recovery phenomenon occurs until the minority carriers accumulated in the pn junction of the reverse conducting diode D1 disappear due to recombination. Therefore, a reverse current flows from the cathode to the anode of the reverse conducting diode D1 (in the figure, iD1 has a negative value). At time t3, the current iD1 in the reverse direction becomes maximum, and this current value can be increased as the di/dt of the currents iS2 and iD1 increases.

At time t4, the minority carriers disappear and the reverse recovery phenomenon ends, but a surge voltage Vsurge is generated across the reverse conducting diode D1. The surge voltage Vsurge at this time can take a higher value as the di/dt at the time of reverse recovery of the reverse conducting diode D1 increases.

The voltage across the capacitor 33 is Vov, which is the overvoltage detection level. After time t4, the voltage applied across the reverse conducting diode D1 is Vov. That is, a maximum voltage of Vov+Vsurge can be applied across the reverse conducting diode D1.

The surge voltage Vsurge increases as di/dt from time t1 to time t3 increases. In the switching operation in the normal operation, the switching element 31b switches at high speed, and di/dt of the collector current increases. In the present embodiment, during bypass operation, the ON time of the switching element 31b is suppressed so as to be delayed, so di/dt of iS2 is suppressed more than during normal operation. Therefore, the magnitude of the surge voltage Vsurge during bypass operation is also suppressed. Even if Vov higher than normal is applied to both ends of the reverse conducting diode D1, the surge voltage Vsurge is suppressed, so that the diode D1 is less likely to be damaged.

Effects of the power converter 10 of the embodiment will be described.
In the power converter 10 of the present embodiment, the ON time of the switching element 31b during bypass operation is set to be longer than the ON time of the switching element 31b during normal operation. Therefore, it is possible to suppress the surge voltage generated across the reverse conducting diode 32a during the bypass operation, thereby preventing damage to the reverse conducting diode D1 due to the surge voltage. On the other hand, during normal operation, the ON time and OFF time of the switching element 31b are set sufficiently fast, so that the efficiency of the unit converter 30 can be sufficiently improved.

Since bypass operation is activated when the voltage across capacitor 33 becomes an overvoltage, the voltage level (Vov) when bypass operation starts is set higher than the voltage level for normal operation. Therefore, the maximum voltage that can be applied across the reverse conducting diode D1 in bypass operation is the sum of the voltage magnitude Vov at the overvoltage detection level and the surge voltage Vsurge. As for the voltage value of the overvoltage detection level, the voltage that the reverse conducting diode D1 can withstand must be Vov+Vsurge or more. can be set. In this embodiment, since the magnitude of the surge voltage can be suppressed, the voltage of the overvoltage detection level can be set higher. Therefore, the operating voltage range of the unit converter 30 can be widened with a sufficient margin.

Further, when Vov is set to a constant value based on the withstand voltage of the capacitor 33, etc., suppressing Vsurge makes it possible to lower the withstand voltage of the reverse conducting diode D1, resulting in further miniaturization. , cost reduction, etc. can be achieved.

In the above description, the unit converter 30 having the half-bridge type main circuit shown in FIG. 2(a) has been described as an example. matter can be applied as well. As described above, in the case of the full-bridge type, the switching elements 31b and 31d on the low potential side are turned on, and the switching elements 31a and 31c on the high potential side are turned on. When the switching elements 31b and 31d are turned on, by setting the on-time of the switching elements 31b and 31d to be slow, even if one of the reverse conducting diodes 32a and 32d causes a reverse recovery phenomenon, the reverse conducting diode 32a is turned on. , 32d can be suppressed. Even when the switching elements 31a and 31c are turned on by bypass operation, by setting the ON time of the switching elements 31a and 31c to be slow, even if the reverse recovery phenomenon occurs in one of the reverse conducting diodes 32b and 32d, It is possible to suppress the magnitude of the surge voltage applied across the reverse conducting diodes 32a and 32c.

In the above description, the power conversion device 10 including the MMC power conversion unit 20 including 6 arms for three-phase alternating current has been described. It can also be easily applied to devices (STATic synchronous COMpensator, STATCOM).

In this way, a power conversion device that can safely bypass is realized.

Although several embodiments of the invention have been described above, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are included within the scope of the invention described in the claims and equivalents thereof. Moreover, each of the above-described embodiments can be implemented in combination with each other.

1 AC circuit 3 DC circuit 10 Power converter 20 Power converter 22 Arm 30 Unit converter 31a, 31b, 31c, 31d Switching element 32a, 32b, 32c, 32d Reverse conducting diode 33 Capacitor, 35 drive circuit 50 control device 352a, 352b drive transistor 355a, 355b, 357 resistor 356 bypass operation drive transistor

Claims (6)

a power converter including a plurality of unit converters connected in series;
a control device that controls the power conversion unit;
with
The plurality of unit converters are
a first switching element;
a second switching element connected in series with the first switching element;
a first diode connected in anti-parallel to the first switching element;
a second diode connected in anti-parallel to the second switching element;
a capacitor connected in parallel to the series circuit of the first switching element and the second switching element;
each containing
each of the plurality of unit converters,
when the voltage value across the capacitor is lower than a predetermined overvoltage threshold, normal operation is performed to control the voltage across the capacitor by switching operations of the first switching element and the second switching element;
turning off the first switching element and turning on the second switching element for bypass operation when the voltage value across the capacitor exceeds the overvoltage threshold;
di/dt of the current flowing through the second switching element when the second switching element is turned on during the bypass operation is A power converter set smaller than the di/dt of the flowing current. 2. The power converter according to claim 1, wherein the ON time of said second switching element during said bypass operation is set to be later than the ON time of said second switching element during said normal operation. The second switching element is a voltage-driven switching element,
The plurality of unit converters are
each including a drive circuit for driving the second switching element,
The drive circuit controls a current value for driving the second switching element during the bypass operation by:
3. The power conversion device according to claim 2, wherein the current value is set smaller than the current value driving the second switching element during the normal operation. The drive circuit is
a first drive transistor arranged to turn on the second switching element in the normal operation;
a second drive transistor arranged to turn on the second switching element in the bypass operation;
a first resistor provided between the first drive transistor and the gate of the second switching element;
a second resistor provided between the second drive transistor and the gate of the second switching element;
including
4. The power converter according to claim 3, wherein the resistance value of said second resistor is set to a value greater than the resistance value of said first resistor. The plurality of unit converters are
5. The capacitor according to any one of claims 1 to 4, further comprising a control circuit for detecting a voltage across the capacitor to determine whether the voltage across the capacitor is equal to or higher than the overvoltage threshold value, and switching between the normal operation and the bypass operation. The power converter according to any one. detecting the voltage across the capacitor in each of the plurality of unit converters;
5. The control device includes a control circuit that determines whether or not the voltage across the both ends is equal to or greater than the overvoltage threshold value and switches between the normal operation and the bypass operation based on the determination result. The power converter according to any one of.

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