JP7284202B2 - Semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device .

2. Description of the Related Art Conventionally, a trench gate structure is known in semiconductor devices such as IGBTs (see, for example, Patent Document 1).
Patent Document 1 Japanese Patent Application Laid-Open No. 08-255902

It is preferable that the manufacturing efficiency of the semiconductor device does not deteriorate.

According to the first aspect of the present invention , a second conductivity type first semiconductor region formed on the front surface side of a first conductivity type semiconductor substrate; A second semiconductor region of the first conductivity type selectively formed in part of the semiconductor device may include forming a plurality of trenches. The trench may extend in a predetermined extending direction on the front surface side of the semiconductor substrate. The method of manufacturing a semiconductor device may include the step of forming a conductive portion. The conductive portion may be filled inside the plurality of trenches. The method of manufacturing a semiconductor device may include the step of forming an interlayer insulating film. The interlayer insulating film may cover the front surface of the semiconductor substrate in a predetermined pattern. The method of manufacturing a semiconductor device may include the step of forming a first electrode. The first electrode may be connected to the semiconductor substrate through an exposed region exposed from the interlayer insulating film in the mesa region sandwiched between the trenches. A first trench portion may be formed in a cross section perpendicular to the extending direction of the semiconductor device. The first trench part has a predetermined distance from the surface of the semiconductor substrate to the deepest part of the surface of the conductive part. A second trench portion may be formed in a cross section perpendicular to the extending direction of the semiconductor device. In the second trench portion, the distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion may be longer than a predetermined distance. Each of the first trench portion and the second trench portion may extend below the first semiconductor region and have a shoulder portion at the upper end that is inclined toward the center of the mesa region from the inclination of the side wall of the trench. . The second semiconductor region may be formed by implanting an impurity into a range including at least the shoulder. The first electrode may include an emitter electrode. The first electrode may include an emitter electrode and a plug portion arranged between the semiconductor substrate and the emitter electrode. The semiconductor device may comprise a second contact region of the second conductivity type. The second contact region may have a higher impurity concentration than the first semiconductor region. The second contact region may be arranged below the plug portion. The lower end of the plug portion may be provided at a position deeper than the lower end of the second semiconductor region. The semiconductor device may comprise an accumulation region of first conductivity type. The accumulation region may be arranged below the first semiconductor region. The accumulation region may be more heavily doped than the semiconductor substrate.

According to a second aspect of the present invention, a first semiconductor region of the second conductivity type formed on the front surface side of a semiconductor substrate of the first conductivity type; A method of manufacturing a semiconductor device comprising a second semiconductor region of a first conductivity type selectively formed in part and a first contact region of the second conductivity type having a higher impurity concentration than the first semiconductor region, comprising: Forming a plurality of trenches may be included. The trench may extend in a predetermined extending direction on the front surface side of the semiconductor substrate. The method of manufacturing a semiconductor device may include the step of forming a conductive portion. The conductive portion may be filled inside the plurality of trenches. The method of manufacturing a semiconductor device may include the step of forming an interlayer insulating film. The interlayer insulating film may cover the front surface of the semiconductor substrate in a predetermined pattern. The method of manufacturing a semiconductor device may include the step of forming a first electrode. The first electrode may be connected to the semiconductor substrate through an exposed region exposed from the interlayer insulating film in the mesa region sandwiched between the trenches. A first trench portion may be formed in a cross section perpendicular to the extending direction of the semiconductor device. The first trench part has a predetermined distance from the surface of the semiconductor substrate to the deepest part of the surface of the conductive part. A second trench portion may be formed in a cross section perpendicular to the extending direction of the semiconductor device. In the second trench portion, the distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion may be longer than a predetermined distance. Each of the first trench portion and the second trench portion may extend below the first semiconductor region and have a shoulder portion at the upper end that is inclined toward the center of the mesa region from the inclination of the side wall of the trench. . The first contact region may be formed by implanting an impurity into a range including at least the shoulder portion from the front surface side of the semiconductor substrate.

The first semiconductor region may be a base region. The second semiconductor region may be the emitter region.

The emitter region may be relatively long on the side adjacent to the trench. The emitter region is arranged in the mesa region sandwiched between the first trench portion and the second trench portion in a cross section perpendicular to the extending direction, and the emitter region is arranged on the first trench portion side and the second trench portion side. They do not have to be arranged symmetrically. The emitter region may have different depths on the first trench side and the second trench side.

In the first trench part or the second trench part, the deepest part of the surface of the conductive part may be arranged at the center of the trench in a cross section perpendicular to the extending direction. In the first trench portion or the second trench portion, the sidewall side of the surface of the conductive portion may be relatively close to the front surface of the semiconductor substrate in a cross section perpendicular to the extending direction. The cross section perpendicular to the extending direction may be a cross section passing through the second semiconductor region.

The conductive portion may be polysilicon. The semiconductor device may include an insulating film. The insulating film may cover the inner walls of the trench. The insulating film may ensure insulation between the semiconductor substrate and the conductive portion. A portion of the conductive portion may be connected to the gate electrode and at least a portion of the other portion may be connected to the emitter electrode. The shoulder may have a larger average inclination with respect to the depth direction of the semiconductor substrate than the sidewall. The shoulder may include a straight shape at least in part.

The shoulder may have a length D1 in the depth direction of the semiconductor substrate greater than a width W1 in the direction perpendicular to the extending direction. The width W1 of the shoulder portion may be 1/2 or less and 1/20 or more of the width of the trench at the position facing the upper end of the conductive portion. The width W1 of the shoulder may be 1/4 or less of the width of the trench at the position facing the upper end of the conductive portion. The width W1 of the shoulder portion may be 1/10 or more of the width of the trench at the position facing the upper end of the conductive portion.

At least part of the shoulder may have an angle of 20 degrees or more with respect to the depth direction of the semiconductor substrate.

The first trench portion and the second trench portion may be arranged such that the upper end of each conductive portion is deeper than the surface of the semiconductor substrate.

It should be noted that the above summary of the invention does not list all the features of the invention. Subcombinations of these feature groups can also be inventions.

1 is a diagram showing part of the surface of a semiconductor device 100 according to a first embodiment; FIG. FIG. 2 is a diagram showing a cross section taken along line AA' in FIG. 1; FIG. 3 is a diagram illustrating a part of a manufacturing process of a gate trench portion 40 and an emitter region 12 in the semiconductor device 100; 4A and 4B are diagrams illustrating the shape of a gate trench portion 40; FIG. 4A and 4B are diagrams illustrating shapes of an emitter region 12 and a gate conductive portion 44; FIG. FIG. 8 is a diagram showing a modification of the shape of the shoulder portion 33; FIG. 8 is a diagram showing a modification of the shape of the shoulder portion 33; FIG. 2 is a view showing a BB′ cross section in FIG. 1; 4 is a perspective view of a gate trench 41, a gate conductive portion 44, an emitter region 12 and a contact region 15; FIG. FIG. 9 is a view showing a CC' cross section in FIG. 8; FIG. 9 is a diagram showing a DD′ cross section in FIG. 8; 4A and 4B are diagrams showing an example of a manufacturing process of the gate conductive portion 44; FIG. It is a figure which shows the cross section of the semiconductor device 100 which concerns on 2nd Embodiment. FIG. 10 is a diagram showing an example of a process of forming a shoulder portion 33; It is a figure which shows a part of surface of the semiconductor device 100 which concerns on 3rd Embodiment. FIG. 14 is a view showing a CC′ cross section in FIG. 13;

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution of the invention.

FIG. 1 is a diagram showing part of the surface of a semiconductor device 100 according to the first embodiment. A semiconductor device 100 of this example includes a plurality of gate trench portions 40 extending in a predetermined extending direction on the surface of a semiconductor substrate. The plurality of gate trench portions 40 are arranged at predetermined intervals along the arrangement direction orthogonal to the extending direction. The gate trench portion 40 functions as a gate of a power semiconductor element such as an IGBT.

A P− type base region 14 is formed in a region sandwiched between the gate trench portions 40 on the surface of the semiconductor substrate. A P+ type contact region 15 is formed on the surface of the base region 14 . Also, an N + -type emitter region 12 is selectively formed on part of the surface of the contact region 15 . Emitter region 12 is an example of a first region. Contact region 15 is an example of a second region. Base region 14 is an example of a third region. Also, each region may have a conductivity type opposite to that described herein.

In this example, each of the contact region 15 and the emitter region 12 is formed from one adjacent gate trench portion 40 to the other gate trench portion 40 . The contact regions 15 and the emitter regions 12 are formed so as to be alternately exposed along the extending direction of the gate trench portions 40 in the regions sandwiched between the gate trench portions 40 .

Alternatively, the emitter regions 12 may be formed on both sides of each gate trench portion 40 along the extension direction, and the contact regions 15 may be formed in regions sandwiched between the emitter regions 12 . Although an interlayer insulating film, an emitter electrode, and the like are formed on the surface of the semiconductor device 100, they are omitted in FIG.

FIG. 2 is a diagram showing a cross section taken along line AA' in FIG. The AA′ cross section is a cross section perpendicular to the surface of the semiconductor device 100 and perpendicular to the extending direction of the gate trench portion 40 . The semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52 and a collector electrode 24 in the cross section.

The interlayer insulating film 26 is formed in a predetermined pattern on the surface of the semiconductor substrate 10 . The interlayer insulating film 26 covers the opening of the gate trench portion 40 and exposes at least a portion of the mesa region sandwiched between the gate trench portions 40 . The interlayer insulating film 26 is, for example, a PSG film or a BPSG film. Emitter electrode 52 is formed above interlayer insulating film 26 . Emitter electrode 52 is connected to the surface of semiconductor substrate 10 not covered with interlayer insulating film 26 .

A collector electrode 24 is formed on the back surface of the semiconductor substrate 10 . Emitter electrode 52 and collector electrode 24 are made of a conductive material such as metal. In this specification, the emitter electrode 52 side surface of each member such as a substrate, layer, and region is referred to as a top surface or top surface, and the collector electrode 24 side surface is referred to as a back surface or bottom. A direction connecting the emitter electrode 52 and the collector electrode 24 is called a depth direction. The direction from the collector electrode 24 to the emitter electrode 52 is defined as the top, and the direction from the emitter electrode 52 to the collector electrode 24 is defined as the bottom.

The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate, or the like. A P− type base region 14 is formed on the surface side of the semiconductor substrate 10 . An N + -type emitter region 12 is selectively formed in a part of the surface side of the base region 14 .

The semiconductor substrate 10 also has an N− type drift region 18 , an N− type buffer region 20 and a P+ type collector region 22 . Drift region 18 is formed on the back side of base region 14 .

Buffer region 20 is formed on the rear surface side of drift region 18 . The impurity concentration of the buffer region 20 is higher than that of the drift region 18 . Buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the back side of base region 14 from reaching collector region 22 . Collector region 22 is formed on the back side of buffer region 20 . A collector electrode 24 is provided on the back surface of the collector region 22 .

One or more gate trench portions 40 are formed on the surface side of the semiconductor substrate 10 . Each gate trench portion 40 extends from the surface of the semiconductor substrate 10 through the base region 14 to reach the drift region 18 . The gate trench portion 40 in this cross section extends from the surface of the semiconductor substrate 10 through the emitter region 12 and the base region 14 to reach the drift region 18 .

The gate trench portion 40 has a gate trench 41 , an insulating film 42 and a gate conductive portion 44 formed on the surface side of the semiconductor substrate 10 . Insulating film 42 is formed to cover the inner wall of gate trench 41 . The insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench 41 . The gate conductive portion 44 is formed inside the insulating film 42 inside the gate trench 41 . That is, the insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10 from each other. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

An upper end 45 of the gate conductive portion 44 is provided at a position deeper than the surface of the semiconductor substrate 10 . That is, the upper end 45 of the gate conductive portion 44 is depressed inside the gate trench 41 . The upper end 45 of the gate conductive portion 44 refers to the uppermost end of the gate conductive portion 44 .

An interlayer insulating film 26 is formed in a region inside gate trench 41 where gate conductive portion 44 and insulating film 42 are not provided. Thereby, the gate conductive portion 44 is insulated from the emitter electrode 52 . However, the gate trench portion 40 is provided extending to the lower side of the metal gate electrode in the semiconductor device 100 . A contact hole for electrically connecting the gate conductive portion 44 and the gate electrode is formed in the interlayer insulating film 26 under the gate electrode.

Gate conductive portion 44 includes at least a region facing adjacent base region 14 . When a predetermined voltage is applied to the gate conductive portion 44 , a channel is formed in the surface layer of the interface contacting the gate trench 41 in the base region 14 .

Note that the semiconductor device 100 may be provided with dummy trench portions instead of some of the gate trench portions 40 . The dummy trench portion has a structure similar to that of the gate trench portion 40 . However, the conductive portion inside the dummy trench portion is electrically connected to the emitter electrode 52 . In this case, a contact hole is provided in the interlayer insulating film 26 between the dummy trench portion and the emitter electrode 52 . By providing the dummy trench portion, the on-voltage can be reduced by enhancing the effect of promoting carrier injection into the drift region (IE effect).

In the cross section of the semiconductor substrate 10 in the depth direction, the average slope of the sidewall of the gate trench 41 between the upper end 45 of the gate conductive portion 44 and the surface of the semiconductor substrate 10 is greater than the slope of the side wall at the position where In addition, unless otherwise specified, the “tilt” in this specification refers to the tilt of the cross section with respect to the depth direction of the semiconductor substrate 10 . For example, the "inclination" of the surface of the semiconductor substrate 10 is approximately 90 degrees, and the "inclination" of a straight line parallel to the depth direction is 0 degrees. Note that the average inclination of the side walls of the gate trench 41 within a predetermined range is obtained by integrating the inclination of the side walls of the gate trench 41 in the cross section over a predetermined length of the side walls of the gate trench 41, and It may be calculated by dividing by the length.

The gate trench 41 of this example has a shoulder portion 33 in a region in contact with the surface of the semiconductor substrate 10 . The shoulder portion 33 is formed in the sidewall of the gate trench 41 between the gate conductive portion 44 and the surface of the semiconductor substrate 10 (that is, above the upper end 45 of the gate conductive portion 44). In the cross section, the average slope of the sidewalls of the gate trench 41 at the shoulder portion 33 is smaller than the slope of the sidewalls at the position facing the upper end 45 of the gate conductive portion 44 . The slope of the side wall of the gate trench 41 between the shoulder portion 33 and the upper end 45 of the gate conductive portion 44 is substantially equal to the slope of the side wall of the gate trench 41 at the position facing the upper end 45 of the gate conductive portion 44 . good.

By increasing the inclination of the sidewall of the gate trench 41 above the upper end 45 of the gate conductive portion 44 in this way, the depth of the emitter region 12 in the region contacting the gate trench 41 can be easily controlled. By controlling the depth of emitter region 12, the length of remaining base region 14 can be controlled. The length of base region 14 in contact with gate trench 41 corresponds to the channel length. Therefore, it becomes easier to control the threshold voltage of the semiconductor device 100 .

3A and 3B are diagrams for explaining part of the manufacturing process of the gate trench portion 40 and the emitter region 12 of the semiconductor device 100. FIG. First, in the gate trench forming step S300, the gate trench 41 is formed in the surface of the semiconductor substrate 10. As shown in FIG. Gate trench 41 has a shoulder portion 33 in a region in contact with the surface of semiconductor substrate 10 . For example, after etching the surface of the semiconductor substrate 10 using a first mask having a predetermined opening to form trenches, the surface of the semiconductor substrate 10 is wet-etched using a second mask having a larger opening than the first mask. This may form a gate trench 41 having a shoulder 33 . The second mask may be formed by wet etching the first mask to widen the opening area.

Next, in the gate conductive portion forming step S302, the insulating film 42 and the gate conductive portion 44 are formed on the inner wall of the gate trench 41. As shown in FIG. The insulating film 42 may be formed by oxidizing the semiconductor substrate 10 . The gate conductive portion 44 is formed such that the upper end 45 of the gate conductive portion 44 is positioned deeper than the surface 11 of the semiconductor substrate 10 . In this example, the upper end 45 of the gate conductive portion 44 is provided below the shoulder portion 33 . The gate conductive portion 44 is formed of polysilicon doped with impurities, for example.

After forming the gate conductive portion 44 , a P-type impurity is implanted and diffused into the surface of the semiconductor substrate 10 to form the base region 14 . A P-type impurity is, for example, boron. The diffusion temperature of the base region 14 is, for example, approximately 1100 degrees. The gate trench portion 40 may be formed after the base region 14 is formed.

Next, in the emitter region forming step S304, N-type impurities are implanted into the semiconductor substrate 10 and diffused. An N-type impurity is, for example, arsenic. Also, a P-type impurity such as boron is implanted into the contact region 15 and diffused. Impurities in emitter region 12 and contact region 15 may be diffused in the same step. The temperature of the diffusion step may be lower than the diffusion temperature of base region 14 . The temperature of the diffusion process is, for example, 1000 degrees or less.

An emitter region 12 is thus formed. In S304, impurities are injected not only into the surface of the semiconductor substrate 10 but also into the side walls of the gate trench 41 using the gate conductive portion 44 as a mask. By such a method, the emitter region 12 is formed such that the portion in contact with the gate trench 41 is the deepest.

In S<b>304 , the N-type impurity is diffused in the region contacting the gate trench 41 to a depth corresponding to the threshold voltage that the semiconductor device 100 should have. When diffusing impurities to a deeper position, heat treatment at a higher temperature or for a longer time is required. However, since heat treatment over a long period of time deteriorates production efficiency, heat treatment at a high temperature is preferable. However, when the heat treatment is performed at a high temperature, the diffusion length of impurities increases per unit time, making it difficult to control the diffusion depth of the impurities.

On the other hand, in the semiconductor device 100 and the manufacturing method of this example, since the gate trench 41 has the shoulder portion 33, the length for diffusing the impurity in the region in contact with the gate trench 41 can be reduced. In other words, the impurity is implanted below the surface 11 of the semiconductor substrate 10 in the region where the shoulder portion 33 is provided. Therefore, when forming the emitter region 12 with a predetermined depth, the length required to diffuse the impurity can be reduced.

Therefore, even if the impurity is diffused at a lower temperature, the heat treatment time is not lengthened and the manufacturing efficiency is not deteriorated. Moreover, since the impurity can be diffused at a low temperature, the depth of the emitter region 12 in the region contacting the gate trench 41 can be accurately controlled.

Further, since the gate trench 41 has the shoulder portion 33, the area of the mesa region sandwiched between the gate trench portions 40 can be reduced. Therefore, an electron injection promoting effect (IE effect) can be obtained.

In S304, the impurity may be implanted into the side wall of gate trench 41 from a direction having a predetermined inclination θ1 with respect to the depth direction of semiconductor substrate 10. Next, as shown in FIG. As a result, impurities can be efficiently implanted. The inclination θ1 is, for example, 10 degrees or less.

Moreover, since the emitter region 12 is formed by self-alignment using the gate conductive portion 44 as a mask, the emitter region 12 can be easily brought into contact with the gate trench portion 40 . On the other hand, when the emitter region 12 is formed using a mask independent of the gate trench portion 40, the emitter region 12 and the gate trench portion 40 do not come into contact with each other due to manufacturing variations in mask alignment and the like. 100 may not operate.

FIG. 4 is a diagram for explaining the shape of the gate trench portion 40. As shown in FIG. In this example, the inclination of the side wall of the gate trench 41 at the position 31 facing the upper end 45 of the gate conductive portion 44 is θ2. The width of the shoulder portion 33 in the radial direction of the opening of the gate trench 41 is W1, and the length in the depth direction is D1. The starting point of the shoulder portion 33 may be the edge of the side wall of the gate trench 41 on the surface 11 of the semiconductor substrate 10 . The end point of the shoulder portion 33 is a position where, when the sidewall of the gate trench 41 is traced from the position 31 toward the surface 11 of the semiconductor substrate 10, the inclination of the sidewall of the gate trench 41 is larger than θ2 by a predetermined value or more. It can be. As an example, the predetermined value is 10 degrees. The predetermined value may be 0 degrees, 20 degrees, or 30 degrees.

The shoulder portion 33 may have a curved portion that protrudes toward the inside of the semiconductor substrate 10 . That is, the inclination of the shoulder portion 33 increases as the distance from the surface of the semiconductor substrate 10 increases. With such a shape of the shoulder portion 33, the impurity can be implanted in a deep position more efficiently. Therefore, the impurity diffusion length for forming the emitter region 12 with a predetermined depth can be shortened.

Also, the length D1 of the shoulder portion 33 may be greater than the width W1. As a result, the opening area of the gate trench 41 can be reduced to allow miniaturization, and the impurity can be implanted at a deep position in the region adjacent to the gate trench 41 . Also, the length D1 may be equal to the width W1, and the length D1 may be less than the width W1.

The width W1 of shoulder 33 may be less than or equal to half the width of gate trench 41 at location 31, and may be less than or equal to 1/4. This can suppress an increase in the area of the gate trench 41 on the surface 11 of the semiconductor substrate 10 . Also, the width W1 may be 1/20 or more of the width of the gate trench 41 at the position 31, or may be 1/10 or more. As a result, the impurity can be efficiently implanted into a deep position.

Also, the length D1 of the shoulder portion 33 may be half or less of the distance R1 between the upper end 45 of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10 . Also, the length D1 may be greater than half the distance R1. Also, the length D1 may be substantially equal to the distance R1. As an example, when the length D1 is 90% or more and 110% or less of the distance R1, the length D1 and the distance R1 are considered to be substantially equal.

Moreover, the sidewall of the gate trench 41 has a portion with an inclination of 20 degrees or more between the upper end 45 of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10 . For example, the inclination θ3 of at least a portion of the shoulder portion 33 is 20 degrees or more. In this way, since the slope of the side wall of the gate trench 41 becomes large above the upper end 45 , the impurity can be efficiently implanted into a deep position, and the diffusion of the impurity into the region adjacent to the gate trench 41 can be easily controlled. Become.

FIG. 5 is a diagram illustrating shapes of the emitter region 12 and the gate conductive portion 44. As shown in FIG. As described above, impurities are also implanted from the inner walls of the gate trenches 41, so that the lower ends 34 of the portions adjacent to the gate trenches 41 of the emitter region 12 are provided at deeper positions than the other portions. With such a shape, the length of the base region 14 in the region adjacent to the gate trench 41 can be controlled, and the threshold voltage of the semiconductor device 100 can be controlled.

Further, in emitter region 12 , length D<b>2 in the depth direction of the portion in contact with gate trench 41 may be longer than the length of other portions of emitter region 12 . For example, the length D3 of the emitter region 12 in the mesa region where the gate trench 41 is not provided is smaller than the length D2.

Further, the end surface of the gate conductive portion 44 on the surface 11 side of the semiconductor substrate 10 is formed so that the portion adjacent to the side wall of the gate trench 41 (upper end 45 in this example) is closest to the surface 11 of the semiconductor substrate 10 . In this example, the deepest portion 46 located in the center of the gate trench 41 of the end face of the gate conductive portion 44 on the surface 11 side of the semiconductor substrate 10 is formed at the farthest position from the surface 11 of the semiconductor substrate 10 .

As an example, the end surface of the gate conductive portion 44 gradually increases in distance from the surface of the semiconductor substrate 10 from the sidewall of the gate trench 41 toward the center of the gate trench 41 . That is, as the depth from the surface 11 of the semiconductor substrate 10 increases, the thickness of the gate conductive portion 44 adjacent to the sidewall of the gate trench 41 gradually increases. As described above, when an impurity is obliquely implanted using the gate conductive portion 44 as a mask, the impurity penetrates the gate conductive portion 44 and is implanted into the semiconductor substrate 10 where the thickness of the gate conductive portion 44 is small. As a result, in the region adjacent to the gate trench 41 , the impurity can be easily implanted and diffused to a deep position as viewed from the surface 11 of the semiconductor substrate 10 .

FIG. 6A is a diagram showing a modification of the shape of the shoulder portion 33. FIG. The shoulder portion 33 of this example has a curved surface portion that protrudes toward the surface side of the semiconductor substrate 10 . That is, the inclination of the shoulder portion 33 in this example decreases as the distance from the surface of the semiconductor substrate 10 increases. Even with such a shape, the impurity can be easily diffused to a deep position when viewed from the surface 11 of the semiconductor substrate 10 .

6B is a diagram showing a modification of the shape of the shoulder portion 33. FIG. The shoulder portion 33 of this example has a linear shape at least in part. The linear shape has an inclination larger than the inclination .theta.2 of the side wall of the gate trench 41 at the position facing the upper end 45 of the gate conductive portion 44 by a predetermined value or more. The predetermined value may be 10 degrees, 20 degrees, or 30 degrees. Even with such a shape, the impurity can be easily diffused to a deep position when viewed from the surface 11 of the semiconductor substrate 10 .

FIG. 7 is a diagram showing a BB' section in FIG. In this cross section, the semiconductor device 100 has a contact region 15 instead of the emitter region 12 in the cross section shown in FIG. Other structures are the same as the cross section shown in FIG.

That is, gate trench 41 has shoulders 33 both in the region adjacent to emitter region 12 and in the region adjacent to contact region 15 . The shoulder 33 in the region adjacent to the emitter region 12 and the shoulder 33 in the region adjacent to the contact region 15 may have the same shape.

With such a structure, the depth of the contact region 15 can be controlled similarly to the emitter region 12 . That is, even in the contact region 15, the portion in contact with the gate trench 41 is formed to the deepest position.

FIG. 8 is a perspective view of gate trench 41 , gate conductive portion 44 , emitter region 12 and contact region 15 . Shoulder portion 33 is formed extending along the extending direction of gate trench 41 .

FIG. 9A is a diagram showing a CC' cross section in FIG. The cross section is a cross section along the extending direction of the gate trench 41 in a region (that is, a mesa region) where the gate trench 41 is not provided. As described above, the emitter regions 12 and the contact regions 15 are alternately exposed on the surface 11 of the semiconductor substrate 10 along the extending direction of the gate trenches 41 . Contact region 15 is formed to a position deeper than emitter region 12 .

9B is a diagram showing a DD' section in FIG. 8. FIG. The cross section is a cross section along the extending direction of the gate trench 41 in the region where the shoulder portion 33 is provided. The emitter region 12 in the shoulder portion 33 is formed to a deeper position than the emitter region 12 in the mesa region shown in FIG. 9A. Further, the contact region 15 in the shoulder portion 33 is formed to a deeper position than the contact region 15 in the mesa region.

Also, the length D6 of the emitter region 12 in the depth direction at the shoulder portion 33 is greater than the length D3 of the emitter region 12 at the mesa region. The length D8 of the contact region 15 in the depth direction at the shoulder portion 33 is greater than the length D5 of the contact region 15 at the mesa region. Moreover, the length difference D7 between the emitter region 12 and the contact region 15 at the shoulder portion 33 is equal to or greater than the length difference D4 between the emitter region 12 and the contact region 15 at the mesa region.

10A and 10B are diagrams showing an example of a manufacturing process of the gate conductive portion 44. FIG. First, a gate trench 41 having a shoulder 33 is formed in surface 11 of semiconductor substrate 10 . Next, an insulating film 42 is formed on the surface of the gate trench 41 and the semiconductor substrate 10 . A conductive material 47 is then deposited on the gate trench 41 and the surface of the semiconductor substrate 10 . As the conductive material 47 is deposited, the thickness of the conductive material 47 deposited on the sidewalls inside the gate trench 41 increases. Also, the thickness of the conductive material 47 increases while maintaining the shape along the shoulder portion 33 .

When the conductive material 47 is filled up to the center of the gate trench 41, the conductive material 47 above the opening of the gate trench 41 has a downward convex shape as shown in the lower side of FIG. Then, by etching the conductive material 47 to a predetermined depth inside the gate trench 41, the gate conductive portion 44 as shown in FIG. 5 is formed. Since the gate trench 41 has a shoulder portion in this manner, the gate conductive portion 44 having a downwardly convex upper surface can be easily formed. Therefore, impurities can be easily implanted into the side surfaces of the gate trenches 41 .

FIG. 11 is a diagram showing a cross section of a semiconductor device 100 according to the second embodiment. The semiconductor device 100 of this example has a plurality of gate trench portions 40 with different distances from the surface 11 of the semiconductor substrate 10 to the upper ends of the gate conductive portions 44 . That is, the gate conductive portion 44 has a plurality of gate trench portions 40 with different depths at the upper end. Each gate trench portion 40 penetrates through the base region 14 having a uniform depth at the lower end. Also, the cross section where each gate trench portion 40 appears may not be a single plane.

If the depth of the upper end of the gate conductive portion 44 is different, the depth of the emitter region 12 in the region adjacent to the gate trench 41 is also different. Specifically, when the upper end of the gate conductive portion 44 is shallow, the emitter region 12 is also shallow, and when the upper end of the gate conductive portion 44 is deep, the emitter region 12 is also deep.

In this example, the distance between the upper end of the gate conductive portion 44 in the first gate trench portion 40-1 and the surface 11 of the semiconductor substrate 10 is L1. Also, the distance between the upper end of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10 in the second gate trench portion 40-2 is L2. Distance L1 is less than distance L2.

As described above, the greater the distance between the upper end of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10, the deeper the emitter region 12 adjacent to the gate trench 41 and the shorter the channel length. Therefore, the channel length C1 of the first gate trench portion 40-1 is longer than the channel length C2 of the second gate trench portion 40-2. Therefore, the threshold voltage of the first gate trench portion 40-1 becomes higher than the threshold voltage of the second gate trench portion 40-2.

By controlling the depth of the upper end of the gate conductive portion 44 in this manner, the threshold voltage of each gate trench portion 40 can be controlled. Therefore, an appropriate threshold voltage can be set according to the use or function of each gate trench portion 40 .

The gate trenches 41 in the first gate trench portion 40-1 and the second gate trench portion 40-2 may have different depths from the surface 11 of the semiconductor substrate 10. FIG. Specifically, the gate trench 41 of the gate trench portion 40 whose threshold voltage is desired to be increased is formed deeper. Gate conductive portions 44 having the same length are formed in the respective gate trenches 41 . Accordingly, the depth of the upper end of each gate conductive portion 44 differs according to the depth of the gate trench 41 . According to this example, it is possible to adjust the threshold voltage of each gate trench portion 40 while simultaneously forming each gate conductive portion 44 to improve the efficiency of the manufacturing process.

Also, a plurality of gate trenches 41 having different depths may be formed by etching the surface 11 of the semiconductor substrate 10 using a mask having a plurality of openings with different areas. If the opening area of the mask is large, a deep gate trench 41 can be formed. As a result, the gate trenches 41 having different depths can be formed simultaneously to improve the efficiency of the manufacturing process, and the threshold voltages of the respective gate trench portions 40 can be adjusted.

12A and 12B are diagrams showing an example of a process for forming the shoulder portion 33. FIG. As described above, the gate trenches 41 are formed by anisotropically etching the surface 11 of the semiconductor substrate 10 using the first mask 48 . Next, the first mask 48 is wet-etched to form a second mask 49 with an enlarged mask opening area. The opening in the second mask 49 exposes the area of the surface 11 where the shoulder 33 is to be formed. Then, the surface 11 of the semiconductor substrate 10 is wet-etched using the second mask 49 . As a result, the shoulder portion 33 that is gentler than the side wall of the gate trench 41 can be formed.

FIG. 13 is a diagram showing part of the surface of the semiconductor device 100 according to the third embodiment. A semiconductor device 100 of this example includes a plurality of gate trench portions 40 extending in a predetermined extending direction on the surface of a semiconductor substrate. The gate trench portion 40 is the same as the gate trench portion 40 in any of the embodiments described with reference to FIGS. 1-12.

An N + -type emitter region 12 is formed in a region sandwiched between the gate trench portions 40 on the surface of the semiconductor substrate. The emitter region 12 is formed in stripes in a region adjacent to the gate trench portion 40 . In this example, the base region 14 is not exposed in the region between the gate trench portions 40 on the surface of the semiconductor substrate.

Further, the contact region 15 of this example is formed inside the semiconductor substrate and is not exposed on the surface of the semiconductor substrate. The contact regions 15 are formed in stripes parallel to the gate trench portion 40 inside the semiconductor substrate. A contact opening is formed in the emitter region 12 to expose the contact region 15 . A plug connecting the contact region 15 and the emitter electrode 52 is formed inside the contact opening.

FIG. 14 is a diagram showing a CC' cross section in FIG. A CC′ cross section is a cross section perpendicular to the surface of the semiconductor device 100 and perpendicular to the extending direction of the gate trench portion 40 . In this example, the emitter region 12 is formed near the upper surface of the semiconductor substrate 10 and the base region 14 is formed below the emitter region 12 in the region sandwiched between the two gate trench portions 40 . Moreover, the semiconductor device 100 of this example further includes a plug portion 28 . A contact region 15 is formed adjacent to the bottom of the plug portion 28 . Other structures may be identical to the structure shown in FIG.

The plug portion 28 is formed through the interlayer insulating film 26 and the emitter region 12 between the two gate trench portions 40 . The plug portion 28 may be arranged in the center of the region sandwiched between the two gate trench portions 40 . The plug portion 28 has an upper end connected to the emitter electrode 52 and a lower end located inside the base region 14 . The plug portion 28 may be made of a material containing tungsten, for example.

A contact region 15 is formed inside the base region 14 . The contact region 15 in this example is entirely surrounded by the base region 14 . Contact region 15 is formed in contact with the lower end of plug portion 28 . Such a structure can reduce the contact resistance between the emitter electrode 52 and the semiconductor region. In particular, when the semiconductor device 100 is miniaturized, the width of the mesa sandwiched between the gate trench portions 40 is reduced, and the contact area between the emitter electrode 52 and the semiconductor region is reduced. On the other hand, according to this example, by providing the plug portion 28, the contact resistance can be kept low even if the semiconductor device 100 is miniaturized.

In addition, the semiconductor device 100 may further include an N+ type accumulation region 16 . The accumulation region 16 has a higher impurity concentration than the drift region 18 . An accumulation region 16 is formed between the base region 14 and the drift region 18 between the two gate trench portions 40 . With such a configuration, the carrier accumulation effect can be enhanced, and the trade-off between on-voltage and turn-off loss can be improved. The accumulation region 16 may be applied to the semiconductor device 100 according to the first and second embodiments described with reference to FIGS. 1-12.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the scope of claims that forms with such modifications or improvements can also be included in the technical scope of the present invention.

"Upper" and "lower" in the claims or the specification refer to opposite directions. However, the term "up" is not limited to the direction opposite to the direction of gravity. Also, the term "lower" is not limited to the direction of gravity.

DESCRIPTION OF SYMBOLS 10... Semiconductor substrate 11... Surface 12... Emitter region 14... Base region 15... Contact region 16... Accumulation region 18... Drift region 20. Buffer region 22 Collector region 24 Collector electrode 26 Interlayer insulating film 28 Plug portion 33 Shoulder portion 34 Lower end 40 Gate trench portion 41 Gate trench 42 Insulating film 44 Gate conductive portion 45 Upper end 46 Deepest portion 47 Conductive material 48. 1st mask 49 2nd mask 52 emitter electrode 100 semiconductor device

Claims (31)

a first semiconductor region of a second conductivity type formed on the front surface side of a semiconductor substrate of the first conductivity type; In a method for manufacturing a semiconductor device comprising: a second semiconductor region of a first conductivity type;
forming a plurality of trenches extending in a predetermined extending direction on the front surface side of the semiconductor substrate;
forming a conductive portion to be filled inside the plurality of trenches;
forming an interlayer insulating film covering the front surface of the semiconductor substrate in a predetermined pattern;
forming a first electrode connected to the semiconductor substrate through an exposed region exposed from the interlayer insulating film in the mesa region sandwiched between the trenches;
In a cross section of the semiconductor device perpendicular to the extending direction, a first trench portion having a predetermined distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion, and a portion of the conductive portion from the surface of the semiconductor substrate. a second trench portion having a length longer than the predetermined distance up to the deepest part of the surface;
Each of the first trench portion and the second trench portion extends below the first semiconductor region and has a shoulder portion that is inclined toward the center of the mesa region from the inclination of the side wall of the trench. has at the top,
The method of manufacturing a semiconductor device, wherein the second semiconductor region is formed by implanting an impurity into a range including at least the shoulder portion. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said first electrode includes an emitter electrode. a first semiconductor region of a second conductivity type formed on the front surface side of a semiconductor substrate of the first conductivity type; In a method for manufacturing a semiconductor device comprising a first conductivity type second semiconductor region and a second conductivity type first contact region having a higher impurity concentration than the first semiconductor region,
forming a plurality of trenches extending in a predetermined extending direction on the front surface side of the semiconductor substrate;
forming a conductive portion to be filled inside the plurality of trenches;
forming an interlayer insulating film covering the front surface of the semiconductor substrate in a predetermined pattern;
forming a first electrode connected to the semiconductor substrate through an exposed region exposed from the interlayer insulating film in the mesa region sandwiched between the trenches;
In a cross section of the semiconductor device perpendicular to the extending direction, a first trench portion having a predetermined distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion, and a portion of the conductive portion from the surface of the semiconductor substrate. a second trench portion having a length longer than the predetermined distance up to the deepest part of the surface;
Each of the first trench portion and the second trench portion extends below the first semiconductor region and has a shoulder portion that is inclined toward the center of the mesa region from the inclination of the side wall of the trench. has at the top,
The method of manufacturing a semiconductor device, wherein the first contact region is formed by implanting an impurity into a range including at least the shoulder portion from the front surface side of the semiconductor substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said first electrode includes an emitter electrode and a plug portion arranged between said semiconductor substrate and said emitter electrode. 5. The method of manufacturing a semiconductor device according to claim 4, wherein said semiconductor device further comprises a second contact region of a second conductivity type arranged below said plug portion and having an impurity concentration higher than that of said first semiconductor region. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the lower end of said plug portion is provided at a position deeper than the lower end of said second semiconductor region. 7. The semiconductor device according to any one of claims 4 to 6, further comprising a first conductivity type accumulation region arranged below the first semiconductor region and having an impurity concentration higher than that of the semiconductor substrate. manufacturing method. 8. The method of manufacturing a semiconductor device according to claim 1, wherein said first semiconductor region is a base region. 9. The method of manufacturing a semiconductor device according to claim 1, wherein said second semiconductor region is an emitter region. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the emitter region has a relatively long side adjacent to the trench. The emitter region is arranged in a mesa region sandwiched between the first trench portion and the second trench portion in a cross section perpendicular to the extending direction. 11. The method of manufacturing a semiconductor device according to claim 9, wherein the two trench portions are not arranged symmetrically. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the emitter region has different depths on the side of the first trench portion and on the side of the second trench portion. 13. The first trench portion or the second trench portion according to any one of claims 1 to 12, wherein the deepest portion of the surface of the conductive portion is arranged in the center of the trench in a cross section perpendicular to the extending direction. 2. A method for manufacturing a semiconductor device according to item 1. 13. In the first trench portion or the second trench portion, the sidewall side of the surface of the conductive portion is relatively close to the front surface of the semiconductor substrate in a cross section perpendicular to the extending direction. The method of manufacturing a semiconductor device according to any one of Claims 1 to 3. 15. The method of manufacturing a semiconductor device according to claim 1, wherein said cross section perpendicular to said extending direction is a cross section passing through said second semiconductor region. the conductive portion is polysilicon;
16. The method of manufacturing a semiconductor device according to claim 1, wherein the trench of the second trench section has a depth from the surface of the semiconductor substrate different from that of the trench of the first trench section. 17. The method of manufacturing a semiconductor device according to claim 1, further comprising an insulating film that covers inner walls of the trench and ensures insulation between the semiconductor substrate and the conductive portion. 8. The method of manufacturing a semiconductor device according to claim 2, wherein a part of said conductive part is connected to the gate electrode, and at least another part of said conductive part is connected to said emitter electrode. . 19. The method of manufacturing a semiconductor device according to claim 1, wherein said shoulder has a larger average inclination with respect to the depth direction of said semiconductor substrate than said sidewall. 20. The method of manufacturing a semiconductor device according to claim 1, wherein at least part of said shoulder portion has a linear shape. 21. The method of manufacturing a semiconductor device according to claim 1, wherein said shoulder has a length D1 in the depth direction of said semiconductor substrate greater than a width W1 in a direction perpendicular to said extending direction. 22. The method of manufacturing a semiconductor device according to claim 21, wherein the width W1 of the shoulder portion is 1/2 or less and 1/20 or more of the width of the trench at the position facing the upper end of the conductive portion. 23. The method of manufacturing a semiconductor device according to claim 22, wherein the width W1 of the shoulder portion is 1/4 or less of the width of the trench at a position facing the upper end of the conductive portion. 24. The method of manufacturing a semiconductor device according to claim 22, wherein the width W1 of the shoulder portion is 1/10 or more of the width of the trench at a position facing the upper end of the conductive portion. 25. The method of manufacturing a semiconductor device according to claim 1, wherein at least part of said shoulder has an angle of 20 degrees or more with respect to the depth direction of said semiconductor substrate. 26. The semiconductor according to any one of claims 1 to 25, wherein the first trench portion and the second trench portion are arranged such that upper ends of the conductive portions are located at positions deeper than the surface of the semiconductor substrate. Method of manufacturing the device. 27. The second semiconductor region according to any one of claims 1 to 26, wherein the second semiconductor region includes a concave portion recessed inside the second semiconductor region on the back surface side of the semiconductor substrate in a portion overlapping with the shoulder portion when viewed from above. A method of manufacturing a semiconductor device. 27. The recess is recessed inside the second semiconductor region from a portion overlapping with the shoulder portion to a portion overlapping a boundary between the interlayer insulating film and the exposed region with which the shoulder portion is in contact when viewed from above. A method for manufacturing the semiconductor device according to 1. The shoulder portion has, in a cross section perpendicular to the extending direction, a curved surface portion that protrudes toward the inside of the semiconductor substrate, a curved surface portion that protrudes toward the surface side of the semiconductor substrate, and at least a portion of which is linear. 29. The method of manufacturing a semiconductor device according to claim 27 or 28, including at least one of the linear portions. The length in the depth direction of the semiconductor substrate of the first semiconductor region in contact with the first trench portion is longer than the length in the depth direction of the first semiconductor region in contact with the second trench portion. 2. The method for manufacturing the semiconductor device according to 1. The second semiconductor region according to claim 1 or 30, wherein the depth of said second semiconductor region in contact with said shoulder of said first trench is shallower than the depth of said second semiconductor region in contact with said shoulder of said second trench. A method of manufacturing a semiconductor device.

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