JP2021082838A - Semiconductor device and manufacturing method - Google Patents

Abstract

To control a threshold voltage of a semiconductor device.SOLUTION: A semiconductor device comprises: a semiconductor substrate; a trench formed on a surface of the semiconductor substrate; a conductive part formed in the trench, and whose upper end is provided at a position deeper than the surface of the semiconductor substrate, and that is insulated from the semiconductor substrate; and a first region formed on the surface of the semiconductor substrate adjacently to the trench, and that has an impurity concentration higher than that of the semiconductor substrate. On a side wall of the trench between the upper end of the conductive part and the surface of the semiconductor substrate, a shoulder part is provided whose average inclination to a depth direction of the semiconductor substrate is larger than an inclination of the side wall of the trench at a position opposed to the upper end of the conductive part. In the first region, a part that comes into contact with the trench is formed deepest.SELECTED DRAWING: Figure 2

Description

The present invention relates to semiconductor devices and manufacturing methods.

Conventionally, a trench gate structure is known in semiconductor devices such as IGBTs (see, for example, Patent Document 1).
Patent Document 1 Japanese Patent Application Laid-Open No. 08-255902

A semiconductor device such as an IGBT preferably has a predetermined threshold voltage according to a function or the like.

The semiconductor device according to the first aspect of the present invention has a second conductive type first semiconductor region formed on the front surface side of the first conductive type semiconductor substrate and a front side of the first semiconductor region. A first conductive type second semiconductor region selectively formed on a part of the surface side may be provided. The semiconductor device may include a plurality of trenches. The trench may extend in a predetermined stretching direction on the front surface side of the semiconductor substrate and may reach below the first semiconductor region. The semiconductor device may include a conductive portion. The conductive portion may be filled inside a plurality of trenches. The semiconductor device may include an interlayer insulating film. The interlayer insulating film may cover the front surface of the semiconductor substrate with a predetermined pattern. The semiconductor device may include a first electrode. The first electrode may be connected to the semiconductor substrate via the exposed region exposed from the interlayer insulating film in the mesa region sandwiched between the trenches. The semiconductor device may include a first trench portion in a cross section perpendicular to the stretching direction. The first trench portion has a predetermined distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion. The semiconductor device may include a second trench portion in a cross section perpendicular to the stretching direction. In the second trench portion, the distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion may be longer than a predetermined distance. Each of the first trench portion and the second trench portion may have a shoulder portion inclined toward the exposed region side with respect to the inclination of the side wall of the trench at the upper end.

The first electrode may include an emitter electrode. The semiconductor device may include a second conductive type first contact region. The first contact region may have a higher impurity concentration than the first semiconductor region. The first contact region may be selectively formed on a part of the front surface side of the first semiconductor region. The first electrode may include an emitter electrode and a plug portion arranged between the semiconductor substrate and the emitter electrode. The semiconductor device may include a second conductive type second contact region. The second contact region may have a higher impurity concentration than the first semiconductor region. The second contact area may be located below the plug portion. The lower end of the plug portion may be provided at a position deeper than the lower end of the second semiconductor region. The semiconductor device may include a first conductive type storage region. The storage region may be located below the first semiconductor region. The storage region may have a higher impurity concentration than the semiconductor substrate.

The first semiconductor region may be a base region. The second semiconductor region may be an emitter region.

The emitter region may be relatively long on the side adjacent to the trench. The emitter region is arranged in the mesa region sandwiched between the first trench portion and the second trench portion in the cross section perpendicular to the stretching direction, but is located on the first trench portion side and the second trench portion side. It does not have to be arranged symmetrically. The depth of the emitter region may be different between the first trench portion side and the second trench portion side.

In the first trench portion or the second trench portion, the deepest portion of the surface of the conductive portion may be arranged in the center of the trench in the cross section perpendicular to the stretching direction. In the cross section perpendicular to the stretching direction of the first trench portion or the second trench portion, the side wall side of the surface of the conductive portion may be relatively close to the front surface of the semiconductor substrate. The cross section perpendicular to the stretching direction may be a cross section that passes through the second semiconductor region.

The conductive portion may be polysilicon. The semiconductor device may include an insulating film. The insulating film may cover the inner wall of the trench. The insulating film may ensure insulation between the semiconductor substrate and the conductive portion. A part of the conductive part may be connected to the gate electrode, and at least a part of the other may be connected to the emitter electrode. The shoulder portion may have a larger average inclination with respect to the depth direction of the semiconductor substrate than the side wall portion. The shoulder may include a linear shape, at least in part.

The shoulder portion may have a length D1 in the depth direction of the semiconductor substrate larger than a width W1 in the direction perpendicular to the stretching direction. The width W1 of the shoulder portion may be 1/2 or less, 1/20 or more of the width of the trench at a position facing the upper end of the conductive portion. The width W1 of the shoulder portion may be 1/4 or less of the width of the trench at a position facing the upper end of the conductive portion. The width W1 of the shoulder portion may be 1/10 or more of the width of the trench at a position facing the upper end of the conductive portion.

At least a part of the shoulder portion may have an angle of 20 degrees or more with respect to the depth direction of the semiconductor substrate.

In the first trench portion and the second trench portion, the upper ends of the respective conductive portions may be arranged at positions deeper than the surface of the semiconductor substrate.

The outline of the above invention does not list all the features of the present invention. Sub-combinations of these feature groups can also be inventions.

It is a figure which shows a part of the surface of the semiconductor device 100 which concerns on 1st Embodiment. It is a figure which shows the AA' cross section in FIG. It is a figure explaining a part of the manufacturing process of the gate trench part 40 and the emitter region 12 in the semiconductor device 100. It is a figure explaining the shape of the gate trench portion 40. It is a figure explaining the shape of the emitter region 12 and the gate conductive part 44. It is a figure which shows the modification of the shape of the shoulder part 33. It is a figure which shows the modification of the shape of the shoulder part 33. It is a figure which shows the BB' cross section in FIG. It is a perspective view of a gate trench 41, a gate conductive part 44, an emitter area 12, and a contact area 15. It is a figure which shows the CC'cross section in FIG. It is a figure which shows the DD'cross section in FIG. It is a figure which shows an example of the manufacturing process of a gate conductive part 44. It is a figure which shows the cross section of the semiconductor device 100 which concerns on 2nd Embodiment. It is a figure which shows an example of the process of forming a shoulder part 33. It is a figure which shows a part of the surface of the semiconductor device 100 which concerns on 3rd Embodiment. It is a figure which shows the CC'cross section in FIG.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the inventions that fall within the scope of the claims. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

FIG. 1 is a diagram showing a part of the surface of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 of this example includes a plurality of gate trench portions 40 extending in a predetermined stretching direction on the surface of the semiconductor substrate. The plurality of gate trench portions 40 are arranged at predetermined intervals along an arrangement direction orthogonal to the stretching direction. The gate trench portion 40 functions as a gate for a power semiconductor element such as an IGBT.

On the surface of the semiconductor substrate, a P-type base region 14 is formed in a region sandwiched between the gate trench portions 40. A P + -shaped contact region 15 is formed on the surface of the base region 14. Further, an N + type emitter region 12 is selectively formed on a part of the surface of the contact region 15. The emitter region 12 is an example of the first region. The contact region 15 is an example of the second region. The base region 14 is an example of a third region. Further, each region may have a conductive type opposite to the conductive type described in the present specification.

In this example, each of the contact region 15 and the emitter region 12 is formed from one adjacent gate trench portion 40 to the other gate trench portion 40. The contact region 15 and the emitter region 12 are formed so as to be alternately exposed along the extending direction of the gate trench portion 40 in the region sandwiched between the gate trench portions 40.

Further, the emitter region 12 may be formed on both sides of each gate trench portion 40 along the stretching direction, and the contact region 15 may be formed in the region sandwiched between the emitter regions 12. An interlayer insulating film, an emitter electrode, and the like are formed on the surface of the semiconductor device 100, but they are omitted in FIG.

FIG. 2 is a diagram showing a cross section taken along the line AA'in FIG. The AA'cross section is a cross section perpendicular to the surface of the semiconductor device 100 and perpendicular to the stretching direction of the gate trench portion 40. The semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52, and a collector electrode 24 in the cross section.

The interlayer insulating film 26 is formed in a predetermined pattern on the surface of the semiconductor substrate 10. The interlayer insulating film 26 covers the opening portion of the gate trench portion 40 and exposes at least a part of the mesa region sandwiched between the gate trench portions 40. The interlayer insulating film 26 is, for example, a PSG film or a BPSG film. The emitter electrode 52 is formed on the upper side of the interlayer insulating film 26. The emitter electrode 52 is connected to the surface of the semiconductor substrate 10 which is not covered with the interlayer insulating film 26.

The collector electrode 24 is formed on the back surface of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a conductive material such as metal. Further, in the present specification, the surface of each member such as a substrate, a layer, and a region on the emitter electrode 52 side is referred to as a front surface or an upper surface, and a surface on the collector electrode 24 side is referred to as a back surface or a bottom surface. Further, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as a depth direction. Further, the direction from the collector electrode 24 to the emitter electrode 52 is upward, and the direction from the emitter electrode 52 to the collector electrode 24 is downward.

The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate, or the like. A P-type base region 14 is formed on the surface side of the semiconductor substrate 10. Further, the N + type emitter region 12 is selectively formed in a part of the region on the surface side of the base region 14.

Further, the semiconductor substrate 10 further has an N-type drift region 18, an N-type buffer region 20, and a P + -type collector region 22. The drift region 18 is formed on the back surface side of the base region 14.

The buffer region 20 is formed on the back surface side of the drift region 18. The impurity concentration in the buffer region 20 is higher than the impurity concentration in the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the back surface side of the base region 14 from reaching the collector region 22. The collector area 22 is formed on the back surface side of the buffer area 20. Further, a collector electrode 24 is provided on the back surface of the collector region 22.

One or more gate trench portions 40 are formed on the surface side of the semiconductor substrate 10. Each gate trench portion 40 penetrates the base region 14 from the surface of the semiconductor substrate 10 and reaches the drift region 18. The gate trench portion 40 in this cross section penetrates the emitter region 12 and the base region 14 from the surface of the semiconductor substrate 10 and reaches the drift region 18.

The gate trench portion 40 has a gate trench 41, an insulating film 42, and a gate conductive portion 44 formed on the surface side of the semiconductor substrate 10. The insulating film 42 is formed so as to cover the inner wall of the gate trench 41. The insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench 41. The gate conductive portion 44 is formed inside the gate trench 41 inside the insulating film 42. That is, the insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

The upper end 45 of the gate conductive portion 44 is provided at a position deeper than the surface of the semiconductor substrate 10. That is, the upper end 45 of the gate conductive portion 44 is depressed inside the gate trench 41. The upper end 45 of the gate conductive portion 44 refers to the uppermost end portion of the gate conductive portion 44.

An interlayer insulating film 26 is formed in a region inside the gate trench 41 where the gate conductive portion 44 and the insulating film 42 are not provided. As a result, the gate conductive portion 44 is insulated from the emitter electrode 52. However, the gate trench portion 40 is provided so as to extend to the lower side of the metal gate electrode in the semiconductor device 100. A contact hole for electrically connecting the gate conductive portion 44 and the gate electrode is formed in the interlayer insulating film 26 under the gate electrode.

The gate conductive portion 44 includes at least a region facing the adjacent base region 14. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed in the surface layer of the interface of the base region 14 in contact with the gate trench 41.

The semiconductor device 100 may be provided with a dummy trench portion instead of a part of the gate trench portion 40. The dummy trench portion has the same structure as the gate trench portion 40. However, the conductive portion inside the dummy trench portion is electrically connected to the emitter electrode 52. In this case, a contact hole is provided in the interlayer insulating film 26 between the dummy trench portion and the emitter electrode 52. By providing the dummy trench portion, the carrier injection promoting effect (IE effect) in the drift region can be enhanced and the on-voltage can be reduced.

In the cross section of the semiconductor substrate 10 in the depth direction, the average inclination of the side wall of the gate trench 41 between the upper end 45 of the gate conductive portion 44 and the surface of the semiconductor substrate 10 faces the upper end 45 of the gate conductive portion 44. It is larger than the inclination of the side wall at the position where it is to be. Unless otherwise specified, the “inclination” in the present specification refers to the inclination of the semiconductor substrate 10 with respect to the depth direction in the cross section. For example, the "tilt" of the surface of the semiconductor substrate 10 is approximately 90 degrees, and the "tilt" of a straight line parallel to the depth direction is 0 degrees. For the average inclination of the side wall within a predetermined range of the gate trench 41, the inclination of the side wall of the gate trench 41 in the cross section is integrated over a predetermined length of the side wall of the gate trench 41, and the integrated value is the predetermined value. It may be calculated by dividing by the length.

The gate trench 41 of this example has a shoulder portion 33 in a region in contact with the surface of the semiconductor substrate 10. The shoulder portion 33 is formed between the gate conductive portion 44 and the surface of the semiconductor substrate 10 (that is, above the upper end 45 of the gate conductive portion 44) in the side wall of the gate trench 41. In the cross section, the average inclination of the side wall of the gate trench 41 in the shoulder portion 33 is smaller than the inclination of the side wall at the position facing the upper end 45 of the gate conductive portion 44. The inclination of the side wall of the gate trench 41 between the shoulder portion 33 and the upper end 45 of the gate conductive portion 44 is substantially equal to the inclination of the side wall of the gate trench 41 at a position facing the upper end 45 of the gate conductive portion 44. Good.

By increasing the inclination of the side wall of the gate trench 41 above the upper end 45 of the gate conductive portion 44 in this way, it becomes easier to control the depth of the emitter region 12 in the region in contact with the gate trench 41. By controlling the depth of the emitter region 12, the length of the remaining base region 14 can be controlled. The length of the base region 14 in contact with the gate trench 41 corresponds to the channel length. Therefore, it becomes easy to control the threshold voltage of the semiconductor device 100.

FIG. 3 is a diagram illustrating a part of the manufacturing process of the gate trench portion 40 and the emitter region 12 in the semiconductor device 100. First, in the gate trench forming step S300, the gate trench 41 is formed on the surface of the semiconductor substrate 10. The gate trench 41 has a shoulder portion 33 in a region in contact with the surface of the semiconductor substrate 10. For example, after etching the surface of the semiconductor substrate 10 with a first mask having a predetermined opening to form a trench, the surface of the semiconductor substrate 10 is wet-etched with a second mask having a larger opening than the first mask. By doing so, a gate trench 41 having a shoulder portion 33 may be formed. The second mask may be formed by wet-etching the first mask to widen the opening area.

Next, in the gate conductive portion forming step S302, the insulating film 42 and the gate conductive portion 44 are formed on the inner wall of the gate trench 41. The insulating film 42 may be formed by oxidizing the semiconductor substrate 10. The gate conductive portion 44 is formed so that the upper end 45 of the gate conductive portion 44 is located deeper than the surface 11 of the semiconductor substrate 10. In this example, the upper end 45 of the gate conductive portion 44 is provided below the shoulder portion 33. The gate conductive portion 44 is formed of, for example, impurity-doped polysilicon.

After forming the gate conductive portion 44, P-type impurities are injected and diffused on the surface of the semiconductor substrate 10 to form the base region 14. The P-type impurity is, for example, boron. The diffusion temperature of the base region 14 is, for example, about 1100 degrees. The gate trench portion 40 may be formed after the base region 14 is formed.

Next, in the emitter region formation step S304, N-type impurities are injected into the semiconductor substrate 10 and diffused. The N-type impurity is, for example, arsenic. Further, a P-type impurity such as boron is injected into the contact region 15 and diffused. Impurities in the emitter region 12 and the contact region 15 may be diffused in the same step. The temperature of the diffusion step may be lower than the diffusion temperature of the base region 14. The temperature of the diffusion step is, for example, 1000 degrees or less.

This forms the emitter region 12. In S304, impurities are injected not only on the surface of the semiconductor substrate 10 but also on the side wall of the gate trench 41 using the gate conductive portion 44 as a mask. By such a method, the emitter region 12 is formed so that the portion in contact with the gate trench 41 is the deepest.

In S304, N-type impurities are diffused in the region in contact with the gate trench 41 to a depth corresponding to the threshold voltage that the semiconductor device 100 should have. Diffusing impurities to deeper locations requires heat treatment at higher temperatures or longer times. However, heat treatment at a high temperature is preferable because the production efficiency deteriorates when the heat treatment is performed over a long period of time. However, when the heat treatment is performed at a high temperature, the length of the diffusion of impurities per unit time becomes large, so that it becomes difficult to control the diffusion depth of impurities.

On the other hand, in the semiconductor device 100 and the manufacturing method of this example, since the gate trench 41 has the shoulder portion 33, the length of diffusing impurities in the region in contact with the gate trench 41 can be reduced. That is, in the region where the shoulder portion 33 is provided, impurities are injected below the surface 11 of the semiconductor substrate 10. Therefore, when forming the emitter region 12 having a predetermined depth, the length at which impurities must be diffused can be reduced.

Therefore, even if impurities are diffused at a lower temperature, the heat treatment time does not become long and the production efficiency does not deteriorate. Since impurities can be diffused at a low temperature, the depth of the emitter region 12 in the region in contact with the gate trench 41 can be controlled with high accuracy.

Further, since the gate trench 41 has the shoulder portion 33, the area of the mesa region sandwiched between the gate trench portions 40 can be reduced. Therefore, an electron injection promoting effect (IE effect) can be obtained.

In S304, impurities may be injected into the side wall of the gate trench 41 from the direction having a predetermined inclination θ1 with respect to the depth direction of the semiconductor substrate 10. As a result, impurities can be injected efficiently. The inclination θ1 is, for example, 10 degrees or less.

Further, since the emitter region 12 is formed by self-alignment with the gate conductive portion 44 as a mask, the emitter region 12 can be easily brought into contact with the gate trench portion 40. On the other hand, when the emitter region 12 is formed by using a mask independent of the gate trench portion 40, the emitter region 12 and the gate trench portion 40 do not come into contact with each other due to manufacturing variations in mask alignment and the like, and the semiconductor device In some cases, 100 cannot operate.

FIG. 4 is a diagram illustrating the shape of the gate trench portion 40. In this example, the inclination of the side wall of the gate trench 41 at the position 31 facing the upper end 45 of the gate conductive portion 44 is set to θ2. Further, the width of the shoulder portion 33 in the radial direction of the opening of the gate trench 41 is W1, and the length in the depth direction is D1. The starting point of the shoulder portion 33 may be the end of the side wall of the gate trench 41 on the surface 11 of the semiconductor substrate 10. Further, the end point of the shoulder portion 33 is a position where the inclination of the side wall of the gate trench 41 becomes larger than a predetermined value by a predetermined value or more when the side wall of the gate trench 41 is traced from the position 31 toward the surface 11 of the semiconductor substrate 10. It may be there. As an example, the predetermined value is 10 degrees. The predetermined value may be 0 degrees, 20 degrees, or 30 degrees.

The shoulder portion 33 may have a curved surface portion that is convex toward the inside of the semiconductor substrate 10. That is, the inclination of the shoulder portion 33 increases as the distance from the surface of the semiconductor substrate 10 increases. Due to the shape of the shoulder portion 33, impurities can be injected into a deep position more efficiently. Therefore, the diffusion length of impurities for forming the emitter region 12 having a predetermined depth can be shortened.

Further, the length D1 of the shoulder portion 33 may be larger than the width W1. As a result, the opening area of the gate trench 41 can be reduced and miniaturized, and impurities can be injected at a deep position in the region adjacent to the gate trench 41. Further, the length D1 may be equal to the width W1, and the length D1 may be smaller than the width W1.

The width W1 of the shoulder portion 33 may be less than half the width of the gate trench 41 at the position 31 and may be less than 1/4. As a result, it is possible to suppress an increase in the area of the gate trench 41 on the surface 11 of the semiconductor substrate 10. Further, the width W1 may be 1/20 or more, or 1/10 or more, the width of the gate trench 41 at the position 31. As a result, impurities can be efficiently injected into a deep position.

Further, the length D1 of the shoulder portion 33 may be less than half of the distance R1 between the upper end 45 of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10. Further, the length D1 may be larger than half of the distance R1. Further, the length D1 may be substantially equal to the distance R1. As an example, when the length D1 is 90% or more and 110% or less of the distance R1, the length D1 and the distance R1 are considered to be substantially equal.

Further, the side wall of the gate trench 41 has a portion having an inclination of 20 degrees or more between the upper end 45 of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10. For example, the inclination θ3 of at least a part of the shoulder portion 33 is 20 degrees or more. As described above, by increasing the inclination of the side wall of the gate trench 41 above the upper end 45, impurities can be efficiently injected into a deep position, and the diffusion of impurities in the region adjacent to the gate trench 41 can be easily controlled. Become.

FIG. 5 is a diagram illustrating the shapes of the emitter region 12 and the gate conductive portion 44. As described above, since impurities are also injected from the inner wall of the gate trench 41, the lower end 34 of the portion adjacent to the gate trench 41 is provided at a position deeper than the other portions in the emitter region 12. With such a shape, the length of the base region 14 in the region adjacent to the gate trench 41 can be controlled, and the threshold voltage of the semiconductor device 100 can be controlled.

Further, in the emitter region 12, the length D2 in the depth direction of the portion in contact with the gate trench 41 may be larger than the length of the other portion of the emitter region 12. For example, the length D3 of the emitter region 12 in the mesa region where the gate trench 41 is not provided is smaller than the length D2.

Further, on the end surface of the gate conductive portion 44 on the surface 11 side of the semiconductor substrate 10, a portion adjacent to the side wall of the gate trench 41 (upper end 45 in this example) is formed closest to the surface 11 of the semiconductor substrate 10. In this example, of the end faces of the gate conductive portion 44 on the surface 11 side of the semiconductor substrate 10, the deepest portion 46 located at the center of the gate trench 41 is formed at a position farthest from the surface 11 of the semiconductor substrate 10.

As an example, the distance of the end surface of the gate conductive portion 44 from the surface of the semiconductor substrate 10 gradually increases from the side wall of the gate trench 41 to the center of the gate trench 41. That is, as the depth from the surface 11 of the semiconductor substrate 10 increases, the thickness of the gate conductive portion 44 adjacent to the side wall of the gate trench 41 gradually increases. As described above, when impurities are injected obliquely using the gate conductive portion 44 as a mask, the impurities pass through the gate conductive portion 44 and are injected into the semiconductor substrate 10 where the thickness of the gate conductive portion 44 is small. As a result, in the region adjacent to the gate trench 41, impurities can be easily injected and diffused from the surface 11 of the semiconductor substrate 10 to a deep position.

FIG. 6A is a diagram showing a modified example of the shape of the shoulder portion 33. The shoulder portion 33 of this example has a curved surface portion that is convex toward the surface side of the semiconductor substrate 10. That is, the inclination of the shoulder portion 33 in this example decreases as the distance from the surface of the semiconductor substrate 10 increases. Even with such a shape, impurities can be easily diffused from the surface 11 of the semiconductor substrate 10 to a deep position.

FIG. 6B is a diagram showing a modified example of the shape of the shoulder portion 33. The shoulder portion 33 of this example has a linear shape at least in part. The linear shape has a slope larger than a predetermined value or more than the slope θ2 of the side wall of the gate trench 41 at a position facing the upper end 45 of the gate conductive portion 44. The predetermined value may be 10 degrees, 20 degrees, or 30 degrees. Even with such a shape, impurities can be easily diffused from the surface 11 of the semiconductor substrate 10 to a deep position.

FIG. 7 is a diagram showing a BB'cross section in FIG. In the cross section, the semiconductor device 100 has a contact region 15 instead of the emitter region 12 in the cross section shown in FIG. Other structures are the same as the cross section shown in FIG.

That is, the gate trench 41 has shoulders 33 in both the region adjacent to the emitter region 12 and the region adjacent to the contact region 15. The shape of the shoulder portion 33 in the region adjacent to the emitter region 12 and the shape of the shoulder portion 33 in the region adjacent to the contact region 15 may be the same.

With such a structure, the depth of the contact region 15 can be controlled in the same manner as the emitter region 12. That is, even in the contact region 15, the portion in contact with the gate trench 41 is formed to the deepest position.

FIG. 8 is a perspective view of the gate trench 41, the gate conductive portion 44, the emitter region 12, and the contact region 15. The shoulder portion 33 is formed by stretching along the stretching direction of the gate trench 41.

FIG. 9A is a diagram showing a CC'cross section in FIG. The cross section is a cross section along the extending direction of the gate trench 41 in the region where the gate trench 41 is not provided (that is, the mesa region). As described above, the emitter region 12 and the contact region 15 are alternately exposed on the surface 11 of the semiconductor substrate 10 along the extending direction of the gate trench 41. The contact region 15 is formed to a position deeper than the emitter region 12.

FIG. 9B is a diagram showing a DD'cross section in FIG. The cross section is a cross section along the extending direction of the gate trench 41 in the region where the shoulder portion 33 is provided. The emitter region 12 on the shoulder portion 33 is formed to a position deeper than the emitter region 12 in the mesa region shown in FIG. 9A. Further, the contact region 15 in the shoulder portion 33 is formed to a position deeper than the contact region 15 in the mesa region.

Further, the length D6 of the emitter region 12 in the shoulder portion 33 in the depth direction is larger than the length D3 of the emitter region 12 in the mesa region. The length D8 of the contact region 15 in the shoulder portion 33 in the depth direction is larger than the length D5 of the contact region 15 in the mesa region. Further, the difference D7 between the lengths of the emitter region 12 and the contact region 15 in the shoulder portion 33 is equal to or greater than the difference D4 in the lengths of the emitter region 12 and the contact region 15 in the mesa region.

FIG. 10 is a diagram showing an example of a manufacturing process of the gate conductive portion 44. First, a gate trench 41 having a shoulder portion 33 is formed on the surface 11 of the semiconductor substrate 10. Next, the insulating film 42 is formed on the surfaces of the gate trench 41 and the semiconductor substrate 10. Next, the conductive material 47 is deposited on the surfaces of the gate trench 41 and the semiconductor substrate 10. As the conductive material 47 is deposited, the thickness of the conductive material 47 deposited on the side wall increases inside the gate trench 41. Further, the thickness of the conductive material 47 increases while maintaining the shape along the shoulder portion 33.

When the conductive material 47 is filled to the center of the gate trench 41, the conductive material 47 above the opening of the gate trench 41 has a downwardly convex shape, as shown on the lower side of FIG. Then, the conductive material 47 is etched to a predetermined depth inside the gate trench 41 to form the gate conductive portion 44 as shown in FIG. As described above, since the gate trench 41 has a shoulder portion, the gate conductive portion 44 whose upper surface is convex downward can be easily formed. Therefore, impurities can be easily injected into the side surface of the gate trench 41.

FIG. 11 is a diagram showing a cross section of the semiconductor device 100 according to the second embodiment. The semiconductor device 100 of this example has a plurality of gate trench portions 40 having different distances from the surface 11 of the semiconductor substrate 10 to the upper end of the gate conductive portion 44. That is, it has a plurality of gate trench portions 40 having different depths of the upper ends of the gate conductive portions 44. Each gate trench portion 40 penetrates the base region 14 having a uniform depth at the lower end. Further, the cross section in which each gate trench portion 40 appears does not have to be a single plane.

When the depth of the upper end of the gate conductive portion 44 is different, the depth of the emitter region 12 in the region adjacent to the gate trench 41 is also different. Specifically, when the upper end of the gate conductive portion 44 is shallow, the emitter region 12 is also shallow, and when the upper end of the gate conductive portion 44 is deep, the emitter region 12 is also deep.

In this example, the distance between the upper end of the gate conductive portion 44 in the first gate trench portion 40-1 and the surface 11 of the semiconductor substrate 10 is L1. Further, the distance between the upper end of the gate conductive portion 44 in the second gate trench portion 40-2 and the surface 11 of the semiconductor substrate 10 is L2. The distance L1 is smaller than the distance L2.

As described above, the larger the distance between the upper end of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10, the deeper the emitter region 12 adjacent to the gate trench 41 and the shorter the channel length. Therefore, the channel length C1 of the first gate trench portion 40-1 is larger than the channel length C2 of the second gate trench portion 40-2. Therefore, the threshold voltage of the first gate trench portion 40-1 becomes larger than the threshold voltage of the second gate trench portion 40-2.

By controlling the depth of the upper end of the gate conductive portion 44 in this way, the threshold voltage of each gate trench portion 40 can be controlled. Therefore, an appropriate threshold voltage can be set according to the application or function of each gate trench portion 40.

The gate trench 41 in the first gate trench portion 40-1 and the second gate trench portion 40-2 may have different depths from the surface 11 of the semiconductor substrate 10. Specifically, the gate trench 41 of the gate trench portion 40 for which the threshold voltage is desired to be increased is formed deeper. Then, a gate conductive portion 44 having the same length is formed in each gate trench 41. As a result, the depth of the upper end of each of the gate conductive portions 44 differs depending on the depth of the gate trench 41. According to this example, the threshold voltage of each gate trench portion 40 can be adjusted while simultaneously forming each gate conductive portion 44 to improve the efficiency of the manufacturing process.

Further, by etching the surface 11 of the semiconductor substrate 10 with a mask having a plurality of openings having different areas, a plurality of gate trenches 41 having different depths may be formed. When the opening area of the mask is large, a deep gate trench 41 can be formed. As a result, the threshold voltage of each gate trench portion 40 can be adjusted while simultaneously forming gate trenches 41 having different depths to improve the efficiency of the manufacturing process.

FIG. 12 is a diagram showing an example of a process of forming the shoulder portion 33. As described above, the gate trench 41 is formed by anisotropically etching the surface 11 of the semiconductor substrate 10 using the first mask 48. Next, the first mask 48 is wet-etched to form a second mask 49 in which the area of the mask opening is enlarged. The opening of the second mask 49 exposes a region of the surface 11 on which the shoulder 33 should be formed. Then, the surface 11 of the semiconductor substrate 10 is wet-etched using the second mask 49. As a result, the shoulder portion 33 that is gentler than the inclination of the side wall of the gate trench 41 can be formed.

FIG. 13 is a diagram showing a part of the surface of the semiconductor device 100 according to the third embodiment. The semiconductor device 100 of this example includes a plurality of gate trench portions 40 extending in a predetermined stretching direction on the surface of the semiconductor substrate. The gate trench portion 40 is the same as the gate trench portion 40 in any of the embodiments described with reference to FIGS. 1 to 12.

On the surface of the semiconductor substrate, an N + -shaped emitter region 12 is formed in a region sandwiched between the gate trench portions 40. The emitter region 12 is formed in a stripe shape in a region adjacent to the gate trench portion 40. In this example, the base region 14 is not exposed in the region sandwiched between the gate trenches 40 on the surface of the semiconductor substrate.

Further, the contact region 15 of this example is formed inside the semiconductor substrate and is not exposed on the surface of the semiconductor substrate. The contact region 15 is formed in a stripe shape in parallel with the gate trench portion 40 inside the semiconductor substrate. A contact opening is formed in the emitter region 12 to expose the contact region 15. Inside the contact opening, a plug connecting the contact region 15 and the emitter electrode 52 is formed.

FIG. 14 is a diagram showing a CC'cross section in FIG. The CC'cross section is perpendicular to the surface of the semiconductor device 100 and perpendicular to the stretching direction of the gate trench portion 40. In this example, in the region sandwiched between the two gate trench portions 40, the emitter region 12 is formed near the upper surface of the semiconductor substrate 10, and the base region 14 is formed below the emitter region 12. Further, the semiconductor device 100 of this example further includes a plug portion 28. Further, a contact region 15 is formed adjacent to the bottom portion of the plug portion 28. Other structures may be the same as those shown in FIG.

The plug portion 28 is formed between the two gate trench portions 40 so as to penetrate the interlayer insulating film 26 and the emitter region 12. The plug portion 28 may be arranged in the center of the region sandwiched between the two gate trench portions 40. The upper end of the plug portion 28 is connected to the emitter electrode 52, and the lower end is arranged inside the base region 14. The plug portion 28 may be made of, for example, a material containing tungsten.

The contact region 15 is formed inside the base region 14. The contact region 15 of this example is entirely surrounded by the base region 14. The contact region 15 is formed in contact with the lower end of the plug portion 28. With such a structure, the contact resistance between the emitter electrode 52 and the semiconductor region can be reduced. In particular, when the semiconductor device 100 becomes finer, the mesa width sandwiched between the gate trench portions 40 becomes smaller, and the contact area between the emitter electrode 52 and the semiconductor region becomes smaller. On the other hand, according to this example, by providing the plug portion 28, the contact resistance can be kept low even if the semiconductor device 100 is miniaturized.

Further, the semiconductor device 100 may further include an N + type storage region 16. The accumulation region 16 has a higher impurity concentration than the drift region 18. The storage region 16 is formed between the base region 14 and the drift region 18 between the two gate trench portions 40. With such a configuration, the carrier accumulation effect can be enhanced and the trade-off between the on-voltage and the turn-off loss can be improved. The storage region 16 may be applied to the semiconductor device 100 according to the first and second embodiments described with reference to FIGS. 1 to 12.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that such modified or improved forms may also be included in the technical scope of the present invention.

In the claims or the specification, "upper" and "lower" refer in opposite directions. However, the term "above" is not limited to the direction opposite to the direction of gravity. Also, the term "bottom" is not limited to the direction of gravity.

10 ... Semiconductor substrate, 11 ... Surface, 12 ... Emitter region, 14 ... Base region, 15 ... Contact region, 16 ... Storage region, 18 ... Drift region, 20 ...・ ・ Buffer area, 22 ... collector area, 24 ... collector electrode, 26 ... interlayer insulating film, 28 ... plug part, 33 ... shoulder part, 34 ... lower end, 40 ... -Gate trench, 41 ... Gate trench, 42 ... Insulating film, 44 ... Gate conductive part, 45 ... Upper end, 46 ... Deepest part, 47 ... Conductive material, 48. .. 1st mask, 49 ... 2nd mask, 52 ... Emitter electrode, 100 ... Semiconductor device

Claims (26)

A second conductive type first semiconductor region formed on the front surface side of the first conductive type semiconductor substrate and a part of the front surface side of the first semiconductor region were selectively formed. In a semiconductor device including a first conductive type second semiconductor region,
A plurality of trenches extending in a predetermined stretching direction on the front surface side of the semiconductor substrate and extending to the lower side of the first semiconductor region.
Conductive portions filled inside the plurality of trenches,
An interlayer insulating film that covers the front surface of the semiconductor substrate with a predetermined pattern,
In the mesa region sandwiched between the trenches, a first electrode connected to the semiconductor substrate via an exposed region exposed from the interlayer insulating film is further provided.
In the cross section perpendicular to the stretching direction
The first trench portion where the distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion is a predetermined distance,
A second trench portion in which the depth from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion is longer than the predetermined distance is included.
The first trench portion and the second trench portion are semiconductor devices in which each of the trenches has a shoulder portion inclined toward the exposed region side with respect to the inclination of the side wall of the trench at the upper end. The semiconductor device according to claim 1, wherein the first electrode includes an emitter electrode. The second aspect of the present invention further comprises a second conductive type first contact region which has a higher impurity concentration than the first semiconductor region and is selectively formed on a part of the front surface side of the first semiconductor region. The semiconductor device described. The semiconductor device according to claim 1, wherein the first electrode includes an emitter electrode and a plug portion arranged between the semiconductor substrate and the emitter electrode. The semiconductor device according to claim 4, further comprising a second conductive type second contact region arranged below the plug portion, which has a higher impurity concentration than the first semiconductor region. The semiconductor device according to claim 5, wherein the lower end of the plug portion is provided at a position deeper than the lower end of the second semiconductor region. The semiconductor device according to any one of claims 4 to 6, which is arranged below the first semiconductor region and further includes a first conductive type storage region having a higher impurity concentration than the semiconductor substrate. The semiconductor device according to any one of claims 1 to 7, wherein the first semiconductor region is a base region. The semiconductor device according to any one of claims 1 to 8, wherein the second semiconductor region is an emitter region. The semiconductor device according to claim 9, wherein the emitter region is relatively long on the side adjacent to the trench. The emitter region is arranged in a mesa region sandwiched between the first trench portion and the second trench portion in a cross section perpendicular to the stretching direction, but the first trench portion side and the first trench region. 2. The semiconductor device according to claim 9 or 10, which is not arranged symmetrically with the trench portion side. The semiconductor device according to claim 11, wherein the emitter region has a different depth between the first trench portion side and the second trench portion side. The first trench portion or the second trench portion is any one of claims 1 to 12 in which the deepest portion of the surface of the conductive portion is arranged in the center of the trench in a cross section perpendicular to the stretching direction. The semiconductor device according to item 1. Claims 1 to 13 of the first trench portion or the second trench portion, in a cross section perpendicular to the stretching direction, the side of the side wall of the surface of the conductive portion is relatively close to the front surface of the semiconductor substrate. The semiconductor device according to any one of the above items. The semiconductor device according to any one of claims 1 to 14, wherein the cross section perpendicular to the stretching direction is a cross section passing through the second semiconductor region. The semiconductor device according to any one of claims 1 to 15, wherein the conductive portion is polysilicon. The semiconductor device according to any one of claims 1 to 16, further comprising an insulating film that covers the inner wall of the trench and further secures insulation between the semiconductor substrate and the conductive portion. The semiconductor device according to any one of claims 2 to 17, wherein a part of the conductive portion is connected to a gate electrode and at least a part of the other is connected to the emitter electrode. The semiconductor device according to any one of claims 1 to 18, wherein the shoulder portion has a larger average inclination with respect to the depth direction of the semiconductor substrate than the side wall portion. The semiconductor device according to any one of claims 1 to 19, wherein the shoulder portion includes a linear shape at least in part. The semiconductor device according to any one of claims 1 to 20, wherein the shoulder portion has a length D1 in the depth direction of the semiconductor substrate larger than a width W1 in the direction perpendicular to the stretching direction. The semiconductor device according to claim 21, wherein the width W1 of the shoulder portion is ½ or less and 1/20 or more of the width of the trench at a position facing the upper end of the conductive portion. The semiconductor device according to claim 22, wherein the width W1 of the shoulder portion is 1/4 or less of the width of the trench at a position facing the upper end of the conductive portion. The semiconductor device according to claim 22 or 23, wherein the width W1 of the shoulder portion is 1/10 or more of the width of the trench at a position facing the upper end of the conductive portion. The semiconductor device according to any one of claims 1 to 24, wherein at least a part of the shoulder portion has an angle of 20 degrees or more with respect to the depth direction of the semiconductor substrate. The semiconductor according to any one of claims 1 to 25, wherein the upper end of each of the first trench portion and the second trench portion is arranged at a position deeper than the surface of the semiconductor substrate. apparatus.

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