JP7283707B2 - Direct formation of hexagonal boron nitride on silicon-based dielectrics - Google Patents

Description

Cross-reference to related applications

This application claims priority to U.S. Provisional Patent Application No. 62/335,149, filed May 12, 2016, the entire disclosure of which is incorporated herein by reference in its entirety. incorporated.

The field of the invention relates generally to methods for fabricating graphene and boron nitride heterostructures on semiconductor substrates.

Single-atom-thick graphene is the newest allotrope of carbon and over the past decade has become the most studied material in the scientific community due to its excellent optical, mechanical, and electrical properties. . Graphene is a hexagonal array of carbon atoms forming one-atom-thick planar sheets of sp2 ^- hybridized (double-bonded) carbon atoms arranged in a honeycomb lattice. Graphene is a promising electronic material. Graphene has the potential to have a major impact on the semiconductor industry due to its excellent electrical, thermal, mechanical and optical properties, while also offering compatibility with existing semiconductor processing technologies. Graphene has shown surprising applications, including single-molecule detection, ultrafast field effect transistors (FETs), hydrogen visualization templates for transmission electron microscopy (TEM), and tunable spintronic devices. In addition, graphene has high thermal conductivity (25× silicon), high mechanical strength (strongest nanomaterial), high optical transparency (97.7% for single-layer graphene), carrier-controlled interband/optical Transitions, and flexible structures are shown. Electronically, graphene is a semimetal with a zero bandgap due to the conduction band touching the valence band at two points (K and K') in the Brillouin zone. The high density of π-electrons from the ^sp2 carbon atoms of graphene and carrier confinement in the open crystal structure endow it with the highest mobility ever measured.

Atomically smooth, chemically inert, and electrically insulating substrate platforms are important for enhancing charge carrier mobility in interfacial graphene. In addition, typical silicon-based oxide and nitride substrates are rough, dopant-rich, and have poor electron and heat transport properties. For example, Dean, C. R. Boron nitride substrates for high-quality graphene electronics, et al. Nat Nano 5, 722-726, (2010); K. and Grigorieva, I.M. V. Van der Waals heterostructures. See Nature 499, 419-425, (2013). In contrast, wide-bandgap hexagonal boron nitride (h-BN), which has remarkable physical properties and chemical stability, has recently been used for graphene and other two-dimensional nanomaterials (2DN) electronics, deep ultraviolet radiation, Qualified as the ideal gate dielectric for the thinnest tunneling junctions and for chemically resistant films (for protective coatings). For example, Kubota, Y.; , Watanabe, K.; , Tsuda, O. and Taniguchi, T.; Deep Ultraviolet Light-Emitting Hexagonal Boron Nitride Synthesized at Atmospheric Pressure. Science 317, 932-934, (2007); Electron tunneling through ultrathin boron nitride crystalline barriers, et al. Nano letters 12, 1707-1710 (2012); H. , Cervenka, J.; , Watanabe, K.; , Taniguchi, T.; and Chen, Y.; Strong oxidation resistance of atomically thin boron nitride nanosheets. See ACS nano 8, 1457-1462 (2014). Within each layer of h-BN, the boron and nitrogen atoms are bound by strong covalent bonds, while the layers are held together by lip-lip interactions of the AA' stack. See, for example, Blaze, X.; , De Vita, A. , Charlier, J.; C. and Carr, R.J. in Frustration Effects and Microscopic Growth Mechanisms for BN Nanotubes. Physical Review Letters 80, 1666-1669 (1998); Boron Nitride Nanotubes and Nanosheets, et al. See ACS Nano 4, 2979-2993, (2010).

Several techniques have been used to synthesize h-BN, including micromechanical cleaving, chemical exfoliation by sonication, atomic layer deposition, and chemical vapor deposition (CVD). A CVD process by decomposition reactions of various BN precursors produces large area h-BN domains on the catalytic metal surface. For example, Li, C.; Frictional Characters of Atomically Thin Sheets. Science 328, 76-80, (2010); Warner, J.; H. , Rummeli, M.; H. , Bahamatik, A.; and Buchner, B.; Atomic Resolution Imaging and Topography of Boron Nitride Sheets Produced by Chemical Exfoliation. ACS Nano 4, 1299-1304, (2010); , Nguyen, P. , Sri Prasad, T.; S. and Berry, V.; in Electrical Transport and Network Percolation in Graphene and Boron Nitride Mixed-Platelet Structures. ACS Applied Materials & Interfaces, (2016); , Ottson, L.; M. , Hässler, P.; , Carlson, J.; O. and Larson, K.; M. Laser-Assisted Atomic Layer Deposition of Boron Nitride Thin Films. Chemical Vapor Deposition 11, 330-337, (2005); Ferguson, J.; D. , Weimer, A.; W. and George, S.; M's atomic layer deposition of boron nitride using sequential exposures of BC13 and NH3. Thin Solid Films 413, 16-25, (2002); Large Scale Growth and Characterization of Atomic Hexagonal Boron Nitride Layers. Nano Letters 10, 3209-3215, (2010); Kim, K.; K. Synthesis of monolayer hexagonal boron nitride on Cu foil using chemical vapor deposition. Nano Lett 12, 161-166, (2012); Toward the Controlled Synthesis of Hexagonal Boron Nitride Films. See ACS Nano 6, 6378-6385, (2012).

In addition, this process requires pretreatment steps such as electrochemical or chemical mechanical polishing, and high temperature annealing, respectively. Subsequent repositioning of h-BN from a metal surface to another dielectric substrate results in unintended surface waviness on the h-BN surface and additional wet/dry transfer where polymer impurities can be adsorbed. process is required. Therefore, direct, transfer-free, and scalable synthesis of h-BN films on dielectric surfaces is important for 2D electronics and industrial-scale applications. Tay, R. Y. Direct growth of nanocrystalline hexagonal boron nitride films on dielectric substrates, et al. Applied Physics Letters 106, 101901, (2015); and Wang, M.; A Platform for Large-Scale Graphene Electronics-CVD Growth of Single-Layer Graphene on CVD-Grown Hexagonal Boron Nitride. See Advanced Materials 25, 2746-2752, (2013).

Limited research has been conducted on the fabrication of amorphous, nanocrystalline, and polycrystalline h-BN films on SiO ₂ /Si surfaces by thermal and plasma-enhanced CVD. Li, Q. , Jie, Y.; , Mingyu, L. , Fay, L. and Zedon, B.; Catalyst-free growth of mono- and few-atomic-layer boron nitride sheets by chemical vapor deposition. Nanotechnology 22, 215602 (2011); and Shouno, K.; CVD-BN for Boron Diffusion in Si and Its Applications to Si Devices. Journal of The Electrochemical Society 122, 1671-1676, doi: 10.1149/1.2134107 (1975); J. and Robert,. F. Preparation and Properties of Thin Film Boron Nitride. See Journal of The Electrochemical Society 115, 423-429, doi: 10.1149/1.2411238 (1968).

In summary, the present invention provides a boron-containing gas and a nitrogen-containing gas on the front surface of a silicon nitride-containing layer at a temperature sufficient to directly deposit a layer containing hexagonal boron nitride in interfacial contact with the front surface of the silicon nitride-containing layer. It relates to a method of forming a multilayer structure comprising contacting with a gas.

The present invention is a multilayer process comprising contacting a front surface of a silicon substrate with a boron-containing gas and a nitrogen-containing gas at a temperature sufficient to directly deposit a layer comprising hexagonal boron nitride in interfacial contact with the front surface of the silicon substrate. It relates to a method of forming a structure.

The present invention further provides two primarily substantially parallel surfaces, one of which is the front surface of a single crystal semiconductor wafer and the other of which is the back surface of a single crystal semiconductor wafer. A monocrystalline semiconductor comprising a peripheral edge joining the front and back surfaces of a crystalline semiconductor wafer, a central plane between the front and back surfaces of the monocrystalline semiconductor wafer, and a bulk region between the front and back surfaces of the monocrystalline semiconductor wafer A wafer; a layer comprising silicon nitride in interfacial contact with the front surface of a monocrystalline semiconductor wafer; a layer comprising hexagonal boron nitride in interfacial contact with the layer comprising silicon nitride; and a graphene comprising in interfacial contact with the layer comprising hexagonal boron nitride. It relates to a multilayer structure comprising layers.

1 illustrates a process flow according to some embodiments of the invention; 1 illustrates a process flow according to some embodiments of the invention; 1 illustrates a process flow according to some embodiments of the invention; 1 illustrates a process flow according to some embodiments of the invention; 1 illustrates a process flow according to some embodiments of the invention;

Raman spectra corresponding to h-BN films on Si ₃ N ₄ /Si surfaces with schematic phonon mode vibrations (inset). Optical microscope image of h-BN on Si ₃ N ₄ /Si. Raman spatial mapping of h-BN on Si ₃ N ₄ /Si surface. XPS spectra of B1s (Fig. 2D) and N1s (Fig. 2E). XPS spectra of B1s (Fig. 2D) and N1s (Fig. 2E). Surface roughness histogram of height distribution measured by AFM for Si ₃ N ₄ /Si (squares) and h-BN/Si ₃ N ₄ /Si (diamonds) by a Gaussian fit to the distribution represented by the solid blue line. . 1 is a schematic diagram of the h-BN growth process on a Si ₃ N ₄ /Si surface, with the inset showing a camera image of a 1×5 cm ² area of h-BN/Si ₃ N ₄ /Si. FIG. Figure 2 shows changes in h-BN film thickness with CVD growth time on Si-based oxide and nitride substrates. Atomic MD simulations showing adsorption of ( _BN ) _{xHy active} species on _Si3N4 /Si and _SiO2 /Si surfaces. Raman spectra of h-BN formation on bare Si and O ₂ plasma treated Si. Raman spectra of h-BN formation on Si-based oxide and nitride substrates at different temperatures. Raman G-band spectra of graphene/h-BN and graphene/Si ₃ N ₄ heterostructures with spatial mapping. Raman 2D band spectra of graphene/h-BN and graphene/Si ₃ N ₄ heterostructures with spatial mapping. It exhibits electrotransport properties. Schematic of a graphene/h-BN heterostructure device, inset showing an optical microscope image (scale bar is 20 μm) of a back-gate field effect transistor. It exhibits electrotransport properties. FIG. 5 is a graph of conductance versus carrier concentration characteristics of graphene/h-BN and graphene/Si ₃ N ₄ heterostructures at 15 K and VDS=5 mV. The top inset shows the carrier mobility values for both devices at 15K. It exhibits electrotransport properties. FIG. 4 shows the change in conductance (log-log scale) with carrier concentration for graphene/h-BN and graphene/Si ₃ N ₄ heterostructures. It exhibits electrotransport properties. Figure 2 shows resistivity variation with applied bias for graphene/h-BN and graphene/Si ₃ N ₄ heterostructures at 15K and 300K. It exhibits electrotransport properties. Figure 2 shows the variation of field-effect mobility with carrier concentration for graphene/h-BN and graphene/Si ₃ N ₄ heterostructures at 15K.

According to some embodiments of the present invention, the hexagonal boron nitride deposited on the silicon-based dielectric surface is enhanced to enhance the electrical transport properties of the graphene/h-BN heterostructure. A growth mechanism is demonstrated.

In some embodiments, by exploiting the interaction of (BN) _x H _y -radicals with N-terminated ((100)Si ₃ N ₄ /Si) surfaces, the present invention provides silicon nitride on silicon surfaces. It relates to a method for nitride assisted radical deposition of hexagonal boron nitride (h-BN) on (Si ₃ N ₄ /Si) and crystallization of large area continuous thin films. In addition, the process developed here eliminates the need for metal catalysts and associated pretreatment steps for the deposition of h-BN on semiconductor wafer substrates, as well as post-synthesis transfer steps, and eliminates some electronics, It further provides tools that can potentially be used in photonic, composite, and mechanical applications. Furthermore, we directly applied the h-BN modified Si ₃ N ₄ /Si substrates to realize van der Waals heterostructures with monolayer graphene for high mobility electronics. In some embodiments, these tightly interfacially bonded van der Waals bonded heterostructures ( _graphene / _h -BN) fabricated by all CVD growth processes exhibit h - Benefit from a 3.4-fold reduction in BN roughness. This in turn reduces surface roughness scattering and charged impurity scattering for enhanced intrinsic charge carrier mobility for graphene-based heterostructures. Thus, an intrinsic charge carrier mobility enhancement of 1200 cm ² /Vs for graphene on h-BN/Si ₃ N ₄ /Si is found as opposed to 400 cm ² /Vs for graphene on Si ₃ N ₄ /Si. be Moreover, the heterostructures are clean and devoid of surface corrugations (eg, tears, creases, and wrinkles) and residual adsorbates, which are key requirements for high-speed nanoelectronics. The mechanism of direct h-BN formation on silicon (Si)-based oxide and nitride surfaces has been clearly described by controlled experiments supported by atomic molecular dynamics (MD) simulations.
I. Substrate for layer deposition

According to the method of the invention, deposition occurs on a semiconductor substrate, ie a semiconductor wafer. Referring now to FIG. 1A, an exemplary, non-limiting single crystal semiconductor wafer 100 is shown. In general, single crystal semiconductor wafer 100 includes two predominantly substantially parallel surfaces. One parallel surface is the front surface 102 of the single crystal semiconductor wafer 100 and the other parallel surface is the back surface 104 of the single crystal semiconductor wafer 100 . Single crystal semiconductor wafer 100 includes a peripheral edge 106 that joins front surface 102 and back surface 104 . Single crystal semiconductor wafer 100 includes a central axis 108 perpendicular to two predominantly substantially parallel surfaces 102 , 104 and perpendicular to the central plane defined by the midpoint between front surface 102 and back surface 104 . . A single crystal semiconductor wafer 100 includes a bulk region 110 between two predominantly substantially parallel surfaces 102 and 104 . Semiconductor wafers, e.g., silicon wafers, typically have some degree of total thickness variation (TTV), warpage, and warpage, so that the The intermediate point does not have to lie exactly in the plane. However, as a practical matter, TTV, warpage, and distortion are typically very slight to the polar approximation, so the midpoint is a virtual It can be said to fall within the center plane. Prior to any operations described herein, the front side 102 and back side 104 of single crystal semiconductor wafer 100 may be substantially identical. For convenience, the surfaces are simply referred to as "front" or "back" to generally distinguish the surface on which the method operations of the present invention are performed.

In some embodiments, monocrystalline semiconductor wafer 100 is selected from silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Including materials. A semiconductor wafer may comprise a combination of such materials, for example in a multi-layer structure. Generally, semiconductor wafers have a diameter of at least about 20 mm, more typically from about 20 mm to about 500 mm. In some embodiments, the diameter is at least about 20 mm, at least about 45 mm, at least about 90 mm, at least about 100 mm, at least about 150 mm, at least about 200 mm, at least about 250 mm, at least about 300 mm, at least about 350 mm, or even at least about 450 mm. Semiconductor wafers are about 100 micrometers to about 5000 micrometers, such as about 100 micrometers to about 1500 micrometers, such as about 250 micrometers to about 1500 micrometers, such as about 300 micrometers to about 1000 micrometers, preferably It may have a thickness in the range of about 500 microns to about 1000 microns. In some particular embodiments, the wafer thickness may be about 725 microns. In some embodiments, the wafer thickness may be about 775 microns.

In a particularly preferred embodiment, the semiconductor wafers comprise wafers sliced from monocrystalline silicon wafers sliced from monocrystalline ingots grown according to conventional Czochralski crystal growth techniques. Such methods, as well as standard silicon slicing, lapping, etching, and polishing techniques are described, for example, in F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989 and Silicon Chemical Etching (J. Grabmaier ed.) Springer-Verlag, N.G. Y. , 1982, incorporated herein by reference. Preferably, the wafer is polished and cleaned by standard methods known to those skilled in the art. For example, W. C. See O'Mara et al., Handbook of Semiconductor Silicon Technology, Noyes Publications. If desired, the wafer can be cleaned, for example, with standard SC1/SC2 solutions. In some embodiments, the single crystal silicon wafers of the present invention are sliced from single crystal ingots grown according to conventional Czochralski (“Cz”) crystal growth methods, typically at least about 150 mm, at least about A single crystal silicon wafer having a nominal diameter of 200 mm, at least about 300 mm, or at least about 450 mm. Preferably, both the single crystal silicon wafer and the single crystal silicon donor wafer have a mirror polished front surface finish free of surface defects such as scratches, large particles, and the like. The thickness of the wafer is from about 100 micrometers to about 5000 micrometers, such as from about 100 micrometers to about 1500 micrometers, such as from about 250 micrometers to about 1500 micrometers, such as from about 300 micrometers to about 1000 micrometers, preferably may vary from about 500 microns to about 1000 microns. In some particular embodiments, the wafer thickness may be about 725 microns. In some embodiments, the wafer thickness may be about 775 microns. In some particular embodiments, the wafer thickness may be about 725 microns.

In some embodiments, the single crystal semiconductor wafer includes interstitial oxygen at concentrations commonly achieved by the Czochralski growth method. In some embodiments, the single crystal semiconductor wafer includes oxygen at a concentration of about 4 PPMA to about 18 PPMA. In some embodiments, the semiconductor wafer contains oxygen at a concentration of about 10 PPMA to about 35 PPMA. In some embodiments, the single crystal semiconductor silicon wafer contains oxygen at a concentration of about 10 PPMA or less. Interstitial oxygen may be measured according to SEMI MF 1188-1105.

The resistivity of the silicon wafer is not critical to the method of the invention. However, the resistivity may vary depending on end-use requirements. With this in mind, the wafer may be heavily doped, semi-insulating, or have a doping profile in between. Single crystal semiconductor wafer 100 may have any resistivity obtained by the Czochralski or Float Zone method. Therefore, resistivity can vary from sub-milliohms to mega-ohms or higher. In some embodiments, single crystal semiconductor wafer 100 includes a p-type dopant or an n-type dopant. Suitable dopants include boron (p-type), gallium (p-type), phosphorous (n-type), antimony (n-type), and arsenic (n-type). Dopant concentrations are selected based on the desired resistivity of the wafer. In some embodiments, the single crystal semiconductor wafer includes a p-type dopant. In some embodiments, the single crystal semiconductor wafer is a single crystal silicon wafer that includes a p-type dopant such as boron.

In some embodiments, the single crystal semiconductor wafer 100 has a relatively low minimum bulk resistivity, such as less than about 100 ohm-cm, less than about 50 ohm-cm, less than about 1 ohm-cm, about 0.1 ohm-cm. cm, or even less than about 0.01 ohm-cm. In some embodiments, single crystal semiconductor wafer 100 has a relatively low minimum bulk resistivity, eg, less than about 100 ohm-cm, or between about 1 ohm-cm and about 100 ohm-cm. Low resistivity wafers may include electrically active dopants such as boron (p-type), gallium (p-type), phosphorous (n-type), antimony (n-type), and arsenic (n-type). The choice of substrate resistivity depends on the application (e.g., lower resistivity is preferred if the substrate is used as a back gate), but should not affect the growth of the hBN and graphene layers.

In some embodiments, single crystal semiconductor wafer 100 has a relatively high minimum bulk resistivity. High resistivity wafers are commonly sliced from single crystal ingots grown by the Czochralski or Float Zone method. High resistivity wafers typically have very low concentrations of boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorous (n-type), antimony (n-type), and It may also include electrically active dopants such as arsenic (p-type). Cz-grown silicon wafers may be subjected to thermal annealing at temperatures in the range of about 600° C. to about 1000° C. to quench thermal donors caused by oxygen incorporated during crystal growth. In some embodiments, the single crystal semiconductor wafer is at least 100 ohm-cm, or even at least about 500 ohm-cm, such as from about 100 ohm-cm to about 100,000 ohm-cm, or from about 500 ohm-cm about 100,000 ohm-cm, or about 1000 ohm-cm to about 100,000 ohm-cm, or about 500 ohm-cm to about 10,000 ohm-cm, or about 750 ohm-cm to about 10,000 ohm-cm -cm, from about 1000 ohm-cm to about 10,000 ohm-cm, from about 1000 ohm-cm to about 6000 ohm-cm, from about 2000 ohm-cm to about 10,000 ohm-cm, from about 3000 ohm-cm to about It has a minimum bulk resistivity of 10,000 ohm-cm, or from about 3000 ohm-cm to about 5,000 ohm-cm. In some preferred embodiments, the single crystal semiconductor substrate has a bulk resistivity between about 1000 ohm-cm and about 6,000 ohm-cm. In some preferred embodiments, the single crystal semiconductor substrate comprises an electrically active dopant selected from the group consisting of boron, aluminum, gallium, indium, and any combination thereof. In some preferred embodiments, the single crystal semiconductor wafer has less than about 2×10 ¹³ atoms/cm ³ , less than about 1×10 ¹³ atoms/cm ³ , such as less than about 5×10 ¹² atoms/cm ³ , or about It contains boron, which can be present in concentrations less than 1×10 ¹² atoms/cm ³ . Methods for preparing high resistivity wafers are known in the art and such high resistivity wafers are available from SunEdison Semiconductor Ltd. (St. Peters, MO; formerly MEMC Electronic Materials, Inc.).

Single crystal semiconductor wafer 100 may include single crystal silicon. Single crystal semiconductor wafer 100 may have, for example, either a (100), (110), or (111) crystallographic orientation, and the choice of crystallographic orientation may be dictated by the end use of the structure. .

Referring now to FIG. 1B, one or more of the major surfaces of the semiconductor substrate 100 may be modified with a dielectric layer 200 in some embodiments of the method of the present invention. Dielectric layer 200 may include silicon dioxide, silicon nitride, silicon oxynitride, or a combination of silicon dioxide, silicon nitride, or silicon oxynitride layers, ie, multiple layers.

In some embodiments, semiconductor substrate 100 comprises a silicon wafer with its front layer oxidized. In a preferred embodiment, the semiconductor substrate 100 comprises a silicon wafer or a silicon wafer whose front side is preferably oxidized such that the front layer of the silicon wafer comprises a dielectric layer 200 comprising silicon dioxide (SiO ₂ ). In some embodiments, the silicon dioxide layer is about 10 nm to about 1000 nm, about 30 nm to about 1000 nm, about 50 nm to about 500 nm, preferably about 50 nm to about 300 nm thick, such as about 90 nm to about 300 nm thick. , or from about 90 nm to about 200 nanometers thick. The front side of the silicon wafer can be thermally oxidized by wet oxidation or dry oxidation as known in the art. In some embodiments, the front and back sides of the wafer can be thermally oxidized in a furnace such as ASM A400 or ASM A400XT. Thermal oxidation generally occurs at elevated temperatures, such as from about 800°C to about 1200°C. Oxidation may be wet (eg, in water vapor, such as ultrapure steam for oxidation, ambient atmosphere) or dry (eg, in an oxygen gas atmosphere). Optionally, the ambient atmosphere may contain hydrochloric acid, for example up to about 10% by volume, to remove surface impurities during oxidation.

In some embodiments, the oxide layer is relatively thin, such as from about 5 Angstroms to about 25 Angstroms, such as from about 10 Angstroms to about 15 Angstroms. Thin oxide layers can be obtained on both sides of the semiconductor wafer by exposure to standard cleaning solutions such as SC1/SC2 cleaning solutions. In some embodiments, the SC1 solution is 5 parts deionized water, 1 part aqueous NH ₄ OH (ammonium hydroxide, 29 wt% NH ₃ ), and 1 part aqueous H ₂ O ₂ (peroxide hydrogen, 30%). In some embodiments, the handle wafer may be oxidized by exposure to an aqueous solution containing an oxidizing agent such as SC2 solution. In some embodiments, the SC2 solution comprises 5 parts deionized water, 1 part aqueous HCl (hydrochloric acid, 39% by weight), and 1 part _{aqueous H2O2} (hydrogen peroxide, 30%). .

In some embodiments, semiconductor substrate 100 may include dielectric layer 200 comprising silicon nitride. In some embodiments, semiconductor substrate 100 comprises a bare silicon wafer on which a silicon nitride layer is deposited. In some embodiments, the semiconductor substrate 100 comprises a silicon wafer on which a silicon nitride layer is deposited after its front layer has been oxidized as described above. A silicon nitride layer may be deposited over the exposed silicon or silicon dioxide layer as silicon nitride advantageously forms a barrier layer to reduce the diffusion of metal atoms, such as nickel, into the silicon oxide layer. In some embodiments, the thickness of the silicon nitride layer can range from about 10 nm to about 1000 nm, from about 30 nm to about 1000 nm, or from about 50 nanometers to about 1000 nanometers. In some embodiments, the thickness of the silicon nitride layer can range from about 50 nanometers to about 500 nanometers. In some embodiments, the thickness of the silicon nitride layer can range from about 70 nanometers to about 250 nanometers. The thickness of the silicon nitride layer is a trade-off between device performance, where thinner layers are preferred, and effective barrier to prevent inter-diffusion of impurities into the semiconductor substrate, where thicker layers are preferred. It is determined. Silicon nitride may be deposited on the surface of a silicon or silicon oxide layer by contacting the substrate with an atmosphere of nitrogen and/or ammonia at elevated temperatures. For example, the semiconductor may be exposed to nitrogen gas or ammonia at temperatures ranging from about 700.degree. C. to about 1300.degree.

In some embodiments, silicon nitride is formed by chemical vapor deposition at approximately 800 degrees Celsius. In some embodiments, silicon nitride may be deposited by plasma enhanced chemical vapor deposition. Plasma surface activation tools are commercially available tools, such as those available from the EV Group, such as the EVG® 810LT Low Temperature Plasma Activation System. Common requirements for plasma-enhanced CVD chambers include various electrode designs, power generation electronics, impedance matching networks for transferring power to gas loads, mass flow controllers for input gases, and pressure control systems. A typical system is a vertical tube reactor powered by an inductively coupled RF source. A single crystal semiconductor handle wafer 100 is loaded into the chamber and placed on a heated support chamber. The chamber is evacuated and backfilled to sub-atmospheric pressure using a nitrogen gas source in a carrier gas such as argon to generate a plasma. Ammonia and/or nitrogen and/or nitric oxide (NO) and/or nitrous oxide (N ₂ O) gases are preferred source gases for plasma nitride processing. For depositing silicon nitride plasma films, suitable silicon precursors are methylsilane, silicon tetrahydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane ( _{SiH2CI2 )} , trichlorosilane. (SiHCl ₃ ), silicon tetrachloride (SiCI ₄ ), tetraethyl orthosilicate (Si(OCH ₂ CH ₃ ) ₄ ) and the like. The flow ratio of the gaseous silicon precursor to the gaseous oxygen and/or nitrogen precursors can be from about 1/200 to about 1/50, such as about 1/100.

In some embodiments, PECVD deposition, particularly PECVD deposition of silicon nitride layers, can be enhanced by microwave excitation. Microwave-enhanced PECVD is advantageous because it allows the discharge region to be separated from the reaction region, reducing damage to the deposited layer. Precursor compounds, such as silane and ammonia, are excited by a microwave discharge at microwaves of, for example, 2.45 GHz, and the excited gas diffuses from the plasma chamber into the reaction chamber. Such films may be tailored to be at or near stoichiometric, eg, Si ₃ N ₄ .

In some embodiments, deposition may be accomplished by low pressure chemical vapor deposition. The LPCVD process can be performed in a cold or hot wall quartz tube reactor. Hot-wall furnaces enable high throughput by enabling batch processing. They also provide good thermal uniformity, resulting in uniform films. A disadvantage of hot wall systems is that deposition also occurs on the furnace walls, resulting in frequent cleaning or replacement of the tubes to avoid flaking of deposited material and subsequent particle contamination. Cold wall reactors are less maintainable as films do not build up on the reactor walls. Low pressure chemical vapor silicon nitride may be formed in low pressure chemical vapor deposition at pressures from about 0.01 Torr to about 100 Torr, such as from about 0.1 Torr to about 1 Torr. The temperature can range from 425°C to 900°C. Suitable precursors include those listed for PECVD.

Silicon nitride produced from PECVD is structurally different from silicon nitride deposited according to conventional chemical or physical vapor deposition techniques. Conventional CVD or PVD deposition generally results in _a silicon nitride layer with a stoichiometry of _Si3N4 . The plasma process can be controlled to deposit a film having _a composition such as _SixNyHz depending on the ratio of injected reactant gases, power levels, wafer temperature, and overall reactor pressure _. can be done. Pathways in plasma systems exist to form Si—N, Si═N, and Si≡N bonds. This is due to _the fact that plasma energy is a hammer producing _{Six Hz} and Ny _Hz species. For example, the refractive index and optical gap change dramatically with the Si/N ratio. At higher silane concentrations, the films can become Si-rich and reach a refractive index of up to 3.0 (compared to 2 for LPCVD).

In some embodiments, the semiconductor substrate 100 including the dielectric layer 200 is cleaned prior to depositing the cobalt-containing layer, eg, to remove organics or other impurities. A suitable _cleaning liquid is a piranha solution comprising _H2SO4 (concentrated) and _H2O2 (30% solution), typically in _a 3:1 ratio, but other ratios such as 4:1 or 7:1 is preferred. The washing period is preferably from about 15 minutes to about 2 hours.
II. Synthesis of hexagonal boron nitride

According to some embodiments of the methods of the present invention, referring to FIG. 1C, layer 300 comprising hexagonal boron nitride is deposited on single crystal semiconductor wafer substrate 100 (eg, exposed single crystal in the absence of dielectric layer 200). silicon substrate) or directly on the front side of a dielectric layer 200, for example silicon nitride, on the front side of a single crystal semiconductor wafer substrate 100; The method of the present invention deposits a layer 300 comprising hexagonal boron nitride on the front side of a single crystal semiconductor wafer substrate 100 or dielectric layer 200 without the use of a metal catalyst. In some embodiments, single crystal semiconductor wafer substrate 100 is exposed or unmodified with a dielectric layer. In some embodiments, dielectric layer 200 comprises one or more insulating layers comprising materials selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and any combination thereof, for example, in multiple layers. include. In some embodiments, the dielectric layer is at least about 1 nanometer thick, such as from about 1 nanometer to about 10 nanometers, such as from about 10 nanometers to about 10,000 nanometers, from about 10 nanometers to about 5 nanometers. ,000 nanometers, 50 nanometers to about 400 nanometers, or about 100 nanometers to about 400 nanometers, such as about 50 nanometers, 100 nanometers, or 200 nanometers. In some preferred embodiments, dielectric layer 200 comprises silicon nitride and layer 300 comprising hexagonal boron nitride is deposited directly on the silicon nitride. Preferably, dielectric layer 200 comprising silicon nitride is cleaned of surface oxides before being deposited, for example in a piranha solution.

Materials for deposition onto dielectric layer 200 include silicon nitride and may be deposited by vapor deposition or vapor deposition techniques. For example, layer 300 comprising hexagonal boron nitride may be formed by metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or molecular beam vapor deposition. It may also be deposited using epitaxy (MBE). In some preferred embodiments, layer 300 comprising hexagonal boron nitride may be deposited by low pressure chemical vapor deposition (LPCVD). A suitable instrument is the MTI OTF-1200X. Generally, the boron and nitrogen sources are gaseous or vapor at the deposition temperature. Suitable boron sources include diborane (B ₂ H ₆ ), trichloroborane (BCI ₃ ), trifluoroborane (BF ₃ ), and borane in tetrahydrofuran (THF) (THF-BH ₃ ). Suitable nitrogen sources include nitrogen, or hydrazine ( _{N2H4 )} , or ammonia. If separate boron and nitrogen sources are used, preferably the gas flow rates to the CVD chamber are such that the molar ratio of B:N is between about 1.3:1 and 1:1.3, such as about 1.2. :1 to about 1:1.2, or about 1.1:1 to about 1:1.1, such as about 1:1. In some embodiments, gases may include nitrogen and hydrogen. In some embodiments, the gas is both boron and nitrogen, eg, borazine (B ₃ H6N ₃ ), trichloroborazine (eg, 2,4,6-trichloroborazine, H _{3 )} , preferably in a 1:1 ratio. B ₃ CI ₃ N ₃ ), aminoborane (BH ₂ NH ₂ ), ammonia borane (BH3-NH ₃ ), ammonia borane complex (H ₃ N—BH ₃ ), borazine (B ₃ N ₃ H ₆ ), diborane. Ammoniades [(NH ₃ ) ₂ BH ₂ ] ⁺ [BH ₄ ] ⁻ , and BN polymer complexes (polyborazylene). In addition to these carriers, the gaseous atmosphere may contain inert carrier gases such as helium and argon. Hydrogen with a suitable flow rate can also be the carrier gas.

LPCVD is performed by heating an optionally cleaned substrate to a suitable temperature within a CVD chamber, which is, for example, an ultra-high vacuum environment (eg, from about 10 ⁻³ to about 10 −3 ⁾ . ⁶ torr) or at least about 800°C, such as at least about 900°C, at least about 1000°C, such as at least about 1100°C in an inert gas such as argon or hydrogen. A source gas is then transported into the chamber. The solid source gas may optionally be heated to vaporize or sublimate the source gas, for example by heating ammonia borane to a temperature above 100°C. The liquid source gas may be bubbled into the chamber with carrier gases (Ar and _H2 ). Deposition of hexagonal boron nitride can occur at reduced pressures, such as less than about 250 torr, or pressures from about 10 ⁻⁶ torr to about 10 torr. Reaction times can be from about 5 minutes to about 72 hours, such as from about 5 minutes to 120 minutes, such as from about 15 minutes to about 60 minutes, or from about 1 hour to about 72 hours. After the desired deposition period, the substrate is slowly cooled, eg, at a maximum rate of 40° C./minute, or rapidly cooled, eg, at a rate of at least about 40° C./minute or about 100° C./minute. In some embodiments, a single monolayer of hexagonal boron nitride is deposited. In some embodiments, the plurality of layers of monatomic hexagonal boron nitride is, for example, at least two layers of monatomic hexagonal boron nitride, such as 2 to about 100 layers of monatomic hexagonal boron nitride, or 2 to about 50 layers of crystalline boron nitride, or 3 to about 50 layers of monatomic hexagonal boron nitride. Hexagonal boron nitride has a B:N molar ratio of about 1.3:1 to 1:1.3, such as about 1.2:1 to about 1:1.2, or about 1.1:1 to Contains equimolar concentrations of boron and nitrogen such as about 1:1.1.

Referring to the examples, in one embodiment h-BN synthesis on Si ₃ N ₄ /Si was performed via a low pressure CVD (LPCVD) system. LPCVD is a preferred deposition technique because growth is limited by surface reactions and film formation is independent of substrate or gas flow effect geometry. The quality and uniformity of h-BN films formed by nitride-assisted LPCVD on Si ₃ N ₄ /Si substrates can be confirmed by confocal Raman spectroscopy, which corresponds to the E _2g phonon vibrational mode at 1372 cm ⁻¹ . A characteristic peak is shown. Referring to FIG. 2A, the inset shows atomic vibrations. The continuity and uniformity of h-BN films are important criteria for further graphene electronics, clearly informed in optical microscopy (OM) images (see Fig. 2B) and Raman spatial mapping (see Fig. 2C), indicating that the circular The region marked with corresponds to the consistent Raman spectrum of FIG. 2A. The upper left circles in FIGS. 2B and 2C correspond to the lower curve in FIG. 2A. The central circles in FIGS. 2B and 2C correspond to the upper curves in FIG. 2A. The lower right circles in FIGS. 2B and 2C correspond to the central curve in FIG. 2A. Homogeneous color contrast of both OM images and Raman mapping clearly indicate the formation of continuous and uniform h-BN films on Si ₃ N ₄ /Si substrates. To further confirm the formation of h-BN films on Si ₃ N ₄ /Si substrates, the elemental composition and stoichiometry were analyzed by X-ray photoelectron spectroscopy (XPS). Figures 2D and 2E show high-resolution XPS spectra of boron (B) 1s and nitrogen (N) 1s, respectively, fitted by a Gaussian function. The B1s spectrum consists of two peaks located at bond energies (BE) of 191.09 eV and 192.39 eV, which correspond to internal BN bonding and BN bonding of the edge, respectively. The N1s signal appears at a BE of 398.87 eV and is due to BN bonding. Furthermore, the atomic concentration ratio of N and B is 1:1.11±0.09, suggesting that the composition of the B and N elements in h-BN is almost equal. there is Furthermore, the h-BN surface is atomically smooth, so it is important to probe the surface. FIG. 2F shows roughness histograms fitted by a Gaussian distribution with a standard deviation of 0.66 nm for the h-BN-modified Si ₃ N ₄ /Si surface and a standard deviation of 2.22 nm for the Si ₃ N ₄ /Si surface. , which means that the surface smoothness of the h-BN-modified Si ₃ N ₄ /Si was improved by 3.4 times. This is smaller than the standard deviation value of 1.37 nm for the h-BN modified SiO ₂ surface and 8.59 nm for the SiO ₂ surface. Befla, S. , Nguyen, P. , Che, S. , DeVerma, R. and Berry, V.; Large-Area, Transfer-Free, Oxide-Assisted Synthesis of Hexagonal Boron Nitride Films and Their Heterostructures with MoS2 and WS2. See Journal of the American Chemical Society 137, 13060-13065, (2015).

Studies on h-BN formation on metal surfaces show growth kinetics (based on surface mediation of Cu and segregation of Ni and Fe). Kim, S. M. Synthesis of large-area multilayerer hexagonal boron nitride for high material performance. See Nat Commun 6, (2015). However, a clear understanding of the h-BN growth mechanism is lacking, especially on non-metallic surfaces such as: Si surfaces and Si-based dielectric surfaces (Si ₃ N ₄ /Si and SiO ₂ /Si). Here an attempt is made to understand the growth kinetics of h-BN films on Si ₃ N ₄ /Si and SiO ₂ /Si surfaces, which are well supported by atomic molecular dynamics (MD) simulations. there is A schematic of the h-BN growth mechanism on the Si ₃ N ₄ /Si surface is shown in FIG. 3A. Nominally, CVD growth of h-BN is processed through the following five basic steps: (1) solid ammonia borane (AB) is sublimed at about 100° C. and a hydrogen (H ₂ ) gas flow (30 sccm) is applied; ) into the reaction zone. (2) _The AB complex is thermally decomposed into _H2 , aminoborane ( _BH2NH2 ), and borazine (HBNH) ₃ in the reaction zone below the growth temperature. (3) (HBNH) ₃ and (BH ₂ NH ₂ ) molecules undergo thermal dehydrogenation and cross-linking reactions with B—H and NH groups in adjacent chains at 120° C. to 300° C. to form active species (BN ) _x H _y . This active species (BN) _x H _y is further dehydrogenated at 700°C to 1100°C. Paffett, M. T. , Simonson, R. J. , Papin, P.; and Payne, R.; T. Borazine adsorption and decomposition at Pt(111) and Ru(001) surfaces. Surface Science 232, 86-296, (1990); I, Beck, J.; S. , Lynch, A.; T. , Remsen, E. E. and Sneddon, L.; G. in Thermally induced borazine dehydropolymerization reactions. Synthesis and ceramic conversion reactions of a new high-yield polymeric precursor to boron nitride. See Chemistry of Materials 2, 96-97, (1990). (4) These active species (BN) _x H _y are adsorbed to the active sites of the Si-based substrate. (5) If the attachment rate of the active species to the active sites on the Si-based substrate surface is faster than its detachment rate, then the active species (BN) _{x H xH} Stitch _{the y-} species h-BN domain.

（３）活性種（ＢＮ）_ｘＨ_ｙ形成：

（４）表面吸着：

Ｓは、Ｓｉ系表面の活性部位である。
（５）表面反応：
これらの活性種、（ＢＮ）_ｘＨ_ｙ－ＳがＳｉ系基板の表面で反応する速度は、以下によって提供される：

Furthermore, _the ^left inset _of FIG. It reflects the fact that it is possible without any associated processes. The key steps above can be summarized as follows:
(1, 2) Gas phase dissociation:

(3) Active species (BN) _x H _y formation:

(4) Surface adsorption:

S is an active site on the Si-based surface.
(5) Surface reaction:
The rate at which these active species, (BN) _x H _y -S, react at the surface of Si-based substrates is provided by:

として定義される。

この微分方程式の解は、次の通りである：

During the CVD synthesis of h-BN at high temperatures, the growth of h-BN occurs very rapidly due to (i) the dependence of the surface reaction rate on the Arrhenius term ( _ks ~ exp(-E _A /RT), and (ii) dominated by the surface adsorption process (k _a <<k _s ) as the active species are poorly adsorbed on the surface (k ∼ _l /sqrt(T). These two processes occur in succession , so at steady state the total flux is
r _process = r _adsorption = r _{surface reaction}

defined as

The solution of this differential equation is:

Where T _hBN is the thickness of the h-BN film, T _s is the characteristic thickness of the h-BN film (i.e., the maximum thickness of the h-BN film) and t is the growth time. , τ is the characteristic time of adsorption. The data fit well with the derived equation (1) where the characteristic thicknesses of h-BN on Si ₃ N ₄ /Si and SiO ₂ /Si at the given growth conditions are 5 and 20 nm, respectively. (solid line in FIG. 3B). This characteristic thickness, T _s , depends on the density of active sites (SiO ₂ /Si surfaces have four times more active sites than Si ₃ N ₄ /Si surfaces). Furthermore, the characteristic times indicate that adsorption of active species as (BN) _xHy favors the _SiO2 /Si _surface over the _Si3N4 /Si surface _.

Models derived for the growth kinetics of h-BN films on SiO ₂ /Si and Si ₃ N ₄ /Si surfaces indicate that the film thickness on the substrate depends on the adsorption of reactants from the gas phase to the substrate. It is based on the assumption that The model also assumes that hydrogen evolution and hexagonal boron nitride formation are the final steps in the growth process. To understand the effect of the substrate on reactant adsorption, we performed atomic molecular dynamics simulations using the open-source LAMMPS package. Plimpton, S.; Fast Parallel Algorithms for Short-Range Molecular Dynamics. See Journal of Computational Physics 117, 1-19, (1995). To model the adsorption of borazine molecules on surfaces, we used the total atom interaction potential. Van der Waals interactions are modeled using the 6-12 Lennard Jones potential and electrostatic potentials are modeled using Coulomb's law. The adsorption of borazine molecules on _SiO2 /Si and _Si3N4 /Si surfaces was studied using NVT ensemble simulations at a temperature _of 1000K. In the entire simulation, only the borazine molecule remains mobile, and the molecule is treated as _a rigid body, and the force on each molecule is the sum of the forces of all 12 atoms in the molecule ( _B3N3H6 ) _. is. The simulation was performed for a total time of 500 picoseconds using a time step of 0.25 femtoseconds. Initially, borazine molecules are attracted toward the substrate by long-range electrostatic forces, and once they are on the substrate, short-range van der Waals and Coulomb forces keep them attached to the substrate. Due to the polar nature of the borazine molecules, we observed that initially in the gas phase they tended to form planar 2D clusters. A few molecules that do not form clusters in the gas phase are adsorbed onto the substrate. We found that four borazine molecules were adsorbed on the _SiO2 /Si after 12 ps, whereas only one borazine molecule was adsorbed on the _Si3N4 /Si surface _. Observed. The higher adsorption for _SiO2 /Si compared to _Si3N4 /Si is explained by the surface charge on the top layer of the substrates, even though both substrates maintain overall charge _neutrality . be able to. The (001) plane (top layer) of SiO ₂ /Si consists only of dangling oxygen atoms, and the silicon atoms are 1.24 Å smaller than the surface oxygen atoms. See FIG. 3C. Therefore, the top layer of the _SiO2 /Si substrate is negatively charged. On the other hand, the (001) plane (top layer) of the Si ₃ N ₄ /Si substrate has the planar arrangement of both Si and N atoms, and the total charge of the top layer is zero. See FIG. 3C. _Negatively charged dangling oxygen atoms in _SiO2 /Si tend to adsorb more borazine molecules compared to planar and neutral surfaces of _Si3N4 /Si. The planar clusters that eventually form in the gas phase are adsorbed onto the substrate. For both substrates we observed clusters attaching to already adsorbed borazine molecules. Since the SiO ₂ /Si substrate adsorbs more borazine molecules, the clusters have more sites attached on the SiO ₂ /Si substrate compared to the Si ₃ N ₄ /Si substrate. It was also observed that the total adsorption time of borazine molecules from the gas phase to the substrate was about 75 ps and ₂₀₀ ps for _SiO2 /Si and _Si3N4 /Si, respectively. Adsorbed clusters cover the surface and eventually undergo dehydrogenation to form h-BN as predicted by the proposed growth model.

Experimental validation using the proposed growth model and subsequent MD simulations suggest that surface adsorption is the rate-limiting step in h-BN nucleation on Si-based dielectric surfaces. To further confirm the adsorption kinetics-induced mechanism, we designed an innovative experimental setup to grow h-BN on exposed Si and O _plasma- treated Si while maintaining the same CVD conditions. As expected, higher Raman intensities imply thicker films, so _O plasma treatment, in contrast to exposed Si surfaces, as evidenced by the increase in Raman intensity for the E _2g peak of h-BN. The growth rate of h-BN is higher on the annealed Si surface (Fig. 3D). Gorbachev, R. V. Hunting for Monolayer Boron Nitride: Optical and Raman Signatures. See Small 7, 465-468, (2011). Thus, the process is clearly assisted adsorption kinetics as the _O2 plasma treated Si surface exhibits more active sites (Cs) compared to the bare Si surface. Furthermore, the effect of growth temperature on h-BN formation on SiO ₂ /Si and Si ₃ N ₄ /Si surfaces was investigated by Raman spectroscopy and shown in FIG. 3E. Metal catalyst surfaces nucleate h-BN films at a _temperature of 750.degree. C., while h-BN formation on _SiO.sub.2 /Si and _{Si.sub.3N.sub.4} /Si surfaces occurs at about 900.degree. Wang, L. Monolayer Hexagonal Boron Nitride Films with Large Domain Size and Clean Interface for Enhancing the Mobility of Graphene-Based Field-Effect Transistors. See Advanced Materials 26, 1559-1564, (2014). This is consistent with previous reports of nanocrystalline h-BN formation directly on SiO ₂ /Si substrates. However, no h-BN growth or mechanism on Si ₃ N ₄ /Si surfaces has been reported, although there are reports of powdered Si ₃ N ₄ /hBN complexes. Kusunose, T.; , Sekino, T.; , Choa, Y. H. and Niihara, K.; Fabrication and Microstructure of Silicon Nitride/Boron Nitride Nanocomposites. See Journal of the American Ceramic Society 85, 2678-2688, (2002). Figure 3E shows that h-BN formation does not occur below 800°C. Since high Raman intensity implies thicker h-BN, Si ₃ N ₄ /Si surfaces adsorb less (BN) _x H _y -radicals and thinner h-BN compared to SiO ₂ /Si surfaces. - allows the formation of BN films; The small peak at about 1450 cm ⁻¹ in FIG. 3E demonstrates the 3rd order transverse optical phonon mode of silicon since the underlying substrate is Si ₃ N ₄ /Si. Spitzli, P. G., J. -H. F. , , S. R. , ,E. G. and Plower, a. S. Nano-Raman spectroscopy of silicon surfaces, (2010). Furthermore, the mechanism behind the difference in h-BN growth kinetics on SiO ₂ /Si and Si ₃ N ₄ /Si surfaces can be understood by detailed surface analysis. A more recent report explains that the Si ₃ N ₄ /Si surface is more hydrophobic than the SiO ₂ /Si surface, which suggests that the SiO ₂ /Si surface favors h-BN formation. , clearly demonstrating that it nucleates a thicker but rougher film in contrast to a thinner and smoother film on the Si ₃ N ₄ /Si surface. Agarwal, D. K. , Maheshwari, N. , Mukerji, S.; and Rao, V.; R. Asymmetric immobilization of antibodies on a piezo-resistive micro-cantilever surface. See RSC Advances 6, 17606-17616, (2016).

To test the potential of h-BN directly for nanoelectronics, single-layer graphene (MLG) was grown on h-BN/Si ₃ N ₄ /Si and Si ₃ N ₄ /Si substrates. transcribed. To understand the charge impurity effects of h-BN and Si ₃ N ₄ /Si substrates on graphene films, we used the G-band position, the full width at half maximum of the G-band (FWHM(G)), the 2D band position , and the doping-dependent parameters of the ratio of the intensities of the 2D and G bands (I _2D /I _G ) by confocal Raman spectroscopy. Das A. et al., Monitoring dopants by Raman scattering in an electrochemically top-gated graphene transistor. See Nat Nano 3, 210-215, (2008). In FIG. 4A, the G peak of graphene on h-BN (denoted as G/h-BN) and the G peak of graphene on Si ₃ N ₄ /Si (denoted as G/SiN) are 1581.5 cm −1 , respectively ^. predominantly centrally located at ¹ and 1586.8 cm ⁻¹ . The calculated G-band FWHM decreases from 26.5 cm ⁻¹ (h-BN substrate) to 23.6 cm ⁻¹ (Si ₃ N/Si substrate). Furthermore, in FIG. 4B, the 2D bands of G/h-BN and G/SiN are shown at 2673.3 cm ⁻¹ and 2683.4 cm ⁻¹ respectively. Furthermore, the ratio I _2D /I _G was found to increase from 2.3 for G/SiN to 3 for G/h-BN. Observation of the softening of the G and 2D bands indicates that the sharpening of the G-peak FWHM in addition to the high I _2D /I _G is significant for graphene on hBN substrates compared to graphene on Si ₃ N ₄ /Si counterparts. clearly shows the low-charged impurities of In our device configuration, such charge impurities originate from (i) photoresist residue (during the fabrication of transistor devices described below) and (ii) electron-hole paddling (bottom h-BN substrate). obtain. Since the processes _for device fabrication on hBN and _Si3N4 /Si substrates were similar and the same graphene films were used, in our measurements the charge donating impurity (n*) from the underlying substrate is important. clearly play a role. Shu, J. Scanning tunneling microscopy and spectroscopy of ultra-flat graphene on hexagonal boron nitride. Nat Mater 10, 282-285, (2011); , Brahl, V.; W. , Girit, C, Zettle, A.; and Clomie, M.; F. Origin of spatial charge inhomogeneity in graphene. See NatPhys 5, 722-726, (2009). Raman spectra of the G and 2D peaks were averaged over the entire area of the graphene device and fitted with a Lorentzian curve.

Charge heterogeneity not only affects the Raman scattering parameters as discussed, but is also the dominant cause of electron scattering in G/h-BN and G/SiN heterostructure devices. A typical schematic of a G/h-BN back-gate field effect transistor with an optical image of the device geometry (27 μm×7.5 μm) with Cr/Au (15/95 nm) as source and drain contacts in the inset. It is shown in FIG. 5A. Our directly grown h-BN substrate platform, characterized by small charge variability, compared to high-k dielectric substrates (Si ₃ N ₄ /Si in our work), graphene It promises to provide a competitive advantage in enhancing charge carrier mobility in devices. Therefore, both devices were designed with the same contact materials (Cr/Au) and similar device processing, and we can infer the same effect of contact resistance on the electrical performance of both devices. It is important to note that you can It is clearly reported in Fig. 5(B) that the conductance is strongly nonlinear in carrier density, which is due to the low carrier density where scattering is dominated by charge impurities and the large Crossover with carrier density is shown. Nomura, K. and McDonald, A.; H. Quantum Transport of Massless Dirac Fermions. See Physical Review Letters 98, 076602 (2007). The data obtained (Fig. 5B) can be fit to a self-consistent Boltzmann equation for diffusive transport that includes both long-range and short-range scattering:

where μ _c is the density-independent mobility due to charged impurity Coulombic (long-range) scattering, p _s is the resistivity contribution from short-range scattering, and σ _res is the charge-neutral point is the residual conductivity. fan, E. H. , Adam, S.; and Salma, S.; D. Carrier Transport in Two-Dimensional Graphene Layers. See Physical Review Letters 98, 186806 (2007). As shown in the inset of FIG. 5B, the calculated mobility μ _c is 1200 cm ² V ⁻¹ s ⁻¹ for the G/h-BN device (3.5 times that of G/SiN). expensive). The enhanced mobility of the G/h-BN system can be elucidated by two main mechanisms: (i) Coulomb scattering near the charge neutral point and (ii) electron-phonon scattering at high carrier densities. can. In the first mechanism (Coulomb scattering), the minimum conductivity of G/h-BN devices (σ _min =7e ² /h) is 3.5 times higher than that of G/SiN devices (σ _min =2e ² /h ), which means that the charge impurities located in the h-BN substrate are about 12 times less than in the Si ₃ N ₄ /Si substrate. Furthermore, the charge inhomogeneity point (n*) is the inflection point where Coulomb scattering becomes dominant and vice versa. At low charge heterogeneity, the conductance peak of G/h-BN is narrower than that of G/SiN due to electron-hole puddle formation at low carrier concentrations. The corresponding concentration can therefore be estimated by plotting the low temperature conductivity (σ) against the carrier density (n) on a logarithmic scale as shown in FIG. 5C. Cout, N. J. G. Random Strain Fluctuations as Dominant Disorder Source for High-Quality On-Substrate Graphene Devices. Physical Review X 4, 041019 (2014); et al., Ultrahigh-mobility graphene devices from chemical vapor deposition on reusable copper. See Science Advances 1, (2015). In our heterostructure device, n* extracted for G/h-BN and G/SiN at 1.1×10 ¹² cm ⁻² and 1.6×10 ¹² cm ⁻² are, respectively, It shows a more homogenous potential background of h-BN substrate than Si ₃ N ₄ /Si substrate counterpart. These observations are in good agreement with our Raman spectroscopy data and the results of some previous studies. fan, E. H. , Adam, S.; and Salma, S.; D. Carrier Transport in Two-Dimensional Graphene Layers. See Physical Review Letters 98, 186806 (2007). Another contribution to the mobility enhancement in our G/hBN device is due to electron-phonon scattering, which is assumed to be a significant contribution in our sample. Katznelson, M. I. and Geim, A.; K, Electron scattering on microscopic corruptions in graphene. See Philosophical Transactions of the Royal Society of London A: Mathematical, Physical and Engineering Sciences 366, 195-204, (2008).

In the inset of FIG. 5C, the short-range resistivity (p _s ) is calculated to be 600 Ω/sq and 1800 Ω/sq for G/h-BN and G/SiN, respectively. The origin of the short-range resistivity is still a matter of debate, but in our samples, for example: (i) lattice or point defects in graphene films, (ii) bending excited inside graphene ripples (out-of-plane) phonons, and (iii) surface-polarized optical phonons of the underlying substrate. Morozov, S. V. Giant Intrinsic Carrier Mobilities in Graphene and Its Bilayer. Physical Review Letters 100, 016602 (2008); Ishigami, M.; , Chen, JH. , Karen, W.; G, Fuller, M.; S. and Williams, E. D. Atomic Structure of Graphene on SiO2. Nano Letters 7, 1643-1648, (2007); H. and Das Salma, S.M. Acoustic phonon scattering limited carrier mobility in two-dimensional extrinsic graphene. See Physical Review B 77, 115449 (2008). The first factor is speculated to have negligible effect as our Raman data show high quality transferred graphene on h-BN and Si ₃ N ₄ . On the other hand, a smooth h-BN substrate implies a lower density of graphene ripples in the G/SiN device, as shown in FIG. Suppress scattering. fan, E. H. and Das Salma, S.M. Acoustic phonon scattering limited carrier mobility in two-dimensional extrinsic graphene. Physical Review B 77, 115449 (2008); and Louis, C.; H. , Liu, L.; , Mak, K. F. , Flynn, G.; W. and Heinz, T.; F. Ultraflat graphene. See Nature 462, 339-341, (2009). Moreover, the surface optical phonon modes of h-BN have twice the energy of similar modes in Si ₃ N ₄ /Si, suggesting less phonon scattering in the graphene channel. In this sample, despite the cleaner substrate, the Dirac point of the G/h-BN heterostructure has a similar value (~9 V) to that of the G/SiN device, which needs further understanding of this phenomenon. Please note.

Temperature dependence of sheet resistivity of G/h-BN devices on applied back gate voltage (V _BG −V _D ) at low temperature (T=15 K, red curve) and room temperature (T=300 K, black curve) is shown in FIG. 5D. shown in Jan, Y. , Mendez, E. E. and Du, X. Mobility-Dependent Low-Frequency Noise in Graphene Field-Effect Transistors. See ACS Nano 5, 8124-8130, (2011). With increasing temperature in the low density region, n<|n*|, the G/hBN device exhibits non-metallic behavior (dρ/dt<0), and in the high density region, n>|n*|, the device , is distinctly metallic (dρ/dt>0). Ho, J. Nonmonotonic temperature dependent transport in graphene grown by chemical vapor deposition. Physical Review B 84, 035421 (2011); I. , Sykes, K.; J. , Hong, J. , Stormer, H.; L. and Kim, P.S. in Temperature-Dependent Transport in Suspended Graphene. See Physical Review Letters 101, 096802 (2008).

The increase in sheet resistance of graphene in dense regions is attributed to longitudinal acoustic phonon scattering:

where p _s is the mass density of graphene (7.6×10 ⁻⁷ kg.m ⁻² ), Vj is the Fermi velocity (1×10 ⁶ ms ⁻¹ ), and v _s is the longitudinal acoustic phonon velocity ( 2×10 ⁴ ms ⁻¹ ), and D _A is the acoustic deformation potential. A linear fit on the electron and hole sides gives a D _A of 39 eV and 19 eV, respectively. The findings are in good agreement with previous studies. Bolotin, K. I. , Sykes, K.; J. , Hong, J. , Stormer, H.; L. and Kim, P.S. in Temperature-Dependent Transport in Suspended Graphene. Physical Review Letters 101, 096802 (2008); Chen, J.; -H. , Zhang, C, Xiao, S.; , Ishigami, M.; and Fuhaler, M.; S. Intrinsic and extrinsic performance limits of graphene devices on SiO2. Nat Nano 3, 206-209, (2008); , Tayari, V.; , island, . O. , Porter, J.; M. and Champaign, A.; R. Electronic thermal conductivity measurements in intrinsic graphene. See Physical Review B 87, 241411 (2013).

の導関数として定義されることが文献から周知されている。Ｇ／ｈ－ＢＮ（Ｇ／ＳｉＮ）デバイスの場合、μ_ＦΕは、高密度で５００ＣｄＶ_ＢＧｃｍ^２Ｖ^－１ｓ^－１（２５０ｃｍ^２Ｖ^－１ｓ^－１）から１３００ｃｍ^２Ｖ^－１ｓ^－１（３５０ｃｍ^２Ｖ^－１ｓ^－１）近くの電荷中性点に変化する。これは、図５Ｅに示すように、全体の密度領域にわたってＳｉ_３Ｎ_４／Ｓｉ基板と比較して、ｈ－ＢＮ基板上のグラフェンの移動度の向上をさらに確認する。
ＩＩＩ．触媒金属層の堆積 The inset also shows the G/h-BN conductance as a function of (V _BG and V _DS )—the I _on I _off ratio of the G/h-BN device is −5.5, which we making our h-BN substrates applicable to large-scale graphene and other 2DNs electronics. The field-effect mobility is calculated according to the Drude equation,
_μFε =

It is well known from the literature to be defined as the derivative of For G/h-BN (G/SiN) devices, μ _Fε ranged from 500 CdV _BG cm ² V ⁻¹ s ⁻¹ (250 cm ² V ⁻¹ s ⁻¹ ) to 1300 cm ² V ⁻¹ s ⁻¹ at high density. (350 cm ² V ⁻¹ s ⁻¹ ) near the charge neutral point. This further confirms the enhanced mobility of graphene on h-BN substrates compared to Si ₃ N ₄ /Si substrates over the entire density region, as shown in FIG. 5E.
III. Deposition of catalytic metal layer

Referring to FIG. 1D, according to the method of the present invention, after depositing a layer 300 comprising hexagonal boron nitride directly on the front surface of the single crystal semiconductor substrate or the front surface of the dielectric layer 200, the layer comprising hexagonal boron nitride is deposited. Substrate 100, including 300 and optional dielectric layer 200, may be processed to deposit a catalytic metal layer 400 for subsequent growth of graphene on the multilayer structure. In some embodiments, catalytic metal layer 400 may be deposited over layer 300 comprising hexagonal boron nitride. In some embodiments, the catalytic metal layer 400 comprises, for example, at least about 10% of the total area of the major surfaces, or at least about 25% of the total area, or at least about 50% of the total area, or at least about 50% of the total area. It may be deposited over a portion of layer 300 comprising 75% hexagonal boron nitride. In some embodiments, the catalytic metal layer 400 is deposited over the layer 300 comprising hexagonal boron nitride, followed by selective removal of the metal using conventional lithographic techniques to etch the major surfaces of the substrate. A desired pattern of metal deposition may be left on top. The surfaces of the catalytic metal layer 400 may be referred to herein as the "front metal layer surface" and the "back metal layer surface." Here, the back metal layer surface is in contact with the layer 300 containing hexagonal boron nitride. The bulk metal region is between the front metal film surface and the back metal film surface.

Metals suitable for the present invention include nickel, copper, iron, platinum, palladium, ruthenium, cobalt, aluminum, and alloys thereof. In some preferred embodiments, catalytic metal layer 400 comprises nickel. In some preferred embodiments, catalytic metal layer 400 comprises cobalt. In some preferred embodiments, catalytic metal layer 400 comprises nickel and cobalt, such as an alloy of nickel and cobalt. In some preferred embodiments, catalytic metal layer 400 comprises copper. Catalytic metal layer 400 may be deposited by techniques known in the art, including sputtering, thermal evaporation, ion beam deposition, chemical vapor deposition, electroplating, and metal foil bonding. In some embodiments, catalytic metal layer 400 is deposited by sputtering or evaporation using, for example, a sputtering and metal evaporation unit. Electrolytic metal plating is described in Supriya, L; O. Solution-Based Assembly of Conductive Gold Film on Flexible Polymer Substrates: Langmuir 2004, 20, 8870-8876. In some embodiments, catalytic metal layer 400 may be deposited by chemical vapor deposition at a relatively low temperature, eg, about 100°C to about 300°C, eg, about 200°C. Preferably, the metal film is about 50 nanometers to about 20 micrometers thick, such as about 50 nanometers to about 10 micrometers thick, such as about 50 nanometers to about 1000 nanometers, such as about 100 nanometers to about 500 nanometers thick. meters, such as from about 100 nanometers to about 400 nanometers, such as about 300 nanometers or about 500 nanometers.

In some embodiments, catalytic metal layer 400 may comprise a metal that has relatively high solubility in carbon at high temperatures (i.e., generally above 500° C., or above 800° C., such as about 1000° C.), which is graphene Allows diffusion of carbon during the layering process. Highly soluble metal films at the temperature of interdiffusion include nickel, iron, palladium, and cobalt. In some embodiments, the catalytic metal layer 400 is at least about 0.05 atomic percent at 1000 degrees Celsius, preferably at least about 0.10 atomic percent at 1000 degrees Celsius, and even more preferably at least about 0.15 atomic percent at 1000 degrees Celsius. % carbon solubility. In some embodiments, catalytic metal layer 400 comprises a metal having a carbon solubility of less than about 3 atomic percent at 1000 degrees Celsius, preferably less than about 2 atomic percent at 1000 degrees Celsius. For example, in some preferred embodiments, the catalytic metal layer 400 comprises nickel with a carbon solubility of about 0.2 atomic percent at 1000° C., providing a chamber for carbon inter-diffusion when nickel is the metal film. temperature. In some embodiments, the catalytic metal layer 400 comprises iron, which is about 0.02 atomic percent carbon at 800° C., which is the chamber temperature for carbon interdiffusion when iron is the metal film. have solubility. In some embodiments, the catalytic metal layer 400 comprises cobalt, which is about 1.6 atomic percent carbon at 1000° C., which is the chamber temperature for carbon in-diffusion when cobalt is the metal film. have solubility.

In some embodiments, the catalytic metal layer 400 comprises boron, nitrogen, and carbon with low or substantially zero solubility even at high temperatures (i.e., generally above 500° C., or above 800° C., such as about 1000° C.). may include metals having Low-solubility metal films include copper, platinum, and ruthenium. For example, carbon solubility is virtually zero in copper at temperatures above 500°C and above 800°C, such as 1000°C. During the inter-diffusion process, gaseous atoms, such as carbon, inter-diffuse into the bulk metal regions between metal particles, such as copper particles. If copper is chosen as the metal for the catalytic metal layer 400, the carbon-containing gas or carbon-containing polymer will be decomposed by the hydrogen on the copper. Carbon-carbon bond formation to graphene is catalyzed on the copper surface.

After deposition of the catalytic metal layer 400, the multi-layer structure may be cleaned. The multilayer structure includes a single crystal semiconductor wafer substrate 100 , a dielectric layer 200 , a layer 300 comprising hexagonal boron nitride, and a catalytic metal layer 400 . In some preferred embodiments, the multilayer structure may be cleaned by heating the structure in a vacuum furnace in a reducing atmosphere. A chemical vapor deposition system may be used if only baking under high vacuum is performed. In preferred embodiments, the reducing atmosphere comprises hydrogen gas or other reducing gas. An inert carrier gas such as argon or helium may be used. In preferred embodiments, the temperature during exposure to the reducing atmosphere is preferably from about 800°C to about 1200°C, eg about 1000°C. The pressure is preferably less than about 100 Pa (less than 1 Torr), preferably less than about 1 Pa (less than 0.01 Torr), even more preferably less than about 0.1 Pa (less than 0.001 Torr), even more preferably about 0 Sub-atmospheric pressure of less than 0.01 Pa (less than 0.0001 Torr). The cleaning anneal can adjust the grain size of the metal film, eg, it may increase the grain size at elevated temperatures.
IV. Deposition of graphene layers

After depositing the catalytic metal layer 400, the multilayer structure is treated to deposit a layer of graphene, according to some embodiments of the method of the present invention.

In some embodiments, the structure may be cleaned in a reducing atmosphere. In some preferred embodiments, the multilayer structure may be cleaned by heating the structure in a vacuum furnace in a reducing atmosphere. A chemical vapor deposition system may be used if only baking under high vacuum is performed. In preferred embodiments, the reducing atmosphere comprises hydrogen gas or other reducing gas. An inert carrier gas such as argon or helium may be used. The atmosphere is preferably a reducing atmosphere and may contain about 1% to about 99% hydrogen, such as about 70% to about 99% hydrogen, preferably about 95% hydrogen, the balance being inert gas. . In preferred embodiments, the temperature during exposure to the reducing atmosphere is preferably from about 800°C to about 1200°C, eg about 1000°C. The pressure is preferably less than about 10000 Pa (less than 100 torr), preferably less than about 1000 Pa (less than 1 torr), preferably less than about 1 Pa (less than 0.01 torr), even more preferably less than about 0.1 Pa (0.01 torr). 001 torr), even more preferably less than about 0.01 Pa (less than 0.0001 torr). The cleaning anneal can adjust the grain size of the metal film, eg, it may increase the grain size at elevated temperatures.

According to some embodiments of the method of the present invention, the multilayer structure may be exposed to a carbon source, whereby atomic carbon diffuses into the bulk region of the metal film. Atomic carbon may be solubilized in metal films containing metals with high carbon solubility, such as nickel, and may migrate between metal particles in metal films containing metals with low carbon solubility, such as copper. In some embodiments, a carbon-containing gas or carbon-containing vapor stream may be added to the reducing gas stream. Carbon-containing gases may be selected among volatile hydrocarbons such as methane, ethane, ethylene, acetylene, propane, propylene, propyne, butane, isobutane, butylene, butyne, and the like. Carbon-containing vapors may be selected from liquid hydrocarbons such as cyclohexane, benzene, pentane, hexane, heptane, and the like. Note that these hydrocarbon gases or liquids can be saturated or unsaturated hydrocarbons. A carbon-containing gas, such as methane, is a carbon source that can be deposited into graphene according to the process of the present invention. The atmosphere may be a reducing atmosphere and may further contain a reducing gas such as hydrogen. In some embodiments, the gas may comprise methane gas and hydrogen gas in a ratio of about 1:1 to about 200:1, such as about 1:1 to about 100:1, such as about 144:15. The minimum temperature during carbon absorption and/or adsorption is generally at least about 500°C. The maximum temperature during carbon absorption and/or adsorption is generally below about 1100°C. Generally, the temperature is preferably from about 700°C to about 1000°C. Generally, the pressure within the reaction chamber in the hydrogen gas/methane stream is from about 0.1 torr to about 100 torr, such as from about 0.4 torr to about 150 torr. toll).

Optionally, and preferably after sufficient carbon has interdiffused into the bulk region of the metal film, the gas flow is stopped and the multiple layers are held for a period of time sufficient for the carbon to diffuse throughout the bulk region of the metal film. while being held at the temperature of the internal diffusion. The proper duration of carbon interdiffusion to produce a product with the desired number of monoatom-thick graphene layers is determined by the number of separated graphene layers in the final product, given the length of the carbon interdiffusion period. It may be determined by constructing a calibration curve that is a function. The calibration curve may be used to determine the ideal carbon interdiffusion period sufficient to produce a single monoatom thick graphene layer or multiple monoatom thick graphene layers. The period of equilibrium after the flow of carbon-containing gas is stopped can range from about 5 seconds to about 3600 seconds, such as from about 600 seconds to about 1800 seconds. In some embodiments, the duration of carbon diffusion is very short, eg, about 10 seconds. After the metal has absorbed a sufficient concentration of carbon, the multilayer structure is cooled, causing the graphene to separate and precipitate during cooling.

In some embodiments, carbon is provided in solid form either as a carbon-containing self-assembled monolayer and/or a carbon-rich polymer in addition to the carbon-containing gas or vapor, or as an alternative to carbon inclusions. may Herein, the hydrocarbon-containing moieties are carbon sources (or B and/or or N), the metal film comprises a metal with low or substantially zero carbon solubility. The hydrocarbon provides a carbon source for graphene formation on the intervening layer of boron nitride deposited on the front layer of the semiconductor substrate.

Generally, a wide variety of carbon-containing polymers are suitable. In some embodiments, the carbon-rich polymer is polymethylmethacrylate (PMMA), polybutadiene, polystyrene, poly(acrylonitrile-co-butadiene-co-styrene) (ABS), polyethylene, polypropylene, poly(4'-vinyl hexaphenylbenzene), and combinations thereof. In some embodiments, the polymer or carbon-containing film may contain nitrogen or boron to produce nitrogen-doped or boron-doped graphene sheets. Nitrogen-containing polymers suitable for the present invention include melamine formaldehyde, polyacrylonitrile, poly(2,5-pyridine), polypyrrole, polycarbazole, polyaniline, and combinations thereof. Boron doping may be accomplished by preparing a carbon-containing layer with a boron alcohol (non-polymer) or by depositing Boramer™.

Carbon-rich polymers may be deposited by spin-coating a substrate with a polymer film from a polymer-containing solution. Other suitable deposition methods include spray coating and electrochemical deposition. Suitable solvents for spin coating solutions include toluene, hexane, xylene, pentane, cyclohexane, benzene, chloroform. The polymer concentration is generally from about 0.01 wt% to about 1 wt%, from about 0.05 wt% to about 0.5 wt%, such as about 0.1 wt%.

The carbon-rich polymer layer may be deposited from about 1 nanometer to about 100 nanometers thick, such as from about 5 nanometers to about 100 nanometers thick, preferably from about 10 nanometers to about 50 nanometers thick. In some embodiments, the carbon-rich polymer layer may be deposited to a thickness of about 1 nanometer to about 10 nanometers.

The temperature during carbon in-diffusion may range from about 500° C. to about 1000° C., such as from about 700° C. to about 1000° C., such as from about 800° C. to about 1000° C. for nickel. After the metal has absorbed a sufficient concentration of carbon, the multilayer structure is cooled, causing the graphene to separate and precipitate during cooling.

The multilayer structure is then quenched. Cooling the multilayer structure reduces the solubility of carbon in the bulk region of the metal film, causing the carbon to separate from the metal film and deposit graphene between the boron nitride layer and the backside of the metal film. The cooling rate can be at least about 10°C/min, at least about 50°C/min, at least about 100°C/min. Generally, the pressure in the reaction chamber during cooling is from about 0.1 torr to about 100 torr, such as from about 0.4 torr to about 150 torr. . The atmosphere is preferably a reducing atmosphere and may contain about 1% to about 99% hydrogen, such as about 70% to about 99% hydrogen, preferably about 95% hydrogen, the balance being inert gas. . High temperature growth and rapid cooling rapidly enhance precipitation and surface nucleation such that the graphene nuclei preferentially attach to each other in the same direction, resulting in epitaxial growth of broad coverage, high quality single-layer graphene.

In embodiments where the solubility of carbon in metals is low or zero (eg, copper), the methods of the present invention advantageously yield monolayers of graphene. In embodiments where graphene formation relies on solubilization of carbon into a metal film followed by separation and deposition of graphene (e.g., nickel, cobalt), the methods of the present invention control the amount of carbon absorbed and deposited to There is a need to control the number of graphene layers produced. In some embodiments, the methods of the present invention allow deposition of a single monoatomic layer of graphene between a boron nitride layer on the front surface of a semiconductor substrate and the back surface of a metal film. In some embodiments, the methods of the present invention enable deposition of multiple layers of graphene of monoatomic thickness between a boron nitride layer on the front surface of a semiconductor substrate and the back surface of a metal film. The graphene layers may include 2 to about 100 monoatomic graphene layers, such as 2 to about 50 monoatomic graphene layers, or 3 to about 50 monoatomic graphene layers. A second layer of graphene may be deposited on the front metal film surface. Current results so far indicate that nickel layers in particular are suitable for the preparation of multilayer graphene films.

According to embodiments in which a graphene layer is deposited on the front metal film surface, this outer layer of graphene may be removed. In some embodiments, the outer graphene layer may be removed by etching, such as wet etching, plasma etching, or oxidation with ozone/UV light. In a preferred embodiment, the outer layer of graphene may be removed by an oxygen plasma etch.

According to some embodiments of the next step of the present invention, the metal film is removed to expose the graphene layer in contact with the boron nitride layer, thereby contacting the front surface of the semiconductor substrate. Metal films may be removed by techniques known in the art suitable for dissolving metals of metal films, such as, for example, dissolving nickel, copper, iron, or alloys thereof. In preferred embodiments, the metal film is contacted with an aqueous metal etchant. Metal etchants useful for removing metal films include ferric chloride, iron(III) nitrate, aqua regia, and nitric acid. Advantageously, these metal etchants do not remove graphene.

In some embodiments, removal of the metal film results in a semiconductor substrate 100 (eg, a silicon wafer including a silicon oxide layer and/or a silicon nitride layer), a dielectric layer 200, a layer of boron nitride 300, and a monoatomic thickness of graphene. A multi-layer substrate is fabricated comprising a single layer or multi-layer 500 of . See FIG. 1E. In some embodiments, one or both of the graphene and boron nitride layers may include multiple layers of each material, each layer having a single atomic thickness. The graphene layers may be characterized to ascertain the number of layers by techniques known in the art, such as Raman spectroscopy.

In summary, the present invention provides a basic understanding of h-BN growth kinetics on Si, Si-based oxide (SiO ₂ /Si), and nitride (Si ₃ N ₄ /Si) surfaces. The present disclosure shows that nitrogen on the Si ₃ N ₄ /Si surface combines with boron and nitrogen reactive species to produce nucleation sites for the adsorption kinetics assisted growth of h-BN in large areas and continuous films. We provide details of the growth mechanism supported by molecular dynamics simulations. The influence of kinetic processes on h-BN synthesis on non-metallic catalyst surfaces (SiO ₂ /Si and Si ₃ N ₄ /Si) under LPCVD conditions was not resolved. In addition, large area, van der Waals bonds, and electronically isolated graphene/h-BN heterostructures were also designed. Interestingly, low-temperature electron transport studies show that the graphene/h-BN heterostructure exhibits a 3-fold enhancement in charge carrier mobility and electron-hole puddling compared to its graphene/Si ₃ N ₄ /Si counterpart. It has been shown to work exceptionally with respect to fluctuations. Unlike transition metal-assisted hBN formation, the method developed here, ie, a diverse process for direct and scalable production of h-BN, is more compatible with the current semiconductor industry. The processes developed here are potentially envisioned to include a variety of intelligently engineered 3D heterostructures via 2DNs with applications ranging from nanoscale electronics to energy conversion and optoelectronics. can be done.

The following non-limiting examples are provided to further illustrate the invention.
Example 1.
Synthesis of Hexagonal Boron Nitride (h-BN) on Si Nitride (Si ₃ N ₄ /Si) Substrates

h-BN synthesis was carried out via a low-pressure CVD (LPCVD) system (MTI OTF-1200X) equipped with a specially designed separate chamber for ammonia-borane (AB) ²² . A piranha solution (3:1 by volume mixture of 98% H ₂ SO ₄ and 35% H ₂ O ₂ ) was used to clean Si ₃ N ₄ /Si substrates (from SunEdison Semiconductor). For h-BN synthesis, the Si ₃ N ₄ substrate was placed directly in the center of the heating zone of the quartz tube and heated to 1100° C. in H ₂ atmosphere to limit further oxidation. After the tube heating zone reached 1100° C., AB was sublimed at about 100° C. and then transported to the chamber containing the substrate via supplied H ₂ carrier gas. h-BN syntheses were carried out at pressures of 5-10 torr and reaction times varied from 15-60 minutes followed by rapid cooling (approximately 100° C./min). The thin films of h-BN synthesized were characterized by confocal Raman atomic force microscopy (Raman-AFM, WITEC α-300RA with laser wavelength 532 nm) and X-ray photoelectron spectroscopy (XPS, Kratos AXIS-165). For AFM measurements of h-BN surface roughness and film thickness, h-BN on Si ₃ N ₄ surfaces was subjected to microfabricated etching processes: e-beam evaporation (Varian), UV-photolithography (Karl Suss MA6), and patterned by reactive ion etching (RIE, Oxford Instruments).

Example 2. Graphene Synthesis by Chemical Vapor Deposition of Graphene on Cu _Foil (1 _″ ×2 '') High-quality monolayer graphene was grown by chemical vapor deposition (CVD) process on copper foil (25 μm, 99.98% purity). A standard 1 inch quartz tube in a split CVD furnace (MTI OTF-1200X) was used as the reaction chamber. A typical graphene synthesis was as follows. First, the copper foil was thoroughly washed with copious amounts of water, acetone, and IPA (in sequence). The native oxide of the Cu foil was then removed by soaking in a solution of Fe(NO ₃ ) ₂ :HNO ₃ (1M:3M) for 10 minutes. The Cu foil was subsequently rinsed (in order) with copious amounts of water, acetone, and IPA. To further remove residual ions, the Cu foil was sonicated in 100 mL of acetone (ACS spectrophotometric grade, >99.5%, Fisher Scientific). The foil was then washed thoroughly with copious amounts of water, acetone, and IPA (in sequence) before drying with a stream of purified air for 2 minutes. Additionally, the clean foil was loaded into the CVD furnace and the reaction chamber was evacuated to 1 mTorr for 5 minutes. 100 sccm of H ₂ was then introduced to flush the system for an additional 10 minutes. The furnace temperature was increased to 1050° C. for 15 minutes while maintaining the H ₂ gas flow. At 1050° C., the Cu foil was annealed for an additional 30 minutes to increase the grain size and smoothen its surface. 10 sccm of CH ₄ was then introduced into the chamber for 1 minute (PTot=500 mTorr). After growth, the chamber was rapidly cooled to room temperature by turning off the _CH4 and opening the half-furnace.

Example 3. Graphene Transfer to hB/Si ₃ N ₄ /Si and Si ₃ N ₄ Si Substrates The graphene transfer process was used as follows. First, 25 mg/mL poly(methyl methacrylate) (PMMA) (MW 996,000, Sigma Aldrich) in anisole (99% purity, Acros Organics) was (i) press-spinned at 500 RPM for 5 seconds (500 rpm/s (ramp speed of 1000 rpm/s), and (ii) full spin: spin coated onto the graphene/Cu foil at 4000 RPM for 30 seconds (1000 rpm/s ramp speed). The PMMA-coated graphene/Cu foil was then air-dried for 5 minutes, followed by etching of the Cu foil with 1 mL:3 mL HNO3 (65% purity) and DI water for 1 hour. Floating PMMA/graphene samples were collected by submerging a clean quartz substrate into the solution and lifting it at a 60° angle to the surface of the etchant solution. Immediately it was transferred to DI water in the same manner as the pick-up step (repeated twice). Similarly, subsequent substrates (SiN and directly grown hBN) were then used to pick up PMMA/graphene samples. These PMMA/graphene/SiN/n++-Si and PMMA/graphene/hBN/SiN/n++-Si were dried overnight in air. To remove PMMA, these samples were immersed in acetone for 10 minutes at room temperature, followed by copious acetone and IPA washing (in sequence), and drying with a stream of purified air for 2 minutes.

Example 4. Field Effect Transistor (FET) Device Fabrication and Electrical Measurements Photolithography: Graphene samples with Cr/Au (15 nm/95 nm) layers after transfer to advanced n++ silicon substrates with different dielectric layers (SiN and hBN/SiN). deposited. A positive photoresist (AZ1818) was spin coated onto the samples at 4000 rpm for 45 seconds. The samples were then baked on a hot plate at 110°C for 1 minute. A dose of UV light (365 nm and lamp power 900 W) was subsequently introduced to the sample with an aligned mask for 12 seconds using a Karl Suss MA6 mask aligner. The samples were then developed in a solution of 3:1 (DI water:AZ340) for 18 seconds before etching the unprotected Cr/Au areas with Au etchant (36 seconds) and Cr etchant (36 seconds) in sequence at room temperature. 18 seconds) to form electrode contacts. After defining the metal contacts, the samples were washed with copious amounts of acetone and IPA (in sequence) and dried with a stream of purified air for 2 minutes.

A bar structure with a channel length of 27 μm and a channel width of 7 μm was fabricated with another layer of positive photoresist by repeating the previous steps. After developing to form a protective pattern of graphene bars, these samples were placed in an Oxford RIE chamber and exposed to an oxygen plasma (10 W power, 20 sec exposure, 535-550 V peak-to-peak voltage, and 260 V bias voltage). ) to remove the unprotected graphene. Subsequently, the sample was immersed in a first bath of AZ351 solution for 5 minutes, immersed in a second bath of AZ351 solution for an additional 3 minutes to further remove photoresist residue, and immersed in an IPA solution for 5 minutes. , stripped the overlying photoresist. Finally, the samples were washed with copious amounts of acetone and IPA (in sequence) and dried with a stream of purified air for 2 minutes.

Device Pretreatment and Electrical Measurements: Samples were placed in clean 1 inch quartz tubes in a split furnace prior to electrical measurements. The chamber was evacuated to 1 mTorr for 5 minutes. A further 20 sccm of H ₂ was introduced to flush the system for an additional 10 minutes. The furnace temperature was increased to 150° C. for 15 minutes while maintaining the H ₂ flow at 200 mTorr. At 150° C., the photoresist residue was further removed by reducing gas (H ₂ ) for 2 hours. After cooling to room temperature, the samples were immediately placed inside the Janis Cryostat system for electrical measurements.

This written description is an example to disclose the invention, including the best mode, including making and using any device or system, and implementing the methods incorporated therein, to enable a person skilled in the art to An example is used to make it possible to implement the invention. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are those having structural elements that do not differ from the literal description of the claims, or equivalents where the differences from the literal description of the claims are not material differences. If it does include a structural element, it is intended to be within the scope of the claim.

Claims (12)

Two parallel main surfaces, one of which is the front surface of the single crystal semiconductor wafer and the other is the rear surface of the single crystal semiconductor wafer, a peripheral portion that joins the front surface and the rear surface of the single crystal semiconductor wafer, and a single crystal A single crystal semiconductor wafer comprising a central plane between the front and back sides of the semiconductor wafer and a bulk region between the front and back sides of the single crystal semiconductor wafer;
a silicon nitride layer in interfacial contact with the front surface of a single crystal semiconductor wafer;
a layer comprising hexagonal boron nitride in interfacial contact with the layer comprising silicon nitride; and
A layer comprising graphene in interfacial contact with a layer comprising hexagonal boron nitride, wherein the layer comprising graphene has a ratio _I2D / _IG of at least 3, where _IG is the full width at half maximum of the G band and _I2D is 2D. A multilayer structure comprising a layer comprising graphene, wherein the ratio of the intensity of the 2D band to the G band (I _2D /I _G ) is determined by confocal Raman spectroscopy. 2. The method of claim 1, wherein the single crystal semiconductor wafer comprises a material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. A multilayer structure as described. 2. The multilayer structure of claim 1, wherein the single crystal semiconductor wafer comprises silicon. 2. The multilayer structure of claim 1, wherein the silicon nitride layer is neutrally charged. 2. The multilayer structure of claim 1, wherein the hexagonal boron nitride has a B:N molar ratio between 1.3:1 and 1:1.3. 2. The multilayer structure of claim 1, wherein the hexagonal boron nitride has an atomic concentration ratio of nitrogen to boron of 1:1.11±0.09. 2. The multilayer structure of claim 1, wherein the layer comprising graphene has a field effect mobility of 500 cm ² V ⁻¹ s ⁻¹ to 1300 cm ² V ⁻¹ s ⁻¹ . 2. The multilayer structure of claim 1, wherein the layer comprising graphene has an intrinsic charge carrier mobility of at least 1200 cm ^<2> /Vs. 3. The multilayer structure of claim 1, further comprising a metal film in interfacial contact with the layer comprising graphene. 10. The multilayer structure of Claim 9, wherein the metal film comprises a metal selected from the group consisting of nickel, copper, iron, platinum, palladium, ruthenium, aluminum, cobalt, and alloys thereof. 10. The multilayer structure of claim 9, wherein the metal film comprises nickel, cobalt, or nickel and cobalt. 10. The multilayer structure of Claim 9, wherein the metal film comprises copper.

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