JP7281933B2 - amplifier - Google Patents

Description

The present invention relates to an amplification device for amplifying signals.

In wireless communication, when handling signals of many operators at the same time, it is necessary to perform transmission and reception in a wider band. Therefore, a wide dynamic range of output power and input power to the amplifier is required. For example, in the 2 GHz band with a bandwidth of 60 MHz, the required dynamic range may be 10 dB or more.

Further, in recent years, in wireless communication, signals with a high peak-to-average power ratio (PAPR) are often handled. When amplifying a high-PAPR signal with a high-power amplifier used in a normal transmitter, power consumption increases when trying to maintain the linearity of amplification.

In particular, the number of high-power amplifiers is large in base stations, which may occupy a large portion of the power consumption of the system. Therefore, various techniques for improving the efficiency of amplifiers, such as Doherty, envelope tracking, and outphasing, have been studied.

In outphasing, an input signal is separated into two signals with constant amplitude and different phases, and the signals are combined after being amplified by separate amplifiers. Specifically, two signals are combined so that the phase relationship when the input signals are separated is maintained. At this time, it is common to synthesize with a Chireix synthesizer equipped with an element for canceling the reactance component generated between the two amplifiers so that load modulation occurs with a desired backoff value.

Outphasing can be highly efficient with a desired designed back-off value, but the efficiency drops significantly with a back-off value lower than the designed value. Therefore, in a system with a wide dynamic range of output power and input power, there is a problem that the overall efficiency is lowered.

On the other hand, a technique of switching between outphasing amplification and Doherty amplification according to input power is disclosed (Patent Document 1). According to this technology, it is said that high efficiency can be maintained even when the dynamic range of input power is relatively large.

Japanese Patent Publication No. 2018-521592

By the way, there is a demand for a configuration that achieves high efficiency even when the dynamic range is wide without unnecessarily increasing the circuit scale.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an amplifying device that achieves high efficiency even when the dynamic range is wide without enlarging the circuit scale.

In order to solve the above-described problems and achieve the object, an amplifier device according to an aspect of the present invention includes a plurality of amplifiers arranged in parallel. a detection unit for detecting the amplitude level of an input signal in a stage preceding the amplifier group; and the out-phase amplification unit according to the amplitude level of the input signal detected by the detection unit. or to amplify and output the input signal in the Doherty amplifier, and a power supply unit to supply power to each amplifier constituting the amplifier group and wherein the power supply section changes the backoff point of the Doherty amplification section based on the amplitude level of the input signal.

In the amplifying device according to an aspect of the present invention, the power supply section changes power supplied to the plurality of amplifiers constituting the Doherty amplification section in a plurality of stages based on the amplitude level of the input signal, It is characterized by changing the back-off point of the amplifier.

In the amplifying device according to an aspect of the present invention, the power supply unit adjusts the power supplied to the plurality of amplifiers constituting the Doherty amplification unit to one or more stages based on the amplitude level and dynamic range of the input signal. It is characterized by changing the back-off point of the Doherty amplifier.

In an amplifier device according to an aspect of the present invention, the amplifier group includes a first amplifier, a second amplifier, and a third amplifier arranged in parallel, and the out-phase amplification section includes the first amplifier and the second amplifier, and the Doherty amplifier is realized by a combination of the second amplifier and the third amplifier.

An amplifier device according to an aspect of the present invention includes a first synthesis point for synthesizing a first signal group amplified and output by the out-phase amplification section, and a second signal amplified and output by the Doherty amplification section. a second combining point for combining the groups, said second combining point being disposed between said second amplifier and said first combining point, and a reactance compensating element for compensating a reactance component occurring between said amplifiers. is arranged between the third amplifier and the second combining point.

The amplifying device according to one aspect of the present invention generates the first signal group and outputs the first signal group to the out-phase amplifying unit when the amplitude level of the input signal is higher than the threshold, and the amplitude level of the input signal is the above A signal generator is provided for generating the second signal group and outputting the second signal group to the Doherty amplifier when the difference is equal to or less than a threshold.

In the amplifying device according to an aspect of the present invention, the first amplifier is supplied with a first bias voltage when the amplitude level of the input signal is higher than the threshold, and when the amplitude level of the input signal is lower than the threshold. , a second bias voltage different from the first bias voltage is supplied, the second amplifier is supplied with the first bias voltage, and the third amplifier is supplied with the second bias voltage. and

An amplifying device according to an aspect of the present invention is characterized in that the third amplifier is composed of a plurality of amplifiers arranged in parallel.

According to the present invention, high efficiency can be achieved even when the dynamic range is wide without enlarging the circuit scale.

FIG. 1 is a schematic configuration diagram of an amplifier according to Embodiment 1. FIG. FIG. 2 is a diagram showing the relationship between amplitude level and drain voltage. FIG. 3 is a diagram showing an example of power efficiency with respect to backoff values. FIG. 4 is a schematic configuration diagram of an amplifier according to Embodiment 2. FIG. FIG. 5 is a diagram showing the relationship between amplitude level and drain voltage.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, this invention is not limited by embodiment described below. In addition, in the description of the drawings, the same or corresponding elements are given the same reference numerals as appropriate.

(Embodiment 1)
FIG. 1 is a schematic configuration diagram of an amplifier according to Embodiment 1. FIG. The amplifier device 100 includes a signal generator 10, a first amplifier 1, a second amplifier 2, a third amplifier 3, and a Shiley combiner 20, which is one form of a combiner. The output side of the amplifier device 100 is connected to the load L. Note that the output side of the amplifier device 100 may be configured such that an antenna is connected instead of the load L. FIG.

The signal generator 10 includes an FPGA (Field Programmable Gate Array) as a signal processing section 11 , DA converters 12 , 13 and 14 , and mixers 15 , 16 and 17 . The signal processing unit 11 includes an input power amplitude determination unit 11a functioning as a detection unit, a control unit 11b functioning as a selection unit, an outphase signal generation unit 11c, and a Doherty signal generation unit 11d. RF local signals (not shown) are input to the mixers 15, 16, and 17, respectively.

In this embodiment, a first amplifier 1, a second amplifier 2, and a third amplifier 3, which are a plurality of amplifiers, are arranged in parallel to form an amplifier group. Each of the first amplifier 1, the second amplifier 2, and the third amplifier 3 is configured using an FET (Field Effect Transistor). Each of the first amplifier 1, the second amplifier 2, and the third amplifier 3 amplifies and outputs an input signal. By using the first amplifier 1 and the second amplifier 2 in combination, an out-phase amplification section 30 is realized. Further, the Doherty amplifier section 40 is realized by using the second amplifier 2 and the third amplifier 3 in combination. In this way, the amplifier group implements the out-phase amplification section 30 and the Doherty amplification section 40 by combining amplifiers.

The amplifying device 100 further includes a power supply section 50 . The power supply unit 50 has a voltage control unit 51 that performs voltage control. The power supply unit 50 supplies power to each amplifier that configures the amplifier group. In this embodiment, the power supply unit 50 applies a power supply voltage (drain voltage) to the first amplifier 1, the second amplifier 2, and the third amplifier 3. FIG. The drain voltage applied to the first amplifier 1 is the drain voltage Vd1. The drain voltage applied to the second amplifier 2 is the drain voltage Vd2. The drain voltage applied to the third amplifier 3 is the drain voltage Vd3. Thus, power is supplied to each of the first to third amplifiers 1-3. As will be described later, the voltage control section 51 has a function of controlling the voltage applied to each of the first to third amplifiers 1 to 3 based on the input command signal.

The Shire combiner 20 includes a first combining point 21 , a second combining point 22 , reactance compensating elements 23 and 24 , and adjusters 25 and 26 .

Next, the configuration and function of each component will be specifically described. In signal generator 10, signal processor 11 receives input signal S0. In the signal processing unit 11, the input power amplitude determination unit 11a determines the amplitude level of the input signal S0 (in this embodiment, the input signal S0 power amplitude level) is detected and determined. The input power amplitude determination section 11a outputs a command signal to the control section 11b according to the amplitude level of the power of the input signal S0.

The control unit 11b generates gate voltage (bias voltage) signals Vg1, Vg2, and Vg3 as control signals for controlling operations of the first amplifier 1, the second amplifier 2, and the third amplifier 3, respectively. , the gate terminals of the second amplifier 2 and the third amplifier 3 . Further, the input power amplitude determination section 11a outputs a command signal to the outphase signal generation section 11c or the Doherty signal generation section 11d according to the amplitude level of the power of the input signal S0. Further, the input power amplitude determination section 11a outputs a command signal to the voltage control section 51 of the power supply section 50 according to the amplitude level of the power of the input signal S0.

In this embodiment, the input power amplitude determination unit 11a determines whether the amplitude level of the power of the input signal S0 is higher than the threshold or below the threshold. When the input power amplitude determining section 11a determines the amplitude level of the power of the input signal S0, it may determine the amplitude level of the average power within a predetermined period. The predetermined period is, for example, several milliseconds to several tens of milliseconds, more specifically 10 milliseconds, but is not particularly limited.

As will be described in detail below, the control unit 11b functioning as a selection unit causes the out-phase amplification unit 30 to amplify the input signal S0 according to the amplitude level of the input signal S0 detected by the input power amplitude determination unit 11a functioning as a detection unit. , or amplified by the Doherty amplifier 40 and output. Furthermore, the power supply unit 50 changes the backoff point of the Doherty amplifier unit 40 under the control of the voltage control unit 51 based on the amplitude level of the input signal S0 detected by the input power amplitude determination unit 11a. In this embodiment, the power supply unit 50 changes the back-off point of the Doherty amplifier unit 40 based on the amplitude level of the input signal S0. Power (drain voltage) is supplied to each.

(When the power amplitude level of the input signal S0 is higher than the threshold)
When the amplitude level of the power of the input signal S0 is higher than the threshold, the control unit 11b sets the gate voltage signal Vg1 to a voltage signal having a value that biases the first amplifier 1 to become a class AB or class C amplifier. Output to amplifier 1. Further, the control unit 11b outputs to the second amplifier 2, as the gate voltage signal Vg2, a voltage signal having a bias value so that the second amplifier 2 becomes an amplifier of the same class as the first amplifier 1. FIG. In addition, the control unit 11b applies a voltage signal (which may be 0 V) to the third amplifier 3 as the gate voltage signal Vg3 such that the third amplifier 3 is biased to become a class C amplifier or lower, or the operation is turned off. Output to amplifier 3 . That is, when the power amplitude level of the input signal S0 is higher than the threshold, the first amplifier 1 is supplied with the gate voltage signal Vg1 corresponding to the first bias voltage, which is a voltage corresponding to class AB. The second amplifier 2 is supplied with a gate voltage signal Vg2 corresponding to the first bias voltage. The third amplifier 3 is supplied with a gate voltage signal Vg3 corresponding to a second bias voltage, which is a voltage (including zero) corresponding to class C, unlike the first bias voltage.

Furthermore, when the amplitude level of the power of the input signal S0 is higher than the threshold, the controller 11b outputs a command signal to the outphase signal generator 11c. The outphase signal generator 11c generates outphase signals S11 and S12 based on the input signal S0. Here, the out-phase signals S11 and S12 are, as is well known, signals obtained by separating the input signal S0 into two signals having constant amplitudes and different phases. The out-phase signals S11 and S12 are two signals to be amplified by the out-phase amplification section 30, and constitute a first signal group. The outphase signal generator 11c outputs the outphase signals S11 and S12 to the DA converters 12 and 13, respectively.

The DA converters 12 and 13 DA-convert the out-phase signals S11 and S12 of the first signal group, respectively, and output the DA-converted signals to the mixers 15 and 16, respectively.

The mixers 15 and 16 up-convert the DA-converted out-phase signals S11 and S12, respectively, to RF signals, and output the RF signals to the first amplifier 1 and the second amplifier 2 constituting the out-phase amplifier 30, respectively. do.

The first amplifier 1 and the second amplifier 2 respectively amplify the out-phase signals S11 and S12 converted to RF signals and output the amplified signals to the Syley synthesizer 20 . At this time, the first amplifier 1 and the second amplifier 2 are operating in saturation.

The Shire synthesizer 20 synthesizes the out-phase signals S11 and S12, which are the amplified and output first signal group, at the first synthesis point 21 and outputs the result to the load L. FIG. Note that the adjustment unit 25 has a function of adjusting the electrical length of the transmission path from the first amplifier 1 to the first combining point 21 to be an odd multiple of λ/4. The adjusting section 26 has a function of adjusting the electrical length of the transmission path from the second amplifier 2 to the first combining point 21 to be an odd multiple of λ/4. Reactance compensating elements 23 and 24 are shunt-connected to transmission lines from first amplifier 1 and second amplifier 2 to first combining point 21, respectively. The reactance compensating elements 23 and 24 are capacitors or inductors having polarities opposite to each other, and compensate by canceling out the reactance components generated between the first amplifier 1 and the second amplifier 2, thereby suppressing a decrease in efficiency. .

(When the power amplitude level of the input signal S0 is equal to or less than the threshold)
When the amplitude level of the power of the input signal S0 is equal to or lower than the threshold, the control unit 11b sets the gate voltage signal Vg1 so that the first amplifier 1 is biased to become a class C amplifier or lower, or is turned off. A signal (which may be 0V) is output to the first amplifier 1 . Further, the control unit 11b outputs to the second amplifier 2, as the gate voltage signal Vg2, a voltage signal having a bias value so that the second amplifier 2 becomes a class A, class AB, or class B amplifier. Further, the control unit 11b outputs to the third amplifier 3, as the gate voltage signal Vg3, a voltage signal having a bias value so that the third amplifier 3 becomes a class C amplifier. Thereby, the second amplifier 2 operates as a carrier amplifier, and the third amplifier 3 operates as a peak amplifier. That is, when the power amplitude level of the input signal S0 is lower than the threshold, the first amplifier 1 is supplied with the gate voltage signal Vg1 corresponding to the second bias voltage. The second amplifier 2 is supplied with a gate voltage signal Vg2 corresponding to the first bias voltage. The third amplifier 3 is supplied with a gate voltage signal Vg3 corresponding to the second bias voltage.

Further, when the amplitude level of the power of the input signal S0 is equal to or less than the threshold, the input power amplitude determination section 11a further determines the magnitude relationship between the amplitude level, the first determination value, and the second determination value. Then, according to the determination result, a command signal for changing the drain voltage applied to the second amplifier 2 and the third amplifier 3 is output to the voltage control section 51 . The power supply unit 50 applies a drain voltage as follows and supplies power under the control of the voltage control unit 51 .

As shown in FIGS. 2A and 2B, when the amplitude level of the input signal S0 is equal to or less than the threshold value and higher than the first determination value, the power supply unit 50 supplies the second amplifier 2 with the first power as the drain voltage Vd2. and a second drain voltage corresponding to the second power is applied to the third amplifier 3 as the drain voltage Vd3. Further, when the amplitude level of the input signal S0 is equal to or lower than the first determination value and higher than the second determination value, the power supply unit 50 supplies the second amplifier 2 with a third power lower than the first power as the drain voltage Vd2. A third drain voltage (lower than the first drain voltage) is applied and a fourth drain voltage (lower than the second drain voltage) corresponding to a fourth power lower than the second power is applied to the third amplifier 3 as a drain voltage Vd3. ) is applied. Furthermore, when the amplitude level of the input signal S0 is equal to or lower than the second determination value, the power supply unit 50 supplies the second amplifier 2 with a fifth drain voltage Vd2 corresponding to a fifth power lower than the third power. 3 drain voltage) is applied, and a sixth drain voltage (lower than the fourth drain voltage) corresponding to the sixth power lower than the fourth power is applied to the third amplifier 3 as the drain voltage Vd3. In this way, the power supply unit 50 supplies power to the second amplifier 2 and the third amplifier 3 constituting the Doherty amplifier unit 40 in multiple stages (three stages in this embodiment) based on the amplitude level of the input signal S0. change to

Accordingly, as the amplitude level of the input signal S0 decreases, the power (applied drain voltage) supplied to each of the second amplifier 2 and the third amplifier 3 with the first judgment value and the second judgment value as boundaries is stepped. (three steps in this embodiment). Accordingly, the back-off point of the Doherty amplifier 40 also decreases stepwise (three steps in this embodiment) with the first decision value and the second decision value as boundaries.

Furthermore, when the amplitude level of the power of the input signal S0 is equal to or lower than the threshold, the control section 11b outputs a command signal to the Doherty signal generation section 11d. The Doherty signal generator 11d generates Doherty signals S21 and S22 based on the input signal S0. Here, the Doherty signals S21 and S22 are, as is well known, signals obtained by separating the input signal S0 into two signals. However, the Doherty signal S22 is 90° behind the Doherty signal S21. The Doherty signals S21 and S22 are two signals to be amplified by the Doherty amplifier 40, and constitute a second signal group. The Doherty signal generator 11d outputs the Doherty signals S21 and S22 to the DA converters 13 and 14, respectively.

The DA converters 13 and 14 DA-convert the Doherty signals S21 and S22 of the second signal group, respectively, and output the DA-converted signals to the mixers 16 and 17, respectively.

The mixers 16 and 17 up-convert the DA-converted Doherty signals S21 and S22 to RF signals, respectively, and output the RF signals to the second amplifier 2 and the third amplifier 3 constituting the Doherty amplification section 40, respectively.

The second amplifier 2 and the third amplifier 3 amplify the Doherty signals S21 and S22 converted to RF signals, respectively, and output the amplified signals to the Shire synthesizer 20 .

The Shire synthesizer 20 synthesizes the Doherty signals S21 and S22, which are the amplified and output second signal group, at the second synthesis point 22 and outputs the result to the load L via the first synthesis point 21 . Here, the second combining point 22 is arranged in the transmission line between the second amplifier 2 and the first combining point 21 . Also, the reactance compensating element 24 is arranged in the transmission line between the third amplifier 3 and the second combining point 22 . The electrical length of the transmission line from the second amplifier 2 to the second combining point 22 is adjusted to be an odd multiple of λ/4. Also, the electrical length of the transmission path from the third amplifier 3 to the second synthesis point 22, including the reactance compensating element 24, is adjusted so that the Doherty signals S21 and S22 are synthesized in phase at the second synthesis point 22. ing.

Table 1 illustrates the gate voltage signals Vg1, Vg2, Vg3 with respect to the relationship between the amplitude level of the power of the input signal S0 and the threshold.

Table 2 illustrates the drain voltages Vd1, Vd2, Vd3 for the operating states of the amplifier device 100. Here, "out-phase", which is one of the operating states, indicates a state in which the amplitude level of the power of the input signal S0 is higher than the threshold and the out-phase amplification section 30 is amplifying. "Doherty A", which is one of the operating states, indicates a state in which the amplitude level of the power of the input signal S0 is equal to or lower than the threshold and higher than the first determination value, and the Doherty amplifier 40 is performing amplification. "Doherty B", which is one of the operating states, indicates a state in which the amplitude level of the power of the input signal S0 is equal to or lower than the first determination value and higher than the second determination value, and the Doherty amplification section 40 is performing amplification. “Doherty C”, which is one of the operating states, indicates a state in which the amplitude level of the power of the input signal S0 is equal to or less than the second determination value and the Doherty amplifying section 40 is performing amplification. Each drain voltage Vd1, Vd2, Vd3 is shown relative to the "out-phase" condition. As shown in Table 2, the drain voltages Vd2 and Vd3 decrease in value as the state transitions from "Doherty A" to "Doherty B" to "Doherty C". Specifically, Vd1:Vd2:Vd3 is 1:1:1 in "out phase", but 1:0.73:1 in "Doherty A", and in "Doherty A" , 1:0.584:0.8, and for "Doherty A", 1:0.438:0.6. Note that the ratios illustrated in Table 2 are examples, and the ratios can be changed so as to achieve a desired backoff point.

In the amplifying apparatus 100 configured as described above, three amplifiers, the first amplifier 1, the second amplifier 2, and the third amplifier 3, are used. are shared. Then, the amplification device 100 switches between out-phase amplification and Doherty amplification according to the amplitude level of the power of the input signal. As a result, the amplifying device 100 has high efficiency even when the dynamic range is wide, and the circuit scale is small. In addition, compared to the configuration of Patent Document 1, the number of synthesis points for out-phase amplification can be reduced, so the synthesis loss can be reduced, resulting in higher efficiency.

Further, in the amplifying device 100 configured as described above, the back-off point of the Doherty amplifying section 40 decreases in a plurality of steps (three steps in this embodiment) with the first decision value and the second decision value as boundaries. As a result, the amplifying device 100 can maintain high efficiency and reduce power consumption while widening the dynamic range.

An example of the power efficiency η with respect to the backoff value of the input signal in the amplifying device 100 configured as described above will be described with reference to FIG. In FIG. 3, the backoff value indicates the average level of input signal power with reference to the designed maximum input signal power (peak power). That is, the backoff value is (average power/peak power). The backoff value is shown in dB units in FIG. A curve L1 is a curve showing the relationship between the back-off value of the input signal amplified by the out-phase amplifier 30 and the power efficiency η. The curve L1 is designed so that the back-off point when amplified by the out-phase amplifier 30 is -6dBdB. The back-off point in the out-phase amplification section 30 is the minimum back-off value at which the out-phase amplification section 30 operates in saturation. A curve L2 is a curve showing the relationship between the power efficiency η and the back-off value of the input signal amplified by the Doherty amplifier 40 in the "Doherty A" state. A curve L3 is the result of amplification by the Doherty amplifier 40 in the "Doherty B" state. Curve L4 is the result of amplification by the Doherty amplifier 40 in the "Doherty C" state. Assuming that the maximum value of the backoff value at which only the carrier amplifier (second amplifier 2) operates with respect to the maximum input signal power value in the Doherty amplifier 40 is the backoff point, "Doherty A", "Doherty B", and "Doherty C”, the back-off point is -7.5 dB. In the example shown in FIG. 3, the threshold Th1 is the point where the curve L1 and the curve L2 intersect, the threshold Th2 is the point where the curve L1 and the curve L3 intersect, and the threshold Th3 is the point where the curve L1 and the curve L4 intersect. there is The threshold Th1 is a threshold and the backoff value is about -9 dB. The threshold Th2 is the first determination value, and the backoff value is approximately -11 dB. The threshold Th3 is the second determination value, and the backoff value is approximately -13 dB.

In the example shown in FIG. 3, the back-off values that become the thresholds Th1, Th2, and Th3 are equal to or lower than the back-off points when amplified by the out-phase amplification unit 30, and "Doherty A," "Doherty B," and "Doherty C." and the intersection of the curve L1 and the curve L2, the curve L3 or the curve L4. As a result, the amplifying device 100 has the characteristics shown by the curve L5, so that a wide dynamic range of about -13 dB can be realized in a highly efficient state in which the power efficiency η is about 0.6 or more. . Therefore, for example, even if the peak power at which the desired efficiency should be obtained changes during the operation of this amplifying device 100, it can be dealt with by changing the back-off point of the Doherty amplifying section 40. FIG. Furthermore, since the drain voltages Vd2 and Vd3 are changed in a plurality of steps (three steps in the example shown in FIG. 3), the band required for the power supply unit 50 is narrower than when the drain voltage is changed continuously, and the amplification device This contributes to miniaturization of the circuit scale of 100, and also reduces control processing. Furthermore, since the drain voltages Vd2 and Vd3 are changed according to the amplitude level of the input signal S0 to realize the states of "Doherty A", "Doherty B" and "Doherty C", the drain voltages Vd2 and Vd3 is set to an excessive voltage value. As a result, the power consumption of the amplifier device 100 can be reduced, and the efficiency can be further improved.

Further, when the amplitude level of the input signal S0 is equal to or less than the threshold, the power supply unit 50 changes the power supplied to the second amplifier 2 and the third amplifier 3 in one or more stages based on the dynamic range of the input signal S0. may be configured. For example, when the dynamic range when the input signal S0 is measured for a predetermined time is within the range D1 shown in FIG. , the drain voltages Vd2 and Vd3 are changed so as to switch to "Doherty B" at the threshold value Th2. Note that the power supply unit 50 may be configured to change the drain voltage using only one of the threshold Th1 and the threshold Th2.

Further, when the dynamic range when the input signal S0 is measured for a predetermined time is within the range D2 shown in FIG. , the drain voltages Vd2 and Vd3 are changed to switch to "Doherty B" at the threshold Th2, and the drain voltages Vd2 and Vd3 are changed to switch to "Doherty C" at the threshold Th3. In addition, the power supply unit 50 may be configured to change the drain voltage with one or any two of the threshold Th1, the threshold Th2, and the threshold Th3. The dynamic range of the input signal S0 is calculated by the input power amplitude determination section 11a. The input power amplitude determination unit 11a measures the input signal S0 for a predetermined period of time and calculates the dynamic range based on the minimum and maximum values of the input signal S0.

(Embodiment 2)
FIG. 4 is a schematic configuration diagram of an amplifier according to Embodiment 2. FIG. The amplification device 100A has a configuration in which the signal generator 10 is replaced with the signal generator 10A in the amplification device 100 according to the first embodiment shown in FIG. 1, the third amplifier 3 is deleted, and third amplifiers 3A and 3B are added. have. Both the third amplifiers 3A and 3B have the same configuration as the third amplifier 3, but both of the third amplifiers 3A and 3B are configured to have the same function as the third amplifier 3. FIG. A Doherty amplifier 40A is realized by combining the second amplifier 2 and the third amplifiers 3A and 3B. That is, the third amplifiers 3A and 3B, which are a plurality of (two in this embodiment) amplifiers arranged in parallel, are configured to correspond to the third amplifier 3. FIG. A first amplifier 1, a second amplifier 2 and third amplifiers 3A and 3B form an amplifier group.

Signal generator 10A has a configuration in which DA converter 14 is removed from signal generator 10, DA converters 14A and 14B are added, mixer 17 is removed and mixers 17A and 17B are added. Both the DA converters 14A and 14B have the same configuration as the DA converter 14. FIG. Both mixers 17A and 17B have the same configuration as mixer 17. FIG. Also, the drain voltage applied to the first amplifier 1 is the drain voltage Vd1A. The drain voltage applied to the second amplifier 2 is the drain voltage Vd2A. The drain voltage applied to the third amplifier 3A is the drain voltage Vd3A. The drain voltage applied to the third amplifier 3B is the drain voltage Vd3B.

The amplification device 100A operates differently from the amplification device 100A by having two third amplifiers 3A and 3B that operate as peak amplifiers.

(When the power amplitude level of the input signal S0 is higher than the threshold)
In this case, the operation of the amplification device 100A is the same as that of the amplification device 100 described above.

(When the power amplitude level of the input signal S0 is equal to or less than the threshold)
When the amplitude level of the power of the input signal S0 is equal to or less than the threshold, the control unit 11b sets the gate voltage signal Vg1A to a voltage value that biases the first amplifier 1 to become a class C or lower amplifier or turns off the operation. A signal (which may be 0V) is output to the first amplifier 1 . Further, the control unit 11b outputs to the second amplifier 2, as the gate voltage signal Vg2A, a voltage signal having a bias value so that the second amplifier 2 becomes a class A, class AB, or class B amplifier. Further, the control unit 11b outputs to the third amplifier 3, as the gate voltage signal Vg3A, a voltage signal having a bias value so that the third amplifier 3A becomes a class C amplifier. Further, the control unit 11b outputs a voltage signal having a bias value so that the third amplifier 3B becomes a class C amplifier as the gate voltage signal Vg3B to the third amplifier 3B. Thereby, the second amplifier 2 operates as a carrier amplifier, and the third amplifiers 3A and 3B operate as peak amplifiers. That is, when the power amplitude level of the input signal S0 is lower than the threshold, the first amplifier 1 is supplied with the gate voltage signal Vg1A corresponding to the second bias voltage. The second amplifier 2 is supplied with a gate voltage signal Vg2A corresponding to the first bias voltage. The third amplifiers 3A, 3B are supplied with gate voltage signals Vg3A, Vg3B corresponding to the second bias voltage.

As shown in FIGS. 5A and 5B, when the amplitude level of the input signal S0 is equal to or less than the threshold value and higher than the first determination value, the power supply unit 50 supplies the second amplifier 2 with the first power as the drain voltage Vd2A. and a second drain voltage corresponding to the second power is applied to the third amplifiers 3A and 3B as drain voltages Vd3A and Vd3B. Further, when the amplitude level of the input signal S0 is equal to or lower than the first determination value and higher than the second determination value, the power supply unit 50 supplies the second amplifier 2 with the drain voltage Vd2A corresponding to the third power lower than the first power. A third drain voltage (lower than the first drain voltage) is applied and a fourth drain voltage (second drain voltage) corresponding to a fourth power lower than the second power is applied to the third amplifiers 3A and 3B as drain voltages Vd3A and Vd3B. voltage). Furthermore, when the amplitude level of the input signal S0 is equal to or lower than the second determination value, the power supply unit 50 supplies the second amplifier 2 with a fifth drain voltage (the fifth drain voltage) corresponding to the fifth power lower than the third power as the drain voltage Vd2A. 3 drain voltage) is applied to the third amplifiers 3A and 3B, and a sixth drain voltage (lower than the fourth drain voltage) corresponding to a sixth power lower than the fourth power is applied as the drain voltages Vd3A and Vd3B to the third amplifiers 3A and 3B. apply. In this way, the power supply unit 50 supplies power to the second amplifier 2 and the third amplifiers 3A and 3B that constitute the Doherty amplifier unit 40 based on the amplitude level of the input signal S0 in multiple stages (three stages in this embodiment). stage).

As a result, as the amplitude level of the input signal S0 decreases, the backoff point of the Doherty amplifier 40A also decreases stepwise in a plurality of steps (three steps in this embodiment) with the first decision value and the second decision value as boundaries. do.

Furthermore, when the amplitude level of the power of the input signal S0 is equal to or lower than the threshold, the control section 11b outputs a command signal to the Doherty signal generation section 11d. The Doherty signal generator 11d generates Doherty signals S21, S22A, and S22B based on the input signal S0. Here, the Doherty signals S21, S22A, and S22B are signals obtained by separating the input signal S0 into two Doherty signals S21 and S22 as well known, and further separating the Doherty signal S22 into Doherty signals S22A and S22B. However, the Doherty signals 22A and S22B are 90 degrees behind the Doherty signal S21. The Doherty signals S21, S22A, and S22B constitute a second signal group to be amplified by the Doherty amplification section 40A. The Doherty signal generator 11d outputs the Doherty signals S21, S22A, and S22B to the DA converters 13, 14A, and 14B, respectively.

The DA converters 13, 14A, 14B DA-convert the Doherty signals S21, S22A, S22B, respectively, and output to mixers 16, 17A, 17B, respectively.

Mixers 16, 17A, and 17B up-convert the DA-converted Doherty signals S21, S22A, and S22B, respectively, to RF signals, thereby forming a Doherty amplification section 40A, forming a second amplifier 2 and third amplifiers 3A, 3B. output to each of the

The second amplifier 2 and the third amplifiers 3 A and 3 B amplify the Doherty signals S 21 , S 22 A and S 22 B converted into RF signals, respectively, and output the amplified signals to the Syley synthesizer 20 . The Doherty signals S22A and S22B are combined in phase at the stage preceding the reactance compensating element 24 .

The Shire synthesizer 20 synthesizes the amplified output Doherty signal S21 and the amplified and output Doherty signals S22A and S22B in phase at the second synthesis point 22, and the first synthesis point 21 output to load L via .

The gate voltage signals Vg1A and Vg2A for the relationship between the amplitude level of the power of the input signal S0 and the threshold value in the amplification device 100A may be the same as the values of the gate voltage signals Vg1 and Vg2 exemplified in Table 1. The gate voltage signals Vg3A and Vg3B may have the same value as the gate voltage signal Vg3 illustrated in Table 1.

Also, the drain voltages Vd1A and Vd2A for the operating state of the amplifier device 100A may be the same as the values of the drain voltages Vd1 and Vd2 exemplified in Table 2. The drain voltages Vd3A and Vd3B may have the same value as the drain voltage Vd3 exemplified in Table 2.

Like the amplifier 100, the amplifier 100A configured as described above can achieve a wide dynamic range in a state where the power efficiency η is high. In addition, compared to the configuration of Patent Document 1, the number of synthesis points for out-phase amplification can be reduced, so the synthesis loss can be reduced, resulting in higher efficiency.

Further, in the amplifying device 100A configured as described above, the back-off point of the Doherty amplifying section 40A is lowered with the first judgment value and the second judgment value as boundaries, thereby widening the dynamic range and increasing the efficiency. can be maintained and power consumption can be reduced.

An example of the power efficiency η with respect to the backoff value of the input signal in the amplifying device 100A configured as described above can be expressed in the same manner as in FIG. Therefore, for example, even if the peak power at which the desired efficiency should be obtained changes during the operation of this amplifying device 100A, it can be dealt with by changing the backoff point of the Doherty amplifying section 40A. Furthermore, since the drain voltages Vd2, Vd3A, and Vd3B are changed in a plurality of steps, the band required for the power supply section 50 is narrowed, which contributes to the reduction of the circuit size of the amplifier 100A, and the control processing is reduced. Furthermore, the power consumption of the amplifier device 100A can be reduced, and even higher efficiency can be achieved.

In Embodiments 1 and 2, the maximum output powers of the first amplifier, the second amplifier, and the third amplifier may be the same or different.

Further, in the above-described embodiment, a mixer for performing up-conversion to an RF signal is provided after each DA converter. However, if an RF DAC capable of DA-converting and directly outputting an RF signal is used as each DA converter, there is no need to provide a mixer.

Also, in the above embodiment, the drain voltage applied to the second amplifier and the third amplifier is changed in three steps, but it may be changed in four or more steps, or may be changed in two steps.

Moreover, the present invention is not limited by the above embodiments. The present invention also includes a configuration obtained by appropriately combining the constituent elements of the above-described embodiments. Further effects and modifications can be easily derived by those skilled in the art. Therefore, broader aspects of the present invention are not limited to the above-described embodiments, and various modifications are possible.

1 first amplifier 2 second amplifiers 3, 3A, 3B third amplifiers 10, 10A signal generator 11 signal processing unit 11a input power amplitude determination unit 11b control unit 11c outphase signal generation unit 11d Doherty signal generation units 12, 13, 14, 14A, 14B DA converters 15, 16, 17A, 17B Mixer 20 Shire synthesizer 21 First synthesis point 22 Second synthesis point 23, 24 Reactance compensating elements 25, 26 Adjustment section 30 Out-phase amplification section 40, 40A Doherty amplification Unit 50 Power supply unit 51 Voltage control unit 100, 100A Amplifier L Load S0 Input signals S11, S12 Out-phase signals S21, S22, S22A, S22B Doherty signals Th1, Th2, Th3 Thresholds Vd1, Vd2, Vd3, Vd3A, Vd3B Drain voltage Vg1, Vg2, Vg3, Vg3A, Vg3B Gate voltage signals

Claims (7)

an amplifier group configured by arranging a plurality of amplifiers in parallel and realizing an out-phase amplifier and a Doherty amplifier by combining amplifiers;
a detection unit that detects an amplitude level of an input signal in the preceding stage of the amplifier group;
According to the amplitude level of the input signal detected by the detection unit, the input signal is amplified and output by the out-phase amplification unit, or the input signal is amplified and output by the Doherty amplification unit. a selection unit for selecting
a power supply unit that supplies power to each amplifier that constitutes the amplifier group,
The amplifier group is configured by arranging a first amplifier, a second amplifier, and a third amplifier in parallel,
The out-phase amplifier is realized by a combination of the first amplifier and the second amplifier,
The Doherty amplifier is realized by a combination of the second amplifier and the third amplifier,
The amplifying apparatus according to claim 1, wherein the power supply section changes a back-off point of the Doherty amplifying section based on the amplitude level of the input signal. The power supply section changes the power supplied to the plurality of amplifiers forming the Doherty amplification section in a plurality of stages based on the amplitude level of the input signal to change the backoff point of the Doherty amplification section. 2. An amplifier device according to claim 1. The power supply unit changes power supplied to the plurality of amplifiers constituting the Doherty amplifier unit in one or a plurality of stages based on the amplitude level and dynamic range of the input signal to back off the Doherty amplifier unit. 2. The amplifying device according to claim 1, wherein the point is changed. a first synthesis point for synthesizing the first signal group amplified and output by the out-phase amplification section; and a second synthesis point for synthesizing the second signal group amplified and output by the Doherty amplification section. wherein the second combining point is arranged between the second amplifier and the first combining point, and a reactance compensating element for compensating a reactance component generated between the amplifiers is provided between the third amplifier and the second combining point 4. The amplifier device according to any one of claims 1 to 3, further comprising a combiner arranged between and. When the amplitude level of the input signal is higher than the threshold , a first signal group is generated and output to the out-phase amplification section, and when the amplitude level of the input signal is equal to or less than the threshold , the second signal group is generated. 5. The amplifying device according to claim 1 , further comprising a signal generating section for outputting to said Doherty amplifying section. The first amplifier is supplied with a first bias voltage when the amplitude level of the input signal is higher than the threshold and a second bias voltage different from the first bias voltage when the amplitude level of the input signal is lower than the threshold. A bias voltage is supplied and
the second amplifier is supplied with the first bias voltage;
6. The amplifying device according to claim 5 , wherein said third amplifier is supplied with said second bias voltage. 7. The amplifying device according to claim 1, wherein said third amplifier comprises a plurality of amplifiers arranged in parallel.

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