JP7263891B2 - power converter - Google Patents

Description

TECHNICAL FIELD The present invention relates to a power converter, and more particularly to a power converter including a smoothing capacitor and an inverter section.

2. Description of the Related Art Conventionally, a power conversion device including a smoothing capacitor and an inverter section has been disclosed (see Patent Document 1, for example).

Patent Document 1 describes a power supply device for induction heating (power conversion device) including a DC power supply unit (AC power supply and converter unit), a smoothing unit (smoothing capacitor), an inverter unit, and an output unit. It is In the power supply device for induction heating described in Patent Document 1, the DC power supply section converts AC power supplied from a commercial AC power supply into DC power. Also, the smoothing section smoothes the pulsating current of the DC power output from the DC power supply section. Further, the inverter section inversely converts the DC power smoothed by the smoothing section into high-frequency AC power. Moreover, an output part outputs the alternating current power converted by the inverter part to a heating coil.

In the power supply device for induction heating described in Patent Document 1, the inverter section includes two bridge circuits each having a plurality of arms in which two power semiconductor elements are connected in series. The output side of the two bridge circuits is connected in parallel to the heating coil. This distributes the power supply to the heating coils over two bridge circuits. That is, in the power supply device for induction heating described in Patent Document 1, a plurality (two) of inverter units are provided on the output side of the bridge circuit so as to be connected in parallel with each other.

JP 2017-118693 A

Here, in the conventional power conversion device as described in Patent Document 1, in order to increase the capacity of power that can be supplied, the number of inverter units connected in parallel is increased to increase the current to be supplied. A method of increasing is conceivable. However, when the current is increased, it is necessary to thicken the conductor at the portion where the currents of the inverter sections connected in parallel are joined, so that the size of the apparatus is increased. In addition, since the heat loss that is lost as heat energy in the resistance (conductor) depends on the magnitude of the current, when the current increases, the energy loss (transmission loss) in the power transmission path increases. Therefore, in the conventional power conversion device as described in Patent Document 1, there is a demand to increase the capacity of power that can be supplied while suppressing the increase in size of the device and the increase in power transmission loss.

The present invention has been made to solve the above problems, and one object of the present invention is to increase the capacity of power that can be supplied while suppressing the increase in the size of the device and the increase in power transmission loss. An object of the present invention is to provide a power conversion device capable of

In order to achieve the above object, a power converter according to one aspect of the present invention includes a smoothing capacitor connected to the output side of a rectifier circuit that rectifies an AC voltage, and a semiconductor switching element section having a plurality of semiconductor switching elements. and an inverter circuit that converts the DC voltage smoothed by the smoothing capacitor into an AC voltage by switching the semiconductor switching element, and the circuit unit composed of the smoothing capacitor and the inverter section is connected in series with each other on the output side of the inverter section. Each of the plurality of circuit units includes an intra-unit connection portion that connects between the smoothing capacitor and the semiconductor switching element portion, and is connected in series with each other in the first direction Intra-unit connection portions of the plurality of circuit units arranged so as to line up are mutually orthogonal to the first direction, and are connected in series to each other and arranged so as to line up in the first direction are configured to be substantially symmetrical about a central plane between them .

In the power converter according to one aspect of the present invention, as described above, a plurality of circuit units each including a smoothing capacitor and an inverter section are provided so as to be connected in series with each other on the output side of the inverter section. As a result, the voltage across the plurality of connected inverter units is the sum of the voltages of the plurality of inverter units connected in series. The applied voltage can be increased (higher voltage). Further, since the current flowing through the inverter section is not increased, there is no need to thicken the conductor (enlarge the device) as in the case where a plurality of inverter sections are connected in parallel. Moreover, the heat loss that is lost as heat energy in the resistance (conductor) does not depend on the magnitude of the voltage, so even if the voltage of the entire inverter section increases, the energy loss (power transmission loss) does not increase. As a result, it is possible to increase the capacity of power that can be supplied while suppressing an increase in the size of the device and an increase in power transmission loss.

In the power conversion device according to the above aspect, preferably, the intra-unit connection portions of the plurality of circuit units connected in series and arranged in the first direction each include a smoothing capacitor and a semiconductor It is configured such that the inductance with the switching element section is substantially equal. Here, in the inverter section where switching of the semiconductor switching element is performed, a surge voltage (a large wave voltage instantaneously generated exceeding the steady state) may be generated when the switching element is turned ON/OFF. Further, when surge voltages of different magnitudes are generated in each of the inverter units connected in series, an unintended circulating current may flow between the inverter units connected in series. That is, in each of the inverter units connected in series, malfunctions of the device such as damage or malfunction of the device due to the surge voltage occur as compared with the case where the surge voltages are equal to each other. Note that the surge voltage depends on the current flowing through the circuit and the inductance in the circuit. Therefore, by configuring as described above, the inductance between the smoothing capacitor and the semiconductor switching element section becomes substantially equal among the plurality of circuit units, so that the surge voltage is reduced among the plurality of circuit units. It is possible to suppress the difference from becoming large. As a result, in each of the inverter units connected in series, it is possible to suppress the occurrence of malfunction of the device due to the surge voltage.

In the power converter according to the above aspect, the circuit unit preferably includes a first circuit unit and a second circuit unit connected in series to each other and arranged side by side in the first direction, and the first circuit unit The structure inside and the structure inside the second circuit unit are configured to be mutually orthogonal to the first direction and substantially symmetrical with respect to a center plane between the first circuit unit and the second circuit unit. ing. With this configuration, the in-unit connection portion of the first circuit unit and the in-unit connection portion of the second circuit unit have substantially the same shape. It is possible to easily realize a configuration in which the inductances between the smoothing capacitor and the semiconductor switching element portion are approximately equal to each other. In addition, in each of the first circuit unit and the second circuit unit, the members other than the intra-unit connection portion also have substantially the same shape, so that the first circuit unit and the second circuit unit connected in series have the same shape. , the currents that flow with each other can be suppressed from being electrically unbalanced.

In a configuration in which the first circuit unit and the second circuit unit are substantially symmetrical with respect to a center plane between the first circuit unit and the second circuit unit, preferably the first circuit unit and the second circuit Each smoothing capacitor of the unit has a substantially rectangular parallelepiped shape including a terminal arrangement surface on which terminals of the smoothing capacitor are arranged, and semiconductor switching element portions of each of the first circuit unit and the second circuit unit are arranged on the terminal arrangement surface. The first circuit unit and the second circuit unit are arranged along the intersecting side surfaces so that the terminal arrangement surface of the first circuit unit faces the terminal arrangement surface of the second circuit unit. . With this configuration, the first circuit unit and the second circuit unit are arranged such that the terminal arrangement surface of the first circuit unit and the terminal arrangement surface of the second circuit unit face each other. Compare the in-unit connections connected to the terminals of the smoothing capacitor arranged on the terminal arrangement surface of the second circuit unit with the in-unit connections connected to the terminals of the smoothing capacitor arranged on the terminal arrangement surface of the second circuit unit can be placed close to the target. Therefore, for example, in order to reduce the inductance between the smoothing capacitor and the semiconductor switching element section, in each of the first circuit unit and the second circuit unit, a If the distance is reduced, the semiconductor switching element section of the first circuit unit and the semiconductor switching element section of the second circuit unit can be arranged relatively close to each other. In this case, it is possible to suppress an increase in the connection distance when connecting the first circuit unit and the second circuit unit, thereby reducing the inductance between the smoothing capacitor and the semiconductor switching element. , the inductance in the member connecting the units can also be reduced. Further, in each of the first circuit unit and the second circuit unit, the semiconductor switching element portion is arranged along a side surface (surface different from the terminal arrangement surface) intersecting the terminal arrangement surface on which the terminals of the smoothing capacitor are arranged. By doing so, the space around the smoothing capacitor having a substantially rectangular parallelepiped shape can be reduced to a member, compared to the case where the semiconductor switching element portion is arranged along the surface on which the terminals of the smoothing capacitor are arranged (terminal arrangement surface). can be effectively used to place

In this case, preferably, an inter-unit connection section for connecting the semiconductor switching element section of the first circuit unit and the semiconductor switching element section of the second circuit unit is further provided, and the semiconductor switching element section of the first circuit unit , a plurality of semiconductor switching element sections are provided so as to be aligned in a second direction orthogonal to the first direction, and the semiconductor switching element sections of the second circuit unit correspond to each of the plurality of semiconductor switching element sections of the first circuit unit. , a plurality of the side surfaces are provided so as to be aligned in a second direction orthogonal to the first direction. With this configuration, the plurality of semiconductor switching element sections provided in the first circuit unit and the plurality of semiconductor switching element sections provided in the second circuit unit are aligned in the second direction so as to correspond to each other. , it is possible to simplify the shape of the inter-unit connecting portion that connects the semiconductor switching element portion of the first circuit unit and the semiconductor switching element portion of the second circuit unit.

In the configuration including the inter-unit connecting portion, the inter-unit connecting portion preferably includes at least one of a notch and a through hole. With this configuration, at least one of the notch and the through hole can be used to adjust the difference in the length of the current path from each of the plurality of semiconductor switching element portions of the circuit unit to be small. . As a result, it is possible to suppress an increase in the electrical imbalance of currents flowing from each of the plurality of semiconductor switching element portions of the circuit unit.

In the configuration including the inter-unit connecting portion, preferably, the inter-unit connecting portion has a shape along the first direction and substantially symmetrical with respect to a center line of the inter-unit connecting portion in the second direction. With this configuration, the length of the current path from each of the plurality of semiconductor switching element portions of the circuit unit becomes substantially equal on the one side and the other side in the second direction centering on the center line. It is possible to suppress an increase in the electrical imbalance of the currents flowing from each of the plurality of semiconductor switching element portions.

In the configuration including the inter-unit connecting portion, preferably, the inter-unit connecting portion is provided at a position corresponding to the plurality of semiconductor switching element portions of the first circuit unit so as to extend along the second direction. a second portion extending in the second direction at positions corresponding to the plurality of semiconductor switching element portions of the second circuit unit; and the first portion and the second portion. , and a third portion provided separately from the first portion and the second portion so as to extend in the first direction. With this configuration, the third portion is provided separately from the first portion provided in the first circuit unit and the second portion in the second circuit unit. , are connected to the first circuit unit and the second circuit unit, and the third part is treated as a connecting part for connecting the units, thereby improving workability during assembly and maintenance of the device. be able to.

According to the present invention, as described above, it is possible to increase the capacity of power that can be supplied while suppressing an increase in the size of the device and an increase in power transmission loss.

1 is a circuit diagram of a power converter according to one embodiment of the present invention; FIG. BRIEF DESCRIPTION OF THE DRAWINGS It is the perspective view which showed the outline of the structure of the power converter by one Embodiment of this invention. 1 is a perspective view of a stack of power converters according to one embodiment of the present invention; FIG. 1 is an exploded perspective view (1) of a stack of power converters according to an embodiment of the present invention; FIG. BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing (side view) of the power converter device by one Embodiment of this invention. FIG. 2 is an exploded perspective view (2) of the power converter according to one embodiment of the present invention; FIG. 2 is a front view for explaining an arrangement between stacks of power converters according to an embodiment of the present invention; FIG. 2 is a side view for explaining the arrangement between stacks of power converters according to an embodiment of the present invention;

Embodiments embodying the present invention will be described below with reference to the drawings.

A configuration of a power converter 100 according to an embodiment of the present invention will be described with reference to FIGS. 1 to 8. FIG. The power conversion device 100 is for an induction heating device 200 used in a melting furnace that melts metal by induction heating. The power converter 100 is configured to generate alternating current from an alternating current power supply 300 using a semiconductor switching element 31 .

(Circuit configuration of power converter)
First, the circuit configuration of the power converter 100 will be described with reference to FIG.

As shown in FIG. 1, the power conversion device 100 includes a plurality of rectifier circuits 10 (rectifier circuits 10a to 10d), a plurality of smoothing capacitors 20 (smoothing capacitors 20a to 20d), a plurality of inverter units 30 (inverter unit 30a ~30d).

Rectifier circuit 10 converts an AC voltage input from AC power supply 300 into a DC voltage. A plurality (two) of rectifier circuits 10 are provided for one AC power supply 300 . That is, a rectifier circuit 10a and a rectifier circuit 10b are provided for an AC power supply 301 (transformer 301). A rectifier circuit 10c and a rectifier circuit 10d are provided for the AC power supply 302 (transformer 302). The anode and cathode sides of the rectifier circuit 10a are electrically connected to the anode and cathode sides of the rectifier circuit 10c, respectively. Also, the anode side and the cathode side of the rectifier circuit 10b are electrically connected to the anode side and the cathode side of the rectifier circuit 10d, respectively.

The smoothing capacitor 20 is connected to the output side of the rectifier circuit 10 that rectifies the AC voltage. A smoothing capacitor 20 is provided for each rectifier circuit 10 . That is, smoothing capacitors 20a, 20b, 20c and 20d are connected to the output sides of rectifier circuits 10a, 10b, 10c and 10d, respectively. The positive and negative sides of the smoothing capacitor 20a are electrically connected to the positive and negative sides of the smoothing capacitor 20c, respectively. The positive and negative sides of the smoothing capacitor 20b are electrically connected to the positive and negative sides of the smoothing capacitor 20d, respectively.

The inverter unit 30 converts the DC voltage smoothed by the rectifier circuit 10 into an AC voltage by switching the semiconductor switching element 31 . Then, the converted AC voltage is output from the inverter section 30 to the induction heating coil 210 of the induction heating device 200 . Also, the inverter unit 30 is provided for each rectifier circuit 10 . That is, inverter units 30a, 30b, 30c and 30d are provided for rectifier circuits 10a, 10b, 10c and 10d, respectively.

Inverter section 30 includes a semiconductor module 32 (semiconductor module 32 a and semiconductor module 32 b ) having a plurality of semiconductor switching elements 31 . The semiconductor module 32a accommodates a semiconductor switching element 31a and a semiconductor switching element 31b. Semiconductor switching element 31c and semiconductor switching element 31d are housed in semiconductor module 32b. The semiconductor module 32 is an example of the "semiconductor switching element section" in the claims.

Although not shown in FIG. 1, the semiconductor modules 32a and 32b each have a plurality of semiconductor modules connected in parallel, for example, six parallel connections. A full bridge circuit is configured by the semiconductor switching elements 31a to 31d. A connection point between semiconductor switching element 31a and semiconductor switching element 31b of inverter section 30a (inverter section 30c) is electrically connected to one end of induction heating coil 210 . A connection point between semiconductor switching element 31c and semiconductor switching element 31d of inverter section 30b (inverter section 30d) is electrically connected to the other end of induction heating coil 210 .

In the power conversion device 100 , a stack (circuit unit) 40 is configured by the smoothing capacitor 20 and the inverter section 30 . A plurality of stacks 40 (stacks 40a to 40d) are provided. Note that the stack 40a and the stack 40c are examples of the "first circuit unit" in the claims. Also, the stack 40b and the stack 40d are examples of the "second circuit unit" in the claims.

Specifically, a stack 40a is configured by the smoothing capacitor 20a and the inverter section 30a. A stack 40b is configured by the smoothing capacitor 20b and the inverter section 30b. A stack 40c is configured by the smoothing capacitor 20c and the inverter section 30c. A stack 40d is configured by the smoothing capacitor 20d and the inverter section 30d.

Here, in the present embodiment, the stack 40 composed of the smoothing capacitor 20 and the inverter section 30 is connected in series with each other on the output side of the inverter section 30 . Specifically, the output side of the inverter section 30a of the stack 40a and the output side of the inverter section 30b of the stack 40b are electrically connected in series. Also, the output side of the inverter section 30c of the stack 40c and the output side of the inverter section 30d of the stack 40d are electrically connected in series.

Specifically, the connection point between the semiconductor switching elements 31c and 31d of the inverter section 30a and the connection point between the semiconductor switching elements 31a and 31b of the inverter section 30b are electrically connected. A connection point between the semiconductor switching elements 31c and 31d of the inverter section 30c and a connection point between the semiconductor switching elements 31a and 31b of the inverter section 30d are electrically connected.

(Overview of structure of power converter)
Next, with reference to FIG. 2, the outline of the structure of the power conversion device 100 will be described.

As shown in FIG. 2 , in power converter 100 , two stacks 40 (stack 40 a and stack 40 b ) are arranged side by side in the vertical direction (Z direction) in one housing 50 . The stack 40a and the stack 40b are arranged on the lower side (Z2 side) and the upper side (Z1 side) of the housing 50, respectively. Although not shown in FIG. 2, the arrangement configuration of the stacks 40c and 40d is substantially the same as the arrangement configuration of the stacks 40a and 40b.

In the following description, the up-down direction, left-right direction, and front-rear direction of the housing 50 are defined as the Z direction, the X direction, and the Y direction, respectively. Moreover, the upward direction (upper side), downward direction (lower side), left side, right side, front side and rear side are defined as Z1 direction (Z1 side), Z2 direction (Z2 side), X1 side, X2 side, Y1 side and Y1 side, respectively. Y2 side. Note that the Z direction and the Y direction are examples of the "first direction" and the "second direction" in the scope of claims, respectively.

(stack structure)
Next, the structure of the stack 40 will be described with reference to FIGS. 3-6. 3 to 6, the stack 40 will be described using the arrangement (orientation) of the stack 40a shown in FIG.

As shown in FIGS. 3 and 4, smoothing capacitor 20 is a film capacitor having a substantially rectangular parallelepiped shape. As shown in FIG. 4, the smoothing capacitor 20 includes a terminal placement surface 22 on which the terminals 21 of the smoothing capacitor 20 are arranged linearly. The terminal arrangement surface 22 is the surface of the smoothing capacitor 20 on the Z1 side. Moreover, the terminal 21 includes a positive terminal 21p and a negative terminal 21n. The positive terminals 21p and the negative terminals 21n are alternately arranged on the terminal arrangement surface 22 along the Y direction.

The semiconductor module 32 includes a positive terminal 32p, a negative terminal 32n, and an output terminal 32o. The positive terminal 32p, the negative terminal 32n, and the output terminal 32o are arranged in this order from the Z1 side to the Z2 side.

The semiconductor module 32 is arranged along the side surface 23 of the smoothing capacitor 20 that intersects the terminal arrangement surface 22 that is symmetrical with respect to the linearly arranged terminals 21 . A plurality of semiconductor modules 32 are provided on the side surface 23 so as to be aligned in the Y direction. Specifically, among the plurality of semiconductor modules 32, for example, six parallel (six) semiconductor modules 32a are arranged along the Y direction on the side surface 23a of the smoothing capacitor 20 on the X2 side. As shown in FIG. 5, six parallel (six) semiconductor modules 32b are arranged along the Y direction on the side surface 23b of the smoothing capacitor 20 on the X1 side. The semiconductor module 32 is arranged such that the surface of the semiconductor module 32 (the surface on which the positive side terminal 32p, the negative side terminal 32n, and the output terminal 32o are provided) is along the side surface 23 .

Further, as shown in FIG. 4, the semiconductor module 32 is arranged near the terminal arrangement surface 22 in the Z direction. Specifically, the semiconductor module 32 is arranged on the Z1 side of the center C of the semiconductor module 32 in the Z direction. Thereby, the distance between the positive terminal 32p of the semiconductor module 32 and the positive terminal 21p of the smoothing capacitor 20 can be made relatively small. Also, the distance between the negative terminal 32n of the semiconductor module 32 and the negative terminal 21n of the smoothing capacitor 20 can be made relatively small. As a result, a bus bar connecting between the positive terminal 32p of the semiconductor module 32 and the positive terminal 21p of the smoothing capacitor 20 and between the negative terminal 32n of the semiconductor module 32 and the negative terminal 21n of the smoothing capacitor 20 is formed. 60 (described later) can be reduced in inductance.

Also, as shown in FIG. 5, with respect to the terminals 21 of the smoothing capacitor 20, the semiconductor module 32a arranged on the side surface 23a on the X2 side with respect to the smoothing capacitor 20 has a height h1 and the side surface 23b on the X1 side. The height position h2 of the semiconductor module 32b with respect to the smoothing capacitor 20 is substantially equal. Specifically, the height h1 of the Z1 side end of the semiconductor module 32a and the height h2 of the Z1 side end of the semiconductor module 32b are substantially equal. Also, the height positions h1 of the six semiconductor modules 32a are equal to each other. Also, the height positions h2 of the six semiconductor modules 32b are equal to each other.

In addition, as shown in FIG. 3, the stack 40 is provided with a busbar 60 (positive busbar 61 and negative busbar 62) that connects the smoothing capacitor 20 and the semiconductor module 32 together. Positive bus bar 61 is electrically connected to positive terminal 32 p of semiconductor module 32 and positive terminal 21 p of smoothing capacitor 20 . Negative bus bar 62 is electrically connected to negative terminal 32 n of semiconductor module 32 and negative terminal 21 n of smoothing capacitor 20 . It should be noted that the bus bar 60 is an example of an "internal connection portion" in the scope of claims.

Here, in the power conversion device 100, the plurality of semiconductor modules 32 are arranged on the terminal arrangement surface 22 such that the impedances (each impedance) between each of the plurality of semiconductor modules 32 and the smoothing capacitor 20 are substantially equal. On the other hand, it is arranged on both the side surface 23a on the X2 side and the side surface 23b on the X1 side.

Specifically, as shown in FIG. 5, a positive side bus bar 61 between the positive side terminal 32p of the semiconductor module 32a arranged on one side (side surface 23a) of the smoothing capacitor 20 and the terminal 21 of the smoothing capacitor 20. The distance L1 above (the distance indicated by the dashed-dotted line in FIG. 5) is between the positive terminal 32p of the semiconductor module 32b arranged on the other side (side surface 23b) of the smoothing capacitor 20 and the terminal 21 of the smoothing capacitor 20. is approximately equal to the distance L2 on the positive side bus bar 61 of . Also, the distance L11 on the negative bus bar 62 between the negative terminal 32n of the semiconductor module 32a and the terminal 21 of the smoothing capacitor 20 is the distance between the negative terminal 32n of the semiconductor module 32b and the terminal 21 of the smoothing capacitor 20 is approximately equal to the distance L12 on the negative bus bar 62 between. As a result, the impedance (each impedance) between each of the plurality of semiconductor modules 32 and the smoothing capacitor 20 can be made substantially equal. can be planned.

Moreover, in the power conversion device 100 , as shown in FIG. 4 , the positive side bus bar 61 and the negative side bus bar 62 are each provided in common for the plurality of semiconductor modules 32 . As shown in FIG. 5, each of the positive bus bar 61 and the negative bus bar 62 has a substantially U-shape covering the terminal arrangement surface 22 and the area of both the side surfaces 23a and 23b of the smoothing capacitor 20. . Specifically, a positive side bus bar 61 and a negative side bus bar 62 are stacked in this order on the smoothing capacitor 20 . That is, the substantially U-shaped positive side bus bar 61 is arranged inside the substantially U-shaped negative side bus bar 62 . Moreover, each of the positive side bus bar 61 and the negative side bus bar 62 is formed by bending one metal plate. As a result, the inductance of the bus bar 60 can be reduced compared to the case where the bus bar 60 is connected to a plurality of metal plates.

Also, as shown in FIG. 6, an insulating paper 70 is arranged between the positive bus bar 61 and the negative bus bar 62 . A plurality of insulating papers 70 are provided in an overlapping manner. That is, the bus bar 60 is a bus bar having a laminated structure in which a conductive layer and an insulating layer are laminated.

As shown in FIG. 5, the positive bus bar 61 has a first portion 61a extending along the X direction and a second portion 61b extending from both ends of the first portion 61a in the X direction toward the Z2 side. ,including. Further, the negative bus bar 62 includes a first portion 62a extending along the X direction and a second portion 62b extending toward the Z2 side from both ends of the first portion 62a in the X direction. A length L21 of the first portion 61a of the positive bus bar 61 along the X direction is smaller than a length L22 of the first portion 62a of the negative bus bar 62 along the X direction. Also, the length L31 along the Z direction of the second portion 61b of the positive bus bar 61 is smaller than the length L32 along the Z direction of the second portion 62b of the negative bus bar 62 .

The positive bus bar 61 has a leg portion 61c connected to the positive terminal 32p of the semiconductor module 32a and the positive terminal 32p of the semiconductor module 32b. Moreover, the negative bus bar 62 has a leg portion 62c connected to the negative terminal 32n of the semiconductor module 32a and the negative terminal 32n of the semiconductor module 32b. A leg portion 61 c of the positive bus bar 61 is connected to the positive terminal 32 p of the semiconductor module 32 by a screw 71 . A leg portion 62 c of the negative bus bar 62 is connected to the negative terminal 32 n of the semiconductor module 32 by a screw 71 . Further, the leg portion 61c and the leg portion 62c are provided along the X direction. Also, the length L41 along the X direction of the leg portion 61c of the positive side bus bar 61 is smaller than the length L42 along the X direction of the leg portion 62c of the negative side bus bar 62 .

A distance D1 along the Z direction between the first portion 61a of the positive busbar 61 and the first portion 62a of the negative busbar 62 is relatively small. Also, the distance D2 along the X direction between the second portion 61b of the positive bus bar 61 and the second portion 62b of the negative bus bar 62 is relatively small. On the other hand, the interval D3 along the Z direction between the leg portion 61c of the positive busbar 61 and the leg portion 62c of the negative busbar 62 is relatively large. However, of the entire area of the positive bus bar 61, only the leg portion 61c (relatively small area) has a relatively large gap from the negative bus bar 62. FIG. As a result, the positive bus bar 61 and the negative bus bar 62 are laminated with the insulating paper 70 interposed therebetween, so that the leg portion 61c has the effect of reducing the inductance of the bus bar 60 (the positive bus bar 61 and the negative bus bar 62). (Leg 62c) has little influence.

Further, as shown in FIG. 6, the positive bus bar 61 is provided with a plurality of holes 61d. Further, the negative bus bar 62 is provided with a plurality of holes 62d. Further, the insulating paper 70 is provided with a plurality of holes 70a. A screw 71 is screwed to the positive terminal 21p of the smoothing capacitor 20 from the Z1 side through the hole 62d of the negative bus bar 62, the hole 70a of the insulating paper 70, and the positive bus bar 61. As shown in FIG. As a result, the positive bus bar 61 is connected to the positive terminal 21 p of the smoothing capacitor 20 . A screw 71 is screwed to the negative terminal 21n of the smoothing capacitor 20 from the Z1 side through the negative bus bar 62, the hole 70a of the insulating paper 70, and the hole 61d of the positive bus bar 61. Thereby, the negative bus bar 62 is connected to the negative terminal 21n of the smoothing capacitor 20 .

(configuration between multiple stacks)
Next, with reference to FIGS. 7 and 8, the configuration between the stacks 40 of the power conversion device 100 will be described.

As shown in FIG. 7, in this embodiment, each of the stacks 40 includes a bus bar 60 connecting between the smoothing capacitor 20 and the semiconductor module 32 . The busbars 60 are configured such that the inductances between the smoothing capacitors 20 and the semiconductor modules 32 are substantially equal to each other.

Specifically, as shown in FIGS. 7 and 8, busbars 60 of stack 40a and busbars 60 of stack 40b are positioned perpendicular to each other in the Z direction and in a central plane 90 in the middle between stacks 40a and 40b. It is configured so as to be substantially symmetrical with respect to. That is, in the power conversion device 100, the structures in the plurality of stacks 40 (stacks 40a to 40d) (the shapes of the members in the stack 40 and the relative arrangement between the members in the stack 40) are substantially equal to each other. is configured to be

Specifically, as shown in FIG. 7, in the power converter 100, the stacks 40a and 40b are arranged such that the terminal arrangement surface 22 of the stack 40a and the terminal arrangement surface 22 of the stack 40b face each other. . That is, the stack 40a is arranged on the lower side (Z2 side) of the housing 50 so that the terminal arrangement surface 22 is on the upper side (Z1 side). Also, the stack 40b is arranged on the upper side of the housing 50 so that the terminal arrangement surface 22 faces downward.

Accordingly, the first portion 61a (first portion 62a) of the positive bus bar 61 (negative bus bar 62) of the stack 40a is arranged on the upper side (Z1 side) of the stack 40a. A first portion 61a (first portion 62a) of the positive bus bar 61 (negative bus bar 62) of the stack 40b is arranged on the lower side (Z2 side) of the stack 40b.

In addition, the semiconductor modules 32 of the stack 40a are arranged on the side surface 23 so as to line up in the Y direction perpendicular to the Z direction. In addition, the semiconductor modules 32 of the stack 40b are arranged in a plurality in the Y direction perpendicular to the Z direction on the side surface 23 so as to correspond to each of the plurality of semiconductor modules 32 of the stack 40a. .

Here, in this embodiment, as shown in FIG. 8, the power conversion device 100 includes a bus bar 80 that connects the semiconductor modules 32 of the stack 40a and the semiconductor modules 32 of the stack 40b. The bus bar 80 is an example of an "inter-unit connection" in the claims.

Specifically, the busbar 80 has a shape along the Z direction and substantially symmetrical with respect to a center line 91 of the busbar 80 in the Y direction. The bus bar 80 is provided so as to connect the first portion 81 provided on the stack 40a side, the second portion 82 provided on the stack 40b side, and the first portion 81 and the second portion 82. a third portion 83;

Specifically, the first portion 81 is provided so as to extend along the Y direction at positions corresponding to the plurality of semiconductor modules 32 of the stack 40a. The second portion 82 is provided to extend along the Y direction at positions corresponding to the plurality of semiconductor modules 32 of the stack 40b. Also, the third portion 83 is provided to extend in the Z direction so as to connect the first portion 81 and the second portion 82 .

The first part 81 , the second part 82 and the third part 83 are provided separately from each other, and the distance between the first part 81 and the third part 83 and between the second part 82 and the third part 83 are fastened with bolts and nuts. Also, the third portion 83 is arranged substantially in the center of the first portion 81 and the second portion 82 in the Y direction.

Moreover, in this embodiment, the busbar 80 includes a through hole 80a. More specifically, slit-like through holes 80a extending in the Y direction are provided in substantially the central portion of the first portion 81 and substantially the central portion of the second portion 82, respectively. The length of the through hole 80a in the Y direction is longer than the length of the third portion 83 in the Y direction.

(Effect of Embodiment)
The following effects can be obtained in this embodiment.

In this embodiment, as described above, a plurality of stacks 40 each including the smoothing capacitor 20 and the inverter section 30 are provided so as to be connected in series with each other on the output side of the inverter section 30 . As a result, the voltage across the plurality of connected inverter units 30 is the sum of the voltages of the plurality of inverter units 30 connected in series. The voltage output from the device 100 can be increased (higher voltage). Further, since the current flowing through the inverter section 30 is not increased, there is no need to thicken the conductor (to increase the size of the power converter 100) as in the case where the plurality of inverter sections 30 are connected in parallel. Moreover, since the heat loss that is lost as heat energy in the resistance (conductor) does not depend on the magnitude of the voltage, even if the voltage of the entire inverter section 30 increases, the energy loss (power transmission loss) does not increase. As a result, it is possible to increase the capacity of power that can be supplied while suppressing an increase in size of the power converter 100 and an increase in power transmission loss.

Further, in this embodiment, as described above, each of the plurality of stacks 40 is configured to include the bus bar 60 connecting between the smoothing capacitor 20 and the semiconductor module 32 . The busbars 60 of each of the multiple stacks 40 are configured such that the inductance between the smoothing capacitor 20 and the semiconductor module 32 is substantially equal. As a result, the inductances between the smoothing capacitors 20 and the semiconductor modules 32 of the plurality of stacks 40 are substantially equal to each other, thereby suppressing an increase in the difference in surge voltage among the plurality of stacks 40. be able to. As a result, in each of the inverter units 30 connected in series, it is possible to suppress the occurrence of malfunction of the power conversion device 100 due to the surge voltage.

Further, in the present embodiment, as described above, the stack 40 is configured to include the stack 40a (stack 40c) and the stack 40b (stack 40d) that are connected in series and arranged side by side in the Z direction. do. Then, the structure in the stack 40a (stack 40c) and the structure in the stack 40b (stack 40d) are arranged perpendicular to the Z direction and in the center between the stack 40a (stack 40c) and the stack 40b (stack 40d). It is configured to be substantially symmetrical with respect to the central plane 90 . As a result, the busbars 60 of the stack 40a (stack 40c) and the busbars 60 of the stack 40b (stack 40d) have substantially the same shape. It is possible to easily realize a configuration in which the inductances between the smoothing capacitor 20 and the semiconductor module 32 are approximately equal to each other. In each of the stack 40a (stack 40c) and the stack 40b (stack 40d), members other than the bus bar 60 also have substantially the same shape. 40d), it is possible to suppress the electric imbalance between the currents flowing with each other.

Further, in the present embodiment, as described above, each of the smoothing capacitors 20 of the stack 40a (stack 40c) and the stack 40b (stack 40d) is provided with the terminal arrangement surface 22 on which the terminals 21 of the smoothing capacitor 20 are arranged. It is configured to have a rectangular parallelepiped shape. Further, semiconductor modules 32 of each of stack 40 a (stack 40 c ) and stack 40 b (stack 40 d ) are arranged along side surface 23 intersecting terminal arrangement surface 22 . Then, the stack 40a (stack 40c) and the stack 40b (stack 40d) are arranged such that the terminal arrangement surface 22 of the stack 40a (stack 40c) faces the terminal arrangement surface 22 of the stack 40b (stack 40d). As a result, the stack 40a (stack 40c) and the stack 40b (stack 40d) are arranged such that the terminal arrangement surface 22 of the stack 40a (stack 40c) faces the terminal arrangement surface 22 of the stack 40b (stack 40d). Therefore, the bus bar 60 connected to the terminal 21 of the smoothing capacitor 20 arranged on the terminal arrangement surface 22 of the stack 40a (stack 40c) and the smoothing capacitor 20 arranged on the terminal arrangement surface 22 of the stack 40b (stack 40d) The busbars 60 connected to the terminals 21 can be arranged relatively close to each other. Therefore, in order to reduce the inductance between smoothing capacitor 20 and semiconductor module 32, in each of stack 40a (stack 40c) and stack 40b (stack 40d), between smoothing capacitor 20 and semiconductor module 32 in bus bar 60 When the distance is reduced, the semiconductor modules 32 of the stack 40a (stack 40c) and the semiconductor modules 32 of the stack 40b (stack 40d) can be arranged relatively close to each other. As a result, it is possible to suppress an increase in the connection distance when connecting the stack 40a (stack 40c) and the stack 40b (stack 40d). can be reduced, and the inductance in the member (bus bar 80) connecting the stacks 40 can also be reduced. In each of the stack 40a (stack 40c) and the stack 40b (stack 40d), the semiconductor module 32 is arranged on the side surface 23 (the terminal arrangement surface 22 is By arranging the semiconductor module 32 along a different plane), the semiconductor module 32 has a substantially rectangular parallelepiped shape compared to the case where the semiconductor module 32 is arranged along the plane (terminal arrangement surface 22) on which the terminals 21 of the smoothing capacitor 20 are arranged. The space around the smoothing capacitor 20 can be effectively used for arranging components.

Further, in the present embodiment, as described above, the power conversion device 100 is configured to include the bus bar 80 that connects the semiconductor modules 32 of the stack 40a (stack 40c) and the semiconductor modules 32 of the stack 40b (stack 40d). do. A plurality of semiconductor modules 32 of the stack 40a (stack 40c) are arranged in the Y direction orthogonal to the Z direction on the side surface 23 intersecting the terminal arrangement surface 22. As shown in FIG. In addition, the semiconductor modules 32 of the stack 40b (stack 40d) are arranged so as to correspond to each of the plurality of semiconductor modules 32 of the stack 40a (stack 40c). A plurality of them are provided so as to line up in the Y direction. As a result, the plurality of semiconductor modules 32 provided in the stack 40a (stack 40c) and the plurality of semiconductor modules 32 provided in the stack 40b (stack 40d) are aligned in the Y direction so as to correspond to each other. Therefore, the shape of the bus bar 80 that connects the semiconductor modules 32 of the stack 40a (stack 40c) and the semiconductor modules 32 of the stack 40b (stack 40d) can be simplified.

Further, in the present embodiment, as described above, the busbar 80 is configured to include the through hole 80a. Thus, the through holes 80a can be used to reduce the difference in the length of the current path from each of the plurality of semiconductor modules 32 (arranged in the Y direction) of the stack 40. FIG. As a result, it is possible to suppress an increase in the electrical imbalance of currents flowing from each of the plurality of semiconductor modules 32 of the stack 40 .

Further, in the present embodiment, as described above, the busbar 80 is configured to have a shape along the Z direction and substantially symmetrical with respect to the center line 91 of the busbar 80 in the Y direction. As a result, the length of the current path from each of the plurality of semiconductor switching element portions of the stack 40 becomes substantially equal on one side (Y1 side) and the other side (Y2 side) in the Y direction centering on the center line 91. Therefore, it is possible to suppress an increase in the electrical imbalance of currents flowing from each of the plurality of semiconductor modules 32 of the stack 40 .

Further, in the present embodiment, the busbar 80 is configured to include the first portion 81, the second portion 82, and the third portion 83, as described above. First portions 81 are provided to extend in the Y direction at positions corresponding to the plurality of semiconductor modules 32 of the stack 40a. Further, second portions 82 are provided so as to extend along the Y direction at positions corresponding to the plurality of semiconductor modules 32 of the stack 40b. A third portion 83 is provided separately from the first portion 81 and the second portion 82 so as to extend in the Z direction so as to connect the first portion 81 and the second portion 82 . As a result, the third portion 83 is provided separately from the first portion 81 provided on the stack 40a (stack 40c) and the stack 40b (stack 40d) from the second portion 82. By treating the portion 82 as each unit connected to the stack 40a and the stack 40b, and treating the third portion 83 as a connection portion that connects the units, the assembly and maintenance of the power conversion device 100 can be facilitated. Workability can be improved.

[Modification]
The embodiments disclosed this time should be considered illustrative and not restrictive in all respects. The scope of the present invention is indicated by the scope of the claims rather than the description of the above-described embodiments, and includes all modifications (modifications) within the scope and meaning equivalent to the scope of the claims.

For example, in the above embodiment, the bus bar 80 is arranged between the first portion 81 provided at positions corresponding to the plurality of semiconductor modules 32 of the stack 40a (stack 40c) and the plurality of semiconductor modules 32 of the stack 40b (stack 40d). A second portion 82 provided at a corresponding position, and a third portion 83 provided separately from the first portion 81 and the second portion 82 so as to connect the first portion 81 and the second portion 82. Although an example configured to include and is shown, the present invention is not limited to this. In the present invention, the "inter-unit connecting portion" may be configured to be provided as one member in which the first portion, the second portion and the third portion are integrally provided.

Moreover, in the above-described embodiment, an example in which the bus bar 80 is configured to include the through hole 80a is shown, but the present invention is not limited to this. In the present invention, the "connecting portion between units" may be configured to include a notch instead of the through hole. Also, the "inter-unit connection" may be configured to include both a through hole and a notch.

In the above embodiment, the semiconductor modules 32 of the stack 40a (stack 40c) are arranged in the Y direction, and the semiconductor modules 32 of the stack 40b (stack 40d) are arranged in the stack 40a (stack 40c). Although an example in which a plurality of them are arranged in the Y direction so as to correspond to each of the semiconductor modules 32 has been shown, the present invention is not limited to this. In the present invention, the "semiconductor switching element section" of the "first circuit unit" and the "semiconductor switching element section" of the "second circuit unit" may be arranged in plural so as to be arranged in different directions. good.

Further, in the above embodiment, each of the smoothing capacitors 20 of the stack 40a (stack 40c) and the stack 40b (stack 40d) has a substantially rectangular parallelepiped shape including the terminal arrangement surface 22 on which the terminals 21 of the smoothing capacitor 20 are arranged. and the stack 40a (stack 40c) and the stack 40b (stack 40d) are arranged such that the terminal arrangement surface 22 of the stack 40a (stack 40c) faces the terminal arrangement surface 22 of the stack 40b (stack 40d). However, the present invention is not limited to this. In the present invention, the "first circuit unit" and the "second circuit unit" may be arranged so that the terminal arrangement surface of the "first circuit unit" and the terminal arrangement surface of the "second circuit unit" do not face each other. good.

Further, in the above embodiment, each of the smoothing capacitors 20 of the stack 40a (stack 40c) and the stack 40b (stack 40d) has a substantially rectangular parallelepiped shape including the terminal arrangement surface 22 on which the terminals 21 of the smoothing capacitor 20 are arranged. , and the semiconductor modules 32 of each of the stack 40a (stack 40c) and the stack 40b (stack 40d) are arranged along the side surface 23 intersecting the terminal arrangement surface 22, but the present invention It is not limited to this. In the present invention, the "semiconductor switching element portion" of each of the "first circuit unit" and the "second circuit unit" is arranged on a side surface other than the side surface intersecting the terminal arrangement surface such as the terminal arrangement surface on which the terminals of the smoothing capacitor are arranged. You can place it along.

In the above embodiment, the stack 40 includes two stacks 40 (stack 40a (stack 40c) and stack 40b (stack 40d)) connected in series and arranged side by side in the Z direction. Although the configured example is shown, the present invention is not limited to this. In the present invention, the "circuit unit" may be configured to include three or more "circuit units" that are connected in series and arranged side by side.

For example, in the above embodiment, the stack 40a (stack 40c) and the stack 40b (stack 40d) are positioned perpendicular to the Z direction and at the center between the stack 40a (stack 40c) and the stack 40b (stack 40d). Although an example in which it is configured to be substantially symmetrical with respect to the surface 90 has been shown, the present invention is not limited to this. In the present invention, the "first circuit unit" and the "second circuit unit" are substantially symmetrical with respect to a plane other than the central plane between the "first circuit unit" and the "second circuit unit". It may be configured as Also, the "first circuit unit" and the "second circuit unit" may be configured asymmetrically with each other. In that case, it is desirable to configure the "first circuit unit" and the "second circuit unit" such that the inductances between the smoothing capacitors and the "semiconductor switching element section" are substantially equal to each other.

10 (10a, 10b, 10c, 10d) rectifier circuit 20 (20a, 20b, 20c, 20d) smoothing capacitor 21 terminal (of smoothing capacitor) 22 terminal arrangement surface 23 side surface (crossing terminal arrangement surface) 30 (30a, 30b) , 30c, 30d) inverter section 31 (31a, 31b, 31c, 31d) semiconductor switching element 32 (32a, 32b) semiconductor module (semiconductor switching element section)
40 stack (circuit unit)
40a, 40c stack (first circuit unit)
40b, 40d stack (second circuit unit)
60 Bus bar (connection inside the unit)
80 Bus bar (connection between units)
80a through hole 81 first part (connection between units) 82 second part (connection between units) 83 third part (connection between units) 90 (between first circuit unit and second circuit unit center plane 91 center line (in the second direction of the inter-unit connection) 100 power converter

Claims (8)

a smoothing capacitor connected to the output side of a rectifier circuit that rectifies an alternating voltage;
an inverter unit including a semiconductor switching element unit having a plurality of semiconductor switching elements, and converting the DC voltage smoothed by the smoothing capacitor into an AC voltage by switching the semiconductor switching elements;
with
A plurality of circuit units each including the smoothing capacitor and the inverter section are provided so as to be connected in series with each other on the output side of the inverter section,
each of the plurality of circuit units includes an intra-unit connection section that connects between the smoothing capacitor and the semiconductor switching element section;
The intra-unit connection portions of the plurality of circuit units connected in series to each other and arranged to line up in the first direction are orthogonal to the first direction and connected in series to each other. A power conversion device configured to be substantially symmetrical with respect to a center plane between the plurality of circuit units arranged so as to line up in a first direction. Each of the intra-unit connection portions of the plurality of circuit units connected in series and arranged in the first direction has an inductance between the smoothing capacitor and the semiconductor switching element portion. 2. The power converter according to claim 1, wherein is configured such that . the circuit unit includes a first circuit unit and a second circuit unit connected in series and arranged side by side in a first direction;
The structure in the first circuit unit and the structure in the second circuit unit are mutually orthogonal to the first direction and with respect to a central plane between the first circuit unit and the second circuit unit. 3. The power conversion device according to claim 1 or 2, which is configured so as to be substantially symmetrical. each of the smoothing capacitors of the first circuit unit and the second circuit unit has a substantially rectangular parallelepiped shape including a terminal arrangement surface on which terminals of the smoothing capacitor are arranged;
The semiconductor switching element portions of each of the first circuit unit and the second circuit unit are arranged along a side surface intersecting the terminal arrangement surface,
4. The first circuit unit and the second circuit unit according to claim 3, wherein the terminal arrangement surface of the first circuit unit faces the terminal arrangement surface of the second circuit unit. power converter. further comprising an inter-unit connection section that connects the semiconductor switching element section of the first circuit unit and the semiconductor switching element section of the second circuit unit;
A plurality of the semiconductor switching element portions of the first circuit unit are provided on the side surface so as to be aligned in a second direction orthogonal to the first direction,
The semiconductor switching element portion of the second circuit unit extends in the second direction orthogonal to the first direction on the side surface so as to correspond to each of the plurality of semiconductor switching element portions of the first circuit unit. 5. The power conversion device according to claim 4, wherein a plurality of the power converters are arranged side by side. 6. The power converter according to claim 5, wherein said inter-unit connecting portion includes at least one of a notch and a through hole. 7. The power converter according to claim 5, wherein said inter-unit connecting portion has a shape along said first direction and substantially symmetrical with respect to a center line of said inter-unit connecting portion in said second direction. . The inter-unit connecting portion includes: a first portion extending along the second direction at a position corresponding to the plurality of semiconductor switching element portions of the first circuit unit; a second portion extending along the second direction at positions corresponding to the plurality of semiconductor switching element portions; The power converter according to any one of claims 5 to 7, further comprising a third portion provided separately from said first portion and said second portion so as to extend in a direction.

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