CN111865100A - Power conversion device - Google Patents

Power conversion device Download PDF

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Publication number
CN111865100A
CN111865100A CN202010136525.3A CN202010136525A CN111865100A CN 111865100 A CN111865100 A CN 111865100A CN 202010136525 A CN202010136525 A CN 202010136525A CN 111865100 A CN111865100 A CN 111865100A
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CN
China
Prior art keywords
semiconductor switching
switching element
circuit
circuit unit
smoothing capacitor
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Pending
Application number
CN202010136525.3A
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Chinese (zh)
Inventor
松永和久
岩丸阳介
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Publication date
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Publication of CN111865100A publication Critical patent/CN111865100A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
    • H02M5/40—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc
    • H02M5/42—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters
    • H02M5/44—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac
    • H02M5/453—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M5/458—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases with intermediate conversion into dc by static converters using discharge tubes or semiconductor devices to convert the intermediate dc into ac using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/49—Combination of the output voltage waveforms of a plurality of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B6/00—Heating by electric, magnetic or electromagnetic fields
    • H05B6/02—Induction heating
    • H05B6/06—Control, e.g. of temperature, of power
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Inverter Devices (AREA)

Abstract

The invention provides a power conversion device, which can restrain the enlargement of the device and the increase of the transmission loss and can increase the capacity of the supplied power.

Description

Power conversion device
Technical Field
The present invention relates to a power conversion device, and more particularly to a power conversion device including a smoothing capacitor and an inverter unit.
Background
Conventionally, a power conversion device including a smoothing capacitor and an inverter unit has been disclosed. Such a power conversion device is disclosed in, for example, japanese patent laid-open publication No. 2017-118693.
Jp 2017 a 118693 a describes an induction heating power supply device (power conversion device) including a dc power supply unit (an ac power supply and a converter unit), a smoothing unit (a smoothing capacitor), an inverter unit, and an output unit. In the power supply device for induction heating described in japanese patent application laid-open No. 2017-118693, a dc power supply unit converts ac power supplied from a commercial ac power supply into dc power. The smoothing unit smoothes a ripple current of the dc power output from the dc power supply unit. The inverter unit also converts the dc power smoothed by the smoothing unit back into a high-frequency ac power. The output unit outputs the ac power converted by the inverter unit to the heating coil.
In the power supply device for induction heating described in japanese patent application laid-open No. 2017-118693, the inverter unit includes two bridge circuits each including a plurality of arms each including two power semiconductor elements connected in series. The output portions of the two bridge circuits are connected in parallel to the heating coil. Thereby, the power supply to the heating coil is distributed to the two bridge circuits. That is, in the power supply device for induction heating described in japanese patent application laid-open No. 2017-118693, a plurality of (two) inverter units are provided on the output side of the bridge circuit so as to be connected in parallel with each other.
Here, in the conventional power conversion device as described in japanese patent application laid-open No. 2017-118693, in order to increase the capacity of the electric power that can be supplied, a method of increasing the number of parallel inverters connected in parallel to each other and increasing the supplied current is considered. However, when the current is increased, the conductor needs to be thickened in accordance with the increased current at the portion where the currents of the parallel-connected inverter portions are merged, and therefore, the device is increased in size. In addition, since the heat loss lost as heat energy at the resistor (conductor) depends on the magnitude of the current, when the current increases, the energy loss (transmission loss) in the transmission path increases. Therefore, in the conventional power conversion apparatus as described in japanese patent application laid-open No. 2017-118693, there is a desire to increase the capacity of the electric power that can be supplied while suppressing an increase in the size of the apparatus and an increase in the transmission loss.
Disclosure of Invention
Problems to be solved by the invention
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power conversion device capable of increasing the capacity of the electric power that can be supplied while suppressing an increase in the size of the device and an increase in the transmission loss.
Means for solving the problems
In order to achieve the above object, one aspect of the present invention provides a power conversion device including: a smoothing capacitor connected to an output side of a rectifier circuit that rectifies an alternating-current voltage; and an inverter unit including a semiconductor switching element unit having a plurality of semiconductor switching elements, the inverter unit converting the dc voltage smoothed by the smoothing capacitor into an ac voltage by switching the semiconductor switching elements, wherein a plurality of circuit units including the smoothing capacitor and the inverter unit are provided on an output side of the inverter circuit so as to be connected in series with each other.
In the power conversion device according to one aspect of the present invention, as described above, a plurality of circuit units including the smoothing capacitor and the inverter unit are provided on the output side of the inverter unit so as to be connected in series with each other. Accordingly, the voltage of the entire plurality of inverter units connected to each other is the sum of the voltages of the respective inverter units connected to each other in series, and therefore the voltage output from the power conversion device can be increased (increased voltage) without increasing the current flowing through the inverter units. Further, since the current flowing through the inverter unit is not increased, it is not necessary to increase the conductor (increase the size of the device) as in the case where a plurality of inverter units are connected in parallel. Further, since the heat loss lost as heat energy in the resistor (conductor) does not depend on the magnitude of the voltage, the energy loss (transmission loss) does not increase even when the voltage of the entire inverter unit increases. As a result, the electric power that can be supplied can be increased in capacity while suppressing an increase in the size of the apparatus and an increase in transmission loss.
In the power conversion device according to the above aspect, it is preferable that each of the plurality of circuit units includes an intra-cell connection portion that connects the smoothing capacitor and the semiconductor switching element portion, and the intra-cell connection portions of the plurality of circuit units are configured such that inductances between the smoothing capacitor and the semiconductor switching element portion are equal to each other. Here, in an inverter section that performs switching of the semiconductor switching elements, a surge voltage (a large-wave voltage generated when the switching elements instantaneously exceed a steady state) may be generated when the switching elements are turned ON/OFF. When surge voltages having different magnitudes are generated in the respective inverter units connected in series, an unexpected circulating current may flow between the inverter units connected in series. That is, in each of the inverter units connected in series, there is a problem of the device such as damage or malfunction of the device due to the surge voltage, as compared with the case where the surge voltages are equal to each other. In addition, the surge voltage depends on the current flowing in the circuit and the inductance in the circuit. Therefore, by configuring as described above, the inductances between the smoothing capacitor and the semiconductor switching element unit are equal to each other among the plurality of circuit units, and therefore, it is possible to suppress an increase in the surge voltage among the plurality of circuit units. As a result, the inverter units connected in series can suppress the malfunction of the device due to the surge voltage.
In this case, the circuit unit preferably includes a 1 st circuit unit and a 2 nd circuit unit connected in series with each other and arranged in a 1 st direction, and the structure in the 1 st circuit unit and the structure in the 2 nd circuit unit are preferably configured to be symmetrical with each other with respect to a central plane orthogonal to the 1 st direction and in the center between the 1 st circuit unit and the 2 nd circuit unit. With this configuration, since the cell-inside connection portion of the 1 st circuit unit and the cell-inside connection portion of the 2 nd circuit unit have the same shape, a configuration in which the inductances between the smoothing capacitor and the semiconductor switching element portion are equal to each other can be easily realized between the 1 st circuit unit and the 2 nd circuit unit. Further, since the members other than the cell-inside connection portion are formed in the same shape in each of the 1 st circuit cell and the 2 nd circuit cell, it is possible to suppress the current flowing between the 1 st circuit cell and the 2 nd circuit cell connected in series from being unbalanced electrically.
In the above-described configuration in which the 1 st circuit unit and the 2 nd circuit unit are symmetrical with each other with respect to the central plane at the center between the 1 st circuit unit and the 2 nd circuit unit, it is preferable that the smoothing capacitor of each of the 1 st circuit unit and the 2 nd circuit unit has a rectangular parallelepiped shape including a terminal disposition surface on which terminals of the smoothing capacitor are disposed, the semiconductor switching element portion of each of the 1 st circuit unit and the 2 nd circuit unit is disposed along a side surface intersecting the terminal disposition surface, and the 1 st circuit unit and the 2 nd circuit unit are disposed so that the terminal disposition surface of the 1 st circuit unit and the terminal disposition surface of the 2 nd circuit unit face each other. With this configuration, since the 1 st circuit unit and the 2 nd circuit unit are arranged so that the terminal arrangement surface of the 1 st circuit unit and the terminal arrangement surface of the 2 nd circuit unit face each other, the intra-cell connection portion connected to the terminal of the smoothing capacitor arranged on the terminal arrangement surface of the 1 st circuit unit and the intra-cell connection portion connected to the terminal of the smoothing capacitor arranged on the terminal arrangement surface of the 2 nd circuit unit can be arranged relatively close to each other. Therefore, for example, when the distance between the smoothing capacitor and the semiconductor switching element portion at the intra-cell connection portion is reduced in each of the 1 st circuit cell and the 2 nd circuit cell in order to reduce the inductance between the smoothing capacitor and the semiconductor switching element portion, the semiconductor switching element portion of the 1 st circuit cell and the semiconductor switching element portion of the 2 nd circuit cell can be arranged relatively close to each other. In this case, since the connection distance when the 1 st circuit unit and the 2 nd circuit unit are connected to each other can be suppressed from increasing, the inductance between the smoothing capacitor and the semiconductor switching element portion and the inductance in the member connecting the units can be reduced. In addition, in each of the 1 st circuit unit and the 2 nd circuit unit, the semiconductor switching element portion can be disposed along a side surface (a surface different from the terminal disposition surface) intersecting with the terminal disposition surface on which the terminals of the smoothing capacitor are disposed, whereby the space around the smoothing capacitor having a rectangular parallelepiped shape can be effectively used for disposing the components, as compared with a case where the semiconductor switching element portion is disposed along the surface (the terminal disposition surface) on which the terminals of the smoothing capacitor are disposed.
In this case, it is preferable that the power conversion device further includes an inter-cell connection portion that connects the semiconductor switching element portion of the 1 st circuit cell and the semiconductor switching element portion of the 2 nd circuit cell, the semiconductor switching element portion of the 1 st circuit cell is provided in plurality on the side surface so as to be aligned in a 2 nd direction orthogonal to the 1 st direction, and the semiconductor switching element portion of the 2 nd circuit cell is provided in plurality on the side surface so as to be aligned in a 2 nd direction orthogonal to the 1 st direction so as to correspond to each of the semiconductor switching element portions of the plurality of semiconductor switching element portions of the 1 st circuit cell. With this configuration, since the plurality of semiconductor switching element portions provided in the 1 st circuit unit and the plurality of semiconductor switching element portions provided in the 2 nd circuit unit are arranged so as to correspond to each other and are aligned in the 2 nd direction, the shape of the inter-cell connection portion connecting the semiconductor switching element portion of the 1 st circuit unit and the semiconductor switching element portion of the 2 nd circuit unit can be simplified.
In the above-described structure including the inter-unit connection portion, the inter-unit connection portion preferably includes at least one of a notch and a through hole. With this configuration, it is possible to make adjustments by using at least either one of the notch and the through hole, and to reduce the difference in the length of the current path from each of the plurality of semiconductor switching element portions of the circuit unit. As a result, it is possible to suppress an increase in electrical imbalance of the current flowing from each of the plurality of semiconductor switching element portions of the circuit unit.
In the above-described configuration including the inter-cell connecting portion, the inter-cell connecting portion preferably has a shape symmetrical with respect to a center line in the 2 nd direction of the inter-cell connecting portion along the 1 st direction. With this configuration, the lengths of the current paths of the respective semiconductor switching element portions in the plurality of semiconductor switching element portions of the circuit unit can be made equal on one side and the other side in the 2 nd direction with respect to the center line, and therefore, it is possible to suppress an increase in the electrical imbalance of the currents flowing through the respective semiconductor switching element portions in the plurality of semiconductor switching element portions of the circuit unit.
In the above configuration including the inter-cell connection portion, the inter-cell connection portion preferably includes: a 1 st portion provided at a position corresponding to the plurality of semiconductor switching element portions of the 1 st circuit unit so as to extend in a 2 nd direction; a 2 nd portion provided at a position corresponding to the plurality of semiconductor switching element portions of the 2 nd circuit unit so as to extend in the 2 nd direction; and a 3 rd part which is provided independently from the 1 st part and the 2 nd part in such a manner as to extend in the 1 st direction, and is provided to connect the 1 st part and the 2 nd part. With this configuration, since the 3 rd part is provided independently of the 1 st part provided in the 1 st circuit unit and the 2 nd part provided in the 2 nd circuit unit, the 1 st part and the 2 nd part are handled as respective units connected to the 1 st circuit unit and the 2 nd circuit unit, and the 3 rd part is handled as a connecting part connecting the units, so that workability in assembling and maintaining the apparatus can be improved.
Drawings
Fig. 1 is a circuit diagram of a power conversion device according to an embodiment of the present invention.
Fig. 2 is a perspective view showing a schematic structure of a power conversion device according to an embodiment of the present invention.
Fig. 3 is a perspective view of a stacked portion (japanese: スタック) of a power conversion device according to an embodiment of the present invention.
Fig. 4 is an exploded perspective view (1) of a stack portion of a power conversion device according to an embodiment of the present invention.
Fig. 5 is a sectional view (side view) of a power conversion device according to an embodiment of the present invention.
Fig. 6 is an exploded perspective view (2) of the power converter according to the embodiment of the present invention.
Fig. 7 is a front view for explaining the arrangement between the stacked portions of the power conversion device according to the embodiment of the present invention.
Fig. 8 is a side view for explaining the arrangement between the stacked portions of the power conversion device according to the embodiment of the present invention.
Detailed Description
Hereinafter, embodiments embodying the present invention will be described based on the drawings.
The configuration of a power conversion device 100 according to an embodiment of the present invention will be described with reference to fig. 1 to 8. The power converter 100 is a power converter 100 for an induction heating device 200 of a melting furnace for melting a metal by induction heating. The power converter 100 is configured to generate ac from an ac power supply 300 using a semiconductor switching element 31.
(Circuit configuration of Power conversion device)
First, a circuit configuration of the power conversion apparatus 100 is described with reference to fig. 1.
As shown in fig. 1, the power conversion device 100 includes a plurality of rectifier circuits 10 (rectifier circuits 10a to 10d), a plurality of smoothing capacitors 20 (smoothing capacitors 20a to 20d), and a plurality of inverter units 30 (inverter units 30a to 30 d).
The rectifier circuit 10 converts an ac voltage input from the ac power supply 300 into a dc voltage. The rectifier circuit 10 is provided in plurality (two) with respect to 1 ac power supply 300. That is, a rectifier circuit 10a and a rectifier circuit 10b are provided for the ac power supply 301 (transformer 301). Further, a rectifier circuit 10c and a rectifier circuit 10d are provided for the ac power supply 302 (transformer 302). Further, the anode side and the cathode side of the rectifier circuit 10a are electrically connected to the anode side and the cathode side of the rectifier circuit 10c, respectively. Further, the anode side and the cathode side of the rectifier circuit 10b are electrically connected to the anode side and the cathode side of the rectifier circuit 10d, respectively.
The smoothing capacitor 20 is connected to the output side of the rectifier circuit 10 that rectifies the ac voltage. The smoothing capacitor 20 is provided one for each rectifying circuit 10. That is, smoothing capacitors 20a, 20b, 20c, and 20d are connected to the output sides of the rectifier circuits 10a, 10b, 10c, and 10d, respectively. The positive electrode side and the negative electrode side of the smoothing capacitor 20a are electrically connected to the positive electrode side and the negative electrode side of the smoothing capacitor 20c, respectively. The positive electrode side and the negative electrode side of the smoothing capacitor 20b are electrically connected to the positive electrode side and the negative electrode side of the smoothing capacitor 20d, respectively.
The inverter unit 30 converts the dc voltage smoothed by the rectifier circuit 10 into an ac voltage by switching of the semiconductor switching element 31. Then, the converted ac voltage is output from the inverter unit 30 to the induction heating coil 210 of the induction heating device 200. In addition, the inverter section 30 is provided one for each rectifier circuit 10. That is, inverter units 30a, 30b, 30c, and 30d are provided for the rectifier circuits 10a, 10b, 10c, and 10d, respectively.
The inverter section 30 includes a semiconductor module 32 (a semiconductor module 32a and a semiconductor module 32b) having a plurality of semiconductor switching elements 31. The semiconductor module 32a accommodates a semiconductor switching element 31a and a semiconductor switching element 31 b. The semiconductor module 32b accommodates a semiconductor switching element 31c and a semiconductor switching element 31 d. The semiconductor element 32 is an example of the "semiconductor switching element portion" in the claims.
Although not shown in fig. 1, the semiconductor devices 32a and 32b are each provided such that a plurality of the semiconductor devices are connected in parallel, for example, 6 in parallel. The semiconductor switching elements 31a to 31d form a full bridge circuit. Further, a connection point at which the semiconductor switching element 31a and the semiconductor switching element 31b of the inverter unit 30a (inverter unit 30c) are connected is electrically connected to one end side of the induction heating coil 210. Further, a connection point at which the semiconductor switching element 31c and the semiconductor switching element 31d of the inverter unit 30b (inverter unit 30d) are connected is electrically connected to the other end side of the induction heating coil 210.
Further, in the power conversion apparatus 100, the smoothing capacitor 20 and the inverter section 30 constitute a stacked section (circuit unit) 40. The stacking unit 40 is provided in plurality (stacking units 40a to 40 d). Further, the stacked portion 40a and the stacked portion 40c are an example of "1 st circuit unit" of the claims. In addition, the stacked portion 40b and the stacked portion 40d are an example of the "2 nd circuit unit" of the claims.
Specifically, the smoothing capacitor 20a and the inverter 30a constitute a stack 40 a. Further, the smoothing capacitor 20b and the inverter 30b constitute a stack 40 b. In addition, the smoothing capacitor 20c and the inverter section 30c constitute a stack section 40 c. In addition, the smoothing capacitor 20d and the inverter section 30d constitute a stacked section 40 d.
Here, in the present embodiment, the stacked portion 40 including the smoothing capacitor 20 and the inverter portion 30 is connected in series with each other on the output side of the inverter portion 30. Specifically, the output side of the inverter section 30a of the stack section 40a and the output side of the inverter section 30b of the stack section 40b are electrically connected in series. In addition, the output side of the inverter section 30c of the stack section 40c and the output side of the inverter section 30d of the stack section 40d are electrically connected in series.
Specifically, a connection point between the semiconductor switching element 31c and the semiconductor switching element 31d of the inverter unit 30a is electrically connected to a connection point between the semiconductor switching element 31a and the semiconductor switching element 31b of the inverter unit 30 b. Further, a connection point between the semiconductor switching element 31c and the semiconductor switching element 31d of the inverter unit 30c is electrically connected to a connection point between the semiconductor switching element 31a and the semiconductor switching element 31b of the inverter unit 30 d.
(schematic structure of Power conversion device)
Next, a schematic structure of the power conversion device 100 will be described with reference to fig. 2.
As shown in fig. 2, in the power conversion apparatus 100, two stacking portions 40 (a stacking portion 40a and a stacking portion 40b) are arranged in a vertical direction (Z direction) in 1 case 50. The stacking unit 40a and the stacking unit 40b are disposed on the lower side (Z2 side) and the upper side (Z1 side), respectively, of the case 50. The arrangement of the stacking portions 40c and 40d is substantially the same as that of the stacking portions 40a and 40b, and is not shown in fig. 2.
In the following description, the vertical direction, the horizontal direction, and the front-rear direction of the housing 50 are referred to as the Z direction, the X direction, and the Y direction, respectively. The up direction (upper side), the down direction (lower side), the left side, the right side, the front side, and the rear side are referred to as the Z1 direction (Z1 side), the Z2 direction (Z2 side), the X1 side, the X2 side, the Y1 side, and the Y2 side, respectively. Further, the Z direction and the Y direction are examples of "1 st direction" and "2 nd direction" of the claims, respectively.
(Structure of Stacking portion)
Next, the structure of the stack portion 40 will be described with reference to fig. 3 to 6. In fig. 3 to 6, the arrangement (direction) of the stacking portion 40a shown in fig. 2 is used as the stacking portion 40.
As shown in fig. 3 and 4, the smoothing capacitor 20 is formed of a film capacitor having a substantially rectangular parallelepiped shape. As shown in fig. 4, the smoothing capacitor 20 includes a terminal arrangement surface 22 on which the terminals 21 of the smoothing capacitor 20 are linearly arranged. The terminal disposition surface 22 is a surface on the Z1 side of the smoothing capacitor 20. The terminal 21 includes a positive terminal 21p and a negative terminal 21 n. The positive-side terminals 21p and the negative-side terminals 21n are alternately arranged along the Y direction on the terminal arrangement surface 22.
The semiconductor element 32 includes a positive side terminal 32p, a negative side terminal 32n, and an output terminal 32 o. The positive terminal 32p, the negative terminal 32n, and the output terminal 32o are arranged in order from the Z1 side toward the Z2 side with respect to the positive terminal 32p, the negative terminal 32n, and the output terminal 32 o.
The semiconductor element 32 is disposed along the side surface 23 of the smoothing capacitor 20 intersecting the terminal disposition surface 22, and the side surface 23 is line-symmetric with respect to the linearly disposed terminals 21. A plurality of semiconductor elements 32 are provided on the side surface 23 so as to be aligned in the Y direction. Specifically, for example, 6 parallel (6) semiconductor modules 32a among the plurality of semiconductor modules 32 are arranged along the Y direction on the side surface 23a on the X2 side of the smoothing capacitor 20. As shown in fig. 5, the 6 parallel (6) semiconductor modules 32b are arranged along the Y direction on the side surface 23b on the X1 side of the smoothing capacitor 20. The semiconductor element 32 is arranged such that the front surface (the surface on which the positive-side terminal 32p, the negative-side terminal 32n, and the output terminal 32o are provided) of the semiconductor element 32 is along the side surface 23.
As shown in fig. 4, the semiconductor element 32 is disposed in the vicinity of the terminal disposition surface 22 in the Z direction. Specifically, the semiconductor element 32 is disposed on the Z1 side with respect to the center C of the side surface 23 in the Z direction. This makes it possible to reduce the distance between the positive terminal 32p of the semiconductor module 32 and the positive terminal 21p of the smoothing capacitor 20. Further, the distance between the negative terminal 32n of the semiconductor element 32 and the negative terminal 21n of the smoothing capacitor 20 can be made relatively small. As a result, it is possible to reduce the inductance of the bus bar 60 (described later) connecting the positive terminal 32p of the semiconductor module 32 and the positive terminal 21p of the smoothing capacitor 20 and to reduce the inductance of the bus bar 60 (described later) connecting the negative terminal 32n of the semiconductor module 32 and the negative terminal 21n of the smoothing capacitor 20.
As shown in fig. 5, the height position h1 of the semiconductor element 32a disposed on the side surface 23a on the X2 side with respect to the terminal 21 of the smoothing capacitor 20 with respect to the smoothing capacitor 20 is substantially equal to the height position h2 of the semiconductor element 32b disposed on the side surface 23b on the X1 side with respect to the terminal 21 of the smoothing capacitor 20 with respect to the smoothing capacitor 20. Specifically, the height position h1 of the end portion on the Z1 side of the semiconductor package 32a and the height position h2 of the end portion on the Z1 side of the semiconductor package 32b are substantially equal. In addition, the height positions h1 of the 6 semiconductor elements 32a are equal to each other. In addition, the height positions h2 of the 6 semiconductor elements 32b are equal to each other.
As shown in fig. 3, bus bars 60 (a positive side bus bar 61 and a negative side bus bar 62) connecting between the smoothing capacitor 20 and the semiconductor module 32 are provided in the stack portion 40. The positive-side bus bar 61 is electrically connected to the positive-side terminal 32p of the semiconductor assembly 32 and the positive-side terminal 21p of the smoothing capacitor 20. The negative-side bus bar 62 is electrically connected to the negative-side terminal 32n of the semiconductor assembly 32 and the negative-side terminal 21n of the smoothing capacitor 20. The bus bar 60 is an example of the "in-unit connection portion" in the claims.
In the power conversion device 100, the plurality of semiconductor modules 32 are arranged on both the side surface 23a on the X2 side with respect to the terminal arrangement surface 22 and the side surface 23b on the X1 side with respect to the terminal arrangement surface 22 so that the impedances (impedances) between each of the plurality of semiconductor modules 32 and the smoothing capacitor 20 are substantially equal.
Specifically, as shown in fig. 5, a distance L1 (distance indicated by a one-dot chain line in fig. 5) on the positive bus bar 61 between the positive terminal 32p of the semiconductor element 32a disposed on one side (side surface 23a) of the smoothing capacitor 20 and the terminal 21 of the smoothing capacitor 20 is substantially equal to a distance L2 on the positive bus bar 61 between the positive terminal 32p of the semiconductor element 32b disposed on the other side (side surface 23b) of the smoothing capacitor 20 and the terminal 21 of the smoothing capacitor 20. Further, a distance L11 on the negative side bus bar 62 between the negative side terminal 32n of the semiconductor package 32a and the terminal 21 of the smoothing capacitor 20 is substantially equal to a distance L12 on the negative side bus bar 62 between the negative side terminal 32n of the semiconductor package 32b and the terminal 21 of the smoothing capacitor 20. This makes it possible to make the impedances (impedances) between the semiconductor elements 32 of the plurality of semiconductor elements 32 and the smoothing capacitor 20 substantially equal, and thus to stabilize the current flowing between the semiconductor elements 32 and the smoothing capacitor 20.
In addition, in the power conversion device 100, as shown in fig. 4, the positive-side bus bar 61 and the negative-side bus bar 62 are respectively provided in common to the plurality of semiconductor packages 32. As shown in fig. 5, each of the positive-side bus bar 61 and the negative-side bus bar 62 has a substantially U-shape covering the terminal disposition surface 22 and the regions of the side surfaces 23a and 23b on both sides of the smoothing capacitor 20. Specifically, with respect to the smoothing capacitor 20, the positive-side bus bar 61 and the negative-side bus bar 62 are laminated in the order of the positive-side bus bar 61 and the negative-side bus bar 62. That is, the substantially U-shaped positive bus bar 61 is disposed inside the substantially U-shaped negative bus bar 62. In addition, the positive-side bus bar 61 and the negative-side bus bar 62 are each formed by bending 1 metal plate. This makes it possible to reduce the inductance of the bus bar 60, as compared with a case where the bus bar 60 is formed by connecting a plurality of metal plates.
As shown in fig. 6, an insulating paper 70 is disposed between the positive bus bar 61 and the negative bus bar 62. The insulating paper 70 is provided in a plurality of sheets in an overlapping manner. That is, the bus bar 60 has a laminated structure in which a conductive layer and an insulating layer are laminated.
In addition, as shown in fig. 5, the positive-side bus bar 61 includes a 1 st portion 61a extending along the X direction and a 2 nd portion 61b extending toward the Z2 side from both ends of the 1 st portion 61a in the X direction. In addition, the negative-side bus bar 62 includes a 1 st portion 62a extending along the X direction and a 2 nd portion 62b extending toward the Z2 side from both ends of the 1 st portion 62a in the X direction. Also, the length L21 in the X direction of the 1 st portion 61a of the positive-side bus bar 61 is smaller than the length L22 in the X direction of the 1 st portion 62a of the negative-side bus bar 62. In addition, the length L31 in the Z direction of the 2 nd portion 61b of the positive-side bus bar 61 is smaller than the length L32 in the Z direction of the 2 nd portion 62b of the negative-side bus bar 62.
The positive-side bus bar 61 has a leg portion 61c connected to the positive-side terminal 32p of the semiconductor package 32a and the positive-side terminal 32p of the semiconductor package 32 b. In addition, the negative side bus bar 62 has a leg portion 62c connected to the negative side terminal 32n of the semiconductor package 32a and the negative side terminal 32n of the semiconductor package 32 b. The leg portion 61c of the positive side bus bar 61 is connected to the positive side terminal 32p of the semiconductor package 32 by a screw 71. In addition, the leg portion 62c of the negative side bus bar 62 is connected to the negative side terminal 32n of the semiconductor module 32 by the screw 71. In addition, the leg portion 61c and the leg portion 62c are disposed along the X direction. In addition, the length L41 in the X direction of the leg portion 61c of the positive-side bus bar 61 is smaller than the length L42 in the X direction of the leg portion 62c of the negative-side bus bar 62.
The interval D1 in the Z direction between the 1 st portion 61a of the positive side bus bar 61 and the 1 st portion 62a of the negative side bus bar 62 is relatively small. In addition, the interval D2 in the X direction between the 2 nd portion 61b of the positive side bus bar 61 and the 2 nd portion 62b of the negative side bus bar 62 is relatively small. On the other hand, the interval D3 in the Z direction between the leg portion 61c of the positive-side bus bar 61 and the leg portion 62c of the negative-side bus bar 62 is relatively large. However, the portion of the entire region of the positive-side bus bar 61 that is relatively large in comparison with the interval between the negative-side bus bars 62 is only the leg portion 61c (only a relatively small region). Thus, the leg portion 61c (leg portion 62c) has a small influence on the effect of reducing inductance of the bus bar 60 (positive bus bar 61 and negative bus bar 62) which is achieved by laminating the positive bus bar 61 and the negative bus bar 62 with the insulating paper 70 interposed therebetween.
As shown in fig. 6, the positive bus bar 61 is provided with a plurality of holes 61 d. Further, the negative bus bar 62 is provided with a plurality of holes 62 d. Further, the insulating paper 70 is provided with a plurality of holes 70 a. The screw 71 is screwed to the positive terminal 21p of the smoothing capacitor 20 from the Z1 side through the hole 62d of the negative bus bar 62, the hole 70a of the insulating paper 70, and the positive bus bar 61. Thereby, the positive bus bar 61 is connected to the positive terminal 21p of the smoothing capacitor 20. Further, the screw 71 is screwed to the negative terminal 21n of the smoothing capacitor 20 from the Z1 side through the negative bus bar 62, the hole 70a of the insulating paper 70, and the hole 61d of the positive bus bar 61. Thereby, the negative side bus bar 62 is connected to the negative side terminal 21n of the smoothing capacitor 20.
(Structure between plural Stacking portions)
Next, the structure between the plurality of stacking portions 40 of the power conversion device 100 will be described with reference to fig. 7 and 8.
As shown in fig. 7, in the present embodiment, each of the plurality of stacked portions 40 includes a bus bar 60 connecting between the smoothing capacitor 20 and the semiconductor module 32. The bus bars 60 are configured such that the inductances between the smoothing capacitor 20 and the semiconductor module 32 are substantially equal to each other.
Specifically, as shown in fig. 7 and 8, the bus bar 60 of the stack portion 40a and the bus bar 60 of the stack portion 40b are configured to be substantially symmetrical with respect to a central plane 90 orthogonal to the Z direction and located at the center between the stack portion 40a and the stack portion 40 b. That is, in the power conversion device 100, the structures (the shapes of the members in the stacking unit 40 and the relative arrangement between the members in the stacking unit 40) in the plurality of stacking units 40 (stacking units 40a to 40d) are configured to be substantially equal to each other.
Specifically, as shown in fig. 7, in the power conversion device 100, the stack portion 40a and the stack portion 40b are arranged such that the terminal arrangement surface 22 of the stack portion 40a and the terminal arrangement surface 22 of the stack portion 40b face each other. That is, the stacking portion 40a is disposed on the lower side (Z2 side) of the housing 50 such that the terminal disposition surface 22 is on the upper side (Z1 side). The stacking portion 40b is disposed above the housing 50 so that the terminal disposition surface 22 is located below.
Accordingly, the 1 st portion 61a (the 1 st portion 62a) of the positive side bus bar 61 (the negative side bus bar 62) of the stacked portion 40a is arranged on the upper side (the Z1 side) of the stacked portion 40 a. In addition, the 1 st portion 61a (the 1 st portion 62a) of the positive side bus bar 61 (the negative side bus bar 62) of the stacked portion 40b is disposed on the lower side (the Z2 side) of the stacked portion 40 b.
A plurality of semiconductor modules 32 of the stacking portion 40a are provided on the side surface 23 so as to be aligned in the Y direction orthogonal to the Z direction. In addition, the semiconductor modules 32 of the stack portion 40b are provided in a plurality on the side surface 23 so as to be aligned in the Y direction orthogonal to the Z direction so as to correspond to the respective semiconductor modules 32 of the plurality of semiconductor modules 32 of the stack portion 40 a.
Here, in the present embodiment, as shown in fig. 8, the power conversion device 100 includes the bus bar 80 that connects the semiconductor module 32 of the stack portion 40a and the semiconductor module 32 of the stack portion 40 b. The bus bar 80 is an example of the "inter-unit connection portion" in the claims.
Specifically, the bus bar 80 has a substantially symmetrical shape with respect to a center line 91 in the Y direction of the bus bar 80 along the Z direction. In addition, the bus bar 80 includes a 1 st portion 81 provided on the stacking portion 40a side, a 2 nd portion 82 provided on the stacking portion 40b side, and a 3 rd portion 83 provided in such a manner as to connect the 1 st portion 81 and the 2 nd portion 82.
Specifically, the 1 st portion 81 is provided at a position corresponding to the plurality of semiconductor elements 32 of the stack portion 40a so as to extend in the Y direction. In addition, the 2 nd portion 82 is provided at a position corresponding to the plurality of semiconductor elements 32 of the stack portion 40b so as to extend in the Y direction. In addition, the 3 rd portion 83 is provided extending in the Z direction so as to connect the 1 st portion 81 and the 2 nd portion 82.
The 1 st part 81, the 2 nd part 82, and the 3 rd part 83 are provided independently of each other, and are fastened by bolts and nuts between the 1 st part 81 and the 3 rd part 83 and between the 2 nd part 82 and the 3 rd part 83. In addition, the 3 rd portion 83 is disposed substantially at the center of the 1 st portion 81 and the 2 nd portion 82 in the Y direction.
In addition, in the present embodiment, the bus bar 80 includes a through hole 80 a. Specifically, a through hole 80a formed in a slit shape so as to extend in the Y direction is provided in each of a substantially central portion of the 1 st part 81 and a substantially central portion of the 2 nd part 82. Further, the length of the through hole 80a in the Y direction is larger than the length of the 3 rd portion 83 in the Y direction.
(effects of the embodiment)
In the present embodiment, the following effects can be obtained.
In the present embodiment, as described above, a plurality of stacked portions 40 including the smoothing capacitor 20 and the inverter portion 30 are provided on the output side of the inverter portion 30 so as to be connected in series with each other. Accordingly, the voltage of the entire plurality of inverter units 30 connected to each other becomes the sum of the voltages of the respective inverter units 30 in the plurality of inverter units 30 connected to each other in series, and therefore the voltage output from the power conversion device 100 can be increased (increased voltage) without increasing the current flowing through the inverter units 30. Further, since the current flowing through the inverter unit 30 is not increased, it is not necessary to increase the conductor (increase the size of the power conversion device 100) as in the case where a plurality of inverter units 30 are connected in parallel. Further, since the heat loss lost as heat energy in the resistor (conductor) does not depend on the magnitude of the voltage, the energy loss (transmission loss) does not increase even when the voltage of the entire inverter unit 30 increases. As a result, the electric power that can be supplied can be increased in capacity while suppressing an increase in the size of the power conversion device 100 and an increase in the transmission loss.
In the present embodiment, as described above, each of the plurality of stacked portions 40 is configured to include the bus bar 60 that connects the smoothing capacitor 20 and the semiconductor module 32. The bus bars 60 of the plurality of stacked portions 40 are configured such that the inductances between the smoothing capacitor 20 and the semiconductor module 32 are substantially equal to each other. Accordingly, since inductances between the smoothing capacitor 20 and the semiconductor element 32 are substantially equal to each other among the plurality of stacked portions 40, it is possible to suppress a large difference in surge voltage among the plurality of stacked portions 40. As a result, the failure of the power conversion device 100 due to the surge voltage can be suppressed in the inverter units 30 connected in series.
In the present embodiment, as described above, the stacking unit 40 includes the stacking unit 40a (stacking unit 40c) and the stacking unit 40b (stacking unit 40d) which are connected in series and arranged in the Z direction. The structure in the stacking portion 40a (stacking portion 40c) and the structure in the stacking portion 40b (stacking portion 40d) are configured to be substantially symmetrical with respect to a central plane 90 in the center between the stacking portion 40a (stacking portion 40c) and the stacking portion 40b (stacking portion 40d) which is orthogonal to the Z direction. Thus, since the bus bar 60 of the stack portion 40a (stack portion 40c) and the bus bar 60 of the stack portion 40b (stack portion 40d) have substantially the same shape, a structure in which inductances between the smoothing capacitor 20 and the semiconductor module 32 are substantially equal to each other can be easily realized between the stack portion 40a (stack portion 40c) and the stack portion 40b (stack portion 40 d). Further, since members other than the bus bar 60 are formed in substantially the same shape in each of the stacking portions 40a (stacking portion 40c) and 40b (stacking portion 40d), it is possible to suppress an electrical imbalance in the currents flowing between the stacking portions 40a (stacking portion 40c) and 40b (stacking portion 40d) connected in series.
In the present embodiment, as described above, the smoothing capacitors 20 of the stacked portion 40a (stacked portion 40c) and the stacked portion 40b (stacked portion 40d) are each configured to have a substantially rectangular parallelepiped shape including the terminal arrangement surface 22 on which the terminals 21 of the smoothing capacitor 20 are arranged. The semiconductor modules 32 of the stacking portion 40a (stacking portion 40c) and the stacking portion 40b (stacking portion 40d) are arranged along the side surface 23 intersecting the terminal arrangement surface 22. The stacking portion 40a (stacking portion 40c) and the stacking portion 40b (stacking portion 40d) are arranged such that the terminal arrangement surface 22 of the stacking portion 40a (stacking portion 40c) and the terminal arrangement surface 22 of the stacking portion 40b (stacking portion 40d) face each other. Thus, since the stack portion 40a (stack portion 40c) and the stack portion 40b (stack portion 40d) are arranged so that the terminal arrangement surface 22 of the stack portion 40a (stack portion 40c) and the terminal arrangement surface 22 of the stack portion 40b (stack portion 40d) are opposed to each other, the bus bar 60 connected to the terminal 21 of the smoothing capacitor 20 arranged on the terminal arrangement surface 22 of the stack portion 40a (stack portion 40c) and the bus bar 60 connected to the terminal 21 of the smoothing capacitor 20 arranged on the terminal arrangement surface 22 of the stack portion 40b (stack portion 40d) can be arranged relatively close to each other. Thus, in the case where the distance between the smoothing capacitor 20 and the semiconductor component 32 on the bus bar 60 is reduced in each of the stacking portions 40a (the stacking portions 40c) and 40b (the stacking portions 40d) in order to reduce the inductance between the smoothing capacitor 20 and the semiconductor component 32, the semiconductor component 32 of the stacking portion 40a (the stacking portion 40c) and the semiconductor component 32 of the stacking portion 40b (the stacking portion 40d) can be arranged relatively close. As a result, since the connection distance when the stacked portion 40a (stacked portion 40c) and the stacked portion 40b (stacked portion 40d) are connected to each other can be suppressed from increasing, the inductance between the smoothing capacitor 20 and the semiconductor element 32 can be reduced, and the inductance in the member (bus bar 80) connecting the stacked portions 40 to each other can also be reduced. In addition, in each of the stacked portions 40a (the stacked portion 40c) and the stacked portion 40b (the stacked portion 40d), the semiconductor module 32 can be disposed along the side surface 23 (the surface different from the terminal disposition surface 22) intersecting the terminal disposition surface 22 on which the terminals 21 of the smoothing capacitor 20 are disposed, whereby the space around the smoothing capacitor 20 having a substantially rectangular parallelepiped shape can be effectively used for the arrangement member as compared with the case where the semiconductor module 32 is disposed along the surface (the terminal disposition surface 22) on which the terminals 21 of the smoothing capacitor 20 are disposed.
In the present embodiment, as described above, the power conversion device 100 is configured to include the bus bar 80 that connects the semiconductor module 32 in the stacking portion 40a (stacking portion 40c) and the semiconductor module 32 in the stacking portion 40b (stacking portion 40 d). A plurality of semiconductor modules 32 of the stack portion 40a (stack portion 40c) are arranged on the side surface 23 intersecting the terminal disposition surface 22 in the Y direction orthogonal to the Z direction. In addition, a plurality of semiconductor modules 32 in the stacking portion 40b (stacking portion 40d) are provided so as to be aligned in the Y direction orthogonal to the Z direction on the side surface 23 intersecting the terminal disposition surface 22 so as to correspond to each of the plurality of semiconductor modules 32 in the stacking portion 40a (stacking portion 40 c). Thus, since the plurality of semiconductor modules 32 provided in the stack portion 40a (stack portion 40c) and the plurality of semiconductor modules 32 provided in the stack portion 40b (stack portion 40d) are arranged so as to correspond to each other and are aligned in the Y direction, the shape of the bus bar 80 connecting the semiconductor modules 32 of the stack portion 40a (stack portion 40c) and the semiconductor modules 32 of the stack portion 40b (stack portion 40d) can be simplified.
In the present embodiment, as described above, the bus bar 80 is configured to include the through hole 80 a. Thus, the through-holes 80a can be used to adjust the lengths of the current paths of the semiconductor elements 32 (arranged in the Y direction) from the stacked portion 40 to be smaller in the plurality of semiconductor elements 32. As a result, it is possible to suppress an increase in electrical imbalance of the current flowing from each of the plurality of semiconductor modules 32 in the stacked portion 40.
In the present embodiment, as described above, the bus bar 80 is configured to have a substantially symmetrical shape with respect to the center line 91 in the Y direction of the bus bar 80 along the Z direction. Accordingly, the lengths of the current paths from the respective semiconductor switching element portions of the plurality of semiconductor switching element portions of the stacked portion 40 can be made substantially equal on one side (Y1 side) and the other side (Y2 side) in the Y direction with respect to the center line 91, and therefore, it is possible to suppress an increase in the electrical imbalance of the currents flowing from the respective semiconductor modules 32 of the plurality of semiconductor modules 32 of the stacked portion 40.
In the present embodiment, as described above, the bus bar 80 includes the 1 st portion 81, the 2 nd portion 82, and the 3 rd portion 83. The 1 st portion 81 is provided at a position corresponding to the plurality of semiconductor elements 32 of the stack portion 40a so as to extend in the Y direction. In addition, the 2 nd portion 82 is provided at a position corresponding to the plurality of semiconductor elements 32 of the stacked portion 40b so as to extend in the Y direction. In addition, the 3 rd portion 83 is provided independently from the 1 st portion 81 and the 2 nd portion 82 so as to extend in the Z direction, and the 3 rd portion 83 is provided to connect the 1 st portion 81 and the 2 nd portion 82. Since the 3 rd part 83 is provided independently of the 1 st part 81 provided in the stack 40a (stack 40c) and the 2 nd part 82 provided in the stack 40b (stack 40d), the workability in assembling and maintaining the power conversion device 100 can be improved by handling the 1 st part 81 and the 2 nd part 82 as respective units connected to the stack 40a and the stack 40b and the 3 rd part 83 as a connecting portion connecting the units.
[ modified examples ]
The presently disclosed embodiments are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is indicated by the claims, rather than by the description of the embodiments described above, and all changes (modifications) that come within the meaning and range of equivalency of the claims are intended to be embraced therein.
For example, in the above-described embodiment, the bus bar 80 is configured to include the 1 st part 81 provided at a position corresponding to the plurality of semiconductor devices 32 of the stack portion 40a (stack portion 40c), the 2 nd part 82 provided at a position corresponding to the plurality of semiconductor devices 32 of the stack portion 40b (stack portion 40d), and the 3 rd part 83 provided independently of the 1 st part 81 and the 2 nd part 82 and connecting the 1 st part and the 2 nd part, but the present invention is not limited thereto. In the present invention, the "inter-cell connection portion" may be 1 member formed by integrally providing the 1 st portion, the 2 nd portion, and the 3 rd portion.
In the above embodiment, the bus bar 80 is configured to include the through hole 80a, but the present invention is not limited thereto. In the present invention, the "inter-cell connecting portion" may be configured to include a notch instead of the through hole. The "inter-cell connection portion" may be configured to include both a through hole and a notch.
In the above embodiment, the semiconductor devices 32 of the stack portion 40a (stack portion 40c) are provided in plural so as to be aligned in the Y direction, and the semiconductor devices 32 of the stack portion 40b (stack portion 40d) are provided in plural so as to be aligned in the Y direction so as to correspond to the respective semiconductor devices 32 of the stack portion 40a (stack portion 40c), but the present invention is not limited thereto. In the present invention, a plurality of "semiconductor switching element units" of the "1 st circuit unit" and a plurality of "semiconductor switching element units" of the "2 nd circuit unit" may be arranged in different directions from each other.
In the above embodiment, the smoothing capacitor 20 of each of the stack portion 40a (stack portion 40c) and the stack portion 40b (stack portion 40d) is configured to have a substantially rectangular parallelepiped shape including the terminal disposition surface 22 on which the terminals 21 of the smoothing capacitor 20 are disposed, and the stack portion 40a (stack portion 40c) and the stack portion 40b (stack portion 40d) are disposed so that the terminal disposition surface 22 of the stack portion 40a (stack portion 40c) and the terminal disposition surface 22 of the stack portion 40b (stack portion 40d) face each other, but the present invention is not limited thereto. In the present invention, the "1 st circuit unit" and the "2 nd circuit unit" may be arranged such that the terminal arrangement surface of the "1 st circuit unit" and the terminal arrangement surface of the "2 nd circuit unit" do not face each other.
In the above embodiment, the smoothing capacitor 20 of each of the stack portion 40a (stack portion 40c) and the stack portion 40b (stack portion 40d) is configured to have a substantially rectangular parallelepiped shape including the terminal arrangement surface 22 on which the terminals 21 of the smoothing capacitor 20 are arranged, and the semiconductor element 32 of each of the stack portion 40a (stack portion 40c) and the stack portion 40b (stack portion 40d) is arranged along the side surface 23 intersecting the terminal arrangement surface 22, but the present invention is not limited thereto. In the present invention, the "semiconductor switching element units" of the "1 st circuit unit" and the "2 nd circuit unit" may be arranged along a surface other than a side surface intersecting a terminal arrangement surface such as a terminal arrangement surface on which terminals of the smoothing capacitor are arranged.
In the above-described embodiment, the example in which the stacking unit 40 is configured to include two stacking units 40 (the stacking unit 40a (the stacking unit 40c) and the stacking unit 40b (the stacking unit 40d)) connected in series with each other and arranged in the Z direction has been described, but the present invention is not limited thereto. In the present invention, the "circuit unit" may be configured to include 3 or more "circuit units" connected in series with each other and arranged in the Z direction.
For example, in the above-described embodiment, the stacking portion 40a (stacking portion 40c) and the stacking portion 40b (stacking portion 40d) are configured to be substantially symmetrical with respect to the center plane 90 at the center between the stacking portion 40a (stacking portion 40c) and the stacking portion 40b (stacking portion 40d) that is orthogonal to the Z direction, but the present invention is not limited thereto. In the present invention, the "1 st circuit element" and the "2 nd circuit element" may be configured to be substantially symmetrical with respect to a plane other than a center plane between the "1 st circuit element" and the "2 nd circuit element". In addition, the "1 st circuit unit" and the "2 nd circuit unit" may be configured to be asymmetrical to each other. In this case, it is desirable that the "1 st circuit unit" and the "2 nd circuit unit" be configured such that inductances between the smoothing capacitor and the "semiconductor switching element unit" are substantially equal to each other.

Claims (8)

1. A power conversion apparatus, wherein,
the power conversion device is provided with:
a smoothing capacitor connected to an output side of a rectifier circuit that rectifies an alternating-current voltage; and
an inverter unit including a semiconductor switching element unit having a plurality of semiconductor switching elements, the inverter unit converting the DC voltage smoothed by the smoothing capacitor into an AC voltage by switching the semiconductor switching elements,
A plurality of circuit units including the smoothing capacitor and the inverter unit are provided on an output side of the inverter unit so as to be connected in series with each other.
2. The power conversion apparatus according to claim 1,
each of the plurality of circuit units includes an intra-unit connection portion connecting the smoothing capacitor and the semiconductor switching element portion,
the intra-cell connection portion of each of the plurality of circuit cells is configured such that inductances between the smoothing capacitor and the semiconductor switching element portion are equal to each other.
3. The power conversion apparatus according to claim 2,
the circuit units include a 1 st circuit unit and a 2 nd circuit unit connected in series with each other and arranged in a manner of being arranged in a 1 st direction,
the 1 st and 2 nd circuit units are configured to be plane-symmetric with respect to a center of a center between the 1 st and 2 nd circuit units, the center being orthogonal to the 1 st direction.
4. The power conversion apparatus according to claim 3,
the smoothing capacitor of each of the 1 st circuit unit and the 2 nd circuit unit has a rectangular parallelepiped shape including a terminal arrangement surface on which terminals of the smoothing capacitor are arranged,
The semiconductor switching element portions of the 1 st circuit unit and the 2 nd circuit unit are arranged along a side surface intersecting the terminal arrangement surface,
the 1 st circuit unit and the 2 nd circuit unit are arranged such that the terminal arrangement surface of the 1 st circuit unit and the terminal arrangement surface of the 2 nd circuit unit face each other.
5. The power conversion apparatus according to claim 4,
the power conversion device further includes an inter-cell connection portion that connects the semiconductor switching element portion of the 1 st circuit cell and the semiconductor switching element portion of the 2 nd circuit cell,
a plurality of the semiconductor switching element portions of the 1 st circuit unit are provided on the side surface so as to be aligned in a 2 nd direction orthogonal to the 1 st direction,
the semiconductor switching element portions of the 2 nd circuit unit are provided in plurality in the 2 nd direction orthogonal to the 1 st direction on the side surface so as to correspond to the respective semiconductor switching element portions of the plurality of semiconductor switching element portions of the 1 st circuit unit.
6. The power conversion apparatus according to claim 5,
the inter-unit connection portion includes at least any one of a notch and a through hole.
7. The power conversion apparatus according to claim 5 or 6,
the inter-cell connecting portion has a shape symmetrical with respect to a center line in the 2 nd direction of the inter-cell connecting portion along the 1 st direction.
8. The power conversion apparatus according to claim 5,
the inter-cell connection portion includes:
a 1 st portion provided at a position corresponding to the plurality of semiconductor switching element portions of the 1 st circuit unit so as to extend in the 2 nd direction;
a 2 nd portion provided at a position corresponding to the plurality of semiconductor switching element portions of the 2 nd circuit unit so as to extend along the 2 nd direction; and
a 3 rd part provided independently from the 1 st part and the 2 nd part in such a manner as to extend in the 1 st direction, and provided to connect the 1 st part and the 2 nd part.
CN202010136525.3A 2019-04-04 2020-03-02 Power conversion device Pending CN111865100A (en)

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