JP7247998B2 - game machine - Google Patents

Description

The present invention relates to gaming machines.

Pachinko game machines and slot machines are known as game machines. For example, a pachinko machine is provided with a storage section for storing game balls, and the game balls stored in the storage section are guided to a game ball launching device and directed to a game area in response to a player's shooting operation. is fired. Then, for example, when a game ball enters a ball entry section provided in the game area, for example, a lottery process is executed, or a process for increasing the number of game balls that can be used by the player is executed. be.

In a slot machine, when a game value such as medals is betted and a new game is started by operating a start lever, a lottery process is executed by a control means. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means Rotation of the reel is stopped by execution of rotation stop control. Then, when the stop result after the rotation of the reels is stopped corresponds to a winning combination in the lottery process, a privilege corresponding to the winning combination is given to the player (see Patent Document 1, for example).

JP 2014-045989 A

Here, in the game machines such as those exemplified above, it is necessary to suitably execute the transmission of the information group, and there is still room for improvement in this regard.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a game machine capable of suitably transmitting information groups.

In order to solve the above-mentioned problems, the invention according to claim 1 provides first transmission means for transmitting a first information group having a plurality of unit data based on occurrence of a first transmission trigger;
second transmission means for transmitting a second information group having a plurality of unit data based on occurrence of a second transmission trigger;
with
The first transmission means comprises a first identification means for identifying unit data to be transmitted as the first information group by referring to a predetermined reference information group,
The second transmitting means comprises second identifying means for identifying unit data to be transmitted as the second information group by referring to the predetermined reference information group ,
An information storage means having a plurality of storage areas set in association with addresses,
The predetermined reference information group is stored in a storage area of a continuous predetermined address range in the information storage means,
The first identifying means identifies a plurality of storage areas included in a predetermined aggregation target range including at least a part of a plurality of storage areas in which the predetermined reference information group is stored in the information storage means. It is characterized by comprising means for specifying, as unit data to be transmitted as the first information group, predetermined aggregated information in which information of bits at predetermined positions in the information specified by reference is aggregated.

ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to perform transmission of a group of information suitably.

1 is a front view of a slot machine according to a first embodiment; FIG. 1 is a perspective view of a slot machine showing a state in which a front door is opened; FIG. It is a front view of a housing|casing. It is a figure which shows the pattern arrangement|sequence of each reel. FIG. 10 is an explanatory diagram showing the relationship between a pattern and a combination line that can be visually recognized through the display window; FIG. 10 is an explanatory diagram showing the relationship between the winning mode and the privilege to be given; (a) It is a front view of a common display area, (b) It is explanatory drawing for demonstrating the display content of the display corresponding to the stop order performed by the dual-use display part. 4(a) and 4(b) are explanatory diagrams for explaining the relationship between the content of the stop order notification executed by the image display device and the display content of the stop order corresponding display executed by the combined display unit. FIG. 1 is an electrical configuration diagram of a slot machine; FIG. 4 is a flowchart showing main processing executed by the main MPU; 4 is a flowchart showing timer interrupt processing executed by the main MPU; It is a flowchart which shows the process at the time of a power failure performed by main side MPU. 4 is a flowchart showing normal processing executed by the main MPU; It is an explanatory view for explaining composition of main side RAM. It is a flowchart which shows the start waiting process performed by main side MPU. FIG. 10 is a flowchart showing bet handling processing executed by the main MPU; FIG. (a) is a flowchart showing a bet state management process executed by the main MPU; (b) is a flowchart showing a setting process at the start executed by the main MPU; FIG. 11 is a flow chart showing a lottery process for a winning combination executed by the main MPU; FIG. FIG. 11 is an explanatory diagram for explaining a combination lottery table when betting 3 coins; FIG. 11 is an explanatory diagram for explaining a combination lottery table when two cards are bet; FIG. 10 is an explanatory diagram for explaining the relationship between the order in which the reels are stopped and the winning mode to be established; 4 is a flowchart showing reel control processing executed by the main MPU; It is an explanatory diagram for explaining the game state and the game section that exist in the slot machine. (a) Explanatory diagrams for explaining the conditions under which the stop order correspondence display is executed, the conditions under which the ratio display is executed, and the conditions under which the given number display is executed in the combined display unit, and (b) an index value counter. is an explanatory diagram for explaining the relationship between the value of , the value of the stop order type counter, and the display contents of the stop order correspondence display executed by the combined display unit; It is an explanatory diagram. It is a flowchart which shows the lottery result handling process performed by main side MPU. FIG. 10 is a flow chart showing winning determination processing executed by the main MPU; FIG. FIG. 10 is a flowchart showing management processing executed by the main MPU; FIG. 4 is a flowchart showing port output processing executed by the main MPU; (a) to (i) are time charts showing how display corresponding to the stop order and display of the given number are executed on the combined display unit. (a) to (f) are time charts showing how ratio display and given number display are executed in the combined display section. (a) An explanatory diagram for explaining the configuration of a game section area, and (b) an explanatory diagram for explaining the configuration of a game state area. FIG. 10 is a flow chart showing a corresponding process at the end of a game, which is executed by the main MPU; FIG. It is a flowchart which shows the process for CB performed by main side MPU. It is a flowchart which shows the 1st control processing of the game area performed by main side MPU. (a) An explanatory diagram for explaining the contents of a number-of-releases lottery table, and (b) a flowchart showing a number-of-releases-games lottery process executed by the main MPU. It is a flowchart which shows the 2nd control processing of the game area performed by main side MPU. FIG. 10 is a flowchart showing ending handling processing executed by the main MPU; FIG. FIG. 10 is a flowchart showing advantageous lottery processing at the start of a game, which is executed by the main MPU; FIG. It is a flowchart which shows the normal process performed by main side MPU. FIG. 10 is a flow chart showing advantageous state processing at the start of a game, which is executed by the main MPU; FIG. FIG. 10 is a flow chart showing a pseudo-bonus process executed by the main MPU; FIG. FIG. 10 is a flowchart showing AT processing executed by the main MPU; FIG. (a) is an explanatory diagram for explaining the contents of a first additional lottery table; (b) is an explanatory diagram for explaining the contents of a second additional lottery table; It is a flow chart showing a process for addition at the time of starting. 4 is a flowchart showing command output processing executed by the main MPU; It is an explanatory diagram for explaining the electrical configuration of the main control board and effect control board for transmitting a command from the main side MPU to the effect side MPU. (a) is an explanatory diagram for explaining the data structure of the header; (b) is an explanatory diagram for explaining the data structure of the footer; FIG. 10 is an explanatory diagram for explaining a setting mode in the main side RAM of a storage area to be stored; (a) is an explanatory diagram for explaining the data configuration of the start command and the end command; (b) is an explanatory diagram for explaining the data configuration of the post-conversion start command; (c) post-conversion end FIG. 4 is an explanatory diagram for explaining the data configuration of an hour command; (a) is an explanatory diagram for explaining a conversion mode of a start command; (b) is an explanatory diagram for explaining a conversion mode of an end command; (a) It is an explanatory diagram for explaining the contents grasped by the production side MPU based on the post-conversion start time command, and (b) for explaining the contents grasped by the production side MPU based on the post-conversion end time command. is an explanatory diagram of . FIG. 11 is a flowchart showing common command transmission processing executed by the main MPU; FIG. FIG. 11 is a flow chart showing top-level aggregation processing executed by the main MPU; FIG. It is a flowchart which shows the command reception correspondence process performed by production|presentation side MPU. It is a flowchart which shows the top setting process performed by production|presentation side MPU. It is a flowchart which shows the command conversion process performed by production|presentation side MPU. It is a flowchart which shows the reception correspondence process at the time of start performed by production|presentation side MPU. It is a flowchart which shows the winning-awards receiving correspondence process performed by production|presentation side MPU. It is a flowchart which shows the reception correspondence process at the time of completion|finish performed by production|presentation side MPU. It is a flowchart which shows the 2nd area correspondence process performed by production|presentation side MPU. It is a flowchart which shows the pseudo-bonus state correspondence process performed by production side MPU. It is a flowchart which shows AT state correspondence processing performed by production|presentation side MPU. (a) is an explanatory diagram for explaining the configuration of the main MPU, and (b) is an explanatory diagram for explaining how data and programs are set in the main ROM. (a) An explanatory diagram for explaining types of jump instructions, (b) an explanatory diagram for explaining program contents of a power-off standby process executed by the main MPU, and (c) line numbers. FIG. 10 is an explanatory diagram for explaining the state of jump flags when an OUT instruction of “1001” is executed; (a) is an explanatory diagram for explaining a configuration for externally outputting a signal from the slot machine to the hall computer; (b) is a flowchart showing an external output setting process executed by the main MPU; ) is an explanatory diagram for explaining the relationship between the value of the AT state flag, the value of the AT state signal counter, and the AT state signal. (a) is an explanatory diagram for explaining the program contents of the AT state signal setting process executed by the main MPU, and (b) and (c) are comparative examples of the AT state signal setting process and the AT state signal setting process; 3 is an explanatory diagram for explaining a jump instruction set for jumping from the program address "ADR112" to the program address "ADR114" in FIG. FIG. 10 is an explanatory diagram for explaining the relationship between the value of the A register before adding "246" and the value of the A register and the value of the carry flag CF after adding "246"; FIG. 10 is an explanatory diagram for explaining program contents of a lottery result handling process executed by the main MPU; (a) is an explanatory diagram for explaining the program contents of the first comparative example of the lottery result handling process; FIG. 10 is an explanatory diagram for explaining a command set for executing a process of setting a stop order type number in a counter; (a), (b) In the lottery result corresponding process and the second comparative example of the lottery result corresponding process, the program address "ADR122" and the program address "ADR125" are set to jump to the program address "ADR126". FIG. 10 is an explanatory diagram for explaining a jump instruction that is (a) is an explanatory diagram for explaining the relationship between the value of the A register before subtraction of "11", the value of the A register after subtraction of "11", and the value of the carry flag after subtraction of "11"; b) It is an explanatory diagram for explaining the program content of the process for addition at the time of start executed by the main MPU. (a) is an explanatory diagram for explaining program contents of a first comparative example of additional processing at start; FIG. 10 is an explanatory diagram for explaining a command set for selecting a lottery table and a command set for selecting a second additional lottery table; (a), (b) Setting for jumping from the program address "ADR131" and the program address "ADR132" to the program address "ADR133" in the second comparative example of the additional processing at the start and the additional processing at the start FIG. 10 is an explanatory diagram for explaining a jump instruction that is executed; (a) It is an explanatory diagram for explaining the configuration of a main-side RAM 74 in the second embodiment, and (b) a flowchart showing a common command transmission process executed by the main-side MPU. FIG. 11 is a flow chart showing top-level aggregation processing executed by the main MPU; FIG. (a) It is an explanatory diagram for explaining the configuration of the main side RAM in the third embodiment, and (b) is a flowchart showing a common command transmission process executed by the main side MPU. FIG. 11 is a flow chart showing top-level aggregation processing executed by the main MPU; FIG. (a) It is explanatory drawing for demonstrating the data structure of the common data table in 4th Embodiment, (b) explanatory drawing for demonstrating the structure of main side RAM. FIG. 11 is a flowchart showing common command transmission processing executed by the main MPU; FIG. FIG. 11 is a flow chart showing top-level aggregation processing executed by the main MPU; FIG. (a) Among the address range in which the common data table of the main ROM in the fifth embodiment is set, the address of the storage area of the main RAM storing the data set in the start command is set. (b) is an explanatory diagram for explaining the address range in which the address range in which the data set in the command at the end is set and the address range in which the address of the storage area of the main RAM in which the data set in the command at the end is set; (c) is an explanatory diagram for explaining the data configuration of a command at the time of termination. (a) It is an explanatory diagram for explaining the electrical configuration of the main control board and the effect control board for transmitting commands from the main side MPU to the effect side MPU, and (b) the configuration of the highest setting area. It is an explanatory view for explaining. FIG. 11 is a flowchart showing common command transmission processing executed by the main MPU; FIG. It is a flowchart which shows the command reception correspondence process performed by production|presentation side MPU. It is a flowchart which shows the top setting process performed by production|presentation side MPU. (a) is an explanatory diagram for explaining the structure of a common data table in the sixth embodiment; (b) is an explanatory diagram for explaining the data structure of a start command; FIG. 4 is an explanatory diagram for explaining a data structure; It is an explanatory view for explaining composition of main side RAM. FIG. 11 is a flowchart showing common command transmission processing executed by the main MPU; FIG. FIG. 11 is a flow chart showing top-level aggregation processing executed by the main MPU; FIG. It is a flowchart which shows the top setting process performed by production|presentation side MPU. (a) The condition that the dual-purpose display unit in the seventh embodiment is in a completely extinguished state, the condition that the display corresponding to the stop order is executed on the dual-purpose display unit, the condition that the ratio display is executed, and the given number display are executed (b) is an explanatory diagram for explaining the configuration of the main-side RAM; (c) is a flowchart showing a setting process at the time of start executed by the main-side MPU; . 4 is a flowchart showing reel control processing executed by the main MPU; 4 is a flowchart showing port output processing executed by the main MPU; (a) to (k) are time charts showing how the dual-purpose display section is in a fully extinguished state in a game in which stop order correspondence display is performed on the dual-purpose display section. (a) to (i) are time charts showing how the dual-purpose display section is in a fully extinguished state in a game in which stop order correspondence display is not performed on the dual-purpose display section. (a) It is an explanatory diagram for explaining the configuration of the main side RAM in the eighth embodiment, and (b) is a flowchart showing lottery result corresponding processing executed by the main side MPU. 7 is a flowchart showing timer subtraction processing executed by the main MPU; (a) to (j) are time charts showing how the dual-use display section is in a completely extinguished state in a game in which stop order correspondence display is not performed on the dual-use display section. (a) is an explanatory diagram for explaining the display mode of the non-leading display executed by the combined display unit in the ninth embodiment, (b) conditions for executing the non-leading display by the combined display unit; FIG. 10 is an explanatory diagram for explaining the conditions under which the stop order correspondence display is executed, the conditions under which the ratio display is executed, and the conditions under which the granted number display is executed; It is a flow chart which shows processing. 4 is a flowchart showing port output processing executed by the main MPU; (a) to (h) are time charts showing how non-guidance display is executed in the combined display unit. (a) is an explanatory diagram for explaining the contents of a program for an additional process at start executed by the main MPU in the tenth embodiment; FIG. 14 is an explanatory diagram for explaining jump instructions set for jumping from program addresses “ADR141” and program addresses “ADR142” to program addresses “ADR133” in the third comparative example of the add-on processing; (a) is an explanatory diagram for explaining a jump instruction execution circuit provided in the main MPU in the eleventh embodiment, and (b) is for explaining the configuration of the main ROM for executing the additional lottery (c) is an explanatory diagram for explaining the contents of the third addition lottery table; (d) the value of the index value counter and the zero flag and carry after execution of the operation of subtracting "2" FIG. 4 is an explanatory diagram for explaining the relationship with flag values; (a) is an explanatory diagram for explaining the program content of the additional processing at start executed by the main MPU; (b) is an explanatory diagram for explaining the program content of the fourth comparative example of the additional processing at start; FIG. 11 is an explanatory diagram for explaining commands set for selecting the first to third additional lottery tables in (c) the additional processing at the start and the fourth comparative example of the additional processing at the start; It is a diagram. (a) is an explanatory diagram for explaining the configuration of the main side ROM for executing the additional lottery in the twelfth embodiment, and (b) is for explaining the configuration of the main side RAM for executing the lottery effect; (c) is a flowchart showing AT processing executed by the main MPU. FIG. 11 is a flow chart showing a start-time add-on process executed by the main MPU; FIG. (a), (b) In the fifth comparative example of the additional processing at the start and the additional processing at the start, to jump from the program address "ADR161" and the program address "ADR162" to the program address "ADR163" FIG. 10 is an explanatory diagram for explaining jump instructions that are set; (a) is an explanatory diagram for explaining the program contents of the additional processing at the start in the thirteenth embodiment, and (b) and (c) the additional processing at the start and the sixth comparative example of the additional processing at the start; 3 is an explanatory diagram for explaining a command set for calling the lottery execution process in FIG.

<First embodiment>
A first embodiment in which the present invention is applied to a slot machine 10, which is a type of game machine, will be described in detail below with reference to the drawings. 1 is a front view of the slot machine 10, FIG. 2 is a perspective view of the slot machine 10 with the front door 12 opened, and FIG.

As shown in FIGS. 2 and 3, the slot machine 10 has a housing 11 forming its outer shell. A plurality of wooden panels are fixed to the housing 11 so that the housing 11 is formed into a box-like shape that is open forward as a whole.

A front door 12 is attached to the front side of the housing 11 as shown in FIGS. The front door 12 is supported by the housing 11 so as to be able to open and close the internal space of the housing 11 with a shaft portion 15 provided on the left side of the housing 11 as a rotation axis. The front door 12 is locked so that it cannot be opened by a locking device 13 provided on the rear side thereof.

A game panel 20 is provided near the upper center portion of the front door 12 as shown in FIG. The game panel 20 has three vertically long display windows 21L, 21M, and 21R arranged side by side. The display windows 21L, 21M and 21R are made of a transparent or translucent material, and the inside of the slot machine 10 is visible through the display windows 21L, 21M and 21R.

As shown in FIGS. 2 and 3, the inside of the housing 11 is divided into upper and lower parts by a partition plate 11a, and the reel unit 31 is attached to the upper part of the partition plate 11a. The reel unit 31 includes a left reel 32L, a middle reel 32M, and a right reel 32R, which are each formed in a cylindrical shape. Each of the reels 32L, 32M, 32R is rotatably supported such that its center axis coincides with the rotation axis of the reel 32L, 32M, 32R. The rotation axes of the reels 32L, 32M, 32R are arranged on the same axis extending substantially horizontally, and the reels 32L, 32M, 32R correspond to the display windows 21L, 21M, 21R one-to-one. there is Therefore, a part of the surface of each reel 32L, 32M, 32R is visible through the corresponding display window portions 21L, 21M, 21R. Further, when the reels 32L, 32M, 32R rotate forward, the surfaces of the reels 32L, 32M, 32R are projected through the respective display windows 21L, 21M, 21R as if they are moving from top to bottom.

A start lever 41 is provided on the lower left side of the game panel 20 as shown in FIG. When the start lever 41 is operated when a predetermined number or more of game media (or game value), which are either medals or virtual medals, are betted, the reels 32L, 32M and 32R start rotating all at once.

On the right side of the start lever 41, stop buttons 42, 43, 44 are provided to be operated to individually stop the rotating reels 32L, 32M, 32R. The respective stop buttons 42, 43, 44 are arranged directly below the display windows 21L, 21M, 21R corresponding to the reels 32L, 32M, 32R to be stopped, respectively. Each of the stop buttons 42, 43, 44 is in a state in which it can be stopped after a predetermined time has passed since the left reel 32L started rotating.

The reels 32L, 32M, and 32R start rotating based on the operation of the start lever 41, and the reels 32L, 32M, and 32R stop rotating based on the operation of the stop buttons 42, 43, and 44. One game (game cycle) is performed until the execution of various processes such as the granting of and the management of the game state is completed.

A medal slot 45 for inserting medals is provided on the lower right side of the display windows 21L, 21M, and 21R. As shown in FIG. 2, the medals inserted from the medal insertion slot 45 are guided to the hopper device 53 by the selector 52 provided on the back of the front door 12 when reception is permitted, and are guided to the hopper device 53 when reception is prohibited. The medals are led to a medal receiving tray 59 from a medal discharge port 58 provided in the front lower portion of the front door 12 (see FIG. 1). The hopper device 53 has a function of paying out the medals stored in the storage tank to the medal receiving tray 59 through the medal discharge port 58 when a prize corresponding to the awarding of game media is established on the main line ML, which will be described later. have. Below the medal slot 45, as shown in FIG. 1, a return button 46 is provided to be pushed when the medals inserted into the medal slot 45 are stuck in the selector 52. As shown in FIG.

On the lower left side of the display windows 21L, 21M, and 21R are a first credit insertion button 47 for inserting the maximum amount of credited virtual medals that can be betted at once, and a button for inserting two virtual medals at once. A second credit input button 48 is provided. In this slot machine 10, there are situations where the number of game media (medals or virtual medals) that can be betted (that is, bet setting) at one time is "3" and "2".

The first credit insertion button 47 is operated in a situation where the number of bets that can be betted at one time is "3", the current number of bets is "0", and three or more virtual medals are stored. In this case, the number of bets becomes "3" instead of decreasing the number of virtual medals by three. The first credit insertion button 47 is operated in a situation where the number of bets that can be made at one time is "3", the current number of bets is "1", and two or more virtual medals are stored. In this case, the number of bets becomes "3" instead of the number of virtual medals being reduced by two. The first credit insertion button 47 is operated in a situation where the number of bets that can be betted at one time is "3", the current number of bets is "2", and one or more virtual tokens are stored. In this case, the number of bets becomes "3" instead of the number of virtual medals being reduced by one. The first credit insertion button 47 is operated in a situation where the number of bets that can be betted at one time is "2", the current number of bets is "0", and two or more virtual medals are stored. In this case, the number of bets becomes "2" instead of the number of virtual medals being reduced by two. The first credit insertion button 47 is operated in a situation where the number of bets that can be betted at one time is "2", the current number of bets is "1", and one or more virtual medals are stored. In this case, the number of bets becomes "2" instead of the number of virtual medals being reduced by one.

If the number of stored virtual medals is less than the difference between the current bet number and the bettable number, and the first credit insertion button 47 is operated, the bet number will be the number of virtual medals. The number of virtual medals is increased, and the number of virtual medals becomes zero.

The second credit insertion button 48 is operated in a situation where the number of bets that can be betted at one time is "3", the current number of bets is "0", and two or more virtual medals are stored. In this case, the number of bets becomes "2" instead of the number of virtual medals being reduced by two. The second credit insertion button 48 is operated in a situation where the number of bets that can be betted at one time is "3", the current number of bets is "1", and one or more virtual medals are stored. In this case, the number of bets becomes "2" instead of the number of virtual medals being reduced by one. The second credit insertion button 48 is operated in a situation where the number of bets that can be made at one time is "2", the current number of bets is "0", and two or more virtual medals are stored. In this case, the number of bets becomes "2" instead of the number of virtual medals being reduced by two. The second credit insertion button 48 is operated in a situation where the number of bets that can be betted at one time is "2", the current number of bets is "1", and one or more virtual medals are stored. In this case, the number of bets becomes "2" instead of the number of virtual medals being reduced by one.

When the second credit insertion button 48 is operated in a situation where the number of stored virtual medals is one and the current bet number is "0", the bet number will be "1". At the same time, the number of virtual medals becomes zero.

The first credit insertion button 47 has a wider pressing surface than the second credit insertion button 48 when the player operates the button. Thereby, the operability of the first credit insertion button 47 is enhanced.

A settlement button 51 is provided on the left side of the start lever 41 . The slot machine 10 has a credit function of accumulating and storing surplus inserted medals up to a predetermined maximum value (equivalent to 50 medals) and payout medals at the time of winning as virtual medals. When the settlement button 51 is operated under the condition that the virtual medals are stored and stored, the virtual medals are dispensed from the medal discharge port 58 as real medals.

A power supply device 54 is provided inside the housing 11 to the left of the hopper device 53 as shown in FIGS. The power supply device 54 includes a power switch 55 operated when the power is turned on or off, a reset button 56 for resetting various states of the slot machine 10, and a set value of the slot machine 10 from "1" to "6". , a setting key insertion hole 57 into which a setting key owned by the manager of the game hall is inserted and operated is provided.

Next, the symbols attached to each reel 32L, 32M, 32R will be described.

FIG. 4 shows the pattern arrangement of the left reel 32L, middle reel 32M and right reel 32R. As shown in the figure, 21 symbols are arranged in a line on each reel 32L, 32M, 32R. In addition, numbers "0" to "20" are assigned to the respective reels 32L, 32M, 32R, and these numbers are visible from the display windows 21L, 21M, 21R of the main controller 70, which will be described later. It is a number for recognizing the symbol in a state of being in a bad state, and is not actually attached to the reels 32L, 32M, 32R. However, the numbers will be used in the following description.

The symbols include a “bell” symbol (eg, 20th on the left reel 32L), a “replay” symbol (eg, 19th on the left reel 32L), a “watermelon” symbol (eg, 18th on the left reel 32L), and “ Red 7" symbol (e.g., 15th on left reel 32L), "BAR" symbol (e.g., 10th on left reel 32L), "Cherry" symbol (e.g., 9th on left reel 32L), "White 7" symbol (for example, the 5th on the left reel 32L). The number and arrangement order of various symbols are different for each of the reels 32L, 32M, and 32R.

FIG. 5 is a front view of the display windows 21L, 21M and 21R. Each of the display window portions 21L, 21M, 21R is formed so that three of the 21 symbols attached to the corresponding reels 32L, 32M, 32R are visible as a whole. Therefore, when all the reels 32L, 32M, 32R are stopped, 3×3=9 symbols are visible through the display windows 21L, 21M, 21R.

In this slot machine 10, one main line ML is set so as to connect positions where symbols on the reels 32L, 32M, and 32R are visible. The main line ML is a line connecting the middle symbols of the left reel 32L, the middle symbols of the middle reel 32M, and the middle symbols of the right reel 32R. The reels 32L, 32M, and 32R are started to rotate in a state where a predetermined number or more of game media are betted, and when a prize corresponding to the winning combination is established on the main line ML, the profit of giving the game media. , the benefit of replaying, or the transition of the game state.

That is, in the present slot machine 10, only one main line ML is set as a line on which winning can be established. The main line ML is set as a straight line. Therefore, a subline SL1 connecting the upper pattern of the left reel 32L, the middle pattern of the middle reel 32M and the lower pattern of the right reel 32R, and the upper pattern of the left reel 32L, the upper pattern of the middle reel 32M and the upper pattern of the right reel 32R. A subline SL3 connecting a connected subline SL2, a lower pattern of the left reel 32L, a lower pattern of the middle reel 32M, and a lower pattern of the right reel 32R, a lower pattern of the left reel 32L, a middle pattern of the middle reel 32M, and a right reel 32R. Winning is not established even if a winning combination is established on a straight line such as a sub-line SL4 connecting the upper symbols of .

Hereinafter, with reference to FIG. 6, the correspondence relationship between the combination of winning symbols and the privilege given when winning will be described. FIG. 6 is an explanatory diagram for explaining the correspondence relationship between the combination of winning symbols and the privilege given when winning.

The small winnings to which the game media are given include the first compensation winning, the second compensation winning, the third compensation winning, the fourth compensation winning, the fifth compensation winning, the sixth compensation winning, the seventh compensation winning, and the eighth compensation winning. There are supplemental prizes, ninth supplemental prizes, first bell prizes, second bell prizes, first watermelon prizes, second watermelon prizes and cherry prizes. Specifically, in the main line ML, when the stopped symbol on the left reel 32L is a "bell" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "red 7" symbol, It will be the first supplementary prize. In the main line ML, when the stopped symbol on the left reel 32L is a "bell" symbol, the stopped symbol on the middle reel 32M is a "red 7" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, the second compensation winning prize becomes. In the main line ML, when the stopped symbol on the left reel 32L is a "red 7" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, the third compensation winning prize becomes. In the main line ML, when the stopped symbol on the left reel 32L is the "Bell" symbol, the stopped symbol on the middle reel 32M is the "Bell" symbol, and the stopped symbol on the right reel 32R is the "BAR" symbol, the fourth supplementary prize is awarded. Become. In the main line ML, when the stopped symbol on the left reel 32L is a "bell" symbol, the stopped symbol on the middle reel 32M is a "BAR" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, the fifth supplementary prize is awarded. Become. In the main line ML, when the stopped symbol on the left reel 32L is the "BAR" symbol, the stopped symbol on the middle reel 32M is the "Bell" symbol, and the stopped symbol on the right reel 32R is the "Bell" symbol, the sixth supplementary prize is awarded. Become. In the main line ML, when the stopped symbol on the left reel 32L is a "bell" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "white 7" symbol, the seventh compensation winning prize becomes. In the main line ML, when the stopped symbol on the left reel 32L is a "bell" symbol, the stopped symbol on the middle reel 32M is a "white 7" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, the eighth compensation winning prize becomes. In the main line ML, when the stopped symbol on the left reel 32L is a "white 7" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, the ninth compensation prize is won. becomes. If any one of the first to ninth supplementary prizes is won, the number of game media to be given becomes “1”.

When the stopped symbol on the left reel 32L is the "bell" symbol, the stopped symbol on the middle reel 32M is the "bell" symbol, and the stopped symbol on the right reel 32R is the "bell" symbol on the main line ML, the first bell wins. becomes. When the stopped symbol on the left reel 32L is the "bell" symbol, the stopped symbol on the middle reel 32M is the "bell" symbol, and the stopped symbol on the right reel 32R is the "replay" symbol on the main line ML, the second bell wins. becomes. When either the first bell prize or the second bell prize is won, the number of game media to be given becomes “15”.

When the stopped symbol on the left reel 32L is the "watermelon" symbol, the stopped symbol on the middle reel 32M is the "watermelon" symbol, and the stopped symbol on the right reel 32R is the "watermelon" symbol on the main line ML, the first watermelon wins. becomes. On the main line ML, when the stopped symbol on the left reel 32L is a "watermelon" symbol, the stopped symbol on the middle reel 32M is a "watermelon" symbol, and the stopped symbol on the right reel 32R is a "BAR" symbol, the second watermelon wins. becomes. When either the first watermelon prize or the second watermelon prize is won, the number of game media to be given becomes “5”. When the stopped symbol of the left reel 32L on the main line ML is a "cherry" symbol, the cherry prize is won regardless of whether the stopped symbol of the middle reel 32M or the right reel 32R is. In the case of winning a cherry prize, the number of game media to be given becomes “2”.

Winnings that give the privilege of replaying the next game without betting game media include normal replay winnings, first chance replay winnings, and second chance replay winnings. Specifically, when the stopped symbol on the left reel 32L is the "replay" symbol, the stopped symbol on the middle reel 32M is the "replay" symbol, and the stopped symbol on the right reel 32R is the "replay" symbol on the main line ML, On the main line ML, when the stopped symbol on the left reel 32L is a "red 7" symbol, the stopped symbol on the middle reel 32M is a "red 7" symbol, and the stopped symbol on the right reel 32R is a "BAR" symbol, the main line On the ML, when the stopped symbol on the left reel 32L is a "replay" symbol, the stopped symbol on the middle reel 32M is a "red 7" symbol, and the stopped symbol on the right reel 32R is a "replay" symbol, on the main line ML When the stopped symbol on the left reel 32L is a "replay" symbol, the stopped symbol on the middle reel 32M is a "red 7" symbol, and the stopped symbol on the right reel 32R is a "BAR" symbol, or the left reel on the main line ML. When the stopped symbol on the reel 32L is a "watermelon" symbol, the stopped symbol on the middle reel 32M is a "red 7" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, the normal replay prize is won. When the stopped symbol on the left reel 32L is the "replay" symbol, the stopped symbol on the middle reel 32M is the "cherry" symbol, and the stopped symbol on the right reel 32R is the "bell" symbol on the main line ML, the first chance replay. Win a prize. When the stopped symbol on the left reel 32L is a "watermelon" symbol, the stopped symbol on the middle reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "replay" symbol on the main line ML, the second chance replay. Win a prize.

If any of the above replay wins are made, a replay privilege is given that allows the player to play the next game without betting the game medium. Specifically, if any of the replay wins in the game in which "3" game media are betted, the betting of the game media is not required, and the next game is started with the "3" game media being betted. A game can be started. In addition, if any of the replay wins in the game in which the game medium "2" is betted, the play of the next game is started with the game medium "2" betted, while the game medium is not required to be wagered. It becomes possible to

A first CB prize and a second CB prize are available as state transition prizes in which only game state transitions are performed. Specifically, on the main line ML, the stopped symbol on the left reel 32L is the "Red 7" symbol, the stopped symbol on the middle reel 32M is the "Red 7" symbol, and the stopped symbol on the right reel 32R is the "White 7" symbol. If there is, it will be the 1st CB prize. On the main line ML, when the stopped symbol on the left reel 32L is the "white 7" symbol, the stopped symbol on the middle reel 32M is the "white 7" symbol, and the stopped symbol on the right reel 32R is the "red 7" symbol, 2CB award. When the first CB win is established, the game state shifts to the first CB state ST2, and when the second CB win is established, the game state shifts to the second CB state ST3 (see FIG. 23).

The first CB state ST2 and the second CB state ST3 are game states in which when the combination of symbols corresponding to the winning of a minor combination stops on the main line ML, medals are paid out as a winning regardless of whether there is a winning combination. For example, even if winning data corresponding to the first bell winning is not set, game media are provided to the player when the combination of symbols corresponding to the first bell winning is stopped on the main line ML. On the other hand, the replay winning prize is established on the condition that the corresponding combination is won in the lottery.

In the first CB state ST2 and the second CB state ST3, reel control different from that in the non-CB state is performed. In the non-CB state, the reels 32L, 32M, and 32R are controlled so that the reels 32L, 32M, and 32R can slide up to four symbols after the stop buttons 42-44 are operated. In other words, in the non-CB state, reel control is performed for each of the reels 32L, 32M, and 32R to stop the reels within a specified time (190 milliseconds) after the stop buttons 42 to 44 are operated. On the other hand, in the first CB state ST2 and the second CB state ST3, the middle reel 32M and the right reel 32R are controlled as described above, that is, the same reel control as in the normal game, but the left reel 32L is not controlled. As for the left reel 32L, reel control is performed such that the left reel 32L is slid only up to one symbol after the left stop button 42 is operated. That is, in the first CB state ST2 and the second CB state ST3, the left reel 32L is reel-controlled to stop within a specified time (75 msec) shorter than the specified time after the left stop button 42 is operated.

In the first CB state ST2 and the second CB state ST3, the reel control to slide up to one symbol is not limited to the left reel 32L. Control may be performed such that the game is slipped only up to the symbol, or reel control may be performed such that only predetermined reels are slipped for a maximum of one symbol. Further, the stop button operated in a certain order is controlled such that the reel corresponding to the stop button operated second or the stop button operated last is controlled to slide only up to one symbol. Reel control may be performed such that the reel corresponding to the .

In the first CB state ST2 and the second CB state ST3, when a winning combination corresponding to the replay winning is won, the replay winning is given priority, and when the replay winning is not possible, the first bell winning can be established. Also, the first bell winning can be established even when the winning combination corresponding to the replay winning has not been won.

Both the first CB state ST2 and the second CB state ST3 are game states in which the game media owned by the player are not increased. Furthermore, in both the first CB state ST2 and the second CB state ST3, the number of game media owned by the player at the end of the game state is greater than the number of game media owned by the player at the start of the game state. It is a game state in which the number of is reduced.

Next, a device for executing various notifications and various effects will be described.

Above the front door 12, as shown in FIG. 1, an upper lamp 61, a speaker 62, and an image display device 63 are provided. When an abnormality occurs in the slot machine 10, light emission of the upper lamp 61 is controlled in a manner corresponding to the abnormality, and light emission is controlled in a manner corresponding to the winning result. Further, the upper lamp 61 is controlled to emit light so that a light emission effect corresponding to the display effect on the image display device 63 is performed. The speakers 62 are provided as a pair of left and right speakers, and when an abnormality occurs in the slot machine 10, the sound output is controlled so that a sound or voice corresponding to the abnormality is output, and a sound or voice corresponding to the winning result is output. Sound output is controlled so that Further, the speaker 62 is controlled to output sound so that a sound output effect corresponding to the display effect on the image display device 63 is performed.

The image display device 63 has a display surface and is configured as a liquid crystal display device having a liquid crystal display, but is not limited to a liquid crystal display device, and may be a plasma display device, an organic EL display device, or a CRT. It may be another display device having a display surface, or it may be a dot matrix display. When an abnormality occurs in the slot machine 10, display control is performed so that an image corresponding to the abnormality is displayed on the display surface. Further, the image display device 63 is controlled to display on the display surface images corresponding to the winning result of the winning combination in the internal lottery and the winning result in each game. That is, the image display device 63 executes a display effect.

On the game panel 20 of the front door 12, below the display windows 21L, 21M, and 21R, there is a credit display section 65 for displaying the number of virtual medals stored, and a credit display section 65 for displaying the number of virtual medals to be given when a small winning combination is won. When the number of game media is displayed and the stopping order of the reels 32L, 32M, and 32R is reported on the image display device 63, a display corresponding to the reported contents is performed, and furthermore, the management result of the game history is reported. A combined display portion 66 for performing display for the purpose and a section display portion 67 for performing display corresponding to the fact that the game section is the second section are provided. The credit display section 65 is composed of a 7-segment display, and each segment uses a single-color LED such as green.

FIG. 7A is a front view of a common display area 68 provided with a combined display section 66 and a section display section 67. FIG. In the common display area 68, as shown in FIG. 7(a), a combined display section 66 in which two 7-segment displays 66a and 66b are arranged side by side, and a section display section consisting of one light emitting section. 67 are aggregated.

When any of the small wins (1st to 9th compensation wins, 1st bell wins, 2nd bell wins, 1st watermelon wins, 2nd watermelon wins or cherry wins) corresponding to the provision of game media is established , the combined display unit 66 displays the number of given game media corresponding to the small winning combination when the game in which the small winning combination is established is finished. Specifically, when any one of the first to ninth compensation winnings is established in the non-CB state, the left 7-segment display 66a is hidden and "1" is displayed on the right 7-segment display 66b. By being displayed, it is notified that the game media of "1" have been provided. When either the first bell win or the second bell win is established in the non-CB state, "1" is displayed on the left 7-segment display 66a and "5" is displayed on the right 7-segment display 66b. By being displayed, it is notified that "15" game media have been provided. Further, when either the first watermelon winning prize or the second watermelon winning prize is established in the non-CB state, the left 7-segment display 66a is hidden and "5" is displayed on the right 7-segment display 66b. By doing so, it is notified that "5" game media have been provided. In addition, when a cherry prize is won in the non-CB state, the left 7-segment display 66a is hidden, and '2' is displayed on the right 7-segment display 66b, whereby the game medium of '2' is displayed. is given.

In the first CB state ST2 and the second CB state ST3, the number of game media awarded for winning a small winning combination is "1", as will be described later in detail. Therefore, when a small winning combination is established in the first CB state ST2 or the second CB state ST3, the left 7-segment display 66a is hidden and "1" is displayed on the right 7-segment display 66b. By doing so, it is notified that the game medium of "1" has been awarded.

On the other hand, even if a winning such as a replay winning or a CB winning that does not give a game medium is established, the display corresponding to the winning is not displayed on the combined display section 66. When "0" is displayed on the 7-segment display 66a on the left side and the 7-segment display 66b on the right side, it is notified that the small winning combination has not been established. The display of the number of given game media on the dual-purpose display unit 66 is terminated when the game media are betted to start the next game after the game in which the display was performed, and at the timing of this bet, the 7 segments on the left side are displayed. "0" is displayed on the display 66a and the right 7-segment display 66b. The case where game media are betted to start the game means that "1" or more game media are betted by operating the credit insertion buttons 47 and 48, or the game media are inserted into the medal insertion slot 45. This is the case where the inserted medals are detected by an inserted medal detection sensor 45a, which will be described later.

When the stop order of the reels 32L, 32M, and 32R is reported on the image display device 63, information corresponding to the reported stop order is displayed on the combined display section 66. FIG. In this specification, the notification of the stop order of the reels 32L, 32M, and 32R performed by the image display device 63 is also referred to as stop order notification. Further, the display corresponding to the stopping order of the reels 32L, 32M, and 32R performed by the dual-use display unit 66 is also called the stopping order corresponding display. FIG. 7(b) is an explanatory diagram for explaining the display contents of the stop order corresponding display executed by the dual-use display unit 66. As shown in FIG. In the slot machine 10, the reels 32L, 32M, and 32R are stopped in the order indicated by the image display device 63. The first stop is the left reel 32L, the second stop is the middle reel 32M, and the third stop is the right reel 32R. and a second stop order in which the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the middle reel 32M, and the first stop is the middle reel 32M. A third stop sequence in which the second stop is the left reel 32L and the third stop is the right reel 32R, and the first stop is the middle reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L. A fourth stop order, a fifth stop order where the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the middle reel 32M, and the first stop is the right reel 32R and the third stop order. A sixth stop order where the second stop is the middle reel 32M and a third stop is the left reel 32L, a seventh stop order where the first stop is the left reel 32L and the rest are optional, and a first stop is the middle reel 32M. and the rest are optional, and a ninth stop order where the first stop is the right reel 32R and the rest are optional.

The notification of the stop order in the image display device 63 is made when a winning combination including the first bell winning data and any of the first to sixth compensation winning data is won in the winning lottery process in the non-CB state, or It can be executed when a winning combination containing any of the 7th to 9th complementary winning data as well as the 2 bell winning data is won. Specifically, when winning a combination that includes the first bell winning data and any of the first to sixth complementary winning data, the reel 32L is selected in the stop order corresponding to the current winning combination among the above stop orders. , 32M, and 32R are stopped, the first bell winning is established, and if the reels 32L, 32M, and 32R are not stopped in the order of stopping corresponding to the winning combination of this time, the first to sixth compensation winnings are established. Either can be established. When the first bell win is established, as already explained, "15" game media are given to the player. of game media is given to the player.

When a winning combination including the second bell winning data and any of the seventh to ninth complementary winning data is won, the reels 32L, 32M, and 32R are played in the stop order corresponding to the current winning combination among the above stop orders. If the reels 32L, 32M, and 32R are not stopped in the order of stopping corresponding to the winning combination of this time, any one of the seventh to ninth complementary winnings is established. obtain. When the second bell win is established, as already explained, "15" game media are given to the player. of game media is given to the player.

When any one of the stop orders is notified by the image display device 63, the left 7-segment display 66a of the dual-use display unit 66 is maintained in a non-display state, while the right 7-segment display 66b is maintained. , a display corresponding to the stop order of the notification target (stop order corresponding display) is performed. The display contents of the stop order correspondence display on the dual-purpose display unit 66 are set in one-to-one correspondence with the notification contents of the stop order notification on the image display device 63 . Specifically, as shown in FIG. 7(b), when the image display device 63 notifies the first stop order, the combined display unit 66 displays the first stop order corresponding display, and the image is displayed. When the device 63 notifies the second stop order, the combined display unit 66 displays the second stop order, and when the image display device 63 notifies the third stop order, the combined display. When the display corresponding to the third stop order is performed by the unit 66 and the fourth stop order is notified by the image display device 63, the display corresponding to the fourth stop order is performed by the combined display unit 66, and the image display device When the fifth stop order is notified at 63, the combined display unit 66 displays the fifth stop order, and when the image display device 63 reports the sixth stop order, the combined display unit In 66, display corresponding to the 6th stop order is performed, and when the image display device 63 notifies the 7th stop order, display corresponding to the 7th stop order is performed in the combined display unit 66, and the image display device 63 When the 8th stop order is notified by the combined display unit 66, the display corresponding to the 8th stop order is performed, and when the image display device 63 reports the 9th stop order, the combined display unit 66 , the display corresponding to the ninth stop order is performed. It should be noted that a plurality of types of display contents on the combined display section 66 may be set so as to correspond to part or all of the notification contents of the stop order on the image display device 63 .

In this specification, the combination display unit 66 displays the number of game media to be provided, and the combination display unit 66 does not display the corresponding stop order and the ratio display described later. The display is also referred to as “display of number of grants”. The given number display is a display executed by the combined display unit 66 based on the value of a given number counter 74e (see FIG. 14), which will be described later. The display content of the stop order correspondence display on the combined display section 66 is different from the display content of the given number display on the combined display section 66 . This makes it easier to distinguish between the state in which the display of the given number is being performed on the combined display unit 66 and the state in which the display corresponding to the order of stopping is being performed.

8(a) and 8(b) explain the relationship between the contents of the stop order notification executed by the image display device 63 and the display contents of the stop order corresponding display executed by the combined display section 66. It is an explanatory diagram for. When the stop order notification of the reels 32L, 32M, and 32R is executed by the image display device 63, as shown in FIG. The same number of unit display images G1 to G3 are displayed, and image display corresponding to the stopping order of the reels 32L, 32M, and 32R is performed in each of the unit display images G1 to G3. Specifically, a left unit display image G1 corresponding to the left reel 32L, a middle unit display image G2 corresponding to the middle reel 32M, and a right unit display image G3 corresponding to the right reel 32R are displayed. Then, in FIG. 8(a), the stop order (third stop order) is notified when the first stop is the middle reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R. Therefore, the left unit display image G1 displays an image of "2" corresponding to the stop order of the left reel 32L, and the middle unit display image G2 displays "1" corresponding to the stop order of the middle reel 32M. ' is displayed, and an image of '3' corresponding to the stop order of the right reel 32R is displayed on the right unit display image G3.

While the image display device 63 displays an image notifying the stopping order of the reels 32L, 32M, and 32R as described above, the combined display unit 66 displays the reels as shown in FIG. 8(b). "L" corresponding to the stop order (third stop order) of 32L, 32M, and 32R is displayed. That is, on the image display device 63, the unit display images G1 to G3 corresponding to the number of the reels 32L, 32M, 32R are displayed, and the reels 32L, 32M, 32R corresponding to the unit display images G1 to G3 are displayed in the stopping order. While the corresponding image display is performed, the combined display section 66 performs display irrelevant to the number of reels 32L, 32M, and 32R. As a result, the player can be made to pay attention to the display contents on the image display device 63 even if the display corresponding to the notification contents of the stop order of the reels 32L, 32M, and 32R is performed on the combined display section 66 .

The display range of the combined display unit 66 is narrower than the display range of the image display device 63 . Also from this point, it is possible to reduce the player's attention to the combined display unit 66 compared to the image display device 63 . Also, the combined display section 66 is located on the opposite side of the image display device 63 across the display windows 21L, 21M, and 21R that make the reels 32L, 32M, and 32R visible. As a result, the combined display section 66 is arranged at a position spaced apart from the image display device 63 , and this also makes it possible to reduce the player's attention to the combined display section 66 .

When the stop order of the reels 32L, 32M, 32R is notified, the display corresponding to the stop order of the reels 32L, 32M, 32R on the combined display unit 66 and the stop order notification of the reels 32L, 32M, 32R on the image display device 63 are useful. It is started after the lottery is held and before the stop operation of the reels 32L, 32M, 32R is validated. In this case, the display corresponding to the stopping order of the reels 32L, 32M, 32R on the combined display unit 66 is started at the same time or substantially at the same time as the stopping order notification of the reels 32L, 32M, 32R on the image display device 63. In addition, the stop order correspondence display on the combined display unit 66 and the stop order notification on the image display device 63 are performed for all the reels 32L, 32M, and 32R in the game for which the stop order correspondence display and the stop order notification are executed. Terminates when a stop command is issued. The display corresponding to the stopping order of the reels 32L, 32M, and 32R on the dual-use display unit 66 may be configured to start prior to the notification of the stopping order of the reels 32L, 32M, and 32R on the image display device 63. The stop order notification of the reels 32L, 32M and 32R in the device 63 may be started prior to the display corresponding to the stop order of the reels 32L, 32M and 32R in the combined display section 66. FIG. Further, the display corresponding to the stopping order of the reels 32L, 32M, and 32R on the dual-purpose display unit 66 may be configured to end earlier than the notification of the stopping order of the reels 32L, 32M, and 32R on the image display device 63. The notification of the stopping order of the reels 32L, 32M, 32R on the reel 63 may be completed earlier than the display corresponding to the stopping order of the reels 32L, 32M, 32R on the combined display section 66.

The shared display section 66 is arranged on the central side of the common display area 68 , while the section display section 67 is arranged on the corner side of the common display area 68 . The section display section 67 is a display section for notifying that the game section is the second section SC2 out of the first section SC1 and the second section SC2 (see FIG. 23). The second section SC2 includes the reels 32L, 32M, 32R that enable the establishment of a winning that is advantageous to the player when a winning combination to be established is different according to the stop order of the reels 32L, 32M, 32R. As a result of notification of the stop order, the expected value of acquisition of game media in one game (the value obtained by subtracting the "number of game media betted in one game" from the "expected number of game media awarded in one game") is 1 or more. It is a section in which an advantageous game state (specifically, a pseudo-bonus state ST4 and an AT state ST5) can be started and a section in which the advantageous game state can be continued. On the other hand, the first section SC1 is a section in which the advantageous gaming state does not start and does not continue.

The section display section 67 changes from the off state to the on state when the game section shifts from the first section SC1 to the second section SC2. When the section display portion 67 is in the lighting state, the lighting state is maintained until the second section SC2 ends, and when the second section SC2 ends and transitions to the first section SC1, the section display section 67 is turned off. Become. Therefore, even if the pseudo-bonus state ST4 or the AT state ST5 ends and returns to the normal game state ST1, the second section SC2 may be maintained. In this case, the pseudo-bonus state ST4 or the AT state ST5 ends. However, the section display section 67 is maintained in the lighted state, and when the second section SC2 ends, the section display section 67 is turned off. By confirming that the section display section 67 is in the off state, the manager of the game hall can grasp that the game section is the first section SC1, and also confirms that the section display section 67 is in the lighted state. By confirming, it is possible to grasp that the game section is the second section.

Instead of maintaining the lighting state of the section display portion 67 during the second section SC2, the section display section 67 may blink at a predetermined cycle during the second section SC2. Further, as the combined display section 66 and the section display section 67, other displays such as a liquid crystal display device may be used.

The slot machine 10 is provided with various control devices. Specifically, a main controller 70 is provided above the reel unit 31 as shown in FIG. The main controller 70 is attached to the back plate 11b that forms the rear portion of the housing 11. As shown in FIG. The main controller 70 is constructed by housing a main control board 71 in a board box 81 . An MPU 72 is mounted on the element mounting surface, which is one plate surface of the main control board 71 . The board box 81 is formed transparent so that the MPU 72 accommodated in the board box 81 can be visually observed from the outside of the board box 81 . Although the board box 81 is formed colorless and transparent, it may be formed colored and transparent as long as the MPU 72 accommodated in the board box 81 can be visually observed from the outside of the board box 81. The main control device 70 is mounted on the back plate 11b of the housing 11 in the board box 81 so that the facing wall portion 82 facing the element mounting surface of the main control board 71 faces the front of the slot machine 10 . Therefore, by opening the front door 12 toward the front of the slot machine 10 with respect to the housing 11 to expose the internal space of the housing 11, it becomes possible to see the opposing wall portion 82 of the board box 81 and It is possible to see the MPU 72 through the opposing wall portion 82 .

The substrate box 81 is formed by assembling a plurality of case bodies back and forth, and these plurality of case bodies are provided with an adhesive to prevent the case bodies from separating and to leave a trace when the case bodies are separated. A coupling portion 83 is provided. A plurality of coupling portions 83 are arranged side by side on one side of the substantially rectangular parallelepiped board box 81 . As a result, in a state in which separation of the case body is prevented by using some of the joints 83, even if the case body is separated by destroying the part of the joints 83, another joint may be used after that. By connecting 83, separation of the case body can be prevented again. In addition, when the case body is separated, the connecting portion 83 is destroyed and a trace remains, so that it is possible to grasp whether or not the case body is being separated illegally by visually checking the connecting portion 83. Become. A sealing seal 84 is attached to a side of the substrate box 81 other than the side on which the coupling portions 83 are arranged so as to straddle the boundary between the case bodies. When the sealing seal 84 is peeled off, the adhesive layer remains on the case body. As a result, when the sealing seal 84 is peeled off when the case body is separated, it is possible to leave a trace of it.

The slot machine 10 is provided with an effect control device 90 in addition to the main control device 70, as shown in FIG. The effect control device 90 is arranged behind the image display device 63 on the front door 12 . The effect control device 90 controls the upper lamp 61 , the speaker 62 and the image display device 63 based on commands received from the main control device 70 . In addition, the production control device 90 has a control board housed in a board box in the same manner as the main control device 70 .

Next, the electrical configuration of the slot machine 10 will be described with reference to the block diagram of FIG.

The MPU 72 is mounted on the main control board 71 of the main controller 70 as already described. The MPU 72 includes a ROM 73 storing various control programs and fixed value data to be executed by the MPU 72, and a memory for temporarily storing various data when executing the control programs stored in the ROM 73. A RAM 74 and a random number circuit 75 for sequentially updating a first random number within a predetermined numerical range based on a clock signal output from a clock circuit are provided. Further, the main side MPU 72 incorporates a transmission circuit 85 for transmitting commands to the effect control device 90 . In addition, the MPU 72 also incorporates an interrupt circuit, a data input/output circuit, and the like. It should be noted that it is not essential that the ROM 73 and the RAM 74 are integrated into one chip for the MPU 72, and they may be individually integrated into chips.

The MPU 72 is provided with an input port and an output port. The input side of the MPU 72 includes the reel unit 31, a start detection sensor 41a that detects the operation of the start lever 41, stop detection sensors 42a, 43a, and 44a that individually detect the operation of each of the stop buttons 42, 43, and 44, and a medal insertion sensor. Inserted medal detection sensor 45a for detecting medals inserted through slot 45, credit insertion detection sensors 47a and 48a for individually detecting operation of credit insertion buttons 47 and 48, and settlement detection sensor 51a for detecting operation of settlement button 51. , a payout detection sensor of the hopper device 53, a reset detection sensor that detects the operation of the reset button 56 provided on the power supply device 54, a setting key detection sensor that detects that the setting key is inserted into the setting key insertion hole 57, and the like. are connected, and signals from these sensors are input to the MPU 72 .

On the output side of the MPU 72, the reel unit 31, the selector drive section 52a provided in the selector 52, the payout motor of the hopper device 53, the credit display section 65, the combined display section 66, the section display section 67, the production control device 90, and the like. It is connected. In each game, the MPU 72 controls the rotation of the reels 32L, 32M, and 32R of the reel unit 31. FIG. The selector 52 guides the medals inserted from the medal slot 45 to the hopper device 53 after being detected by the inserted medal detection sensor 45a if reception is permitted, and to the inserted medal detection sensor 45a if reception is prohibited. It has a function of ejecting to the medal receiving tray 59 without being detected by the The selector drive unit 52a has a function of switching the state of the selector 52 between the reception permission state and the reception prohibition state. and a position for prohibiting reception. The MPU 72 switches the state of the selector 52 between the reception permission state and the reception prohibition state by switching the output state and the stop state of the driving signal to the selector driving section 52a.

The MPU 72 executes drive control of the hopper device 53 when a small winning combination is established and medals are to be paid out. The MPU 72 also controls the display of the credit display section 65 so that the number of virtual medals stored is displayed. Further, the MPU 72 controls the display of the credit display section 65 so that the current set value is displayed when the set value is updated. Further, the MPU 72 controls display of the combined display unit 66 so that the number of game media to be awarded is displayed when game media are awarded. In addition, the MPU 72 controls the display of the section display section 67 so that when the game section shifts to the second section SC2, it is notified that the game section is the second section SC2. Further, the MPU 72 controls the dual-use display unit 66 so that a display corresponding to the game management result is performed. Further, the MPU 72 transmits a command to the effect control device 90 at each timing of each game, and also transmits a command to the effect control device 90 for notifying the stopping order of the reels 32L, 32M, and 32R in the image display device 63. In this case, display control of the combined display unit 66 is performed so that a display corresponding to the content to be notified is performed. In this case, the direct display control of the image display device 63 is performed by the performance control device 90 , while the direct display control of the combined display section 66 is performed by the MPU 72 . That is, for the image display device 63, which is subject to relatively complicated display control, direct display control is performed by the effect control device 90, and the combined display unit 66, which is subject to relatively simple display control. Direct display control is executed in the MPU 72 for . As a result, it is possible to perform both a display that emphasizes the improvement of attention to the presentation and a display that emphasizes reliability while reducing the processing load of the MPU 72 .

The main control board 71 monitors whether the MPU 72 is operating normally, and outputs a reset signal to the MPU 72 to restore the MPU 72 to a normal state when the MPU 72 is not operating normally. An abnormality monitoring circuit 86 is mounted. The abnormality monitoring circuit 86 is connected to the input side and output side of the MPU 72 . The abnormality monitoring circuit 86 has a watchdog timer 86a. The watchdog timer 86a is a down counter that is updated by subtracting 1 at a predetermined cycle (specifically, once every 10 milliseconds), and the initial value of the watchdog timer 86a is "18H" (24). is. In this specification, "H" attached after a numerical value is a symbol indicating that the numerical value is expressed in hexadecimal.

The abnormality monitoring circuit 86 is electrically connected to the power supply device 54 , and the operating power of the abnormality monitoring circuit 86 is supplied from the power supply device 54 in the same manner as the operating power to the MPU 72 . The supply of operating power to the abnormality monitoring circuit 86 is started when the supply of operating power to the slot machine 10 is started, similarly to the supply of operating power to the MPU 72 . The abnormality monitoring circuit 86 includes an initial value setting hardware circuit that sets an initial value of "18H" to the watchdog timer 86a when the supply of operating power to the abnormality monitoring circuit 86 is started, and the abnormality monitoring circuit 86a. A subtraction hardware circuit (not shown) that subtracts 1 from the value of the watchdog timer 86a at a predetermined cycle (specifically, once every 10 milliseconds) while the circuit 86 is being supplied with operating power; , is equipped with The operation of subtracting 1 from the value of the watchdog timer 86a is executed in the hardware circuit for subtraction without control by the MPU 72. FIG. The calculation of subtracting 1 from the value of the watchdog timer 86a at a predetermined cycle starts when the supply of operating power to the abnormality monitoring circuit 86 is started, and continues until the supply of operating power to the abnormality monitoring circuit 86 is completed. Continued.

The MPU 72 can set an initial value to the watchdog timer 86a, but cannot stop the watchdog timer 86a. The watchdog timer 86a underflows if the initial value is not set for 240 milliseconds. The MPU 72 periodically sets the watchdog timer 86a to an initial value of "18H" (specifically, at intervals of 1.49 milliseconds) in timer interrupt processing (FIG. 11), which will be described later. Therefore, the watchdog timer 86a does not underflow while the MPU 72 is operating normally. A reset signal is output to the input port of the MPU 72 when the watchdog timer 86a underflows. When the reset signal is received, the MPU 72 starts processing for resetting the program. As a result, when the MPU 72 becomes abnormal such that the watchdog timer 86a cannot be set to the initial value, the program of the MPU 72 can be reset to restore the MPU 72 to its normal state.

An input side of the MPU 72 is connected to a power failure monitoring circuit provided in the power supply 54 (not shown). The power supply device 54 is equipped with a power supply unit that supplies driving power to each electronic device of the slot machine 10 including the main controller 70, and a power failure monitoring circuit. A power failure signal is output to the MPU 72 when the voltage is below the reference voltage. The MPU 72 executes power failure processing upon receiving the power failure signal, and after the power is restored, it is possible to return to the processing state before the power failure. Further, the power supply device 54 is provided with a power-off power supply unit for supplying backup power to the RAM 74 as power-off power when the supply of operating power from the external power supply is interrupted. As a result, even when the supply of operating power from the external power supply is cut off, data is stored and retained in the RAM 74 in a situation where backup power can be supplied to the power supply unit during a power failure (for example, for one or two days). be done.

The performance control device 90 includes a performance control board 91 for controlling execution of various notifications and various performances. An MPU 92 is mounted on the effect control board 91 . The MPU 92 includes a ROM 93 storing various control programs and fixed value data to be executed by the MPU 92, and a memory for temporarily storing various data when executing the control programs stored in the ROM 93. A RAM 94 is built in. The MPU 92 also incorporates a receiving circuit 87 for receiving commands transmitted from the MPU 72 of the main control device 70 . Furthermore, the MPU 92 incorporates a clock circuit for outputting a rectangular wave of a predetermined frequency, an interrupt circuit, a data input/output circuit, a random number generation circuit, and the like.

Note that it is not essential that the ROM 93 and the RAM 94 are integrated into one chip for the MPU 92, and they may be individually integrated into chips. In addition, the RAM 94 is not supplied with backup power from the power supply section of the power supply unit 54 when the supply of operating power from the external power supply is interrupted, but the RAM 94 is supplied with backup power. good too.

The MPU 92 is provided with an input port and an output port. The input side of the MPU 92 is connected to the MPU 72 of the main control device 70 as already described, and receives various commands from the MPU 72 . An upper lamp 61 , a speaker 62 and an image display device 63 are connected to the output side of the MPU 92 . Based on commands received from the MPU 72 of the main control device 70, the MPU 92 executes light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63, thereby performing various notifications and various effects. let it happen.

In addition to the MPU 92, the effect control board 91 is equipped with a video display processor (VDP), a character ROM, a video RAM, and the like, although not shown. The VDP is a kind of drawing circuit that directly operates an image processing device as a liquid crystal display driver incorporated in the image display device 63 . The VDP intervenes in the reading and writing of data in the video RAM, reads image data to be stored in the video RAM from the character ROM at a predetermined timing, and causes the image display device 63 to display the image data. The character ROM serves as an image data library for storing character data such as designs displayed on the image display device 63 . This character ROM holds bitmap format image data of various display patterns, a color palette table to be referred to when determining the expression color of each dot of the bitmap image, and the like. The video RAM is a memory for storing display data to be displayed on the image display device 63 . When the MPU 92 determines the execution contents of the effect based on the command received from the MPU 72 of the main control device 70, the MPU 92 stores a drawing list indicating the contents of the image corresponding to each update timing in the VDP according to the determined execution contents of the effect. Output. The VDP reads image data from the character ROM according to the drawing list, and uses the read image data to create display data in the video RAM. Then, the VDP outputs an image signal corresponding to the generated display data to the image display device 63, thereby causing the image display device 63 to display an image corresponding to the display data.

In the following description, for convenience of explanation, the MPU 72, ROM 73 and RAM 74 of the main control device 70 will be referred to as the main MPU 72, main ROM 73 and main RAM 74 respectively, and the MPU 92, ROM 93 and RAM 94 of the effect control device 90 will be referred to as the effect side. They are referred to as an MPU 92, an effect-side ROM 93, and an effect-side RAM 94.

Next, processing executed by the main MPU 72 will be described. First, the main processing executed by the main MPU 72 when the supply of operating power to the main MPU 72 is started will be described with reference to the flowchart of FIG.

In the main process, first, an initial setting process is executed (step S101). In the initial setting process, various initial settings are performed for the register group, I/O device, etc. in the main MPU 72 . After that, the interrupt by the timer interrupt processing (FIG. 11) is permitted (step S102). As described above, in the timer interrupt process (FIG. 11), the process of setting the initial value to the watchdog timer 86a of the abnormality monitoring circuit 86 (the process of step S204) is executed. By permitting the interrupt due to the timer interrupt process in step S102, the process of setting the initial value to the watchdog timer 86a (the process of step S204) is executed at a predetermined cycle (specifically, the cycle of 1.49 milliseconds). can be in a state where This prevents the watchdog timer 86a from underflowing while the main MPU 72 is operating normally.

After that, it is determined whether or not the power is turned on while the setting key is inserted into the setting key insertion hole 57 and turned on (step S103). If the power has been turned on while the ON operation was performed using the setting key (step S103: YES), if the reset button 56 has not been pressed at the time of turning on the power (step S104: NO), After executing the partial clear processing (step S105), the set value update processing is executed (step S107). On the other hand, if the reset button 56 is pressed when the power is turned on (step S104: YES), after executing the all clear process (step S106), the set value update process is executed (step S107).

In the partial clearing process (step S105), the storage area other than the storage area in which the second CB winning data is set in the main RAM 74 (second CB winning data area 74k described later) is initialized, and in the all clearing process (step S106) , initializes all storage areas of the main side RAM 74 including the storage area in which the second CB winning data is set.

In the setting value update process, the current setting value is read on condition that the setting key is inserted and turned on, and the current setting value is displayed on the credit display section 65 . When the setting value updating process is executed, either the partial clearing process (step S105) or the all clearing process (step S106) has been executed before that, so the credit is displayed at the start of the setting value updating process. A display corresponding to the fact that the set value is "1" is displayed in the portion 65. FIG. In the set value update process, the set value is updated by 1 each time the reset button 56 is operated, and the updated set value is displayed on the credit display section 65 . If the reset button 56 is operated while the set value is "6", the set value is updated to "1". When the ON operation of the setting key is released after the start lever 41 is operated, the set value selected at that time becomes the set value set in the current set value update processing, and the set value update processing is terminated. do. In this case, the display of the set value on the credit display section 65 is ended. After that, the process shifts to normal processing (step S108). The normal processing will be explained later in detail.

If the ON operation of the setting key has not been performed in the main process (step S103: NO), the power restoration process from step S109 onwards is executed. The power restoration process is a process for restoring the state of the slot machine 10 to the state before the power shutdown. In the power recovery process, it is determined whether or not the setting values of the slot machine 10 are normal by checking the main RAM 74 (step S109). Specifically, when the value of the set value counter provided in the main side RAM 74 is any one of "1" to "6", it is determined to be normal, and when it is "0" or "7" or more is determined to be abnormal. The setting value counter is a counter that enables the main MPU 72 to grasp the current setting value of the slot machine 10 . The set value counter consists of 1 byte. If the set value is normal, it is determined whether or not the power failure flag is set to "1" (step S110). A power failure flag is provided in the main side RAM 74, and when the predetermined power failure processing is normally executed when the supply of operating power to the main side MPU 72 is stopped, the power failure flag is set to "1". will be set. If the power failure flag is set to "1", it is checked whether the RAM determination value is normal (step S111). Specifically, the checksum value of the main RAM 74 is examined to confirm whether or not the value is normal.

If affirmative determination is made in all of steps S109 to S111, it means that the power failure processing at the time of the previous power failure was normally executed. In this case, by writing the value of the stack pointer saved in the main RAM 74 to the stack pointer of the main MPU 72 and returning the data saved in the main RAM 74 to the register of the main MPU 72, the register of the main MPU 72 The state is returned to the state before the power was cut off (step S112). Also, the power failure flag in the main RAM 74 is cleared to "0" (step S113).

After that, after setting the power recovery command flag provided in the main RAM 74 to "1" (step S114), the address before the power shutdown is restored (step S115). The power recovery command flag is a flag that allows the main side MPU 72 to grasp that a power recovery command for making the effect side MPU 92 recognize the execution of power recovery processing should be transmitted. By setting the power recovery command flag to "1" in step S114, processing for transmitting the power recovery command to the effect side MPU 92 in the command output processing in step S210 of the timer interrupt processing (FIG. 11) described later. is executed. Details of the power recovery command will be described later.

On the other hand, when a negative determination is made in any of steps S109 to S111, operation prohibition processing is executed. In the operation prohibition process, execution of the next timer interrupt process (FIG. 11) is prohibited (step S116), and all the output ports of the main MPU 72 are cleared to "0", thereby all actuators connected to the output ports are cleared. is turned off (step S117), and an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S118).

After that, a power-off standby process is executed (step S119). In the power-off standby process, the process of setting the initial value "18H" ("24") to the watchdog timer 86a is repeatedly executed until the supply of operating power to the main MPU 72 is stopped. If the value of the watchdog timer 86a continues to be updated without being initialized while interrupts due to timer interrupt processing (FIG. 11) are disabled, the watchdog timer 86a underflows and outputs a reset signal. When the reset signal is received, processing for resetting the program of the main MPU 72 is activated, and the operation prohibition state (state in which the operation prohibition processing is being executed) is automatically canceled. On the other hand, in the power shutdown standby process in step S119, by repeatedly executing the process of setting the initial value to the watchdog timer 86a, the underflow of the watchdog timer 86a can be prevented, and The operation prohibited state can be maintained until the slot machine 10 is powered off. The operation-prohibited state is released by executing a partial clear process (step S105) or a full clear process (step S106). Details of the program contents of the power-off standby process (step S119) will be described later.

Next, timer interrupt processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. Note that the timer interrupt process is activated, for example, every 1.49 milliseconds.

In the register saving process (step S201), the values of all the registers in the main MPU 72 used in the normal process (FIG. 13) described later are saved in the main RAM 74. FIG. In step S202, it is checked whether or not the power failure flag is set to "1", and if the power failure flag is set to "1", the process proceeds to step S203 to execute power failure processing. The power failure flag is set to “1” when a power failure signal from the power failure monitoring circuit of the power supply 54 is input to the main MPU 72 . FIG. 12 is a flow chart showing power failure processing (step S203) executed by the main MPU 72. As shown in FIG.

In the power failure process, first, it is determined whether or not command transmission has ended (step S301). If command transmission has not ended (step S301: NO), the power failure processing (FIG. 12) is ended, the timer interrupt processing (FIG. 11) is returned to, and command transmission is ended. If command transmission has been completed (step S301: YES), the value of the stack pointer of the main MPU 72 is saved in the main RAM 74 (step S302). After that, the output state of the output port of the main MPU 72 is cleared (step S303), and all actuators (not shown) are turned off (step S304). Then, a judgment value for judging whether or not the data in the main RAM 74 is normal when the power failure is resolved is calculated (step S305), and the calculated judgment value is stored in the main RAM 74 (step S306). Thereafter, access to the main RAM 74 is prohibited (step S307).

After that, the power-off waiting process is executed (step S308) in the same manner as in step S119 of the main process (FIG. 10) already described. In the power-off standby process, the process of setting the initial value "18H" ("24") to the watchdog timer 86a is repeatedly executed until the supply of operating power to the main MPU 72 is stopped. In the timer interrupt process (FIG. 11), a process of setting an initial value to the watchdog timer 86a is executed in step S204, which will be described later. process is not executed. If the value of the watchdog timer 86a continues to be updated while the process of step S204 for setting the initial value in the watchdog timer 86a is not executed, the watchdog timer 86a underflows and outputs a reset signal. Then, when the reset signal is received, the processing for resetting the program of the main MPU 72 is activated, and the standby state for power failure is automatically canceled. By repeatedly executing the process of setting the initial value to the watchdog timer 86a in the power-off standby process in step S308, underflow of the watchdog timer 86a is prevented, and the supply of operating power to the main MPU 72 is stopped. It is possible to prevent the program of the main side MPU 72 from being reset by the time. Details of the program contents of the power-off standby process (step S308) will be described later.

Returning to the description of the timer interrupt process (FIG. 11), when the power failure flag is not set to "1" in step S202, various processes after step S204 are performed. In step S204, initialization processing of the watchdog timer 86a is performed to set the initial value "18H" ("24") to the watchdog timer 86a. This prevents the watchdog timer 86a from underflowing, and prevents the program of the main MPU 72 from being reset while the main MPU 72 is operating normally.

After that, in step S205, an interrupt end declaration process is performed for the main MPU 72 itself so that the next timer interrupt can be set. In step S206, stepping motor control processing is performed to drive the stepping motors provided for the reels 32L, 32M, 32R in order to rotate the reels 32L, 32M, 32R.

In step S207, sensor monitoring processing is performed to read the states of various sensors connected to the input port and to monitor whether the read results are normal. In step S208, timer subtraction processing is performed to subtract the value of each counter or timer. In step S209, counter processing for outputting the result of counting the number of bets of medals and the number of payouts to the outside is performed. In step S210, command output processing for transmitting various commands to the MPU 92 on the production side is performed. In step S211, port output processing is performed to output data corresponding to the I/O device from the input/output port. In step S212, the values of each register saved in the main RAM 74 in the previous step S201 are returned to the corresponding registers in the main MPU 72, respectively.

In step S213, a management process is executed for managing the game history and displaying the content corresponding to the management result on the combined display section 66. FIG. In the management process in step S213, a process for displaying a ratio of the total number of games in the second section SC2 to the total number of games on the combined display section 66 is executed. Hereinafter, in this specification, the ratio of the total number of games played in the second section SC2 to the total number of games is also referred to as the "stay ratio of the second section SC2". The stay rate of the second segment SC2 is calculated as a percentage of 0% to 100%. Further, in this specification, the display corresponding to the stay ratio of the second section SC2 executed by the dual-purpose display unit 66 is also referred to as "ratio display". The ratio display on the combined display unit 66 is started when a ratio display start operation described later is performed while the game is not being executed, and ends when a ratio display end operation described later is performed. The details of the management process in step S213 will be described later. After that, in step S214, interrupt permission processing for permitting the next timer interrupt is performed, and this series of timer interrupt processing is terminated.

Next, normal processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. Normal processing is executed in step S108 of the main processing (FIG. 10).

In normal processing, first, interrupt permission processing for permitting the next timer interrupt is performed (step S401). After that, start waiting processing is executed (step S402). Here, prior to the description of the start waiting process (FIG. 15), the configuration of the main side RAM 74 for grasping the number of bets in the main side MPU 72 will be described. FIG. 14 is an explanatory diagram for explaining the configuration of the main RAM 74. As shown in FIG.

As shown in FIG. 14, the main RAM 74 is provided with a bet upper limit counter 74a, a bet number setting counter 74b, and a bet number history counter 74c. The bet upper limit number counter 74a is a counter that enables the main side MPU 72 to grasp the bet upper limit number, which is the upper limit number of game media that can be betted in the current game. "2" or "3" is set in the bet upper limit counter 74a. The bet number setting counter 74b is a counter for specifying the bet number of the game to be executed by the main side MPU 72 . An integer from "1" to "3" is set in the bet number setting counter 74b. The bet number history counter 74c is a counter for specifying the bet number of the previous game by the main side MPU 72. FIG. "2" or "3" is set in the bet number history counter 74c.

Next, the start waiting process executed by the main MPU 72 will be described with reference to the flowchart of FIG. The start waiting process is executed in step S402 of the normal process (FIG. 13).

In the start waiting process, first, it is determined whether or not a replay bet setting completion flag provided in the main RAM 74 is set to "1" (step S501). The replay bet set flag specifies whether or not the bet setting for the same number of bets as the previous bet number has already been completed when any of the replay winnings have been established in the previous game. is a flag for If a negative determination is made in step S501, it is determined whether or not the replay winning flag provided in the main side RAM 74 is set to "1", so that any replay winning in the previous game. It is determined whether or not it is established (step S502). The replay winning flag is a flag that enables the main side MPU 72 to grasp that the replay winning has been established. The replay win flag is set to "1" in step S1207 of the win determination process (FIG. 26), which will be described later.

When an affirmative determination is made in step S502, the value of the bet number history counter 74c in the main RAM 74 is set in the bet number setting counter 74b in the main RAM 74 (step S503). The bet number of the previous game is stored in the bet number history counter 74c, and in step S503, the bet number of the previous game stored in the bet number history counter 74c is set in the bet number setting counter 74b. In this way, when any replay winning is established in the previous game, the same number of bets as the previous bet number are set. After that, the replay bet set flag is set to "1" (step S504), and the replay win flag in the main RAM 74 is cleared to "0" (step S505).

When the determination in step S501 is affirmative, when the determination in step S502 is negative, or when the process of step S505 is executed, a bet handling process is executed (step S506). FIG. 16 is a flowchart showing bet handling processing.

In the bet handling process, if the current gaming state is not the second CB state ST3 (step S601: NO), the bet upper limit number counter in the main side RAM 74 is used as the bet upper limit number, which is the upper limit number of gaming media that can be betted in the current game. 74a is set to "3" (step S602). When the current gaming state is the second CB state ST3 (step S601: YES), "2" is set in the bet upper limit counter 74a in the main side RAM 74 as the bet upper limit number, which is the upper limit number of game media that can be betted in the current game. is set (step S603). That is, in the slot machine 10, the maximum bet number is set to "2" in the case of the second CB state ST3, and the maximum bet number is set to "3" in the case of not being in the second CB state ST3.

When the processing of step S602 or step S603 is executed, on condition that the value of the bet number setting counter 74b in the main side RAM 74 is not the current bet upper limit number (step S604: NO), the stored virtual medals are It is determined whether or not a valid bet operation has been performed with one or more cards (step S605). The main side RAM 74 is provided with a credit counter 74d (see FIG. 14) as an area for storing the number of stored virtual medals. In step S605, it is determined whether or not the value of the credit counter 74d is 1 or more, thereby determining whether or not there are one or more virtual medals stored. Also, when the first credit insertion button 47 (FIG. 1) is operated, it is determined that a valid betting operation has been performed, and when the second credit insertion button 48 (FIG. 1) is operated, It is determined that a valid bet operation has been performed on condition that the value of the bet number setting counter 74b is 1 or less.

When an affirmative determination is made in step S605, a bet setting process is executed (step S606). The main MPU 72 grasps the maximum bet number by referring to the maximum bet number counter 74a. In the bet setting process in step S606, when the first credit insertion button 47 is operated and the sum of the value of the bet number setting counter 74b and the value of the credit counter 74d is equal to or greater than the upper bet number, the bet number setting counter 74b is set as the bet upper limit number, the value for the number of virtual medals used for the setting is subtracted from the credit counter 74d, and the sum of the value of the bet number setting counter 74b and the value of the credit counter 74d is the bet. If the number is less than the upper limit, the value of the credit counter 74d is cleared to "0" after adding the value of the credit counter 74d to the bet number setting counter 74b. In addition, in the bet amount setting process, when the second credit insertion button 48 is operated, if the sum of the value of the bet amount setting counter 74b and the value of the credit counter 74d is 2 or more, the value of the bet amount setting counter 74b is set to "2", the value for the number of virtual medals used for the setting is subtracted from the credit counter 74d, and if the sum of the value of the bet number setting counter 74b and the value of the credit counter 74d is less than 2 If so, the value of the credit counter 74d is cleared to "0" after adding the value of the credit counter 74d to the bet number setting counter 74b.

After that, the value of the number-of-givens counter 74e (FIG. 14) provided in the main RAM 74 is cleared to "0" (step S607). The given number counter 74e is a counter that enables the main MPU 72 to grasp the number of game media given to the player when a small winning combination is established. The grant number counter 74e consists of 1 byte. "1", "2", "5" or "15" is set in the grant number counter 74e. The value of the awarded number counter 74e is cleared to "0" when a valid bet operation is performed in a state in which one or more virtual medals are stored.

If the determination is affirmative in step S604, if the determination is negative in step S605, or if the process of step S607 is executed, the inserted medal detection sensor 45a detects that medals have been inserted into the medal slot 45. determines whether or not one medal has been detected (step S608). When the determination in step S608 is affirmative, if the value of the bet number setting counter 74b of the main side RAM 74 is less than the bet upper limit number (step S609: NO), the value of the bet number setting counter 74b is incremented by 1 (step S610). ), if the value of the bet number setting counter 74b is greater than or equal to the bet upper limit number (step S609: YES), the value of the credit counter 74d of the main side RAM 74 is incremented by 1 (step S611).

When the processing of step S610 or step S611 is executed, the value of the number-of-given-granted counter 74e is cleared to "0" (step S612). In this way, the value of the given number counter 74e is cleared to "0" when the medal inserted into the medal slot 45 is detected by the inserted medal detection sensor 45a. Further, as described above, the value of the awarded number counter 74e is also cleared to "0" when a valid bet operation is performed while one or more virtual medals are stored.

After that, on condition that the value of the bet number setting counter 74b is equal to or more than the upper limit bet number and the value of the credit counter 74d is equal to or more than the upper limit storage memory number (specifically, "50") (step S613: YES), An acceptance prohibition process is executed (step S614). By executing the reception prohibiting process, even if a medal is inserted into the medal slot 45, the medal is ejected to the medal receiving tray 59 without being detected by the inserted medal detection sensor 45a.

When a negative determination is made in step S608, when a negative determination is made in step S613, or when the process of step S614 is executed, a bet status management process is executed (step S615), and the main bet handling process is executed. finish. FIG. 17(a) is a flow chart showing the bet status management process (step S615).

In the bet state management process, when the current gaming state is the first CB state ST2 (step S701: YES), on condition that the value of the bet number setting counter 74b is "3" (step S702: YES), the main "1" is set in the bet set flag at the time of acceptance provided in the side RAM 74 (step S703). On the other hand, if the current gaming state is not the first CB state ST2 (step S701: NO), on condition that the value of the bet number setting counter 74b is 2 or more (step S704: YES), the bet setting at the time of acceptance has been completed. The flag is set to "1" (step S703). The bet set completion flag at the time of acceptance is a flag for specifying in the main side MPU 72 whether or not the number of game media capable of starting one game has been betted. When the gaming state is the first CB state ST2, a single game cannot be started in a state where "3" game media are not betted. It is possible to start one game. Further, when the gaming state is not the first CB state ST2, one game cannot be started in a state where two or more game media are not betted, and two or more game media are betted. It is possible to start one game.

Returning to the description of the start waiting process (FIG. 15), after executing the bet handling process in step S506, it is determined whether or not the settlement button 51 has been operated (step S507). If the settlement button 51 has been operated (step S507: YES), after executing settlement processing (step S508), the bet set completion flag at the time of acceptance in the main side RAM 74 is cleared to "0" (step S509), End this start waiting process. In the settlement process of step S508, if the bet set flag at the time of replay in the main RAM 74 is not set to "1", the number of bets corresponding to the sum of the value of the bet number setting counter 74b and the value of the credit counter 74d The hopper device 53 is driven and controlled so that the medals are discharged to the medal receiving tray 59. In this case, the bet number setting counter 74b is cleared to "0" and the credit counter 74d is cleared to "0". On the other hand, when the bet set flag at the time of replay of the main RAM 74 is set to "1", the hopper device 53 is operated so that the number of medals corresponding to the value of the credit counter 74d is discharged to the medal receiving tray 59. Drive control. In this case, the credit counter 74d is cleared to "0".

Returning to the description of the normal processing (FIG. 13), after executing the start waiting processing in step S402, either the replay bet set flag or the acceptance bet set flag in the main RAM 74 is set to "1". is set (step S403). As already explained, the replay bet set flag is set to "1" in step S504 of the start waiting process (FIG. 15), and the bet set flag at the time of acceptance is set to the bet state management process. "1" is set in step S703 (FIG. 17(a)).

If a negative determination is made in step S403, the process returns to step S402. If an affirmative determination is made in step S403, it is determined whether or not the start lever 41 has been operated (step S404). If the start lever 41 has not been operated, the process returns to step S402.

If the start lever 41 has been operated (step S404: YES), after the main line ML is activated, reception prohibition processing is executed (step S405). By executing the reception prohibiting process, even if a medal is inserted into the medal slot 45, the medal is ejected to the medal receiving tray 59 without being detected by the inserted medal detection sensor 45a.

After that, in step S406, setting processing at the time of starting for performing various settings when the game is started is executed, and in step S407, lottery processing for the winning combination in the current game is executed. , in step S408, reel control processing for driving and controlling the respective reels 32L, 32M, 32R in a mode corresponding to the result of the lottery processing for the current combination is executed. The details of the setting process at the start (step S406), the winning lottery process (step S407), and the reel control process (step S408) will be described later.

After that, medium application processing is executed (step S409). In the medium awarding process, when a minor winning combination has been established in the current game, a process for awarding the player with a number of game media corresponding to the winning of the minor winning combination is executed. Specifically, when virtual medals are awarded, a value corresponding to the current minor winning combination is added to the credit counter 74d of the main side RAM 74, and when the value of the credit counter 74d reaches the upper limit storage memory number. drives and controls the hopper device 53 so that the number of medals exceeding the upper limit storage memory number is paid out to the medal receiving tray 59 .

After that, a corresponding process at the end of the game is executed to enable the setting of the game state and the game section corresponding to the result of the current game (step S410). Also, an external output setting process for outputting the state of the slot machine 10 to the management computer of the game hall is executed (step S411). The details of the processing for dealing with the end of the game (step S410) and the external output setting processing (step S411) will be described later. Thereafter, acceptance permission processing is executed (step S412). By executing the acceptance permission process, the medals inserted from the medal slot 45 are collected by the hopper device 53 after being detected by the inserted medal detection sensor 45a.

Next, the setting process at the time of start executed in step S406 of the normal process (FIG. 13) will be described with reference to the flowchart of FIG. 17(b).

In the setting process at the start, first, the value of the index value counter 74f provided in the main RAM 74 is cleared to "0" (step S801). The index value counter 74f is a counter that enables the main side MPU 72 to grasp the index value IV that is won in the winning lottery process (FIG. 18) described later. The index value counter 74f consists of 1 byte. Although the details will be described later, in the winning lottery process (FIG. 18), the index value IV is set to the index value counter 74f when any of the index values IV from "1" to "17" is won. , and if none of the index values IV is won, "0" is set. By clearing the value of the index value counter 74f to "0" in step S801, the data of the index value IV set in the index value counter 74f in the winning lottery process (FIG. 18) is replaced with the data of the index value IV. can be cleared at the start of the game next to the game in which is set in the index value counter 74f.

After that, both the replay bet set flag and the acceptance bet set flag in the main RAM 74 are cleared to "0" (step S802), and the in-game flag provided in the main RAM 74 is set to "1". (step S803). The in-game flag is a flag that enables the main MPU 72 to recognize that the game is being executed. The in-game flag is cleared to "0" at step S1510 of the processing for dealing with the end of the game (FIG. 32), which will be described later. The in-game flag is referenced in management processing (see FIG. 27), which will be described later.

After that, the value of the bet number setting counter 74b in the main RAM 74 is set in the bet number history counter 74c in the main RAM 74 (step S804), and the setting process at the time of this start ends. By setting the value of the bet number setting counter 74b to the bet number history counter 74c in step S804, it is possible for the main MPU 72 to grasp the bet number of the game started this time after the end of the game. It should be noted that the value of the bet number setting counter 74b is cleared to "0" in step S1509 of the processing for dealing with the end of the game (FIG. 32), which will be described later, when the current game is over.

Next, the winning lottery process executed in step S407 of the normal process (FIG. 13) will be described with reference to the flowchart of FIG.

In step S901, a random number used for judging whether a winning combination is right or wrong is acquired. The slot machine 10 is configured such that when the start lever 41 is operated, the random number at that time is latched from the random number circuit 75 . The random number circuit 75 generates a random number from “0” to “65535”, and the main MPU 72 stores the latched value in the random number circuit 75 in the main RAM 74 when the operation of the start lever 41 is confirmed. By adopting such a configuration, it becomes possible to quickly obtain a random number at the timing when the start lever 41 is operated, and it is possible to avoid problems such as synchronization. The random number circuit 75 is configured to latch the value of the free-run counter each time the start lever 41 is operated.

After obtaining the random number, the lottery table for judging the winning combination is read from the main ROM 73 (step S902). In this slot machine 10, six levels of setting values from "1" to "6" are prepared in advance. It is possible to set whether the lottery process for the winning combination is to be executed based on the winning probability corresponding to which set value. A set value of "n+1" is more advantageous to the player than "n" in winning probability. Specifically, the set value of "n+1" is more advantageous for the player than the set value of "n" because the winning probability of the predetermined combination is higher than the set value of "n". . Also, even if the set value is the same level, the number of betted game media of "3" is more advantageous for the player than the number of bets of "2". In addition, there are a first CB state ST2 and a second CB state ST3 as game states. In step S902, a lottery table corresponding to the combination of the current set value, the current bet number, and the current gaming state is selected.

The lottery table in the non-CB state will be described using the case where the set value is "3" as an example. FIG. 19 is an explanatory diagram for explaining the combination lottery table when betting 3 cards, which is selected when the number of bets is "3", and FIG. 20 is selected when the number of bets is "2". FIG. 11 is an explanatory diagram for explaining a combination lottery table when two cards are bet; In the following description, the explanatory diagram of FIG. 21 will be referred to as appropriate.

The index value IV is set in the combination lottery table as shown in FIGS. 19 and 20 regardless of whether 3 or 2 is bet. Each index value IV is associated with winning data (that is, a winning combination), and a point value PV is set. The point value PV determines the winning probability of the corresponding index value IV in relation to the maximum value of the random number circuit 75 (“65535”). In addition, the number of index value IVs is the same when betting 3 cards and when betting 2 cards. It is the same at time and at the time of betting two cards.

Specifically, the index values IV=1 to 6 are set with the first bell winning data and any one of the first to sixth compensation winning data are set. In the case of winning with index value IV=1, as shown in FIG. When the reel 32M is the middle reel 32M and the reel 32R is the third stop (reel where the last stop command is issued), the first bell win is guaranteed regardless of the operation timings of the stop buttons 42 to 44. Otherwise, the first compensation winning prize can be established. When winning with index value IV=2, the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the middle reel 32M, each of the stop buttons 42-44. Regardless of the operation timing of (1), the first bell winning is established without fail, and in other cases, the fourth compensation winning can be established. When winning with index value IV=3, when the first stop is the middle reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, each of the stop buttons 42-44. Regardless of the operation timing of (1), the first bell winning is established without fail, and in other cases, the third complementary winning can be established. When winning with index value IV=4, the first stop is the middle reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, each of the stop buttons 42-44. Regardless of the operation timing of (1), the first bell winning is established without fail, and in other cases, the sixth compensation winning can be established. When winning with index value IV=5, when the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the middle reel 32M, each of the stop buttons 42-44. Regardless of the operation timing of (1), the first bell winning is established without fail, and in other cases, the second compensation winning can be established. When winning with index value IV=6, when the first stop is the right reel 32R, the second stop is the middle reel 32M, and the third stop is the left reel 32L, each of the stop buttons 42-44. Regardless of the operation timing of (1), the first bell winning is surely established, and in other cases, the fifth compensation winning can be established.

In the present slot machine 10, as already explained, when the stop buttons 42 to 44 are operated in the non-CB state, the reels 32L, 32M, and 32R are controlled so that up to four symbols can be slid. done. In other words, the reels 32L, 32M, and 32R are controlled to stop within a specified time (190 milliseconds) after the stop buttons 42-44 are operated. By performing such reel control, it becomes possible to facilitate establishment of a prize corresponding to a winning combination, and to avoid establishment of a prize corresponding to a non-winning combination. becomes possible. However, since the amount of rotation of the reels 32L, 32M, 32R that can be slid is limited as described above, only one reel 32L, 32M, 32R constitutes a combination of symbols for establishing a prize. If there are 5 or more symbols between the constituent symbols, depending on the operation timing of the corresponding stop buttons 42 to 44, the constituent symbols may not stop on the main line ML (this phenomenon is also known as "dropout"). say). The 1st bell winning, 2nd bell winning and various replay winnings are a winning mode in which no loss occurs when the reels 32L, 32M and 32R are stopped in the corresponding order. The watermelon prize, the second watermelon prize, the cherry prize, the first CB prize, and the second CB prize are prize modes in which failure can occur depending on the stop operation timing of the stop buttons 42 to 44 with respect to the rotational positions of the reels 32L, 32M, and 32R.

The index values IV=7 to 9 are set with the second bell winning data and any one of the seventh to ninth compensation winning data. When winning with index value IV=7, as shown in FIG. The second bell winning prize is established without fail regardless of the operation timing of the stop buttons 42 to 44, and in other cases, the seventh compensation winning prize can be established. When winning with the index value IV=8, when the first stop is the middle reel 32M, the types of the reels 32L, 32M, 32R to be the second stop and the third stop and the operation of the stop buttons 42 to 44 Regardless of the timing, the 2nd bell winning is surely established, and in other cases, the 9th compensation winning can be established. When winning with index value IV=9, when the first stop is the right reel 32R, the types of the reels 32L, 32M, 32R to be the second stop and the third stop and the operation of each of the stop buttons 42 to 44 Regardless of the timing, the 2nd bell winning is surely established, and in other cases, the 8th compensation winning can be established.

As shown in FIGS. 19 and 20, the index value IV=10 is set with the first bell winning data. When winning with the index value IV=10, as shown in FIG. 21, the winning of the first bell is surely realized regardless of the order of stopping the reels 32L, 32M, and 32R and the operation timings of the stop buttons 42-44. .

As shown in FIGS. 19 and 20, only the first watermelon winning data is set to the index value IV=11. If a win is made with the index value IV=11, as shown in FIG. 21, the first watermelon win can be established regardless of the order in which the reels 32L, 32M, and 32R are stopped. However, depending on the operation timing of each of the stop buttons 42 to 44, there is a possibility that the first watermelon prize will not be established. As shown in FIGS. 19 and 20, only the second watermelon winning data is set to the index value IV=12. If a win is made with the index value IV=12, as shown in FIG. 21, the second watermelon win can be established regardless of the order in which the reels 32L, 32M, and 32R are stopped. However, depending on the operation timing of each of the stop buttons 42 to 44, there is a possibility that the second watermelon prize will not be established.

As shown in FIGS. 19 and 20, only cherry-winning data is set for the index value IV=13. If a win is made with the index value IV=13, as shown in FIG. 21, a cherry win can be established regardless of the order in which the reels 32L, 32M, and 32R are stopped. However, depending on the operation timing of the left stop button 42 with respect to the rotation position of the left reel 32L, there is a possibility that the cherry winning will not be established.

As shown in FIGS. 19 and 20, only the first chance replay winning data is set to the index value IV=14. When winning with the index value IV=14, as shown in FIG. 21, the first chance replay winning is surely established regardless of the stop order of the reels 32L, 32M, 32R and the operation timing of the stop buttons 42-44. do. Also, as shown in FIGS. 19 and 20, only the second chance replay winning data is set to the index value IV=15. When winning with index value IV=15, as shown in FIG. 21, 2nd chance replay winning is established regardless of the stop order of the reels 32L, 32M, 32R and the operation timing of each stop button 42-44. do. Also, as shown in FIGS. 19 and 20, only the normal replay winning data is set to the index value IV=16. When winning with index value IV=16, as shown in FIG. 21, normal replay winning is established without fail regardless of the stop order of the reels 32L, 32M, 32R and the operation timings of the stop buttons 42-44.

For the index value IV=17, only the 1st CB winning data is set as shown in FIG. Only the second CB winning data is set as shown. In other words, the first CB winning data is set as a winning combination only when the number of bets on the game medium is "3", and the first CB winning is only when the number of bets on the game medium is "3". can be established. The second CB winning data is set as a winning combination only when the number of bets on the game medium is "2", and the second CB winning is only when the number of bets on the game medium is "2". can be established. When the first CB winning data is set, if the number of bets on the game medium is "3", as shown in FIG. 21, the first CB winning can be established regardless of the stop order of the reels 32L, 32M, 32R. However, depending on the operation timing of each stop button 42-44, there is a possibility that the first CB winning will not be established. When the second CB winning data is set, if the number of game media bets is "2", the second CB winning can be established regardless of the order in which the reels 32L, 32M and 32R are stopped, as shown in FIG. However, depending on the operation timing of each stop button 42-44, there is a possibility that the second CB winning will not be established.

Here, the winning data other than the first CB winning data and the second CB winning data are deleted in the winning game regardless of whether or not the corresponding winning has been established, and are deleted in the games following the winning game. is not carried over. On the other hand, the 1st CB winning data and the 2nd CB winning data are cleared by the main side RAM 74 (the 1st CB winning data is partially cleared (step S105) or completely cleared (step S106), and the 2nd CB winning data is stored until the corresponding prize is established, even in the games following the winning game, except when the all clearing process (step S106) is performed. In this case, in a game in which one of the first CB winning data and the second CB winning data is carried over, the index value IV corresponding to the first CB winning data and the second CB winning data is excluded from the lottery.

In other words, as a result of playing the game in a situation where the number of bets is "3", the first CB winning data is set in the main side RAM 74 and the first CB winning data is carried over because the first CB winning has not been established. In this state, the index value IV corresponding to the first CB winning data is excluded from the lottery even if the game is played with the number of bets "3" after that, and the number of bets is increased after that. Even if the game is played under the condition of "2", the index value IV corresponding to the second CB winning data is excluded from the lottery. In addition, as a result of the game being played in a situation where the number of bets is "2", the second CB winning data is set in the main side RAM 74 and the second CB winning data is carried over because the second CB winning has not been established. In this state, the index value IV corresponding to the first CB winning data is excluded from the lottery even if the game is played with the number of bets "3" after that, and the number of bets is increased after that. Even if the game is played under the condition of "2", the index value IV corresponding to the second CB winning data is excluded from the lottery. Thus, to prevent either the first CB winning data or the second CB winning data from being newly stored although either the first CB winning data or the second CB winning data is already stored. is possible, and it is possible to prevent a plurality of CB winning data from being accumulated and stored.

19 is selected, the probability of winning when the index value IV=1, the probability of winning when the index value IV=2, and the probability of winning when the index value IV=3 , the probability of winning when the index value IV=4, the probability of winning when the index value IV=5, and the probability of winning when the index value IV=6 are each about 1/ 21.8. Also, the probability of winning when the index value IV=7, the probability of winning when the index value IV=8, and the probability of winning when the index value IV=9 are approximately 1/21.8. be. Also, the probability of winning when the index value IV=10 is about 1/9.4. Also, the probability of winning when the index value IV=11 is about 1/164. Also, the probability of winning when the index value IV=12 is about 1/146. Also, the probability of winning when the index value IV=13 is about 1/423. Also, the probability of winning when the index value IV=14 is about 1/328. Also, the probability of winning when the index value IV=15 is about 1/164. Also, the probability of winning when the index value IV=16 is about 1/7.3. Also, the probability of winning when the index value IV=17 is about 1/3.3.

On the other hand, when the combination lottery table for betting 2 in FIG. 20 is selected, the probability of winning for each of the index values IV=1 to 16 is higher than when the combination lottery table for betting 3 is selected. low probability. Specifically, when the combination lottery table is selected when a two-coin bet is selected, the probability of winning for each of the index values IV=1 to 16 is the probability when the combination lottery table is selected when the three-coin bet is selected. is less than 2/3 of the probability. As a result, the game executed with the game medium "3" bet is accompanied by the awarding of the game medium, rather than the game executed with the game medium "2" bet. It is possible to increase the probability of occurrence of a replay prize in which a minor winning prize and a replay are awarded.

However, when the combination lottery table for betting two cards is selected, the probability of winning when the index value IV=17 is about 1/2.2. On the other hand, when the combination lottery table for betting 3 cards is selected as described above, the probability of winning when the index value IV=17 is about 1/3.3. As a result, the probability that the second CB winning data is stored in the main side RAM 74 in the game executed in the state where "2" game media is betted is executed in the state where "3" game media are betted. It is possible to increase the probability that the first CB winning data is stored in the main side RAM 74 in the game played.

In addition to the combination lottery table for 3-coin bet and the combination lottery table for 2-coin bet, the main-side ROM 73 also stores the lottery process for the combination in each of the first CB state ST2 and the second CB state ST3 (FIG. 18). ) is stored in the CB lottery table. Only one index value IV is set in the lottery table for CB, and normal replay winning data is set in the one index value IV. The probability of winning with the index value IV is 3/10, and when winning with the index value IV, the reels 32L, 32M and 32R are stopped if the operation timing of the left stop button 42 is a predetermined timing. Regardless of the order, regular replay prizes are established. If the operation timing of the left stop button 42 is not the predetermined timing, the normal replay winning is not established even if the normal replay winning data is stored. On the other hand, if the operation timing of the left stop button 42 is not the predetermined timing even though the index value IV is won, or if the index value IV is not won, the first bell win can be established.

Here, the index values IV other than the index values IV=12 and 15 have the same winning probability among the setting values "1" to "6". This applies both when the number of game media bet is "3" and when it is "2". On the other hand, the winning probabilities of index values IV=12 and 15 are different between set values of "1" to "6". Specifically, the probability of winning with the index value IV=12 is lowest when the setting value is "1", the higher the setting value is, the higher the probability of winning is, and the higher the setting value is, the highest when the setting value is "6". expensive. Also, the probability of winning with the index value IV=15 is lowest for the set value of "1", the higher the set value, the higher the probability of winning, and the higher the set value is, the highest for the set value of "6". As a result, it is possible to provide different advantages among the set values of "1" to "6".

Returning to the description of the winning lottery process (FIG. 18), after selecting the lottery table in step S902, after setting the index value IV to "1" (step S903), the judgment value used when judging whether the winning combination is right or wrong. DV is set (step S904). In this determination value setting process, a new determination value DV is set by adding the current index value IV and the corresponding point value PV to the current determination value DV. In the initial determination value setting process, the value of the random number obtained in step S901 is used as the current determination value DV, and the point value PV corresponding to the index value IV=1, which is the current index value IV, is set to the value of this random number. is added to obtain a new determination value DV.

After that, the winning combination corresponding to the index value IV is determined (step S905). Whether or not the judgment value DV exceeds "65535" is judged in the winning judgment. When the determination value DV exceeds "65535" (step S905: YES), the setting process of the index value counter 74f provided in the main RAM 74 is executed (step S906). As already explained, the index value counter 74f is a counter that enables the main side MPU 72 to grasp the index value IV that has been won in the winning lottery process (FIG. 18). In the setting process of the index value counter 74f in step S906, one of the winning index values IV of "1" to "17" is set in the index value counter 74f. This enables the main side MPU 72 to grasp the index value IV that is won in the winning lottery process (FIG. 18).

Thereafter, winning data acquisition processing is executed (step S907). In the winning data acquisition process, the winning data corresponding to the index value IV that has been won this time is set in the main RAM 74 . As shown in FIG. 14, the main RAM 74 is provided with a first winning data area 74g, a second winning data area 74h, a first CB winning data area 74j and a second CB winning data area 74k. The first winning data area 74g and the second winning data area 74h are the winning data of the winning combination corresponding to the index value IV won in the winning lottery process (FIG. 18), excluding the first CB combination and the second CB combination. is a 1-byte storage area in which is set. The first CB winning data area 74j is a 1-byte storage area for storing the first CB winning data indicating that the first CB winning has occurred, and the second CB winning data area 74k stores the winning of the second CB. This is a 1-byte storage area for storing the second CB winning data indicating that a has occurred. When the index value IV to which the first CB winning data is set is won in the combination lottery process (FIG. 18), the first CB winning data is set in the first CB winning data area 74j, and the first CB winning is established. Then, the first CB winning data is cleared from the first CB winning data area 74j. In addition, when the index value IV to which the second CB winning data is set is won in the winning lottery process (FIG. 18), the second CB winning data is set in the second CB winning data area 74k, and the second CB winning is established. If so, the second CB winning data is cleared from the second CB winning data area 74k. The state in which the first CB winning data is set in the first CB winning data area 74j means that the 0th bit, which is the least significant bit among the 0th to 7th bits of the first CB winning data area 74j, is set to "1". The state in which the 2nd CB winning data is set in the 2nd CB winning data area 74k means that the 0th bit, which is the least significant bit among the 0th to 7th bits of the 2nd CB winning data area 74k, is set. is set to "1".

In the winning data acquisition process in step S907, if the winning combination corresponding to the winning index value IV is the first CB winning combination, the first CB winning data is set in the first CB winning data area 74j (first CB winning data). The 0th bit of the winning data area 74j is set to "1"), and when the winning hand corresponding to the winning index value IV is the second CB winning hand, the second CB winning data area 74k Assume that the second CB winning data is set (the 0th bit of the second CB winning data area 74k is set to "1"). As already explained, in the winning combination lottery table for betting 3 (FIG. 19) and the winning combination lottery table for betting 2 (FIG. 20), the index values IV of "1" to "17" are one or two. A role is set. In the winning data acquisition processing in step S907, if the winning combination corresponding to the winning index value IV is one combination other than the first CB combination and the second CB combination, the winning data corresponding to that combination is selected as the first winning combination. Set in the data area 74g. In addition, in the winning data acquisition process in step S907, if the winning combination corresponding to the index value IV is two combinations other than the first CB combination and the second CB combination, two combinations corresponding to these two combinations are obtained. Winning data is set in the first winning data area 74g and the second winning data area 74h.

If the judgment value DV does not exceed "65535" (step S905: NO), it means that the hand corresponding to the index value IV is lost. In such a case, after adding 1 to the index value IV (step S908), it is determined whether or not there is a combination corresponding to the index value IV, that is, whether or not there is a determination target to be determined (step S909). Specifically, it is determined whether or not the index value IV to which 1 is added has exceeded the maximum value of the index value IV set in the lottery table, ie, "17". If there is a determination target to be determined, the process returns to step S904 to continue determination of the winning combination. At this time, in step S904, the point value PV corresponding to the current index value IV is added to the judgment value DV used for the judgment of the previous combination (that is, the current judgment value DV) to obtain a new judgment value DV, In step S905, it is determined whether the winning combination is correct based on the determination value DV.

If a negative determination is made in step S909, that is, if none of the index values IV of "1" to "17" is won, the value of the index value counter 74f is cleared to "0" (step S910). ). As a result, it is possible for the main MPU 72 to grasp that the result of the winning combination lottery process (FIG. 18) is lost.

If the processing of step S907 or step S910 is executed, it means that the determination of whether the winning combination is correct has ended. In this case, stop information first setting processing for setting stop information for reel stop control is performed (step S911). After that, the advantageous lottery process at the start of the game is executed (step S912), the first control process for the game section is executed (step S913), and the lottery result handling process is executed (step S914). The lottery result corresponding process in step S914 includes a process of setting so that a command at the time of start, which will be described later, is transmitted to the effect-side MPU 92. FIG. The start time command is a command for making the production side MPU 92 recognize that a new game has started, and is a command for making the production side MPU 92 recognize various information determined by the main side MPU 72. . When receiving the start time command, the effect-side MPU 92 grasps various information about the current game from the game start command. Then, the effect-side MPU 92 determines the content of the effect in a manner corresponding to the grasped various information. Then, the data table corresponding to the content of the determined performance is read from the performance side ROM 93 to the performance side RAM 94, and the light emission control of the upper lamp 61, the sound output control of the speaker 62, and the display of the image display device 63 are performed according to the read data table. Execute control. Details of the advantageous lottery process at the start of the game (step S912), the first control process of the game section (step S913), and the lottery result handling process (step S914) will be described later.

Next, the reel control process executed in step S408 of the normal process (FIG. 13) will be described with reference to the flowchart of FIG.

In the reel control process, first, a rotation start process for starting rotation of the reels 32L, 32M, and 32R is performed (step S1001). In the rotation start process, it is checked whether or not a predetermined wait time (for example, 4.1 seconds) has elapsed since the reels 32L, 32M, and 32R started rotating in the previous game. waits until the wait time elapses. When the wait time has passed, the wait time for the next game is set again, and rotation start information is set in the motor control storage area provided in the main RAM 74 . By performing such processing, the acceleration processing of the stepping motor is started in the stepping motor control processing of step S206 in the timer interrupt processing (FIG. 11), and the reels 32L, 32M, 32R start rotating.

After that, it is determined whether or not the acceleration period of the reels 32L, 32M and 32R has ended and the reels 32L, 32M and 32R are rotating at a predetermined rotational speed (step S1002). , 32M, and 32R have not ended (step S1002: NO), the process of step S1002 is repeatedly executed until the acceleration period ends. When the acceleration period of the reels 32L, 32M, and 32R has ended (step S1002: YES), operation activation notification processing is executed (step S1003). In the operation activation notification process, lamps (not shown) provided in one-to-one correspondence with the stop buttons 42 to 44 are turned on to indicate that a stop command can be generated. Players, etc. are notified. After the operation activation notification process (step S1003) is executed, the processes after step S1004 are executed, thereby operating the stop buttons 42 to 44 corresponding to the spinning reels 32L, 32M, 32R. It is possible to generate a stop command by This makes it possible to stop the rotating reels 32L, 32M and 32R.

After that, it is determined whether or not any one of the stop buttons 42 to 44 has been operated (step S1004). If none of the stop buttons 42-44 has been operated (step S1004: NO), the process of step S1004 is repeatedly executed until one of the stop buttons 42-44 is operated. When it is determined that any one of the stop buttons 42 to 44 has been operated, it is determined whether the stop buttons 42 to 44 corresponding to the rotating reels 32L, 32M, 32R have been operated, that is, whether a stop command has been generated. (step S1005). If no stop command has been generated, the process returns to step S1004, and the processes of steps S1004 and S1005 are repeatedly executed until one of the stop buttons 42 to 44 is operated.

If a stop command has been generated (step S1005: YES), operation invalidation notification processing corresponding to the stop buttons 42 to 44 operated this time is executed (step S1006). In step S1006, among the lamps (not shown) of the stop buttons 42 to 44 that were lit in the operation activation notification process in step S1003, the lamps corresponding to the stop buttons 42 to 44 that have been operated this time are turned off. As a result, the player can grasp the stop buttons 42 to 44 for which the stop command has already been issued.

After that, a stop instruction command is transmitted to the effect side MPU 92 (step S1007). The stop instruction command is a command for making the production side MPU 92 recognize which of the stop buttons 42 to 44 has been operated to generate the stop instruction. When the stop instruction command is transmitted, stop control processing shown in steps S1008 to S1014 is performed to stop the rotating reel.

In the stop control process, the symbol number of the reaching symbol that has reached the base position (specifically, the lower row) at the timing when the stop buttons 42 to 44 are operated is confirmed (step S1008). Specifically, the pattern number of the arrival pattern that has reached the base position is confirmed based on the number of excitation pulses output from the time when the detection signal of the reel index sensor is input. After that, based on the stop information stored in the main RAM 74, the number of slips of the reels 32L, 32M, 32R to be stopped this time is calculated (step S1009).

In the slot machine 10, as the stop modes for stopping the reels 32L, 32M, and 32R, when the stop buttons 42 to 44 are operated, the arrival symbol that has reached the base position is stopped as it is. A stop mode in which the reels 32L, 32M and 32R are slid by one symbol and then stopped, a stop mode in which the reels are stopped after being slid by two symbols, a stop mode in which the reels are stopped after being slid by three symbols, and four symbols. There are 5 patterns of stop modes, including a stop mode of stopping after sliding. Therefore, in step S1009, any value from "0" to "4" is calculated as the sliding number based on the stop information stored in the main side RAM74.

After that, the calculated sliding number is added to the symbol number of the reached symbol to determine the symbol number of the stop symbol to be actually stopped at the base position (step S1010). Then, it is determined whether or not the symbol number of the arrival symbol of the reels 32L, 32M, 32R to be stopped this time and the symbol number of the stop symbol are equal (step S1011), and if they are equal, the reels 32L, 32M, 32R A reel stop process for stopping the rotation of is performed (step S1012). After that, it is determined whether or not all the reels 32L, 32M, 32R have stopped (step S1013). If all the reels 32L, 32M, 32R are not stopped, stop information second setting processing is performed (step S1014), and the process returns to step S1004.

Here, the stop information is information for making the stop mode of each of the reels 32L, 32M, and 32R correspond to the result of the winning lottery process (FIG. 18). , it is possible to calculate the number of slips (specifically, "0" to "4") with respect to the arrival symbol that has reached the base position when each of the stop buttons 42 to 44 is operated to stop. As the stop information, sliding number data indicating the correspondence between each symbol and the sliding number is stored in advance in the main ROM 73 in association with each lottery result and the stopping order of the reels 32L, 32M, and 32R. However, the present invention is not limited to this, and the sliding number data corresponding to each lottery result and the stop order of each reel 32L, 32M, 32R may be derived while the reels 32L, 32M, 32R are rotating. .

As the processing for setting the stop information, the first stop information setting processing executed in step S911 of the winning lottery processing (FIG. 18) and the reel control processing (FIG. 22) executed in step S1014. There is a stop information second setting process. In the first stop information setting process, stop information is set according to the result of the lottery process for the combination. In the second stop information setting process, the stop information stored in the main side RAM 74 in the first stop information setting process or the previous second stop information setting process is changed after the reel is stopped. In the second stop information setting process, the stop information is changed based on the set winning data, the order of stopping the reels 32L, 32M and 32R, and the stop numbers of the stopped reels 32L, 32M and 32R. .

When it is determined in step S1013 that all the reels 32L, 32M and 32R are stopped, winning determination processing is executed (step S1015). In the winning determination process, the types of symbols stopped on the main line ML on each of the reels 32L, 32M, 32R are grasped. Then, based on the contents of the winning data stored in the main RAM 74, the combination of symbols stopped and displayed on the main line ML on each of the reels 32L, 32M, 32R becomes the winning combination in the winning combination lottery process. It is determined whether or not there is a combination of corresponding symbols, and in the case of a combination of symbols corresponding to the winning combination, it is specified that the winning combination has been won. When it is specified that a winning combination has been established, information on the number of game media to be awarded is stored in the main side RAM 74 so as to enable the provision of game media in medium provision processing if the winning is a minor winning combination. Along with setting, if the winning is a replay winning, a flag is set so that the replay setting process is executed in the next start waiting process (FIG. 15). Details of the winning determination process (step S1015) will be described later.

After executing the winning determination process, the winning result command flag provided in the main RAM 74 is set to "1" (step S1016). The winning result command flag is a flag that allows the main side MPU 72 to grasp that the winning result command should be transmitted to the effect side MPU 92 . By setting the winning result command flag to "1" in step S1016, the winning result command transmission process for transmitting the winning result command to the effect side MPU 92 is executed in step S2705 of the command output process (FIG. 44) described later. executed. The data stored in the first CB winning data area 74j and the second CB winning data area 74k in the main RAM 74 are set in the winning result command, and the data stored in the winning data area 78 provided in the main RAM 74 are set. data is set. The winning data area 78 is a storage area in which 1-byte data is set so that the main MPU 72 can grasp the winning combination in the current game. Based on the data set in the winning result command, the performance side MPU 92 grasps whether or not the winning is established this time, and also grasps the type of winning when the winning is established. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are executed so that an effect corresponding to the information grasped from the winning result command is performed.

<About game status and game section>
Next, the game state and game section will be described. FIG. 23 is an explanatory diagram for explaining game states and game intervals that exist in the slot machine 10. FIG.

In this slot machine 10, as game states, there are a normal game state ST1, a first CB state ST2, a second CB state ST3, a pseudo-bonus state ST4, an AT state ST5, and an end preparation state ST6. These game states do not overlap each other.

The normal game state ST1 is a game state in which the main side RAM 74 stays by executing partial clear processing (step S105) or full clear processing (step S106). Further, when the first CB state ST2 or the second CB state ST3 generated in the normal game state ST1 ends, the game state becomes the normal game state ST1 when the end preparation state ST6 ends. In the normal game state ST1, one game can be executed regardless of whether the number of game media bet is "3" or "2".

The normal game state ST1 is the expected net increase in game media in one game ("expected number of game media to be given in one game" to "game media bet in one game number of media”) is less than or equal to “0”. In addition, the normal game state ST1 includes a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main side RAM 74, and a state in which either the first CB winning data or the second CB winning data is stored on the main side. There is an internal state stored in RAM 74 .

The first CB state ST2 is a game state to which the game is shifted when the first CB winning is established while the first CB winning data is stored in the main RAM 74 . In the first CB state ST2, one game can be executed when the number of bets on game media is "3", while one game can be executed when the number of bets on game media is "2". can't Also, the second CB state ST3 is a game state to which the game is shifted when the second CB winning is established in a situation where the second CB winning data is stored in the main side RAM74. In the second CB state ST3, one game can be executed when the bet number of game media is "2", while the upper limit bet number is set to "2", so "3" game media are bet. Can not do it.

The first CB state ST2 and the second CB state ST3 are game states in which the game media owned by the player are not increased. Furthermore, in both the first CB state ST2 and the second CB state ST3, the number of game media owned by the player at the end of the relevant game state is greater than the number of game media owned by the player at the start of the relevant game state. It is a game state in which the number of is reduced. Details of the first CB state ST2 and the second CB state ST3 will be described later.

The pseudo-bonus state ST4 is a game state that is shifted to when conditions for shifting to the pseudo-bonus state ST4 are established in the normal game state ST1. The pseudo-bonus state ST4 ends when the remaining number of continuous games in the pseudo-bonus state ST4 becomes "0" or when the ending condition of the second section SC2 is satisfied. When the pseudo-bonus state ST4 ends without fulfilling the ending condition of the second section SC2, which will be described later, and the condition for shifting to the AT state ST5 is not satisfied, the game shifts to the end preparation state ST6. Further, when the pseudo-bonus state ST4 ends by satisfying the ending condition of the second section SC2, which will be described later, the game shifts to the normal game state ST1.

In the pseudo-bonus state ST4, one game can be executed regardless of whether the number of game media bet is "3" or "2". The pseudo bonus state ST4 includes a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main side RAM 74, and a state in which either the first CB winning data or the second CB winning data is stored in the main side RAM 74. There is a stored internal state.

In the pseudo-bonus state ST4, when any one of the index values IV=1 to 6 is won, the stop order of the reels 32L, 32M and 32R that enables establishment of the first bell prize is notified. Further, in the pseudo-bonus state ST4, when any one of the index values IV=7 to 9 is won, the stop order of the reels 32L, 32M and 32R that enables establishment of the second bell prize is notified. A game medium of “15” is awarded when the first bell prize or the second bell prize is established. This makes it possible to increase the expected number of game media to be given in one game in the pseudo-bonus state ST4. In the pseudo-bonus state ST4, if 3 coins are bet, the net increase expected value of game media in one game becomes a value larger than "0", and if 2 coins are bet in the pseudo-bonus state ST4, 1. The net increase expected value of the game media in the game becomes "0" or less.

The AT state ST5 is a game state that is shifted to when conditions for shifting to the AT state ST5 are established in the pseudo-bonus state ST4. The AT state ST5 ends when the remaining number of continuous games in the AT state ST5 becomes "0" or when the ending condition of the second section SC2 is satisfied. When the AT state ST5 ends without satisfying the ending condition of the second section SC2, which will be described later, and when the second section SC2 ends when shifting to the normal game state ST1, the game shifts to the end preparation state ST6. When the AT state ST5 ends without satisfying the ending condition of the second section SC2 described later, and when the second section SC2 does not end when shifting to the normal game state ST1, the state does not shift to the end preparation state ST6. It shifts to the normal game state ST1. Further, when the AT state ST5 is terminated by satisfying the ending condition of the second section SC2, which will be described later, the normal game state ST1 is entered.

In the AT state ST5, one game can be executed regardless of whether the number of game media bet is "3" or "2". The AT state ST5 is a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main RAM 74, and either the first CB winning data or the second CB winning data is stored in the main RAM 74. There exists an internal state where

In the AT state ST5, when any one of the index values IV=1 to 6 is won, the stop order of the reels 32L, 32M and 32R that enables establishment of the first bell prize is notified. Also, in the AT state ST5, when any one of the index values IV=7 to 9 is won, the stopping order of the reels 32L, 32M and 32R that enables establishment of the second bell prize is notified. A game medium of “15” is awarded when the first bell prize or the second bell prize is established. This makes it possible to increase the expected number of game media to be given in one game in the AT state ST5. In the AT state ST5, if 3 coins are bet, the net increase expected value of game media in one game becomes a value larger than "0", and if 2 coins are bet in the AT state ST5, in one game The net increase expected value of game media becomes “0” or less.

The end preparation state ST6 is a game state that is shifted to when the pseudo-bonus state ST4 ends without the conditions for the ending of the second section SC2 (to be described later) being satisfied and the conditions for shifting to the AT state ST5 being satisfied. In addition, the end preparation state ST6 is a case where the AT state ST5 ends without the ending condition of the second section SC2, which will be described later, being satisfied, and the second section SC2 ends when the subsequent transition to the normal game state ST1 occurs. It is a game state that shifts to the case.

The end preparation state ST6 ends when one game is executed. When the ready-to-end state ST6 ends, the game shifts to the normal game state ST1. In the end preparation state ST6, one game can be executed regardless of whether the number of game media bet is "3" or "2". The end preparation state ST6 is a game state in which the net increase expected value of game media in one game is "0" or less regardless of whether 3 or 2 are bet. In addition, the termination preparation state ST6 includes a non-internal state in which neither the first CB winning data nor the second CB winning data is stored in the main side RAM 74, and a state in which either the first CB winning data or the second CB winning data is stored on the main side. There is an internal state stored in RAM 74 .

In the configuration in which various game states (normal game state ST1, first CB state ST2, second CB state ST3, pseudo-bonus state ST4, AT state ST5, and end preparation state ST6) exist as described above, these game states and The game section is set separately. A first section SC1 and a second section SC2 are set as game sections. In other words, in the slot machine 10, the number of game media bets of “2” and “3”, the set values of “1” to “6”, various game states, and the first section There are game sections SC1 and a second section SC2.

The first section SC1 includes the reels 32L, 32M, and 32R that enable establishment of a winning that is advantageous to the player when a winning combination to be established is different depending on the stop order of the reels 32L, 32M, and 32R. As a result, the expected net increase in game media in one game (the value obtained by subtracting the "number of game media bet in one game" from the "expected number of game media given in one game") becomes "0". is a section in which an advantageous game state (pseudo-bonus state ST4 and AT state ST5) that can have a value greater than " is not started, and the advantageous game state does not continue. When the partial clearing process (step S105) or the complete clearing process (step S106) of the main RAM 74 is executed, the game state is the normal game state ST1 and the first section SC1. Further, when the initialization process of the second section SC2 is executed in the second section SC2, the first section SC1 is also set. The second section SC2 is a section in which the advantageous gaming state can be started and in which the advantageous gaming state can be continued.

As described above, when the partial clearing process (step S105) or the complete clearing process (step S106) of the main RAM 74 is executed, the first section SC1 is executed, and the second section SC2 is initialized. also becomes the first section SC1. On the other hand, the second section SC2 is shifted from the first section SC1 by generating an opportunity to shift to the second section SC2 based on the winning lottery process (FIG. 18) in the first section SC1. In this case, when a game with a bet number of "3" is executed in the first section SC1, a transition to the second section SC2 may occur, while the bet number of the first section SC1 is "2". Even if a certain game is executed, there is no opportunity to shift to the second section SC2. Therefore, a player who expects to shift from the first section SC1 to the second section SC2 needs to play a game with a bet number of "3" instead of a game with a bet number of "2". There is

In the first section SC1, the expected value of the net increase in game media in one game is certainly "0" or less. In some cases, the value is greater than "0". Therefore, the second section SC2 is more advantageous than the first section SC1. Therefore, the player expects the first section SC1 to shift to the second section SC2.

The first section SC1 ends when an opportunity to shift to the second section SC2 occurs, and shifts to the second section SC2. On the other hand, the second section SC2 can end when the pseudo-bonus state ST4, the AT state ST5 or the end preparation state ST6 ends and shifts to the normal game state ST1. When the second section SC2 ends, the process proceeds to the first section SC1. In addition, as a condition for ending the second section SC2, the total number of games executed by continuing the second section SC2 without transition to the first section SC1 is the upper limit number of games (specifically, 1500 games). ) and the continuation of the second section SC2 without transition to the first section SC1, the total number of restricted net additions of game media reaches the upper limit net addition number (specifically, 2400). An ending condition is set that either one of the conditions for reaching is satisfied. The restricted total net increase in the number of game media refers to "the total number of game media awarded by the game executed while the second section SC2 is continuing ("0 when no game media are awarded"). ")" minus the "total number of game media consumed to execute the game while the second section SC2 is being continued ("0" when the game is not being executed)" In the case of the difference number of sheets, the minimum value of the predetermined difference number of sheets is set as a predetermined reference value, and the number of sheets is the increase of the predetermined difference number of sheets from the predetermined reference value.

In other words, when the second section SC2 is continued and the total number of net increases with restrictions on the number of game media from the start of the second section SC2 reaches the upper limit net increase number, the second section SC2 ends and the second section SC2 ends. It shifts to 1 section SC1. Further, when the number of times the game is executed since the start of the second section SC2 reaches the upper limit number of games due to the continuation of the second section SC2, the second section SC2 ends and the first section SC1 starts. Transition. When either one of these ending conditions is met, the pseudo-bonus state ST4 or AT state ST5 is terminated in the game in which the ending condition is met even in the middle of the pseudo-bonus state ST4 or AT state ST5. At the same time, the second section SC2 ends and the state shifts to the first section SC1 and the normal game state ST1. This makes it possible to prevent the second section SC2 from continuing excessively.

As shown in FIG. 23, the normal game state ST1, the first CB state ST2 and the second CB state ST3 can be stayed in any of the first section SC1 and the second section SC2. On the other hand, the pseudo bonus state ST4, the AT state ST5, and the end preparation state ST6 do not stay in the first section SC1, but stay only in the second section SC2.

As already explained, in the normal game state ST1, the pseudo-bonus state ST4, the AT state ST5, and the ready-to-end state ST6, the game can be executed in any of the situations where the bet number of game media is "3" or "2". is possible. In the first CB state ST2, the game can be executed only when the number of game media bet is "3", and in the second CB state ST3, the game can be executed only when the number of game media bet is "2". It is possible to run

In the case of the normal game state ST1 in the second section SC2, whether the game with the bet number of "3" or the game with the bet number of "2" is executed. The net increase expected value of game media is “0” or less. In this case, in the normal game state ST1 in the second section SC2, as will be described later, a lottery process for shifting to the pseudo-bonus state ST4 can be executed based on the result of the lottery process (FIG. 18) for the winning combination in each game. , the transition lottery process is executed in the game with the bet number of "3", but is not executed in the game with the bet number of "2". Further, in the normal game state ST1 in the second section SC2, as will be described later, each time one game is executed, the value of the canceled game number counter provided in the main side RAM 74 is decremented by 1, and after the decrement by 1, the game is canceled. When the value of the number-of-games counter is "0", the transition to the pseudo-bonus state ST4 is confirmed, but the subtraction of the number-of-released-games counter is not executed in games where the number of bets is "3". On the other hand, it is not executed in games where the number of bets is "2". Therefore, in the normal game state ST1 in the second interval SC2, a game with a bet number of "3" is better to be executed than a game with a bet number of "2". It is advantageous for the player. The number-of-released-games counter is the number of games required to transition to the pseudo-bonus state ST4 in a situation where none of the first to third transition confirmation flags of the main RAM 74 is set to "1", and the remaining number of released games. A counter for specifying the number of games in the main MPU 72 .

In the pseudo-bonus state ST4, when a game with a bet number of "3" is executed, the net increase expected value of game media can be a value larger than "0", whereas the bet number is "2". ” is executed, the net increase expected value of the game media is “0” or less. Therefore, in the pseudo-bonus state ST4, a game with a bet number of "3" is better for the player than a game with a bet number of "2". Advantageous. In the pseudo-bonus state ST4, as will be described later, lottery processing for shifting to the AT state ST5 can be executed based on the result of the lottery processing (FIG. 18) for the combination in each game. It is executed in games where the number of bets is "3", but is not executed in games where the number of bets is "2". Therefore, from this point of view as well, in the pseudo-bonus state ST4, it is better to execute a game with a bet number of "3" than to execute a game with a bet number of "2". It is advantageous for those who

In the AT state ST5, when a game with a bet number of "3" is executed, the net increase expected value of game media can be a value larger than "0", whereas the bet number is "2". When a game is executed, the expected net increase in game media is "0" or less. Therefore, in the AT state ST5, playing a game with a bet number of "3" is more advantageous for the player than playing a game with a bet number of "2". is. In the AT state ST5, as will be described later, an additional lottery for determining whether or not to increase the remaining number of continuous games in the AT state ST5 based on the result of the lottery process (FIG. 18) for the winning combination in each game. Although processing can be executed, the additional lottery processing is executed in games where the number of bets is "3", but is not executed in games where the number of bets is "2". Therefore, from this point of view as well, in the AT state ST5, a game with a bet number of "3" is better to be executed than a game with a bet number of "2". is advantageous for

As described above, in the normal game state ST1, the pseudo-bonus state ST4, and the AT state ST5 in the second section SC2, even if it is advantageous to execute the game with the number of bets "3". , the number of game media awarded in a game with a bet number of "2" in any of the normal game state ST1, the pseudo-bonus state ST4, and the AT state ST5 in the second section SC2 is the number of game media in the second section SC2. In addition to being added as a limited total net increase number, the game in which the number of bets is "2" in any of the normal game state ST1, the pseudo-bonus state ST4 and the AT state ST5 in the second section SC2 is continued in the second section SC2. is added as the total number of games played. In other words, a game with a bet number of "2" in any of the normal game state ST1, the pseudo-bonus state ST4, and the AT state ST5 in the second section SC2 is disadvantageous to the player. It ends up contributing to the side that satisfies the ending condition of section SC2. From this point of view as well, in the case of any of the normal game state ST1, the pseudo-bonus state ST4 and the AT state ST5 in the second section SC2, it is better to execute a game with a bet number of "3". It is more advantageous to the player than having the game with the number "2" run.

Even in the second section SC2, the first CB winning can be established and the second CB winning can be established in the same manner as in the first section SC1. When the first CB win is established in the second section SC2, the second section SC2 enters the first CB state ST2, and the second section SC2 is maintained even after the first CB state ST2 and after the first CB state ST2 ends. be. In addition, when the second CB winning is established in the second section SC2, the second section SC2 becomes the second CB state ST3, and the second section SC2 continues even after the second CB state ST3 and when the second CB state ST3 ends. maintained. In both the first CB state ST2 and the second CB state ST3, as already explained, the number of game media owned by the player at the end of the game state is greater than the number of game media owned by the player at the start of the game state. This is a game state in which the number of media is reduced. That is, the first CB state ST2 and the second CB state ST3 are game states disadvantageous to the player. On the other hand, the games executed in either the first CB state ST2 or the second CB state ST3 in the second section SC2 are added as the total number of games executed by continuing the second section SC2. In other words, although the games executed in the first CB state ST2 and the second CB state ST3 are disadvantageous to the player, the games contribute to fulfilling the ending condition of the second section SC2. . Therefore, if the first CB state ST2 or the second CB state ST3 occurs in the second section SC2, it is more disadvantageous for the player.

It should be noted that in the end preparation state ST6, the number of game media is reduced regardless of whether a game with a bet number of "3" is executed or a game with a bet number of "2" is executed in the second section SC2. Although the net increase expected value is "0" or less, it is a gaming state in which only one game is executed while the second section SC2 ends with the end of the pseudo-bonus state ST4 or AT state ST5. Therefore, the games executed in the ready-to-end state ST6 do not contribute to the restricted total net increase in the number of game media in the second section SC2, and furthermore do not contribute to the total number of games in the second section SC2. However, the present invention is not limited to this, and even a game executed in the end preparation state ST6 contributes to the restricted total net increase in the number of game media in the second section SC2, and furthermore, in the second section SC2 It may be configured to contribute to the total number of games.

<Regarding CB states ST2 and ST3>
Next, the first CB state ST2 and the second CB state ST3 are described in detail. The first CB combination can be won in games where the number of bets is "3", but cannot be won in games where the number of bets is "2". In a game where the number of bets is "3", the first CB combination is won with a probability of about 1/3.3. However, the winning state of the first CB role (that is, the state in which the first CB winning data is stored in the main RAM 74), the winning state of the second CB role (that is, the state in which the second CB winning data is stored in the main RAM 74), In either the first CB state ST2 or the second CB state ST3, the first CB combination is excluded from the lottery targets in the lottery process (FIG. 18).

The second CB combination can be won in games where the number of bets is "2", but cannot be won in games where the number of bets is "3". In a game where the number of bets is "2", the second CB role is won with a probability of about 1/2.2. However, the winning state of the first CB role (that is, the state in which the first CB winning data is stored in the main RAM 74), the winning state of the second CB role (that is, the state in which the second CB winning data is stored in the main RAM 74), In either the first CB state ST2 or the second CB state ST3, the second CB combination is excluded from the lottery targets in the lottery process (FIG. 18).

In the winning state of the 1st CB combination, the 1st CB winning can be realized in the game with the bet number of "3", while the 1st CB winning can not be established in the game with the bet number of "2". Therefore, when the game with the number of bets "2" is executed in the winning state of the 1st CB combination, even if the lottery process (FIG. 18) for the combination results in no winning of any index value IV. , regardless of the stop order of the reels 32L, 32M, 32R and the stop operation timing of the stop buttons 42 to 44, the first CB prize is not established. Also, when a game with the number of bets of "2" is executed in the winning state of the first CB combination, even if the winning index value IV that can cause a so-called dropout occurs in the combination lottery process (FIG. 18), reel Regardless of the order of stopping 32L, 32M, and 32R and the stop operation timing of the stop buttons 42-44, the first CB prize is not established. When the game with the number of bets of "3" is executed in the winning state of the first CB combination and the first CB prize is established, the state becomes the first CB state ST2.

In the first CB state ST2, a game with a bet number of "3" can be executed, and a game cannot be executed with a bet number of 2 or less. In the first CB state ST2, normal replay winning data is stored in the main side RAM 74 with a probability of 3/10 in the winning lottery process (FIG. 18) in each game. If the operation timing of the button 42 is a predetermined timing, a normal replay prize is established regardless of the stop order of the reels 32L, 32M, 32R. If the operation timing of the left stop button 42 is not the predetermined timing, the normal replay winning is not established even if the normal replay winning data is stored.

In the first CB state ST2, when the normal replay winning data is not stored in the main RAM 74 in the winning lottery process (FIG. 18), or when the normal replay winning data is stored in the main RAM 74 but the left stop button 42 is pressed. When the normal replay winning cannot be established because the operation timing is not the predetermined timing, the first bell winning can be established. In this case, the winning of the first bell is achieved regardless of the order in which the reels 32L, 32M, and 32R are stopped.

However, it is not limited to this, and in the first CB state ST2, when normal replay winning data is stored in the main side RAM 74 in the lottery process (FIG. 18) of the combination, the order of stopping the reels 32L, 32M, 32R Also, a configuration may be adopted in which the normal replay prize is established reliably regardless of the stop operation timing of each of the stop buttons 42-44. Also, in the first CB state ST2, when the normal replay winning data is not stored in the main side RAM 74 in the winning lottery process (FIG. 18), the stop order of the reels 32L, 32M, 32R and the stop of each stop button 42-44 A configuration may be adopted in which the winning of the first bell is surely established regardless of the operation timing.

When the first bell win is established in the first CB state ST2, the game medium of "1" is provided. As already explained, in the first CB state ST2, the game can be executed only when "3" game media are betted. On the other hand, the number of game media awarded in the game in the first CB state ST2 is "1". Then, the first CB state ST2 ends when "30" game media are provided. Therefore, in the first CB state ST2, it is necessary to generate 30 times the event that "1" game media is awarded in the game executed by betting "3" game media. The game media owned by the player will decrease by at least 60 from the start of the first CB state ST2 to the end of the first CB state ST2. Therefore, the first CB state ST2 is a game state disadvantageous to the player.

Further, in the first CB state ST2, as described above, the normal replay winning may be established, and both the normal replay winning and the first bell winning may not be established. Then, when the first CB state ST2 occurs in the second section SC2, the first CB state ST2, which is disadvantageous to the player, continues for 30 games or more, and the number of games is executed in the second section SC2. will be added to the total number of games played.

In the winning state of the second CB combination, the second CB winning can be established in the game with the bet number of "2", while the second CB winning is not established in the game with the bet number of "3". Therefore, when a game with the number of bets of "3" is executed in the winning state of the 2nd CB combination, even if the lottery process for the combination (FIG. 18) results in no winning of any index value IV. , the order in which the reels 32L, 32M, and 32R are stopped and the stop operation timing of the stop buttons 42-44 do not establish the second CB winning. In addition, when a game with the number of bets of "3" is executed in the winning state of the 2nd CB combination, even if the winning index value IV that can cause a so-called dropout occurs in the combination lottery process (FIG. 18), reel The second CB prize is not established regardless of the stop order of 32L, 32M, and 32R and the stop operation timing of the stop buttons 42-44. When a game with a bet number of "2" is executed in the winning state of the second CB combination and the second CB winning is established, the state becomes the second CB state ST3.

In the second CB state ST3, the game can be executed in a situation where the number of bets is "2", and the maximum bet number of game media is "2". In the second CB state ST3, normal replay winning data is stored in the main side RAM 74 with a probability of 3/10 in the winning lottery process (FIG. 18) in each game. If the operation timing of the button 42 is a predetermined timing, a normal replay prize is established regardless of the stop order of the reels 32L, 32M, 32R. If the operation timing of the left stop button 42 is not the predetermined timing, the normal replay winning is not established even if the normal replay winning data is stored.

In the second CB state ST3, when the normal replay winning data is not stored in the main side RAM 74 in the winning lottery process (FIG. 18), or when the normal replay winning data is stored in the main side RAM 74, the left stop button 42 is pressed. When the normal replay winning cannot be established because the operation timing is not the predetermined timing, the first bell winning can be established. In this case, the winning of the first bell is achieved regardless of the order in which the reels 32L, 32M, and 32R are stopped.

However, it is not limited to this, and when the normal replay winning data is stored in the main side RAM 74 in the lottery process (FIG. 18) of the combination in the second CB state ST3, the order of stopping the reels 32L, 32M, 32R Also, a configuration may be adopted in which the normal replay prize is established reliably regardless of the stop operation timing of each of the stop buttons 42-44. In addition, in the second CB state ST3, when the normal replay winning data is not stored in the main side RAM 74 in the winning lottery process (FIG. 18), the order of stopping the reels 32L, 32M, and 32R and the stopping of the stop buttons 42 to 44 A configuration may be adopted in which the winning of the first bell is reliably established regardless of the operation timing.

If the first bell win is established in the second CB state ST3, the game medium of "1" is provided. As already explained, in the second CB state ST3, the game can be executed only when "2" game media are betted. On the other hand, the number of game media awarded in the game in the second CB state ST3 is "1". Then, the second CB state ST3 ends when "30" game media are awarded. Therefore, in the second CB state ST3, it is necessary to generate 30 times the event that "1" game media is awarded in the game executed by betting "2" game media. The game media possessed by the player will decrease by at least 30 from the start of the second CB state ST3 to the end of the second CB state ST3. Therefore, the second CB state ST3 becomes a game state disadvantageous to the player. However, this disadvantage of the second CB state ST3 is lower than that of the first CB state ST2.

Further, in the second CB state ST3, as described above, the normal replay winning can be established, and both the normal replay winning and the first bell winning may not be established. Then, when the second CB state ST3 occurs in the second section SC2, the second CB state ST3, which is disadvantageous to the player, continues for 30 or more games, and the number of games is executed in the second section SC2. added to the total number of games played.

As described above, in the configuration in which the first CB state ST2 and the second CB state ST3 are set as game states disadvantageous to the player, by executing the game with the number of bets "2", the winning state of the second CB combination is obtained. At the same time, after the second CB winning is not established, a game with a bet number of "3" is executed, and as a result of the winning lottery process (FIG. 18) in each game, the reels 32L, 32M, and 32R are stopped. Regardless of the order and the stop operation timing of each of the stop buttons 42 to 44, it is possible to play the game while preventing the transition to the first CB state ST2 and the second CB state ST3. That is, when the second CB role is won by executing a game in which the number of bets is "2", a game in which the number of bets is "3" is subsequently executed to achieve the second CB role. Even in the winning state of , the second CB prize is not established. Also, in the winning state of the second CB role, even if a game with the number of bets of "3" is executed, the first CB role is excluded from the lottery in the role lottery process (FIG. 18). will not be elected. Since the winning state of the first CB combination is not established, the first CB prize is not established, and the game state does not shift to the first CB state ST2. As a result, it is possible to execute a game with a bet number of "3" while preventing transitions to the first CB state ST2 and the second CB state ST3. Then, by executing a game in which the number of bets is "3", a transition to the second section SC2 can occur as already described, and a transition to the pseudo-bonus state ST4 can occur.

The probability of winning the second CB role in a game where the number of bets is "2" is about 1/2.2, whereas the probability of winning the first CB role in a game where the number of bets is "3". is about 1/3.3. That is, the probability of winning the second CB combination is set higher than the probability of winning the first CB combination. As a result, when the second CB role is won by executing a game in which the number of bets is "2" in a game hall or the like, the number of games required until the second CB role is won is reduced. becomes possible. On the other hand, even if a game with the number of bets of "3" is executed before the 2nd CB role is erroneously won, the probability of winning the 1st CB role is higher than the probability of winning the 2nd CB role. By making it low, it is possible to make it difficult to win the first CB combination.

The probability of winning the 2nd CB role is not limited to a configuration higher than the probability of winning the 1st CB role, and the probability of winning the 1st CB role is higher than the probability of winning the 2nd CB role. A high configuration may be employed, and a configuration may be employed in which the probability of winning the first CB role and the probability of winning the second CB role are the same or substantially the same.

<Contents of Display on Combined Display Unit 66>
Next, the contents displayed on the combined display unit 66 will be described. As already explained, in the combined display unit 66, the display corresponding to the stopping order of the reels 32L, 32M, and 32R, the ratio display for displaying the staying ratio of the second section SC2, and the giving in the main RAM 74 The given number is displayed based on the value of the number counter 74e.

As already explained, the main side RAM 74 is provided with a given number counter 74e (FIG. 14) which enables the main side MPU 72 to grasp the number of game media given to the player when a minor win is established. there is The value of the awarded number counter 74e is set to "0" in step S607 when a valid bet operation is performed while one or more virtual medals are stored in the already-described bet handling process (FIG. 16). ' is cleared, and when a medal inserted into the medal slot 45 is detected by the inserted medal detection sensor 45a, it is cleared to '0' in step S612.

As already described with reference to FIG. 7(b), the first to ninth stopping orders of the reels 32L, 32M, and 32R notified by the image display device 63 exist, and the combined display unit 1st to 9th stop order correspondence displays exist as the stop order correspondence displays executed at 66 . As shown in FIG. 14, the main RAM 74 is provided with a stop order type counter 74m and a ratio display counter 74n. The stopping order type counter 74m sends a stopping order type number indicating the type of display corresponding to the stopping order of the reels 32L, 32M, and 32R to be displayed on the combined display unit 66 when the stopping order correspondence display is executed. It is a counter that can be grasped by The stop order type counter 74m consists of 1 byte. The stop order type counter 74m is set to one of the stop order type numbers "1" to "9" or "0" indicating that the combined display section 66 does not display the stop order correspondence.

The ratio display counter 74n enables the main MPU 72 to grasp that ratio display should be executed by the combined display unit 66 and the calculation result data of the stay ratio of the second section SC2 to be displayed in the ratio display. is a counter. The ratio display counter 74n consists of 1 byte. The initial value of the ratio display counter 74n is "255", which indicates that the dual-use display section 66 does not display the ratio. When the partial clearing process is executed in step S105 of the main process (FIG. 10), or when the all clearing process is executed in step S106, the ratio display counter 74n has the initial value ("255"). set. In the management processing in step S213 of the timer interrupt processing (FIG. 11), if the operation for starting the ratio display, which will be described later, is performed while the game is not being executed, the stay ratio of the second section SC2 is set to 0% to 100%. is performed, and the result of the calculation is set in the ratio display counter 74n. Numerical information of one of "0" to "100" is set in the ratio display counter 74n as calculation result data of the stay ratio of the second section SC2. When any calculation result data of "0" to "100" is set in the ratio display counter 74n, the dual-use display unit 66 displays the ratio corresponding to the calculation result data. In the management process in step S213 of the timer interrupt process (FIG. 11), when an operation to end the ratio display, which will be described later, is performed, the ratio display counter 74n is set to the initial value "255". As a result, the ratio display on the combined display section 66 is finished. The details of the management process (step S213) will be described later.

FIG. 24(a) is an explanatory diagram for explaining the conditions under which the stop order correspondence display is executed, the conditions under which the ratio display is executed, and the conditions under which the given number display is executed on the combined display unit 66. FIG. As shown in FIG. 24(a), on the condition that one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m in the main RAM 74, display corresponding to the stop order is performed. Also, on the condition that the calculation result data of any one of "0" to "100" is set in the ratio display counter 74n, the dual-use display section 66 executes the ratio display. Furthermore, the stop order type number "1" to "9" is not set in the stop order type counter 74m, and the calculation result data "0" to "100" is set in the ratio display counter 74n. Under the condition that there is no state, the display of the given number is executed on the combined display section 66 . As described above, the numerical information set in the stop order type counter 74m in this embodiment is one of the stop order type numbers "1" to "9" or "0", and the stop order type counter 74m is set to "1". to "9" is not set, specifically, the state in which the value of the stop order type counter 74m is "0". Further, as described above, the numerical information set in the ratio display counter 74n in the present embodiment is any calculation result data of "0" to "100" or the initial value "255", and the ratio display counter 74n Specifically, a state in which "255" is set in the ratio display counter 74n is a state in which calculation result data "0" to "100" is not set in the ratio display counter 74n.

The state in which one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m starts during execution of the game and ends during execution of the game. On the other hand, the state in which the calculation result data of the stay ratio of the second section SC2 is set in the dual-use display unit 66 is started when the game is not being executed, and ends when the game is not being executed. . Also, the game is not started in a state where the calculation result data of the stay ratio of the second section SC2 is set in the combined display section 66 . A period during which one of the stop order classification numbers "1" to "9" is set in the stop order classification counter 74m, and one of calculation result data "0" to "100" is set in the ratio display counter 74n. It is a period that does not overlap with the period that is specified. For this reason, the condition for executing the stop order corresponding display and the condition for executing the ratio display on the combined display unit 66 are not satisfied at the same time.

As described above, in the combined display unit 66, when the game is being executed and the stop order type counter 74m is set to one of the stop order type numbers "1" to "9". , the stop order display is executed with priority over the display of the number of grants based on the value of the number of grants counter 74e. Further, when the game is not being executed and the ratio display counter 74n is in a state where any calculation result data of "0" to "100" is set, the award based on the value of the award number counter 74e Ratio display is executed preferentially over number display.

FIG. 24(b) is an explanatory diagram for explaining the relationship between the value of the index value counter 74f, the value of the stop order type counter 74m, and the display contents of the stop order correspondence display executed by the dual-use display unit 66. FIG. As already explained, when any of the index values IV of "1" to "17" is won in the winning lottery process (FIG. 18), the index value IV is set in the index value counter 74f. At the same time, if none of the index values IV is won in the winning lottery process (FIG. 18), the index value counter 74f is set to "0".

Any index value IV of "1" to "9" is won in the lottery process (FIG. 18) for the combination of the game in which the gaming state is the pseudo-bonus state ST4 or the AT state ST5 and the number of bets is "3". If so, the index value IV of any one of "1" to "9" is set in the stop order type counter 74m as the stop order type number. As shown in FIG. 24(b), when the stop order type counter 74m is set to "1", the combined display unit 66 displays the stop order correspondence display corresponding to the first stop order of "left→middle→right". is performed, and when "2" is set in the stop order type counter 74m, the stop order corresponding display corresponding to the second stop order of "left→right→middle" is performed, and "3" is set in the stop order type counter 74m. is set, the stop order correspondence display corresponding to the third stop order of "middle→left→right" is performed, and when "4" is set in the stop order type counter 74m, "middle→right→ When the stop order corresponding display corresponding to the fourth stop order of "left" is performed and "5" is set in the stop order type counter 74m, the stop order corresponding to the fifth stop order of "right→left→middle" is displayed. When the corresponding display is made and "6" is set in the stop order type counter 74m, the stop order corresponding display corresponding to the sixth stop order of "right→middle→left" is displayed, and the stop order type counter 74m is set to "6". When "7" is set, the stop order correspondence display corresponding to the seventh stop order of "first stop is left" is performed, and when "8" is set in the stop order type counter 74m, "first stop" is displayed. The eighth stop order correspondence display corresponding to the stop order of "medium stop" is displayed, and when "9" is set in the stop order type counter 74m, it corresponds to the ninth stop order of "first stop to the right". Stop order correspondence display is performed.

Winning an index value of any of "10" to "17" in the lottery process (FIG. 18) for a game combination in which the gaming state is the pseudo-bonus state ST4 or the AT state ST5 and the number of bets is "3" , or if none of the index values IV of "1" to "17" is won, the value of the stop order type counter 74m becomes "0". If the gaming state is not the pseudo-bonus state ST4 or the AT state ST5, and if the number of bets is "2", the stop order type counter 74m is set to "0". As shown in FIG. 24(b), the stop order type number of "0" is a number indicating that the dual-purpose display unit 66 does not display the stop order correspondence. When the value of the stop order type counter 74m is "0", the value of the ratio display counter 74n is the initial value ("255"). Numerals are performed. In the display of the given number based on the value of the given number counter 74e, a number indicating the given number when the given number of "1", "2", "5" or "15" is set in the given number counter 74e. and the display of "0" when the value of the given number counter 74e is "0".

As shown in FIG. 14, the main side RAM 74 is provided with a left dual-purpose display section display area 74p and a right dual-purpose display section display area 74q. The left combined display section display area 74p is a storage area in which 1-byte display data to be output to the left 7-segment display 66a in the combined display section 66 is set, and the right combined display section display area 74q is used for combined display. This is a storage area in which 1-byte display data to be output to the 7-segment display 66b on the right side of the section 66 is set.

FIG. 24(c) is an explanatory diagram for explaining the configuration of the main-side ROM 73. As shown in FIG. As shown in FIG. 24(c), the main ROM 73 has a stop order display data table 73a for displaying the stop order correspondence on the combined display unit 66, and the combined display unit 66 displays the ratio and the given number. A numeric display data table 73b for performing In the stop order display data table 73a, display data for stop order display corresponding to the stop order type numbers "1" to "9" are set. When the main-side MPU 72 displays the stop order correspondence on the combined display unit 66, it reads the stop order display data table 73a, and uses the display data corresponding to the stop order number set in the stop order classification counter 74m for the right side. It is set in the display section display area 74q. In addition, non-display data is set in the display area 74p for the left-side display unit. As a result, the left 7-segment display 66a of the dual-use display unit 66 is put into a non-display state, and the right 7-segment display 66b displays a display corresponding to one of the first to ninth stop orders. Correspondence display is performed.

Display data for displaying numbers "1" to "9" on the left 7-segment display 66a and the right 7-segment display 66b of the combined display unit 66 are set in the number display data table 73b. . When displaying the ratio on the combined display unit 66, the main MPU 72 reads out the number display data table 73b, and displays the display data corresponding to the tens digit of the calculation result data set in the ratio display counter 74n on the left side. The display data corresponding to the 1's digit of the calculation result data is set in the dual-purpose display section display area 74p, and the display data corresponding to the one-digit number of the calculation result data is set in the right-side dual-purpose display section display area 74q. As a result, the 7-segment displays 66a and 66b of the dual-purpose display unit 66 display any one of "0", "01" to "99", and "00" for ratio display. In the ratio display, when the value of the ratio display counter 74n is "0", the left 7-segment display 66a is not displayed and the right 7-segment display 66b lights and displays "0". Therefore, "0" is displayed on the dual-purpose display section 66. FIG. Further, when the value of the ratio display counter 74n is "100", "0" is illuminated on the left 7-segment display 66a and the right 7-segment display 66b. Therefore, "00" is displayed on the dual-purpose display section 66. FIG. This makes it easier to distinguish between the display indicating that the stay ratio of the second segment SC2 is 0% and the display indicating that the stay ratio is 100%.

When displaying the given number on the shared display unit 66, the main MPU 72 reads out the number display data table 73b, and displays the display data corresponding to the digits in the tenth place of the given number set in the given number counter 74e. The display data corresponding to the 1's digit in the given number is set in the combined display section display area 74p, and the display data corresponding to the one's digit in the given number is set in the right combined display section display area 74q. As a result, the 7-segment displays 66a and 66b of the dual-use display unit 66 display "00", "01", "02", "05" or "15" to display the given number.

As described above, the main MPU 72 grasps that it is the execution period of the display corresponding to the stop order on the combined display unit 66 based on the value of the stop order type counter 74m being any one of "1" to "9". At the same time, based on the fact that the stop order type numbers "1" to "9" are not set in the stop order type counter 74m, it is understood that it is not the execution period of the stop order correspondence display. The slot machine 10 has a configuration in which, during execution of the game, display corresponding to the stop order based on the value of the stop order type counter 74m or display of the awarded number based on the value of the awarded number counter 74e is executed on the combined display unit 66. A flag that enables the main side MPU 72 to grasp that the unit 66 should execute the stop order display and the state that the given number display should be executed is defective. For this reason, compared to the configuration having the flag, the dual-use display unit 66 can display a state in which the display corresponding to the stop order and a state in which the awarded number is displayed are executed during the execution of the game. The data capacity of the main RAM 74 can be reduced.

The main MPU 72 recognizes that it is the execution period of the ratio display on the dual-purpose display unit 66 based on the calculation result data of any one of "0" to "100" being set in the ratio display counter 74n. , it is determined that it is not the execution period of the ratio display based on the fact that the calculation result data of "0" to "100" is not set in the ratio display counter 74n. In a configuration in which the ratio display based on the value of the ratio display counter 74n or the award number display based on the value of the award number counter 74e is performed on the dual-use display unit 66 during a period in which the game is not being executed, the slot machine 10 can be used for dual-purpose display. A flag that enables the main side MPU 72 to grasp that the unit 66 should execute the ratio display and the state that the given number display should be executed is defective. For this reason, compared to the configuration having the flag, a state in which the ratio display is performed and a state in which the awarded number is displayed on the dual-purpose display unit 66 during a period in which the game is not performed are generated. Therefore, the data capacity of the main RAM 74 can be reduced.

A period during which the stop order type number of one of "1" to "9" is set in the stop order type counter 74m, and one of the calculation result data of "0" to "100" is set in the ratio display counter 74n. It is a period that does not overlap with the period that is specified. For this reason, the condition for executing the stop order corresponding display and the condition for executing the ratio display on the combined display unit 66 are not satisfied at the same time. This eliminates the need for a flag that enables the main MPU 72 to grasp that the dual-use display unit 66 is in a state in which the stop order correspondence display should be executed and that the ratio display should be executed. Compared to the configuration provided, it is possible to reduce the data capacity of the main side RAM 74 for generating the state in which the stop order correspondence display and the state in which the ratio display is performed on the dual-purpose display unit 66 are performed. can.

Next, the lottery result handling process executed by the main MPU 72 will be described with reference to the flowchart of FIG. The lottery result handling process is executed in step S914 of the combination lottery process (FIG. 18).

In the lottery result handling process, if the current gaming state is not the pseudo-bonus state ST4 (step S1101: NO), it is determined whether or not the current gaming state is the AT state ST5 (step S1102). If the current gaming state is the pseudo-bonus state ST4 (step S1101: YES) or if it is the AT state ST5 (step S1102: YES), the value of the bet number setting counter 74b in the main side RAM 74 is "3". It is determined whether or not there is (step S1103). When the value of the bet number setting counter 74b is "3" (step S1103: YES), that is, when the bet number of this game is "3", refer to the index value counter 74f in the main side RAM74. It is determined whether or not any of the index values IV=1 to 9 has been won in the winning lottery process (FIG. 18) (step S1104).

When an affirmative determination is made in step S1104, the value of the index value counter 74f is set in the stop order type counter 74m in the main RAM 74 (step S1105). In step S1105, "n" (n is an integer from "1" to "9") is set in the stop order type counter 74m, so that the display contents of the stop order correspondence display on the combined display unit 66 are changed to the first. The display corresponds to the n stop order. The process of step S1105 is a process of setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m. This is processing for switching to display. Therefore, in addition to the processing of step S1105 for setting the stop order type counter 74m to one of the stop order type numbers "1" to "9", display on the dual-purpose display unit 66 is performed as a separate process. Compared to the configuration in which the processing for switching the display of the number of grants based on the value of the grant number counter 74e to the display corresponding to the stop order is set, the stop order type counter 74m is set to any one of "1" to "9". It is possible to simplify the processing configuration for setting the stop order type number and switching the display content on the dual-use display unit 66 from display of the assigned number to display corresponding to the stop order.

As already explained, the index value IV won in the winning lottery process (FIG. 18) is stored in the index value counter 74f. In a game in which the stop order correspondence display on the combined display unit 66 and the stop order notification on the image display device 63 are executed, the index value IV of any one of "1" to "9" stored in the index value counter 74f is It is set in the stop order type counter 74m as the stop order type number as it is. For this reason, compared to the structure in which the data of the stop order type number set in the stop order type counter 74m is different from the data of the index value IV that was won in the winning lottery process (FIG. 18), The processing configuration for setting the stop order type number in the order type counter 74m is simplified.

If a negative determination is made in step S1102, step S1103 or step S1104, the value of the stop order type counter 74m is cleared to "0" (step S1106). As a result, the current game is a game in which the stop order correspondence display on the combined display unit 66 and the stop order notification on the image display device 63 are not executed.

In this way, in the lottery process (FIG. 18) for the combination of the game in which the gaming state is the pseudo-bonus state ST4 or the AT state ST5 and the number of bets is "3", "n" (n is "1" to "9 ”), “n” is set in the stop order type counter 74m, and the display content of the display corresponding to the stop order on the combined display unit 66 becomes the display corresponding to the n-th stop order. . On the other hand, the condition is that the gaming state is the pseudo-bonus state ST4 or the AT state ST5, the condition is that the number of bets in this game is "3", and the lottery process (FIG. 18) for the combination "1" to "9 is not satisfied, the value of the stop order type counter 74m is cleared to "0", and the current game corresponds to the stop order on the combined display unit 66. This is a game in which the stop order notification on the display and image display device 63 is not executed.

If the process of step S1105 or step S1106 has been performed, the starting command flag provided in the main RAM 74 is set to "1" (step S1107), and the lottery result handling process ends. The start command flag is a flag that allows the main side MPU 72 to grasp that a start time command should be transmitted to the effect side MPU 92 . In step S1107, the command flag at start is set to "1", whereby common command transmission processing (FIG. 50) is executed in step S2709 of command output processing (FIG. 44), which will be described later. In the common command transmission process (FIG. 50), the process for transmitting the start command is executed on condition that the start command flag is set to "1". The details of the start command will be described later.

Next, the winning determination process executed by the main MPU 72 will be described with reference to the flowchart of FIG. Winning determination processing is executed in step S1015 of the reel control processing (FIG. 22).

In the winning determination process, first, the types of symbols stopped on the main line ML on the reels 32L, 32M, and 32R are grasped (step S1201). After that, it is determined whether or not a prize for the winning combination has been established (step S1202). In step S1202, by referring to the first winning data area 74g, the second winning data area 74h, the first CB winning data area 74j and the second CB winning data area 74k in the main RAM 74, the player wins in the winning lottery process (FIG. 18). Grasp the role that has become. Then, it is determined whether or not the combination of symbols stopped and displayed on the main line ML of each of the reels 32L, 32M, 32R is a combination of symbols corresponding to the winning combination in the winning combination lottery process (FIG. 18). If the symbol combination corresponds to the winning combination, it is determined that the winning combination has been won. When the winning combination is established (step S1202: YES), the winning data setting process is executed (step S1203). In the winning data setting process, the winning data corresponding to the winning combination is set in the winning data area 78 provided in the main RAM 74 . As already explained, the winning data area 78 is a storage area in which 1-byte data is set so that the main MPU 72 can grasp the winning combination in the current game.

After that, if the winning achieved this time is a minor winning combination (step S1204: YES), the number of game media to be provided corresponding to the winning combination is set in the provided number counter 74e (step S1205). In step S1205, when the winning of the first to ninth compensation roles is established, the award number counter 74e is set to "1", and when the winning of the cherry role is established, the award number counter 74e is set to "2". set, and when the winning of the first watermelon role or the second watermelon role is established, "5" is set to the award number counter 74e, and when the winning of the first bell role or the second bell role is established, the award is given. "15" is set in the number counter 74e. As a result, the main MPU 72 can grasp the number of given game media by referring to the given number counter 74e in the medium giving process in step S409 of the normal process (FIG. 13).

In a game in which display corresponding to the stop order on the dual-use display unit 66 and notification of the stop order on the image display device 63 are not executed, if any of the small wins is won, the value of the awarded number counter 74e (“0”) is displayed on the dual-use display unit 66 ), "1", "2", "5" or "15" is set to the given number counter 74e in step S1205. As a result, the port output process (FIG. 28) in step S211 of the timer interrupt process (FIG. 11) is executed, and the display contents of the display of the assigned number on the combined display unit 66 are changed from "00" to "01" to "02". , "05" or "15".

If the winning achieved this time is a replay winning (step S1204: NO, step S1206: YES), the replay winning flag of the main RAM 74 is set to "1" (step S1207). As already explained, the replay winning flag is a flag that enables the main MPU 72 to recognize that a replay winning has been established. By setting the replay winning flag to "1" in step S1207, the replay winning flag is referred to in the start waiting process (FIG. 15) after the end of the current game, and any replay is performed in the finished game. It is possible for the main MPU 72 to be able to grasp whether or not a prize has been won. If the win achieved this time is a replay win (step S1206: YES), or if none of the wins have been achieved (step S1206: NO), the process of changing the value of the awarded number counter 74e is not executed.

When a negative determination is made in step S1202, when the process of step S1205 is performed, when a negative determination is made in step S1206, or when the process of step S1207 is performed, the stop order type counter 74m is set to " 0” is cleared (step S1208), and the main winning judgment process is terminated. As already explained, the dual-use display unit 66 supports the stop order on the condition that one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m during execution of the game. display is performed. In the game in which the stop order correspondence display is executed on the combined display unit 66, the value of the stop order type counter 74m is cleared to "0" in step S1208, and the port output process (FIG. 28) is executed. , the display corresponding to the stop order executed by the combined display unit 66 ends, and the display of the given number based on the value of the given number counter 74e is started.

As already explained, when the game is being executed, the main MPU 72 causes the combined display unit 66 to display As well as grasping that it is the execution period of the display corresponding to the stop order, based on the value of the stop order type counter 74m being "0", it is determined that it is the execution period of the display of the number of grants based on the value of the grant number counter 74e. grasp. The process of step S1208 is a process of clearing the value of the stop order type counter 74m to "0" and switching the display content on the combined display unit 66 from display corresponding to the stop order to display of the number of grants based on the value of the number counter 74e of grants. This is a process of setting for Therefore, in addition to the process of clearing the value of the stop order type counter 74m to "0", as a separate process from this process, the display content on the combined display unit 66 is changed from the display corresponding to the stop order to the value of the given number counter 74e. The value of the stop order type counter 74m is cleared to "0" and the display content on the dual-use display unit 66 is changed from the display corresponding to the stop order to the display of the number of grants, compared with the configuration in which the processing for switching to the display of the number of grants based on is set. The processing configuration for switching to can be simplified.

As described above, when a replay win is established or when none of the wins are established, the process of changing the value of the awarded number counter 74e is not executed. In these cases, the value of the stop order type counter 74m is cleared to "0" in step S1208 while the value (specifically, "0") of the given number counter 74e is maintained. display of the given number (display of "00") corresponding to the value ("0") of the given number counter 74e is started. If the display corresponding to the stop order has been executed on the dual-purpose display unit 66, the value of the stop order type counter 74m is cleared to "0" in step S1208. When the display corresponding to the stop order ends, the display of the number of rewards (display of "00") corresponding to the value ("0") of the number of rewards counter 74e is started. In addition, when the dual-use display unit 66 does not perform display corresponding to the stop order, that is, the dual-purpose display unit 66 displays the given number corresponding to the value (“0”) of the given number counter 74e (“00” is displayed). ) has been executed, the display of "00" continues even after the value of the stop order type counter 74m is cleared to "0" in step S1208.

As described above, the stop order correspondence display on the dual-use display unit 66 is obtained by clearing the stop order type counter 74m to "0" in the winning determination process (FIG. 26) executed after all the reels 32L, 32M, and 32R have stopped. end by

In the winning determination process (FIG. 26), when a minor winning combination is established, the timing at which the processing in step S1205 for setting the award number corresponding to the minor winning combination in the award number counter 74e is executed is the stop order type counter 74m. is cleared to "0" before the timing at which the processing of step S1208 is executed. When the stop order type counter 74m is cleared to "0" while the stop order correspondence display is being performed on the dual use display unit 66, the display content of the dual use display unit 66 is switched from the stop order correspondence display to the given number display. If the processing configuration is such that the stop order type counter 74m is cleared to "0" before setting the number of grants corresponding to the small win achieved this time to the number counter 74e of grants, the stop order corresponding display on the combined display unit 66 is finished. There is a risk that "0" will be displayed between the start and the start of display of the award number corresponding to the small winning combination established this time. When the display contents on the dual-purpose display unit 66 are switched twice in a short time (for example, about 3 milliseconds) in the order of display corresponding to the stop order→“00”→display corresponding to the number of game media to be given, the manager of the game hall or confuse the player. On the other hand, the processing configuration is such that the stop order type counter 74m is cleared to "0" in a state in which the number of awarded game media corresponding to the minor win achieved this time is set in the awarded number counter 74e. It is possible to smoothly switch the display content on the display unit 66 from the stop order correspondence display to the given number display.

Next, management processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. The management process is executed in step S213 of the timer interrupt process (FIG. 11).

In the management process, first, it is determined whether or not ratio display is being performed on the combined display unit 66 (step S1301). As already explained, when the game is not being executed, the ratio display counter 74n is also displayed when any one of "0" to "100" is set as the calculation result data of the stay ratio of the second section SC2. When the ratio display is executed by the unit 66 and the calculation result data of "0" to "100" is not set in the ratio display counter 74n, the dual-purpose display unit 66 gives the value based on the value of the given number counter 74e. Numerals are performed. In step S1301, it is determined that the ratio display is being performed when any one of calculation result data from "0" to "100" is set in the ratio display counter 74n (step S1301: YES).

When ratio display is not being executed on the combined display unit 66 (step S1301: NO), the game is executed by determining whether or not the in-game flag in the main RAM 74 is set to "1". It is determined whether or not it is in a state of being in a state of being in a state of being in a state (step S1302). As already described, the in-game flag is set to "1" in step S803 of the setting process at the start (FIG. 17B), and the in-game flag is set in the corresponding process at the end of the game (FIG. 32). is cleared to "0" in step S1510.

If the game is not being executed (step S1302: NO), it is determined whether or not a ratio display start operation has been performed (step S1303). In step S1303, the front door 12 is opened and the power supply unit 54 is opened in a situation where the operating power of the slot machine 10 is being supplied and the setting value update processing in step S107 of the main processing (FIG. 10) is not being executed. It is determined whether or not the reset button 56 provided in is continuously pressed for 3 seconds or more. As already explained, when the supply of operating power to the slot machine 10 is started while the setting key insertion hole 57 is being turned ON and the reset button 56 is being pressed, the main process ( In FIG. 10), the all clear processing of step S106 is executed. Further, in the set value update process in step S107 of the main process (FIG. 10), the reset button 56 is operated to update the set values of the slot machine 10. FIG. When the reset button 56 is continuously pressed for 3 seconds or more in a situation where the operating power of the slot machine 10 is supplied and the set value update process (step S107) is not executed, the ratio display is started. Since it is determined that an operation has been performed, the operation of the reset button 56 for executing the all clear process (step S106) and the reset button for updating the set value in the set value update process (step S107) 56 and operation of the reset button 56 for starting the ratio display can be prevented from being erroneously identified.

On the condition that the ratio display start operation is performed (step S1303: YES) while the game is not being executed (step S1302: NO), the ratio calculation process is executed (step S1304). In the ratio calculation process, a calculation for calculating the stay ratio of the second section SC2 is executed using the total game number counter and the second section game number counter provided in the main RAM74. The total number-of-games counter is a counter for counting the number of games completed regardless of the game state and the game interval. The total number of games counter consists of 2 bytes and can count the number of games with an upper limit of "65535". Further, the value of the total number of games counter is not cleared to "0" unless the all-clearing process of step S106 is executed in the main process (FIG. 10). Therefore, it is possible to count the total number of games played on a plurality of business days in the gaming hall. The second section game number counter is a counter that enables the main MPU 72 to grasp the total number of games executed in the second section SC2. The second section game number counter is provided separately from a continued game number counter 74r, which will be described later, in the main RAM 74, and the value of the continued game number counter 74r is cleared to "0" when the second section SC2 ends. However, the value of the second section game number counter is not cleared to "0". Therefore, when the second section SC2 occurs multiple times with the first section SC1 in between, the total number of games played in the plurality of times of the second section SC2 is counted by the second section game number counter. is possible. The second interval game number counter consists of 2 bytes and can count the number of games with an upper limit of "65535". Also, the value of the second interval game number counter is not cleared to "0" unless the all clearing process of step S106 is executed in the main process (FIG. 10). Therefore, it is possible to count the total number of games in the second section SC2 that have been played on a plurality of business days in the gaming hall. The value of the total number-of-games counter is updated in step S1511 of the game-end handling process (FIG. 32), which will be described later, and the value of the second-section game-number counter is updated in the second control process of the game section, which will be described later (FIG. 36). ) in step S1905. In the ratio calculation process in step S1304, the calculation is performed so that the calculation result=(value of second section game number counter)/'value of total game number counter'×100. The stay rate of the section SC2 is any one of 0% to 100%, and the calculation result data is numerical information of any one of "0" to "100".

After that, the calculation result data in the ratio calculation process (step S1304) is set in the ratio display counter 74n of the main RAM 74 (step S1305), and this management process ends. As already explained, when the game is not being executed, the main MPU 72 is shared based on the calculation result data of any one of "0" to "100" being set in the ratio display counter 74n. Based on the value of the given number counter 74e based on the fact that the execution period of the ratio display on the display unit 66 is grasped and the calculation result data of "0" to "100" is not set in the ratio display counter 74n Understand that it is the execution period for displaying the number of grants. In a state where the game is not being executed, any calculation result data of "0" to "100" is set in the ratio display counter 74n in step S1305, so that the addition executed by the combined display unit 66 The display of the given number based on the value of the number counter 74e is completed, and the ratio display is started. The process of step S1305 is a process for storing the calculation result data in the ratio display counter 74n, and for switching the display content on the dual-purpose display unit 66 from the display of the given number based on the value of the given number counter 74e to the ratio display. This is the processing for setting. For this reason, in addition to the process of storing the calculation result data in the ratio display counter 74n, as a separate process from this process, the display content on the combined display unit 66 is changed from the given number display to the ratio display based on the value of the given number counter 74e. , the calculation result data is stored in the ratio display counter 74n and the display content on the dual-use display unit 66 is set to switch from the number of imparted display to the ratio display. can be simplified.

If ratio display is being performed on the combined display unit 66 (step S1301: YES), it is determined whether or not an operation to end the ratio display has been performed (step S1306). Specifically, it determines whether an ON signal is received from any of the start detection sensor 41a, the stop detection sensors 42a to 44a, the inserted medal detection sensor 45a, the credit insertion detection sensor 47a, and the settlement detection sensor 51a, When it is determined that an ON signal has been received from any of the detection sensors 41a to 45a and 47a, it is determined that the termination operation has been performed. In this case, an affirmative determination is made in step S1306 regardless of whether or not each ON signal is generated during the effective period. That is, regardless of whether or not reception of the ON signal from the start detection sensor 41a triggers the start of rotation of the reels 32L, 32M, and 32R, an affirmative determination is made in step S1306. Also, regardless of whether or not the reception of the ON signal from the stop detection sensors 42a to 44a serves as a trigger for stopping the rotation of the reels 32L, 32M, 32R, a positive determination is made in step S1306. Also, regardless of whether or not the reception of the ON signal from the inserted medal detection sensor 45a is the target of bet setting or credit increase, affirmative determination is made in step S1306. Also, regardless of whether or not the reception of the ON signal from the credit insertion detection sensor 47a is the target of the bet setting, the affirmative determination is made in step S1306. Also, regardless of whether or not the reception of the ON signal from the settlement detection sensor 51a serves as a settlement trigger for the credited virtual medals, a positive determination is made in step S1306.

If the ratio display end operation has been performed (step S1306: YES), the initial value "255" is set to the ratio display counter 74n (step S1307), and this management process ends. By setting the initial value to the ratio display counter 74n in step S1307, the display contents on the dual-purpose display unit 66 are changed assuming that the calculation result data of "0" to "100" are not set in the ratio display counter 74n. It is possible to switch from the ratio display to the grant number display. The process of step S1307 is a process of setting an initial value to the ratio display counter 74n and a process of switching the display content on the combined display unit 66 from the ratio display to the given number display based on the value of the given number counter 74e. . Therefore, in addition to the processing of step S1307 for setting the initial value to the ratio display counter 74n, processing for switching the display content on the dual-purpose display unit 66 from the ratio display to the given number display is performed as a separate processing. Compared to the set configuration, it is possible to simplify the processing configuration for setting the initial value to the ratio display counter 74n and switching the display content on the dual-purpose display unit 66 from the ratio display to the given number display.

If a negative determination is made in step S1306, this management process is terminated. A new game is not started while the ratio display is being performed on the dual-purpose display section 66 . Therefore, during execution of the ratio display, the calculation result data stored in the ratio display counter 74n and the stay ratio of the second section SC2 displayed on the combined display section 66 are not updated.

In this way, the calculation result data of the stay ratio of the second section SC2 is set in the ratio display counter 74n when the ratio display start operation is performed while the game is not being executed. Even in a state where the ratio display is not executed on the dual-purpose display unit 66, the calculation for calculating the stay ratio of the second section SC2 is performed, and the calculation result data is stored in the main side RAM 74. As a result, the ratio In addition to the display counter 74n, it is necessary to provide the main RAM 74 with a counter for storing the calculation result data. On the other hand, since the calculation result data is set to the ratio display counter 74n only during the period in which the ratio display is executed on the dual-purpose display unit 66, the calculation result data can be stored on the main side. The data capacity of the storage area provided in the RAM 74 can be reduced.

Next, the port output processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. Port output processing is executed in step S211 of timer interrupt processing (FIG. 11).

In the port output process, first, it is determined whether or not one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m of the main RAM 74 (step S1401). As already explained, in the lottery process (FIG. 18) for the combination of the game in which the gaming state is the pseudo-bonus state ST4 or the AT state ST5 and the number of bets is "3", "n" ("n" is "1" Any integer from 1 to 9), the stop order type counter 74m is set to 'n'. On the other hand, under the condition that the gaming state is the pseudo-bonus state ST4 or the AT state ST5, under the condition that the number of bets in the current game is "3", or "1" to "9" in the winning lottery process (FIG. 18) is not satisfied, "0" is set to the stop order type counter 74m. If one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m (step S1401: YES), the stop order corresponding display data table stored in the main ROM 73 is displayed. 73a (FIG. 24(c)) is read (step S1402). After that, referring to the stop order display data table 73a read in step S1402, the display data corresponding to the value of the stop order type counter 74m is set in the right dual-purpose display area 74q of the main RAM 74, and is not displayed. data is set in the left combined display unit display area 74p of the main RAM 74 (step S1403). As a result, the processing of step S1409, which will be described later, is executed, so that the dual-use display unit 66 displays the stop order correspondence.

If the value of the stop order type counter 74m is not "1" to "9" (step S1401: NO), the ratio display counter 74n of the main side RAM 74 stores any calculation result data of "0" to "100". is set (step S1404). If any calculation result data from "0" to "100" is set in the ratio display counter 74n (step S1404: YES), the number display data table 73b (FIG. 24) stored in the main ROM 73 is displayed. (c)) is read (step S1405). Thereafter, the display data corresponding to the value of the ratio display counter 74n is set in the left combined display section display area 74p and the right combined display section display area 74q by referring to the number display data table 73b read in step S1405 (step S1406). ). In step S1406, if the value of the ratio display counter 74n is "0", non-display data is set in the left dual-purpose display section display area 74p, and a display corresponding to "0" is displayed in the right dual-purpose display section display area 74q. set the data. In step S1406, when the value of the ratio display counter 74n is "1" to "9", the display data corresponding to "0" is set in the left combined display section display area 74p, and the right combined display section display area 74q is set. is set to the display data corresponding to the ones digit (“1” to “9”). In step S1406, if the value of the ratio display counter 74n is "10" to "99", the display data corresponding to the tens digit ("1" to "9") is displayed in the left dual-purpose display section display area 74p. At the same time, display data corresponding to the ones' digits (“1” to “9”) are set in the right combined display section display area 74q. In step S1406, when the value of the ratio display counter 74n is "100", display data corresponding to "0" is set in the left combined display section display area 74p and the right combined display section display area 74q. As a result, the processing of step S1409, which will be described later, is executed, so that the ratio display is performed on the combined display unit 66. FIG.

The stop order type number of "1" to "9" is not set in the stop order type counter 74m (step S1401: NO), and the calculation result data of "0" to "100" is in the ratio display counter 74n. If it is not set (step S1404: NO), the processing (steps S1407 and S1408) for displaying the number of grants on the combined display unit 66 is executed. Specifically, first, similarly to step S1405, the number display data table 73b stored in the main ROM 73 is read (step S1407). After that, referring to the numeric display data table 73b read in step S1407, the display data corresponding to the value of the given number counter 74e is set in the left combined display section display area 74p and the right combined display section display area 74q (step S1408). ). As a result, the processing of step S1409, which will be described later, is executed, so that the display of the given number is performed on the combined display unit 66. FIG.

When the processing of step S1403, step S1406, or step S1408 is performed, the data (display data or non-display data) set in the left dual-purpose display section display area 74p and the right dual-purpose display section display area 74q are dual-displayed. Output to the unit 66 (step S1409). As a result, when the non-display data is set in the left dual-purpose display section display area 74p and the display data for display corresponding to the stop order is set in the right dual-purpose display section display area 74q, the dual-purpose display section 66 display corresponding to the stop order is executed. In addition, when non-display data or display data for ratio display is set in the left side display area 74p and display data for ratio display is set in the right side display area 74q, A ratio display is performed on the display unit 66 . Furthermore, when display data for displaying the given number is set in the shared display section display areas 74p and 74q, the shared display section 66 displays the given number.

After that, display control processing for the credit display section 65 is executed (step S1410), other port output processing is executed (step S1411), and this port output processing ends. Other port output processing in step S1411 outputs data corresponding to the I/O device from the input/output port.

Next, how the dual-use display unit 66 performs the stop order display and the given number display will be described with reference to the time chart of FIG. 29 . FIG. 29(a) shows the execution period of display corresponding to the stopping order in the combined display section 66, FIG. 29(b) shows the execution period of display of the given number in the combined display section 66, and FIG. 29(c) shows the stop order type. 29(d) shows a period during which the counter 74m is set with any of the stop order classification numbers "1" to "9", and FIG. , FIG. 29(e) shows the timing at which a bet operation or the first medal is inserted while the game is not being executed, FIG. 29(f) shows the timing at which the game is started, and FIG. ) indicates the timing at which the operation of the stop buttons 42 to 44 is validated, and FIG. 29(i) shows the timing at which the port output process (FIG. 28) is executed.

When a bet operation or the first medal insertion is performed as shown in FIG. , and as shown in FIG. 29(d), the value of the award number counter 74e is cleared to "0" at the timing of t1. After that, at timing t2, port output processing is executed as shown in FIG. be. If the display of the given number of "00" has already been executed at the timing of t1, the display of the given number of "00" is continued. Further, when the given number display of '01', '02', '05' or '15' is being executed at the timing t1, the display is switched to the given number display of '00'.

After that, the start lever 41 is operated at the timing t3, and the game is started as shown in FIG. 29(f). After that, as shown in FIG. 29(c), at the timing of t4, one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m. After that, at timing t5, port output processing is executed as shown in FIG. The number display is switched to the stop order display. The timing of t5 is the timing before the timing of t6 when the operation of the stop buttons 42 to 44 is validated. The stop order correspondence display on the dual-purpose display unit 66 is started at a timing before the timing at which the operation of the stop buttons 42 to 44 is validated. After that, at timing t6, the operation of the stop buttons 42 to 44 is validated as shown in FIG. 29(g).

After that, at the timing of t7, as shown in FIG. 29(h), the establishment of a minor winning combination is specified in the winning determination process (FIG. 26), and the number of game media provided corresponding to the minor winning combination achieved this time. (“1”, “2”, “5” or “15”) is set in the grant number counter 74e. After that, at timing t8, the value of the stop order type counter 74m is cleared to "0" as shown in FIG. 29(c). After that, at timing t9, the port output process is executed as shown in FIG. It switches from the order correspondence display to the grant number display.

As already described, in the winning determination process (FIG. 26), when a minor winning combination is established, the processing of step S1205 is executed to set the number of game media to be granted corresponding to the minor winning combination in the granted number counter 74e. The timing (timing t7) is the timing before the timing (timing t8) at which the process of step S1208 for clearing the stop order type counter 74m to "0" is executed. As already explained, when the stop order type counter 74m is cleared to "0" while the stop order corresponding display is being executed on the combined display section 66, the display contents of the combined display section 66 are added from the stop order corresponding display. Switch to number display. If the processing configuration is such that the stop order type counter 74m is cleared to "0" before setting the number of game media to be given corresponding to the minor win achieved this time to the given number counter 74e, the stop order corresponding display is displayed on the combined display unit 66. There is a risk that "0" will be displayed between the end of the game and the start of display of the number of awards corresponding to the small win achieved this time. When the display contents on the dual-purpose display unit 66 are switched twice in a short time (for example, about 3 milliseconds) in the order of display corresponding to the stop order→“00”→display corresponding to the number of game media to be given, the manager of the game hall or confuse the player. On the other hand, the processing configuration is such that the stop order type counter 74m is cleared to "0" in a state in which the number of awarded game media corresponding to the minor win achieved this time is set in the awarded number counter 74e. It is possible to smoothly switch the display content on the display unit 66 from the stop order correspondence display to the given number display.

Next, the manner in which the ratio display and the given number display are performed on the combined display unit 66 will be described with reference to the time chart of FIG. 30 . FIG. 30(a) shows the execution period of the ratio display in the dual-use display unit 66, FIG. 30(b) shows the execution period of the given number display in the dual-use display unit 66, and FIG. FIG. 30(d) shows the timing at which the ratio display start operation is performed, and FIG. 30(e) shows the ratio display. FIG. 30(f) shows the timing at which the port output process (FIG. 28) is executed.

At the timing of t1, which is the state in which the game is not being executed and the combined display unit 66 is displaying the awarded number based on the value of the awarded number counter 74e, the ratio shown in FIG. When the display start operation is performed, as shown in FIG. 30(c), a calculation is performed to calculate the stay ratio of the second section SC2, and the ratio display counter 74n is calculated to be one of "0" to "100". Result data is set. After that, at timing t2, the port output process is executed as shown in FIG. to the ratio display.

After that, as shown in FIG. 30(e), when the ratio display end operation is performed at the timing t3, the ratio display counter 74n is set to the initial value "255" as shown in FIG. 30(c). . Thereafter, at timing t4, port output processing is executed as shown in FIG. Switch to display number of grants.

As already explained, when the game is not being executed, the combined display unit 66 displays the ratio on the condition that the ratio display counter 74n is set to any calculation result data of "0" to "100". is executed, and the given number is displayed on the combined display section 66 on condition that the ratio display counter 74n is set to the initial value "255". For this reason, in a state where the game is not being executed and the awarded number is being displayed on the combined display unit 66, any calculation result data of "0" to "100" is displayed in the ratio display counter 74n. By setting, it is possible to switch the display content on the dual-use display unit 66 from display of the given number to display of the ratio. In addition, while the ratio display is being performed on the dual-use display unit 66, by setting the ratio display counter 74n to the initial value "255", the display content on the dual-use display unit 66 is changed from the ratio display to the given number display. You can switch. This makes it possible to simplify the processing configuration for switching the display content on the combined display unit 66 from the given number display to the ratio display and the processing configuration for switching from the ratio display to the given number display.

As described above, the main MPU 72 grasps that it is the execution period of the display corresponding to the stop order on the combined display unit 66 based on the value of the stop order type counter 74m being any one of "1" to "9". At the same time, based on the fact that the stop order type numbers "1" to "9" are not set in the stop order type counter 74m, it is understood that it is not the execution period of the stop order correspondence display. The slot machine 10 has a configuration in which, during execution of the game, display corresponding to the stop order based on the value of the stop order type counter 74m or display of the awarded number based on the value of the awarded number counter 74e is executed on the combined display unit 66. A flag that enables the main side MPU 72 to grasp that the unit 66 should execute the stop order display and the state that the given number display should be executed is defective. For this reason, compared to the configuration having the flag, the dual-use display unit 66 can display a state in which the display corresponding to the stop order and a state in which the awarded number is displayed are executed during the execution of the game. The data capacity of the main RAM 74 can be reduced.

In a game in which display corresponding to the stop order on the dual-use display unit 66 and notification of the stop order on the image display device 63 are executed, any one of "1" to "9" won in the winning lottery process (FIG. 18) is displayed. The index value IV is stored in the index value counter 74f, and the index value IV of any one of "1" to "9" stored in the index value counter 74f is directly used as the stop order type number and stored in the stop order type counter 74m. is set to For this reason, compared to the configuration in which the data of the stop order type number set in the stop order type counter 74m is different from the data of the index value IV that was won in the winning lottery process (FIG. 18), The processing configuration for setting the stop order type number in the order type counter 74m is simplified.

In the winning determination process (FIG. 26), when a minor winning combination is established, the timing at which the processing in step S1205 for setting the award number corresponding to the minor winning combination in the award number counter 74e is executed is the stop order type counter 74m. is cleared to "0" before the timing at which the processing of step S1208 is executed. When the stop order type counter 74m is cleared to "0" while the stop order correspondence display is being performed on the dual use display unit 66, the display content of the dual use display unit 66 is switched from the stop order correspondence display to the given number display. If the processing configuration is such that the stop order type counter 74m is cleared to "0" before setting the number of grants corresponding to the small win achieved this time to the number counter 74e of grants, the stop order corresponding display on the combined display unit 66 is finished. There is a risk that "0" will be displayed between the start and the start of display of the award number corresponding to the small winning combination established this time. When the display contents on the dual-purpose display unit 66 are switched twice in a short time (for example, about 3 milliseconds) in the order of display corresponding to the stop order→“00”→display corresponding to the number of game media to be given, the manager of the game hall or confuse the player. On the other hand, the processing configuration is such that the stop order type counter 74m is cleared to "0" in a state in which the number of awarded game media corresponding to the minor win achieved this time is set in the awarded number counter 74e. It is possible to smoothly switch the display content on the display unit 66 from the stop order correspondence display to the given number display.

In a state in which the game is being executed and the combined display unit 66 is displaying the awarded number based on the value of the awarded number counter 74e, any one of "1" to "9" is displayed on the stop order type counter 74m. By performing the process of setting the stop order type number (the process of step S1105 in the lottery result correspondence process (FIG. 25)), the display content on the dual-use display unit 66 can be switched from the display of the given number to the display corresponding to the stop order. can. For this reason, in addition to the process of setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m, as a separate process from this process, the display content on the combined display unit 66 is given. Compared to the configuration in which the processing for switching from the display of the assigned number based on the value of the number counter 74e to the display corresponding to the stop order is set, the stop order type counter 74m can display any one of "1" to "9" in the stop order. It is possible to simplify the processing configuration for setting the type number and switching the display content on the dual-purpose display unit 66 from display of the assigned number to display corresponding to the stop order.

A process of clearing the value of the stop order type counter 74m to "0" in a state where the game is being executed and the stop order display is being executed on the combined display unit 66 (in the prize determination process (FIG. 26) By performing the process of step S1208), the display content on the combined display unit 66 can be switched from the display corresponding to the order of stop to the display of the given number based on the value of the given number counter 74e. Therefore, in addition to the process of clearing the value of the stop order type counter 74m to "0", as a separate process from this process, the display content on the combined display unit 66 is changed from the display corresponding to the stop order to the value of the given number counter 74e. The value of the stop order type counter 74m is cleared to "0" and the display content on the dual-use display unit 66 is changed from the display corresponding to the stop order to the display of the number of grants, compared with the configuration in which the processing for switching to the display of the number of grants based on is set. The processing configuration for switching to can be simplified.

The main MPU 72 recognizes that it is the execution period of the ratio display on the dual-purpose display unit 66 based on the calculation result data of any one of "0" to "100" being set in the ratio display counter 74n. , it is determined that it is not the execution period of the ratio display based on the fact that the calculation result data of "0" to "100" is not set in the ratio display counter 74n. In a configuration in which the ratio display based on the value of the ratio display counter 74n or the award number display based on the value of the award number counter 74e is performed on the dual-use display unit 66 during a period in which the game is not being executed, the slot machine 10 can be used for dual-purpose display. A flag that enables the main side MPU 72 to grasp that the unit 66 should execute the ratio display and the state that the given number display should be executed is defective. For this reason, compared to the configuration having the flag, a state in which the ratio display is performed and a state in which the awarded number is displayed on the dual-purpose display unit 66 during a period in which the game is not performed are generated. Therefore, the data capacity of the main RAM 74 can be reduced.

While the game is not being executed and the combined display unit 66 is displaying the awarded number based on the value of the awarded number counter 74e, any one of "0" to "100" is displayed on the ratio display counter 74n. (processing of step S1305 in the management process (FIG. 27)) for setting the calculation result data in (1), the display content on the dual-use display unit 66 can be switched from the display of the given number to the display of the ratio. For this reason, in addition to the process of storing the calculation result data in the ratio display counter 74n, as a separate process from this process, the display content on the combined display unit 66 is changed from the given number display to the ratio display based on the value of the given number counter 74e. Compared to the configuration in which the processing for switching to is set, the processing configuration for storing the calculation result data in the ratio display counter 74n and switching the display content on the dual-use display unit 66 from the given number display to the ratio display is simplified. can be

A process of setting the ratio display counter 74n to the initial value "255" (management process (FIG. 27) )), the display content on the combined display unit 66 can be switched from the ratio display to the given number display based on the value of the given number counter 74e. For this reason, in addition to the process of setting the initial value to the ratio display counter 74n, as a separate process, a process for switching the display content on the combined display unit 66 from the ratio display to the given number display is set. Compared to the configuration, the processing configuration for setting the initial value to the ratio display counter 74n and switching the display content on the dual-purpose display unit 66 from the ratio display to the given number display can be simplified.

The calculation result data of the stay ratio of the second section SC2 is set in the ratio display counter 74n when the ratio display start operation is performed while the game is not being executed. Even in a state where the ratio display is not executed on the dual-purpose display unit 66, the calculation for calculating the stay ratio of the second section SC2 is performed, and the calculation result data is stored in the main side RAM 74. As a result, the ratio In addition to the display counter 74n, it is necessary to provide the main RAM 74 with a counter for storing the calculation result data. On the other hand, since the calculation result data is set to the ratio display counter 74n only during the period in which the ratio display is executed on the dual-purpose display unit 66, the calculation result data can be stored on the main side. The data capacity of the storage area provided in the RAM 74 can be reduced.

A period during which one of the stop order classification numbers "1" to "9" is set in the stop order classification counter 74m, and one of calculation result data "0" to "100" is set in the ratio display counter 74n. It is a period that does not overlap with the period that is specified. For this reason, the condition for executing the stop order corresponding display and the condition for executing the ratio display on the combined display unit 66 are not satisfied at the same time. This eliminates the need for a flag that enables the main MPU 72 to grasp that the dual-use display unit 66 is in a state in which the stop order correspondence display should be executed and the state in which the ratio display should be executed. Compared to the configuration provided, it is possible to reduce the data capacity of the main side RAM 74 for generating the state in which the display corresponding to the stop order and the state in which the ratio display is performed on the combined display unit 66. can.

Next, prior to the description of the game end response process (FIG. 32) executed by the main MPU 72, the game section area 76 and the game state area 77 (see FIG. 14) provided in the main RAM 74 will be described. . 31(a) is an explanatory diagram for explaining the data structure of the game section area 76, and FIG. 31(b) is an explanatory diagram for explaining the data structure of the game state area 77. FIG. The data of the game section area 76 and the game state area 77 are set to the command at the start and the command at the end. The details of the start time command and the end time command will be described later.

As shown in FIG. 31(a), the game interval area 76 is a storage area consisting of 1 byte, the 0th bit of the game interval area 76 is provided with a second interval flag 76a, is provided with a first ending flag 76b, and the second bit is provided with a second ending flag 76c. Also, the 3rd to 7th bits of the game section area 76 are unused bits. The second section flag 76a is a flag for specifying in the main side MPU 72 whether or not the game section is the second section SC2. The second section flag 76a is set to "1" when the game section shifts to the second section SC2, and the second section flag 76a is cleared to "0" when the second section SC2 ends. be. The first ending flag 76b mainly indicates that there is a high possibility that the number of times the game has been executed in the second section SC2, which is counted using a continuous game number counter 74r, will reach the upper limit number of games ("1500"). This is a flag for identification by the side MPU 72 . The second ending flag 76c specifies, by the main MPU 72, that the total number of net increases with restrictions on the number of game media measured using a total number of acquisition counter 74s, which will be described later, is highly likely to reach the upper limit number of net increases. is a flag for

As shown in FIG. 31(b), the game state area 77 is a storage area consisting of 1 byte. has a second CB state flag 77b, a second bit has a pseudo bonus state flag 77c, a third bit has an AT state flag 77d, and a fourth bit has an end preparation flag. A state flag 77e is provided, and an AT transition determination flag 77f is provided at the fifth bit. Also, the sixth and seventh bits of the gaming state area 77 are unused bits. The first CB state flag 77a is a flag that enables the main side MPU 72 to grasp that the state is the first CB state ST2, and the second CB state flag 77b enables the main side MPU 72 to grasp that the state is the second CB state ST3. The pseudo-bonus state flag 77c is a flag that enables the main side MPU 72 to grasp that the state is the pseudo-bonus state ST4, and the AT state flag 77d is a flag that allows the main side MPU 72 to grasp that the state is the AT state ST5. The termination preparation state flag 77e is a flag that enables the main side MPU 72 to grasp that the termination preparation state ST6 is reached. When the values of the first CB state flag 77a, the second CB state flag 77b, the pseudo-bonus state flag 77c, the AT state flag 77d and the termination preparation state flag 77e are "0", the main side MPU 72 is in the normal game state ST1. grasp something. The AT shift determination flag 77f is a flag for the main MPU 72 to specify whether or not the conditions for shifting to the AT state ST5 have already been satisfied in the pseudo-bonus state ST4.

Next, referring to the flowchart of FIG. 32, the processing for dealing with the end of the game, which is executed in step S410 of the normal processing (FIG. 13), will be described. In addition, since the process of step S410 in the normal process (FIG. 13) is executed after the reel control process (step S408), the corresponding process at the end of the game is to stop the rotation of all the reels 32L, 32M, and 32R in one game. will be executed after

In the corresponding processing at the end of the game, first, CB processing for performing transition control to the first CB state ST2, progress control of the first CB state ST2, transition control to the second CB state ST3, and progress control of the second CB state ST3 is performed. Execute (step S1501). The CB processing will be described later in detail. After that, on the condition that neither the first CB state ST2 nor the second CB state ST3 (step S1502: NO), jump to the program address where the CALL instruction for calling the process corresponding to the current gaming state is set (step S1503). Specifically, when the game state is the normal game state ST1, the program jumps to the program address where the CALL instruction for calling the normal process (step S1504) is set, and the normal process (step S1504) to run. When the gaming state is the pseudo-bonus state ST4, jump to the program address where the CALL instruction for calling the pseudo-bonus processing (step S1505) is set, and execute the pseudo-bonus processing (step S1505). . When the gaming state is the AT state ST5, the program jumps to the program address where the CALL instruction for calling the AT process (step S1506) is set, and the AT process (step S1506) is executed. Details of the processing in steps S1504 to S1506 will be described later.

If an affirmative determination is made in step S1502, the process proceeds to step S1507. In addition, when the normal processing called in step S1504, the pseudo-bonus processing called in step S1505, or the AT processing called in step S1506 is ended, and the corresponding processing at the end of the game (FIG. 32) is returned to. Also, the process proceeds to step S1507. With step S1507, the 2nd control processing of the game section is executed. The details of the second control process (step S1507) of the game section will be described later.

Thereafter, the end command flag provided in the main RAM 74 is set to "1" (step S1508). The termination command flag is a flag that allows the main side MPU 72 to grasp that a termination command should be transmitted to the effect side MPU 92 . By setting "1" to the command flag at the end in step S1508, the common command transmission process (FIG. 50) is executed in step S2709 of the command output process (FIG. 44) described later. In the common command transmission process (FIG. 50), the process for transmitting the end command is executed based on the fact that the start command flag in the main RAM 74 is not set to "1". Details of the termination command will be described later.

After that, the value of the bet number setting counter 74b of the main RAM 74 is cleared to "0" (step S1509), and the game running flag of the main RAM 74 is cleared to "0" (step S1510). After that, 1 is added to the value of the total number of games counter in the main RAM 74 (step S1511), and the corresponding processing at the end of the game ends. As already explained, the total number-of-games counter is a counter for counting the number of games completed regardless of the game state and game interval. As already explained, the total number of games counter is a counter referred to in the ratio calculation process in step S1304 of the management process (FIG. 27). By updating the total number of games counter in step S1511, when the ratio display is started on the combined display unit 66, the display contents of the ratio display can be made accurate.

When the current gaming state is the first CB state ST2 or the second CB state ST3, the affirmative determination is made in step S1502, and the normal processing in step S1504, the pseudo-bonus processing in step S1505, and the AT in step S1506 Do not perform processing for Therefore, in the case of the first CB state ST2 or the second CB state ST3, the processing for advancing the normal game state ST1, the processing for advancing the pseudo-bonus state ST4, and the processing for advancing the AT state ST5 are executed. not. On the other hand, even if the current game state is the first CB state ST2 or the second CB state ST3, the processing of steps S1507 to S1511 is executed. Therefore, even in the case of the first CB state ST2 or the second CB state ST3, the processing for advancing the second section SC2 is executed, and the processing for transmitting the end command to the effect-side MPU 92 is executed. executed.

FIG. 33 is a flow chart showing the CB processing executed by the main MPU 72. As shown in FIG. Incidentally, the CB process is executed at step S1501 in the corresponding process at the end of the game (FIG. 32). As already explained, the corresponding processing at the end of the game (FIG. 32) is executed after all the reels 32L, 32M, 32R have stopped rotating in one game, so the processing for CB is also performed in one game. is executed after all rotations of are stopped.

In the CB process, first, by determining whether or not "1" is set to either the first CB state flag 77a or the second CB state flag 77b provided in the game state area 77 of the main side RAM 74, the current state is either the first CB state ST2 or the second CB state ST3 (step S1601). As already explained, the first CB state flag 77a is a flag for specifying whether or not the game state is the first CB state ST2 in the main side MPU 72, and the second CB state flag 77b is a flag for specifying whether the game state is the second CB state ST3. It is a flag for specifying in the main side MPU 72 whether or not.

If a negative determination is made in step S1601, it is determined whether or not the first CB winning has been established in this game (step S1602). That is, it is determined whether or not the combination of symbols corresponding to the first CB winning has stopped on the main line ML while the first CB winning data is stored in the first CB winning data area 74j of the main side RAM74. When the first CB winning has been established (step S1602: YES), the first CB state flag 77a in the game state area 77 of the main side RAM 74 is set to "1" (step S1603). As a result, the gaming state becomes the first CB state ST2. In the first CB state ST2, as already explained, the processing of steps S701 to S703 in the betting state management processing (FIG. 17(a)) is executed, so that only in the situation where "3" game media are betted The game will be executed.

After that, the first CB winning data stored in the first CB winning data area 74j in the main RAM 74 is cleared (step S1604), and this CB processing ends. As already explained, the data in the game state area 77 is set to the end command transmitted to the effect side MPU 92 . The effect-side MPU 92 grasps whether or not the transition to the first CB state ST2 has occurred based on the data of the first CB state flag 77a included in the data of the game state area 77 set in the received end command. .

If a negative determination is made in step S1602, it is determined whether or not the second CB winning has been established in this game (step S1605). That is, it is determined whether or not the combination of symbols corresponding to the second CB winning has stopped on the main line ML while the second CB winning data is stored in the second CB winning data area 74k of the main side RAM 74.例文帳に追加When the second CB winning has been established (step S1605: YES), the second CB state flag 77b in the game state area 77 of the main side RAM 74 is set to "1" (step S1606). As a result, the gaming state becomes the second CB state ST3. In the second CB state ST3, steps S603 and S609 in the bet handling process (FIG. 16) and steps S703 and S704 in the bet state management process (FIG. 17A) are executed as described above. , "2" are betted, the game is executed.

After that, the second CB winning data stored in the second CB winning data area 74k of the main RAM 74 is cleared (step S1607), and this CB processing ends. As already explained, the data in the game state area 77 is set to the end command transmitted to the effect side MPU 92 . The effect-side MPU 92 grasps whether or not the transition to the second CB state ST3 has occurred based on the data of the second CB state flag 77b included in the data of the game state area 77 set in the received end command. .

If an affirmative determination is made in step S1601, it is determined whether or not the first bell winning has been established in the current game (step S1608). When the first bell winning has been established (step S1608: YES), 1 is added to the value of the total grant counter provided in the main side RAM 74 (step S1609). The total given counter is a counter for specifying the total number of game media given in the first CB state ST2 or the second CB state ST3 by the main side MPU 72, and the first CB state ST2 or the second CB state ST3 is started. Cleared to "0" when

When the value of the total grant counter after adding 1 becomes "30" which is the end reference number of the first CB state ST2 and the second CB state ST3 (step S1610: YES), the CBs corresponding to the current CB states ST2 and ST3 The state flags 77a and 77b are cleared to "0" (step S1611), and this CB process is terminated. As already explained, the data in the game state area 77 is set to the end command transmitted to the effect side MPU 92 . The effect-side MPU 92 terminates the CB states ST2 and ST3 based on the data of the first CB state flag 77a and the second CB state flag 77b included in the data of the game state area 77 set in the received end command. grasp whether or not it has been done.

<Regarding the second section SC2>
Next, the second section SC2 will be explained. First, the first control process of the game section executed by the main MPU 72 will be described with reference to the flowchart of FIG. The first control process of the game section is executed in step S913, which is a process executed after completion of the win/loss determination of the win in the win lottery process (FIG. 18).

In the first control process for the game section, first, it is determined whether or not the second section flag 76a in the game section area 76 of the main RAM 74 is set to "1" (step S1701). As already explained, the second section flag 76a is a flag for specifying in the main side MPU 72 whether or not the game section is the second section SC2. If "1" is set in the second interval flag 76a (step S1701: YES), the processing after step S1702 is not executed. As a result, in the case of the second section SC2, the direct hit lottery process in step S1706 and the unlocked game number lottery process in step S1710 are not executed.

If the second interval flag 76a is not set to "1" (step S1701: NO), it is determined whether the current gaming state is the first CB state ST2 or the second CB state ST3 (step S1702). As already explained, the main side MPU 72 can grasp that it is the first CB state ST2 when the first CB state flag 77a of the gaming state area 77 is set to "1", and the second CB state flag 77b. is set to "1", it can be grasped that the state is the second CB state ST3. If the current gaming state is the first CB state ST2 or the second CB state ST3 (step S1702: YES), the processing after step S1703 is not executed. As a result, even if it is the first section SC1, if it is the first CB state ST2 or the second CB state ST3, the process for setting the second section SC2 in step S1705, the direct hit lottery process in step S1706, and the step S1710 , the number-of-release-games lottery process is not executed.

When the current gaming state is neither the first CB state ST2 nor the second CB state ST3 (step S1702: NO), it is determined whether or not the value of the bet number setting counter 74b of the main side RAM 74 is "3". Then, it is determined whether or not the number of bets for the current game is "3" (step S1703). If the number of bets for this game is "2" (step S1703: NO), the processing after step S1704 is not executed. As a result, in the game in which the number of bets is "2" even in the first section SC1, the process for setting the second section SC2 in step S1705, the direct lottery process in step S1706, and the cancellation game in step S1710. The number lottery process will not be executed.

If the number of bets for the current game is "3" (step S1703: YES), it is determined whether or not any index value IV has been won in the lottery process (FIG. 18) for the current combination (step S1704). ). In step S1704, an affirmative determination is made when the index value IV of any one of "1" to "17" is set in the index value counter 74f of the main RAM 74. FIG. If the lottery process (FIG. 18) for this combination is lost (step S1704: NO), the processes after step S1705 are not executed. As a result, even if it is the first section SC1, if it is lost in the winning lottery process (FIG. 18), the process for setting it to the second section SC2 in step S1705 and the direct hit lottery process in step S1706 Also, the number-of-release-games lottery process in step S1710 is not executed.

If any index value IV is won in the lottery process (FIG. 18) for the current combination (step S1704: YES), the second section flag 76a in the game section area 76 of the main side RAM 74 is set to "1". Then, the continued game number counter 74r (see FIG. 14) and the total winning number counter 74s (see FIG. 14) provided in the main RAM 74 are cleared to "0" (step S1705). The second section SC2 is set by setting "1" to the second section flag 76a.

The number-of-continued-games counter 74r is used to specify the number of times games have been executed since the start of the second section SC2 when the second section SC2 continues without intervening the first section SC1. is a counter of When the value of the continuous game number counter 74r reaches a value corresponding to the upper limit number of games (specifically, 1500 games) in the second section SC2, even in the middle of the pseudo-bonus state ST4 or the AT state ST5, In the reached game, the second section SC2 ends, and the state shifts to the first section SC1 and the normal game state ST1. The continuous game number counter 74r consists of 2 bytes.

The total acquisition number counter 74s informs the main side MPU 72 of the restricted total net increase number of game media from the start of the second section SC2 when the second section SC2 is continued without intervening the first section SC1. It is a counter for specifying As already explained, the restricted total net increase in the number of game media refers to the “total number of game media awarded by the game executed while the second section SC2 continues (the total number of game media awarded "0" when the game is not running)" to "the total number of game media consumed for executing the game while the second section SC2 is continuing ("0" when the game is not running) is the predetermined difference number of sheets, the minimum value of the predetermined difference number of sheets is set as a predetermined reference value, and the number of sheets increases by the predetermined difference number of sheets from the predetermined reference value. When the value of the total acquisition number counter 74s reaches the value corresponding to the upper limit net increase number (specifically, 2400 cards) in the second section SC2, even in the middle of the pseudo-bonus state ST4 or AT state ST5, In the reached game, the second section SC2 ends, and the state shifts to the first section SC1 and the normal game state ST1. The total acquisition number counter 74s consists of 2 bytes.

After that, direct hit lottery processing is executed (step S1706). In the direct hit lottery process, a direct hit lottery table provided in the main side ROM 73 and a lottery counter periodically updated in the main side RAM 74 are used to determine by lottery whether or not to win a direct hit in the pseudo-bonus state ST4. do. In the winning lottery process (Fig. 18) of the winning combination in the current game, if the player wins with the index value IV=11, there is a 2% chance that the pseudo-bonus state ST4 will be won directly, and the player will win the index value IV=12. If the index value IV=13, the pseudo-bonus state ST4 will be won directly with a probability of 10%, and the index value IV=13. If 14 is won, the pseudo-bonus state ST4 is won directly with a probability of 5%, and if the index value IV=15 is won, the pseudo-bonus state ST4 is won directly with a probability of 2%. . In this case, the lower the probability of winning in the winning lottery process (FIG. 18), the higher the probability of winning a direct hit in the pseudo-bonus state ST4. As a result, it is possible to increase the advantage of winning an index value IV with a low winning probability in the combination lottery process (FIG. 18).

If the direct hit lottery process results in a direct hit win in the pseudo bonus state ST4 (step S1707: YES), the first transition confirmation flag provided in the main side RAM 74 is set to "1" (step S1708). The first transition confirmation flag is for the main side MPU 72 to specify that the transition to the pseudo-bonus state ST4 was won in the direct hit lottery process (step S1706) executed when transitioning to the second section SC2. is a flag. When the first transition confirmation flag is set to "1", a process is executed to shift the game state to the pseudo-bonus state ST4 when the current game ends.

After that, lighting processing of the section display section 67 is executed (step S1709). In the lighting process of the section display section 67, the section display section 67 is switched from the off state to the on state. As a result, the section display unit 67 starts to notify that it is the second section SC2.

If the direct hit lottery process does not result in a direct hit win in the pseudo-bonus state ST4 (step S1707: NO), the unlocked game number lottery process is executed by calling a subroutine program for unlocked game number lottery process by a CALL command. (Step S1710). The number of unlocked games is the number of games required until the shift to the pseudo-bonus state ST4 occurs in the case where the transition to the pseudo-bonus state ST4 is not won in the transition lottery process (step S2112) described later. In step S1710, when the program of the subroutine called the number-of-release-games lottery process is called by the CALL command, the information of the return address for returning to the process of step S1711, which is the process following step S1710, is stored in the main RAM 74. Stored in the stack area. In the unlocked game number lottery process in step S1710, the unlocked game number lottery table 73c (see FIG. 24(c)) stored in the main ROM 73 is referred to.

Before explaining the unlocked game number lottery process (FIG. 35(b)) in step S1710, the unlocked game number lottery table 73c will be described. FIG. 35(a) is an explanatory diagram for explaining the contents of the unlocked game number lottery table 73c. As shown in FIG. 35(a), the unlocked game number lottery table 73c is set with four kinds of unlocked game numbers, 50 games, 200 games, 400 games, and 600 games, to be judged as winners or losers. In the release game number lottery process, one of these four types of release game numbers is always won. The probability of selecting 50 games as the number of unlocked games, the probability of selecting 200 games as the number of unlocked games, the probability of selecting 400 games as the number of unlocked games, and the probability of selecting 600 games as the number of unlocked games are: 1/4 each.

Next, the unlocked game number lottery process executed by the main MPU 72 will be described with reference to the flowchart of FIG. 35(b). As already explained, the number-of-release-games lottery process is executed in step S1710 of the first control process (FIG. 34) for the game section. The number-of-release-games lottery process is also executed in step S2506 of the AT process (FIG. 42), which will be described later.

In the number-of-released-games lottery process, first, the number-of-released-games lottery table 73c (see FIG. 24C) stored in the main ROM 73 is set as a lottery table to be referenced in the number-of-released-games lottery process (step S1801). After that, lottery execution processing is executed in steps S1802 to S1807. The lottery execution process is also executed when a negative determination is made in step S2603 of the process for addition at start (FIG. 43(c)), which will be described later, or when the process of step S2604 is performed. Here, a case will be described where the lottery execution process (steps S1802 to S1807) is executed in a state in which the unlocked game number lottery table 73c is set as the lottery table to be referenced in step S1801.

In the lottery execution process (steps S1802 to S1807), first, 1-byte lottery numerical information is obtained from the lottery counter that is periodically updated in the main RAM 74, and the obtained lottery numerical information is stored in the main RAM 74. is set in the random number setting counter (step S1802). The lottery numerical information is numerical information indicating any integer from "0" to "255", and the random number setting counter is a counter to which the lottery numerical information is set.

After that, "4" is set in the determination target counter provided in the main RAM 74 (step S1803). The determination target counter is a counter that allows the main MPU 72 to grasp the current number of games to be determined among a plurality of numbers of games to be determined that are set in the lottery table to be referenced (release game number lottery table 73c). is. The determination target counter consists of 1 byte. In the number-of-released-games lottery process, when the value of the determination counter is "4", the number of unlocked games is "50", and when the value of the determination counter is "3", the number of unlocked games is "200". The number of games is the determination target, and when the value of the determination target counter is "2", the number of released games of "400" is the determination target. If the number of unlocked games of "50", "200" and "400" is not won, the number of unlocked games of "600" is won.

After that, the determination value set in the lottery table to be referred to (number-of-release-games lottery table 73c) is added to the value of the random-number setting counter (step S1804). As shown in FIG. 35(a), "64" is set as the determination value in the unlocked game number lottery table 73c, and "64" is added to the value of the random number setting counter in step S1804.

Thereafter, it is determined whether or not the value of the random number setting counter after adding the determination value ("64") in step S1804 exceeds "255" (step S1805), and the value of the random number setting counter exceeds "255". If not exceeded (step S1805: NO), the value of the determination target counter is subtracted by 1 (step S1806). The processing of steps S1804 to S1807 is repeatedly executed until an affirmative determination is made in step S1805 or step S1807. The number of unlocked games to be determined is updated in the order of 50 games→200 games→400 games each time the value of the determination target counter is decremented by 1 in step S1806.

Thereafter, it is determined whether or not the value of the determination target counter after subtracting 1 in step S1806 is "1" (step S1807). If a negative determination is made in step S1807, the process proceeds to step S1804. Then, the processing of steps S1804 to S1807 is repeatedly executed until an affirmative determination is made in step S1805 or step S1807.

When an affirmative determination is made in step S1805 or step S1807, the cancellation game number lottery process called as a subroutine process is ended by executing the command "RET". As already explained, the number-of-release-games lottery process is called at step S1710 of the first control process (FIG. 34) of the game section. For this reason, when the lottery process for the number of games to be unlocked is completed, based on the return address information stored in the stack area of the main RAM 74, step S1710 in the first control process (FIG. 34) for the relevant game section The process returns to the next step S1711. If the number of unlocked games is "50", the process returns to step S1711 with the value of the determination target counter being "4", and if the number of unlocked games is "200", the determination target counter is "3", the process returns to step S1711, and if the number of unlocked games of "400" is won, the process returns to step S1711 with the value of the determination target counter being "2". If the number of unlocked games is "600", the process returns to step S1711 with the value of the determination target counter being "1".

Returning to the description of the first control process (FIG. 34) of the game section, after the unlocked game number lottery process is executed in step S1710, the unlocked game number counter setting process is executed (step S1711). As already explained, the number-of-released-games counter is the number of games required to transition to the pseudo-bonus state ST4 in a situation where none of the first to third transition confirmation flags of the main RAM 74 is set to "1". is a counter for the main MPU 72 to specify the number of remaining unlocked games. In the process of setting the unlocked game number counter, the unlocked game number lottery table 73c (FIG. 35(a)) is referred to, and the unlocked game number corresponding to the value of the determination target counter is set in the unlocked game number counter of the main RAM 74. FIG. Specifically, when the value of the determination target counter is "4", the unlocked game number counter is set to "50", and when the value of the determination target counter is "3", the unlocked game number counter is set to "200". " is set to "400" in the unlocked game number counter when the value of the judgment target counter is "2", and "600" is set in the unlocked game number counter when the value of the judgment target counter is "1". ” is set. After that, the value of the determination target counter is cleared to "0" (step S1712).

After that, the lighting processing of the section display section 67 is executed (step S1713), and the first control processing of this game section is ended. In the lighting processing of the section display section 67 in step S1713, the section display section 67 is switched from the off state to the on state. As a result, the section display unit 67 starts to notify that it is the second section SC2.

Next, the second control process of the game section executed by the main MPU 72 will be described with reference to the flowchart of FIG. The second control process of the game section is executed in step S1507 in the corresponding process (FIG. 32) at the end of the game. As described above, the corresponding processing at the end of the game is executed after all the reels 32L, 32M, 32R have stopped rotating in one game. is executed after all

In the second control process of the game section, when "1" is set to the second section flag 76a in the game section area 76 of the main RAM 74 and the current game section is the second section SC2 (step S1901: YES) By confirming the state of the end preparation state flag 77e in the game state area 77 of the main RAM 74, it is determined whether or not the current game state is the end preparation state ST6 (step S1902). The end preparation state ST6 is a case where the pseudo-bonus state ST4 ends without satisfying the ending condition of the second section SC2 described later, and a case where the second section SC2 ends at the time of transition to the normal game state ST1 thereafter. It is a game state that shifts to .

If it is in the termination preparation state ST6 (step S1902: YES), it is determined whether or not the termination preparation completion flag provided in the main RAM 74 is set to "1" (step S1903). The termination preparation completion flag is a flag for the main side MPU 72 to specify whether or not one game has been executed in the termination preparation state ST6. In the pseudo-bonus processing (step S1505) in the corresponding processing at the end of the game (FIG. 32), the number of remaining games to be continued in the pseudo-bonus state ST4 is 0, and the second interval is set when the subsequent transition to the normal game state ST1 is performed. When it is specified that the SC2 is to be terminated, the termination preparation state flag 77e is set to "1" and the termination preparation completion flag is cleared to "0". In addition, in the AT process (step S1506) in the corresponding process at the end of the game (FIG. 32), the number of remaining continuous games in the AT state ST5 is 0 games, and the second section is performed when the subsequent transition to the normal game state ST1 is performed. When it is specified that the SC2 is to be terminated, the termination preparation state flag 77e is set to "1" and the termination preparation completion flag is cleared to "0".

If the termination preparation completion flag is not set to "1" (step S1903: NO), the termination preparation completion flag is set to "1" (step S1904), and then the processing from step S1905 is executed. If the end preparation completion flag is set to "1" (step S1903: YES), it means that one game has been executed in the end preparation state ST6. In this case, a process for ending the second section SC2 is executed.

Specifically, first, the initialization process for the second section SC2 is executed (step S1915). In the initialization process of the second section SC2, the second section flag 76a in the game section area 76 of the main RAM 74 is cleared to "0". As a result, the game section becomes the first section SC1. Further, in the initialization process of the second section SC2, even if the user stays in the pseudo-bonus state ST4, the pseudo-bonus state ST4 including the counter for storing the remaining number of continuous games in the pseudo-bonus state ST4 is maintained. By clearing various data (including the pseudo-bonus state flag 77c in the game state area 77) indicating that, the game state is shifted to the normal game state ST1. In addition, in the initialization process of the second section SC2, even if the user stays in the AT state ST5, the AT state ST5 including the counter for storing the remaining number of continuous games in the AT state ST5 is indicated. By clearing various data (including the AT state flag 77d in the game state area 77), the game state is shifted to the normal game state ST1. Also, in the initialization process of the second section SC2, the unlocked game number counter of the main side RAM 74 is cleared to "0". Therefore, even if the current game state is any one of the normal game state ST1, the first CB state ST2, and the second CB state ST3, the remaining number of unlocked games (that is, the number of ceiling games) at that time is invalidated, and after that, The number of remaining games to be unlocked is reset at the time of a new shift to the second section SC2. Note that even during the first CB state ST2 and the second CB state ST3, the initialization processing of the second section SC2 is executed and the second section SC2 ends, but the first CB state ST2 and the second CB state ST3 continues without being terminated.

After that, the section display section 67 is extinguished (step S1916). In the extinguishing process, the section display section 67 is switched from the lit state to the extinguished state. As a result, the notification of the second section SC2 on the section display section 67 is terminated.

If it is not the end preparation state ST6 (step S1902: NO), or if the process of step S1904 is executed, the value of the second section game number counter in the main RAM 74 is incremented by 1 (step S1905). As already explained, the second section game number counter is a counter that enables the main MPU 72 to grasp the total number of games that have been executed in the second section SC2. is a counter referred to in the ratio calculation process in . By updating the number-of-games-second-section counter in step S1905, when the ratio display is started on the combined display unit 66, the display contents of the ratio display can be made accurate.

After that, 1 is added to the value of the number-of-continued-games counter 74r of the main RAM 74 (step S1906). As already explained, the number-of-continued-games counter 74r informs the main MPU 72 of the number of times the game has been executed from the start of the second section SC2 when the second section SC2 continues without intervening the first section SC1. It is a counter for specifying

After that, it is determined whether or not the value of the number-of-continued-games counter 74r after adding 1 is equal to or greater than the upper limit number of games of 1500 (step S1907). If the value of the continuous game number counter 74r is 1500 or more, it means that the ending condition of the second section SC2 is met. In this case, an affirmative determination is made in step S1907, and processing for ending the second section SC2 is executed in steps S1915 and S1916. The processing contents of steps S1915 and S1916 have already been described. As a result, the second section SC2 ends and becomes the first section SC1, and when the pseudo-bonus state ST4 is in the middle, the pseudo-bonus state ST4 is forcibly ended and the normal game state ST1 is entered, and AT If it is in the middle of the state ST5, the AT state ST5 is forcibly terminated and the normal game state ST1 is entered.

If the value of the number-of-continued-games counter 74r is less than 1500 (step S1907: NO), is any of the first-chance replay wins, second-chance replay wins, and normal replay wins achieved in the current game? It is determined whether or not (step S1908). In this case, even if the number of bets in the current game is either "2" or "3", the determination in step S1908 is made, and the current game is in the normal game state ST1, the first CB state ST2, and the second CB. Any gaming state of the state ST3, the pseudo-bonus state ST4 and the AT state ST5 is subject to the determination in step S1908.

If none of the replay winnings have been established (step S1908: NO), the number of bets for this game (that is, the value of the bet number setting counter 74b) is subtracted from the total winning number counter 74s of the main RAM 74 (step S1909). . In this case, even if a replay win was established in the previous game, and the current game is a game corresponding to a replay due to the establishment of the replay win, the number of bets for this game (that is, the bet number setting counter 74b value) is subtracted from the total win counter 74s.

As already explained, the total acquisition number counter 74s counts the total net increase in number of game media with restrictions from the start of the second section SC2 when the second section SC2 continues without intervening the first section SC1. This is a counter for identification by the main MPU 72 . As already explained, the restricted total net increase in the number of game media refers to the “total number of game media awarded by the game executed while the second section SC2 continues (the total number of game media awarded "0" when the game is not running)" to "the total number of game media consumed for executing the game while the second section SC2 is continuing ("0" when the game is not running) is the predetermined difference number of sheets, the minimum value of the predetermined difference number of sheets is set as a predetermined reference value, and the number of sheets increases by the predetermined difference number of sheets from the predetermined reference value.

After that, in this game, any small role winning prize (1st to 9th supplementary prize, 1st bell prize, 2nd bell prize, 1st watermelon prize, 2nd watermelon prize and cherry prize) ) is established (step S1910). In this case, regardless of whether the number of bets in the current game is "2" or "3", the determination in step S1910 is made, and the current game is in the normal game state ST1, the first CB state ST2, and the second CB. Any gaming state of the state ST3, the pseudo-bonus state ST4 and the AT state ST5 is subject to the determination in step S1910. When an affirmative determination is made in step S1910, the number of game media provided in the current game is added to the total acquisition number counter 74s of the main RAM 74 (step S1911).

When a negative determination is made in step S1910, or when the process of step S1911 is executed, it is determined whether or not the value of the total acquisition number counter 74s of the main side RAM 74 is 0 or more (step S1912). When the value of the total acquisition number counter 74s is less than 0 (step S1912: NO), the total acquisition number counter 74s is cleared to "0" (step S1913).

As described above, in step S1909, the number of bets for the current number of games is subtracted from the total winning number counter 74s. Therefore, for example, in the game in the normal game state ST1 immediately after the transition to the second section SC2, any small win is established. Otherwise, the value of the total win counter 74s will be less than zero. In this case, by making a negative determination in step S1912, the total acquisition number counter 74s is cleared to "0" in step S1913. As a result, "the total number of game media awarded by the game executed while the second section SC2 is continuing ("0" in the situation where no game medium is awarded)" to "the second section When the value obtained by subtracting the total number of game media consumed to execute the game while SC2 is being continued (“0” when the game is not being executed) is set as the predetermined difference number, Using the minimum value of the predetermined difference number as a predetermined reference value, the total net increase number with limitation of game media, which is the increase of the predetermined difference number from the predetermined reference value, is measured using a total acquisition number counter 74s. becomes possible.

If an affirmative determination is made in step S1908, if an affirmative determination is made in step S1912, or if the process of step S1913 is executed, does the value of the total acquisition number counter 74s exceed the upper limit net increase number "2400"? It is determined whether or not (step S1914). If the value of the total acquisition number counter 74s exceeds "2400", it means that the ending condition of the second section SC2 has been met. In this case, an affirmative determination is made in step S1914, and processing for ending the second interval SC2 is executed in steps S1915 and S1916. The processing contents of steps S1915 and S1916 have already been described. As a result, the second section SC2 ends and becomes the first section SC1, and when the pseudo-bonus state ST4 is in the middle, the pseudo-bonus state ST4 is forcibly ended and the normal game state ST1 is entered, and AT If it is in the middle of the state ST5, the AT state ST5 is forcibly terminated and the normal game state ST1 is entered.

Here, if any of the replay prizes are established, affirmative determination is made in step S1908, and the processing of steps S1909 to S1913 is not executed. In a game in which a replay winning prize is established, the game media owned by the player at the start of the game is used for setting bets, but as a profit from the replay winning establishment, the same number of bets as in the game in which the replay winning prize was established A new game can be played again with the number of bets. In other words, the number of game media owned by the player does not change in the game in which the replay winning has been established. In this case, by not executing the processing of steps S1909 to S1913 in a game in which a replay winning has been established, in a game in which the number of game media owned by the player does not change, the value of the total winning number counter 74s is increased. It is possible to omit the execution of processing for changing , and it is possible to omit the execution of useless processing.

On the other hand, even in a game in which a replay win has been established, it is determined in step S1914 whether or not the value of the total winning number counter 74s exceeds the upper limit net increase number of "2400". As a result, even though the value of the total acquisition number counter 74s had already exceeded the upper limit net increase number of "2400" in the game prior to the game in which the replay winning was established, the second Even if the initialization process of the section SC2 is not executed, it is specified that the value of the total acquisition number counter 74s exceeds "2400" which is the upper limit net increase number in the game in which the subsequent replay winning has been established. , and the initialization process of the second section SC2 can be executed.

When a negative determination is made in step S1914, ending correspondence processing is executed (step S1917), and the second control processing of this game section is terminated. FIG. 37 is a flow chart showing the ending handling process in step S1917.

In the ending correspondence process, first, it is determined whether or not the first ending flag 76b provided in the game section area 76 of the main RAM 74 is set to "1" (step S2001). As already explained, the first ending flag 76b indicates to the main MPU 72 that the number of times the game is executed in the second section SC2, which is counted using the number-of-continued-games counter 74r, is highly likely to reach the upper limit number of games. This is a flag for specifying

If the first ending flag 76b is not set to "1" (step S2001: NO), the value of the continuous game number counter 74r of the main RAM 74 and the pseudo bonus continuous counter 74t provided in the main RAM 74 (Fig. 14 ) and the value of the AT continuation counter 74u (see FIG. 14) provided in the main RAM 74 is equal to or greater than the upper limit number of games in the second section SC2 (step S2002). . The pseudo-bonus continuation counter 74t is a counter for the main MPU 72 to specify the remaining number of continuous games in the pseudo-bonus state ST4. The pseudo bonus continuation counter 74t consists of 1 byte. The AT continuation counter 74u is a counter for the main side MPU 72 to specify the number of remaining continuation games in the AT state ST5. The AT continuation counter 74u consists of 2 bytes. The upper limit number of games in the second section SC2 is set to 1500 games as already explained. The upper limit number of games in the second section SC2 is not limited to 1,500 games, and may be less than 1,500 games or more than 1,500 games.

If an affirmative determination is made in step S2002, the first ending flag 76b is set to "1" (step S2003). When "1" is set in the first ending flag 76b, the conditions for shifting to the AT state ST5 are not satisfied in the pseudo-bonus state ST4, and the number of remaining games remaining in the AT state ST5 will be described later. In the case where the addition does not occur and the pseudo-bonus state ST4 or the AT state ST5 ends and shifts to the normal game state ST1, the second section SC2 surely ends and shifts to the first section SC1. . As a result, in a situation where the ending condition of the second section SC2 is satisfied, it is possible to prevent the transition condition to the AT state ST5 from being satisfied, and the rest of the continuation game in the AT state ST5. It is possible to prevent the further addition of the number from occurring. The situation in which the first ending flag 76b is set to "1" basically occurs in the pseudo-bonus state ST4 or the AT state ST5, but it can also occur in the first CB state ST2 or the second CB state ST3. Further, even if the first ending flag 76b is set to "1" in the first CB state ST2, the second CB state ST3, or the pseudo-bonus state ST4, the game contents are not changed and the performance mode is not changed. .

When a positive determination is made in step S2001, when a negative determination is made in step S2002, or when the process of step S2003 is executed, the second ending flag 76c provided in the game section area 76 of the main side RAM 74 is set to "1 is set (step S2004). As already explained, the second ending flag 76c indicates that there is a high possibility that the total number of net increases with restrictions on the number of game media measured using the total number counter 74s will reach the upper limit net increase number. It is a flag for specifying in .

When "1" is not set to the second ending flag 76c (step S2004: NO), the sum of the value of the pseudo-bonus continuation counter 74t and the value of the AT continuation counter 74u is added to the game in the pseudo-bonus state ST4 and the AT state ST5. It is determined whether or not the result obtained by adding the value obtained by accumulating the acquisition expected value of the medium to the value of the total acquisition number counter 74s is equal to or greater than the upper limit net increase number of the second section SC2 (step S2005). The expected acquisition value of game media in one game in the pseudo-bonus state ST4 and the AT state ST5 is about five. The upper limit net increase number of sheets in the second section SC2 is set to 2400 sheets as already explained. Note that the upper limit net increase number of sheets in the second section SC2 is not limited to 2400 sheets, and may be less than 2400 sheets or more than 2400 sheets.

If an affirmative determination is made in step S2005, the second ending flag 76c is set to "1" (step S2006). When the second ending flag 76c is set to "1", the conditions for shifting to the AT state ST5 are not satisfied in the pseudo-bonus state ST4, and the number of remaining games remaining in the AT state ST5 will be described later. In the case where the addition does not occur and the pseudo-bonus state ST4 or the AT state ST5 ends and shifts to the normal game state ST1, the second section SC2 surely ends and shifts to the first section SC1. . As a result, in a situation where the ending condition of the second section SC2 is satisfied, it is possible to prevent the transition condition to the AT state ST5 from being satisfied, and the rest of the continuation game in the AT state ST5. It is possible to prevent the further addition of the number from occurring. The second ending flag 76c is set to "1" in the pseudo-bonus state ST4 or AT state ST5, but not in the normal game state ST1, first CB state ST2 or second CB state ST3. Further, even if the second ending flag 76c is set to "1" in the pseudo-bonus state ST4, the game contents are not changed, and the effect execution mode is not changed.

<Regarding normal game state ST1>
Next, the processing contents in the normal game state ST1 will be explained. FIG. 38 is a flow chart showing advantageous lottery processing at the start of the game, which is executed by the main MPU 72 . The advantageous lottery process at the start of the game is a step that is executed after the winning judgment is completed in the winning lottery process (FIG. 18) and before the first control process (step S913) of the game section. It is executed in S912.

In the advantageous lottery process at the start of the game, first, it is determined whether or not the second section flag 76a in the game section area 76 of the main RAM 74 is set to "1" (step S2101). If the second section flag 76a is not set to "1" (step S2101: NO), the processing after step S2102 is not executed. As a result, when it is the first section SC1, the processing for shifting the gaming state to the pseudo-bonus state ST4 after step S2106 is not executed.

If the second interval flag 76a is set to "1" (step S2101: YES), if the current gaming state is a pseudo-bonus state ST4 or AT state ST5 (step S2102: YES), an advantage at the start of the game State processing is executed (step S2103). Advantageous state processing at the start of the game will be described later.

When "1" is set to the second interval flag 76a (step S2101: YES), and the gaming state is neither the pseudo-bonus state ST4 nor the AT state ST5 (step S2102: NO), the current It is determined whether or not the gaming state is the first CB state ST2 or the second CB state ST3 (step S2104). As already explained, the main side MPU 72 grasps that it is the first CB state ST2 when the first CB state flag 77a in the gaming state area 77 is set to "1", and sets the second CB state flag 77b to " 1” is set, it is grasped that it is in the second CB state ST3. If the current gaming state is the first CB state ST2 or the second CB state ST3 (step S2104: YES), the processing after step S2105 is not executed. As a result, even if it is the second section SC2, if it is the first CB state ST2 or the second CB state ST3, the processing for shifting the gaming state to the pseudo-bonus state ST4 after step S2106 is not executed. .

When the current gaming state is neither the first CB state ST2 nor the second CB state ST3 (step S2104: NO), it is determined whether or not the value of the bet number setting counter 74b of the main side RAM 74 is "3". Then, it is determined whether or not the number of bets for the current game is "3" (step S2105). If the number of bets for the current game is "2" (step S2105: NO), the processing after step S2106 is not executed. As a result, in the game in which the number of bets is "2" even in the second section SC2, the processing for shifting the gaming state to the pseudo-bonus state ST4 after step S2106 is not executed.

If the number of bets for the current game is "3" (step S2105: YES), it is determined whether or not the value of the continuous game number counter 74r is equal to or greater than the reference number of games (step S2106), and the total winning number counter It is determined whether or not the value of 74s is greater than or equal to the reference acquisition number (step S2107). As already explained, the number-of-continued-games counter 74r informs the main MPU 72 of the number of times the game has been executed from the start of the second section SC2 when the second section SC2 continues without intervening the first section SC1. It is a counter for specifying When the value of the continuous game number counter 74r reaches a value corresponding to the upper limit number of games (specifically, 1500 games) in the second section SC2, the reached game is played even during the pseudo-bonus state ST4. , the second section SC2 ends, and the first section SC1 enters the normal game state ST1. In addition, as already explained, the total acquisition number counter 74s indicates the restricted total net increase of game media from the start of the second section SC2 when the second section SC2 continues without intervening the first section SC1. It is a counter for specifying the number of sheets by the main MPU 72 . As already explained, the restricted total net increase in the number of game media refers to the “total number of game media awarded by the game executed while the second section SC2 continues (the total number of game media awarded "0" when the game is not running)" to "the total number of game media consumed for executing the game while the second section SC2 is continuing ("0" when the game is not running) is the predetermined difference number of sheets, the minimum value of the predetermined difference number of sheets is set as a predetermined reference value, and the number of sheets increases by the predetermined difference number of sheets from the predetermined reference value. When the value of the total win counter 74s reaches the value corresponding to the upper limit net increase number (specifically, 2400 cards) in the second section SC2, the game reached even during the pseudo-bonus state ST4. , the second section SC2 ends, and the first section SC1 enters the normal game state ST1.

The reference number of games is set to be less than the upper limit of 1500 games in the second section SC2, specifically 1450 games. The reference acquisition number is set as a number smaller than 2400, which is the upper limit of net increase in the second section SC2, specifically 2150.

If the value of the continuous game number counter 74r is equal to or greater than the reference number of games (step S2106: YES), or if the value of the total win number counter 74s is equal to or greater than the reference number of wins (step S2107: YES), "1" is set to the received third transition confirmation flag (step S2108). The third transition confirmation flag indicates that the upper limit number of games in the second section SC2 is greater than or equal to the reference number of games, or that the restricted total net increase in the number of game media in the second section SC2 is greater than or equal to the standard acquisition number. This is a flag for specifying in the main side MPU 72 whether or not the transition to the pseudo-bonus state ST4 is confirmed.

When the third transition determination flag is set to "1", a process is executed to transition the game state to the pseudo-bonus state ST4 when the current game ends. That is, in the normal game state ST1, when the pre-end period, which is a period in which the fulfillment of the ending condition of the second section SC2 is near, the pseudo-bonus state ST4 is forced. As a result, it is possible to provide the benefit of generating the pseudo-bonus state ST4 for reaching the pre-end period in the normal game state ST1. 50 games are set as the number of continuous games at the start of the pseudo-bonus state ST4, which is started when the third transition determination flag is set to "1". The number of continuous games set at the start is the number of games that is the difference between 1500 games, which is the upper limit number of games in the second section SC2, and 1450 games, which is the reference number of games. In addition, since the expected acquisition value of game media in one game in the pseudo-bonus state ST4 is about 5 as already explained, the product of the number of continuous games set at the start and the expected acquisition value is the second interval. The difference between 2400, which is the upper limit net increase number of SC2, and 2150, which is the standard acquisition number, is the same or substantially the same.

After executing the process of step S2108, various clear processes are executed (step S2109). In various clearing processes, the values of the second transition confirmation flag and the transition standby counter provided in the main RAM 74 are cleared to "0". The second transition confirmation flag is a flag that is set to "1" when the transition is won in the transition lottery process (step S2112) described later, and the second transition confirmation flag is set to "1" in the transition standby counter. This is a counter for the main MPU 72 to specify that the number of transition standby games (specifically, 5 games) has been completed. In the transition lottery process (step S2112), the transition lottery process (step S2112) not only sets the second transition confirmation flag to "1" but also sets a value corresponding to the number of transition standby games in the transition standby counter, thereby causing the second transition. The value of the transition waiting counter is decremented by 1 each time one game is completed in a situation where the determination flag is set to "1". Then, when the value of the transition standby counter becomes "0" in a situation where "1" is set to the second transition confirmation flag, the game state shifts to the pseudo-bonus state ST4. Therefore, after the transition lottery process (step S2112) wins the transition, the number of transition standby games is consumed, and the transition to the pseudo-bonus state ST4 occurs. In this case, when the third transition confirmation flag is set to "1" as described above, even if the second transition confirmation flag is set to "1" at that time, the second transition confirmation flag is "0" is cleared. As a result, the pseudo-bonus state ST4 triggered by setting the third transition confirmation flag to "1" is changed to the pseudo-bonus state triggered by the second transition confirmation flag being set to "1". It becomes possible to give priority to the occurrence of ST4.

When the value of the continuous game number counter 74r is less than the reference number of games and the value of the total win number counter 74s is less than the reference win number (steps S2106 and S2107: NO), the second transition determination flag of the main RAM 74 Under the condition that "1" is not set (step S2110: NO), it is determined whether or not any of the index values IV=11 to 15 has been won in the lottery process (FIG. 18) for the current combination. (Step S2111). When an affirmative determination is made in step S2111, shift lottery processing is executed (step S2112). In the transition lottery process, a transition lottery table provided in the main ROM 73 and a lottery counter periodically updated in the main RAM 74 are used to determine by lottery whether to transition to the pseudo-bonus state ST4. In the winning lottery process (FIG. 18) of the role in this game, if the index value IV=11 is won, there is a 20% chance that the pseudo-bonus state ST4 will be won, and the index value IV=12 will be won. If the index value IV=13, the transition to the pseudo-bonus state ST4 is won with a probability of 40%, and the index value IV=13. If 14 is won, transition to the pseudo-bonus state ST4 is won with a 30% probability, and if index value IV=15 is won, the transition to the pseudo-bonus state ST4 is won with a 20% probability. . In this case, an index value IV with a lower probability of winning in the winning lottery process (FIG. 18) has a higher probability of winning a transition to the pseudo-bonus state ST4. As a result, it is possible to increase the advantage of winning an index value IV with a low winning probability in the combination lottery process (FIG. 18).

When the pseudo-bonus state ST4 is won in the transition lottery process (step S2113: YES), bonus type determination processing for determining the type of the pseudo-bonus state ST4 is executed in steps S2114 and S2115. A big bonus with a relatively high degree of advantage and a regular bonus with a relatively low degree of advantage are set in the pseudo-bonus state ST4. The big bonus is a pseudo-bonus state ST4 that continues until games with a bet number of "3" are played 50 times, and the regular bonus is a pseudo-bonus that continues until games with a bet number of "3" are played 20 times. This is state ST4. The number of games described above is arbitrary as long as the big bonus is relatively more advantageous than the regular bonus. In addition, if the big bonus is relatively more advantageous than the regular bonus, the number of games to be continued is the same for both bonuses, but the expected value of acquiring game media in one game is higher than the regular bonus. , the big bonus is relatively more advantageous than the regular bonus.

In the bonus type determination process, first, a bonus type lottery process is executed (step S2114). In the bonus type lottery process, a type lottery table provided in the main-side ROM 73 and a lottery counter periodically updated in the main-side RAM 74 are used to determine the type of the pseudo-bonus state ST4 that has been won this time as a big bonus. and regular bonus. The type lottery table is set so that the selection probability of the big bonus and the regular bonus is 50% regardless of the result of the lottery process (Fig. 18) for this role, but it is not limited to this. Alternatively, the big bonus may have a higher selection probability than the regular bonus, or the regular bonus may have a higher selection probability than the big bonus, and the result of the lottery process (Fig. 18) for this role. The selection ratio of the big bonus and the regular bonus may vary depending on.

After that, big winning flag setting processing is executed (step S2115). In the big win flag setting process, if the big bonus is selected in the bonus type lottery process in step S2114, the big win flag provided in the main side RAM 74 is set to "1". The big winning flag is a flag for specifying in the main side MPU 72 that the big bonus has been selected in the bonus type lottery process. In the big win flag setting process, the big win flag in the main RAM 74 is cleared to "0" when the regular bonus is selected in the bonus type lottery process in step S2114.

After that, the second transition confirmation flag provided in the main RAM 74 is set to "1" (step S2116), and the transition standby game number (specifically, 5 games) is set in the transition standby counter provided in the main RAM 74. is set (step S2117), and the advantageous lottery process at the start of the game ends. The second transition confirmation flag is a flag for the main MPU 72 to specify whether or not the transition has been won in the transition lottery process (step S2112). This is a counter for the main MPU 72 to specify that the number of transition standby games (specifically, 5 games) has been completed after being set. In the transition lottery process (step S2112), the transition lottery process (step S2112) not only sets the second transition confirmation flag to "1" but also sets a value corresponding to the number of transition standby games in the transition standby counter, thereby causing the second transition. The value of the transition waiting counter is decremented by 1 each time one game is completed in a situation where the determination flag is set to "1". Then, when the value of the transition standby counter becomes "0" in a situation where "1" is set to the second transition confirmation flag, the game state shifts to the pseudo-bonus state ST4. Therefore, after the transition lottery process (step S2112) wins the transition, the number of transition standby games is consumed, and the transition to the pseudo-bonus state ST4 occurs.

Next, normal processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. The normal process is executed at step S1504 in the corresponding process at the end of the game (FIG. 32). As described above, the corresponding processing at the end of the game is executed after all the reels 32L, 32M, 32R have stopped rotating in one game, so the normal processing also stops all the reels 32L, 32M, 32R from rotating in one game. executed later.

When the second section flag 76a of the game section area 76 of the main RAM 74 is set to "1" and the current game section is the second section SC2 (step S2201: YES), the first transition of the main RAM 74 is confirmed. It is determined whether or not the flag is set to "1" (step S2202). At the start of the current game, when the transition to the second section SC2 has occurred and the direct hit lottery process (step S1706) executed at the time of determining the transition is a direct hit winning, the first transition confirmation flag is set to "1".

If "1" is set in the first transition determination flag (step S2202: YES), the first start setting process is executed (step S2203). In the first start setting process, the pseudo bonus state flag 77c in the game state area 77 of the main side RAM 74 is set to "1". The pseudo-bonus state flag 77c is a flag for specifying in the main side MPU 72 whether or not the gaming state is the pseudo-bonus state ST4. In the first start setting process, a value corresponding to 50 games, which is the number of continuation games of the big bonus, is set as the initial number of continuation games in the quasi-bonus state ST4 in the pseudo-bonus continuation counter 74t in the main RAM 74 . That is, in a configuration in which a big bonus and a regular bonus having relatively high and low degrees of advantage are set as the pseudo-bonus state ST4, the pseudo-bonus state ST4 is entered by winning a direct hit in the direct lottery process (step S1706). In the case of shifting, it will shift to the big bonus. As already explained, the pseudo-bonus continuation counter 74t is a counter for the main side MPU 72 to specify the remaining number of continuous games in the pseudo-bonus state ST4.

If the first transition confirmation flag is not set to "1" (step S2202: NO), it is determined whether or not the third transition confirmation flag of the main RAM 74 is set to "1" (step S2204). As already explained, the third transition confirmation flag is set when the number of continuous games in the second section SC2 is equal to or greater than the reference number of games, or when the total net increase in number of game media with limitation in the second section SC2 is equal to or greater than the reference acquisition number. This is a flag for specifying in the main side MPU 72 whether or not the transition to the pseudo-bonus state ST4 is confirmed due to the fact that

If "1" is set to the third transition determination flag (step S2204: YES), the second start setting process is executed (step S2205). In the second start setting process, the pseudo bonus state flag 77c in the game state area 77 of the main side RAM 74 is set to "1". In the second start setting process, the pseudo-bonus continuation counter 74t of the main RAM 74 is set to a value corresponding to 50 games, which is the number of continuation games of the big bonus, as the initial number of continuation games in the quasi-bonus state ST4. That is, in a configuration in which a big bonus and a regular bonus having relatively high and low degrees of advantage are set as the pseudo-bonus state ST4, the number of continuous games in the second section SC2 is equal to or greater than the reference number of games. In the case of shifting to the pseudo-bonus state ST4 due to the fact that the limited total net increase number of game media in the 2-segment SC2 is equal to or greater than the reference acquisition number, the state shifts to the big bonus.

If "1" is not set to the third transition confirmation flag (step S2204: NO), by referring to the first CB state flag 77a and the second CB state flag 77b, the current game state is the first CB state ST2 or the second It is determined whether or not it is in the 2CB state ST3 (step S2206). If the current gaming state is the first CB state ST2 or the second CB state ST3 (step S2206: YES), the processing after step S2207 is not executed. In the processing after step S2207, the number of games required for shifting to the pseudo-bonus state ST4 is subtracted as one game is completed, and the conditions for shifting to the pseudo-bonus state ST4 are established as the game is completed. If so, a process for shifting to the pseudo-bonus state ST4 is executed. In this case, if the state is the first CB state ST2 or the second CB state ST3, by not executing the processing after step S2207, even if the game is completed in the first CB state ST2 or the second CB state ST3, it is simulated. It is possible to avoid causing the transition to the bonus state ST4 to become closer.

When the current gaming state is neither the first CB state ST2 nor the second CB state ST3 (step S2206: NO), it is determined whether or not the value of the bet number setting counter 74b of the main side RAM 74 is "3". Then, it is determined whether or not the number of bets for this game is "3" (step S2207). If the number of bets for the current game is "2" (step S2207: NO), the processes after step S2208 are not executed. As already explained, in the processing from step S2208 onward, the number of games required for transitioning to the pseudo-bonus state ST4 is subtracted as one game is completed, and the transition to the pseudo-bonus state ST4 is performed as the game is completed. When the condition is established, the process for shifting to the pseudo-bonus state ST4 is executed. In this case, if the game with the bet number of "2" is executed, the process from step S2208 onwards is not executed, so that even if the game with the bet number of "2" is completed, it will be a pseudo game. It is possible to avoid causing the transition to the bonus state ST4 to become closer.

If the number of bets for the current game is "3" (step S2207: YES), it is determined whether or not the second transition determination flag of the main RAM 74 is set to "1" (step S2208). As already explained, the second transition determination flag is a flag for the main MPU 72 to specify whether or not the transition lottery process (step S2112) has won the transition lottery.

If "1" is set to the second transition confirmation flag (step S2208: YES), the value of the transition standby counter in the main RAM 74 is subtracted by 1 (step S2209). As already explained, the transition standby counter is a counter for the main MPU 72 to specify that the number of transition standby games (specifically, 5 games) has been completed after the second transition confirmation flag is set to "1". is. If the value of the transition standby counter after decrementing by 1 is "0" (step S2210: YES), the third start setting process is executed in steps S2213 to S2217. Although the details will be described later, in the third start setting process, a process for shifting to the pseudo-bonus state ST4 is executed.

If "1" is not set to the second transition confirmation flag (step S2208: NO), the value of the canceled game number counter in the main RAM 74 is subtracted by 1 (step S2211). The number-of-released-games counter is the number of games required to transition to the pseudo-bonus state ST4 in a situation where none of the first to third transition confirmation flags of the main RAM 74 is set to "1", and the remaining number of unlocked games. A counter for specifying the number of games in the main MPU 72 . When the game section shifts from the first section SC1 to the second section SC2 and the direct hit lottery process (step S1706) does not result in direct hit winning, the number of released games is set to the counter for the number of released games, and AT. Also when the second section SC2 is maintained after the state ST5 ends, the number of unlocked games is set to the counter for the number of unlocked games.

If the value of the canceled game number counter after subtracting 1 is "0" (step S2212: YES), the third start setting process is executed in steps S2213 to S2217. Although the details will be described later, in the third start setting process, a process for shifting to the pseudo-bonus state ST4 is executed.

In the third start setting process in steps S2213 to S2217, first, the pseudo bonus state flag 77c in the game state area 77 of the main RAM 74 is set to "1" (step S2213). After that, it is determined whether or not the big win flag of the main RAM 74 is set to "1", or whether or not the value of the unlocked game number counter of the main RAM 74 is "0" (step S2214). As already explained, in the case where the transfer lottery process (step S2112) is won, the big bonus is selected in the bonus type lottery process (advantageous lottery process at the start of the game (FIG. 38), step S2114). "1" is set to the big winning flag. As already explained, the unlocked game number counter is a counter for counting the number of unlocked games in the main MPU 72. When the value of the unlocked game number counter is "0", the number of unlocked games is "0". This means that an opportunity to shift to the pseudo-bonus state ST4 has occurred.

When an affirmative determination is made in step S2214, "50" is set in the pseudo bonus continuation counter 74t of the main side RAM 74 (step S2215). As a result, the pseudo-bonus state ST4 occurring this time becomes a big bonus. After that, regardless of whether or not the big winning flag of the main RAM 74 is set to "1", the big winning flag is cleared to "0" (step S2216), and the normal processing ends. On the other hand, if a negative determination is made in step S2214, "20" is set in the pseudo-bonus continuation counter 74t of the main RAM 74 (step S2217), and this normal processing ends. By setting "20" to the pseudo-bonus continuation counter 74t in step S2217, the pseudo-bonus state ST4 occurring this time becomes a regular bonus.

<Regarding Advantageous Playing State>
Next, the details of processing in the pseudo-bonus state ST4 and AT state ST5 will be described. FIG. 40 is a flow chart showing the advantageous state processing at the start of the game, which is executed by the main MPU 72 . As already explained, the advantageous lottery process at the start of the game is executed after the win/loss determination is completed in the lottery process (FIG. 18) and before the first control process (step S913) of the game section. It is executed in step S912, which is a process. Then, the advantageous state processing at the start of the game is executed at step S2103 in the advantageous lottery processing at the start of the game (FIG. 38).

In the advantageous state processing at the start of the game, first, it is determined whether or not the value of the bet number setting counter 74b of the main side RAM 74 is "3". It is determined whether or not (step S2301). If the number of bets for the current game is "2" (step S2301: NO), the processing after step S2302 is not executed. As a result, even if the player is in the pseudo-bonus state ST4 or the AT state ST5, in the game in which the number of bets is "2", the processes after step S2302 are not executed.

If the number of bets in the current game is "3" (step S2301: YES), the current gaming state is the first CB state ST2 or the second CB state by referring to the first CB state flag 77a and the second CB state flag 77b. It is determined whether or not it is ST3 (step S2302). If the current gaming state is the first CB state ST2 or the second CB state ST3 (step S2302: YES), the processing after step S2303 is not executed. As a result, even if the pseudo-bonus state flag 77c or the AT state flag 77d of the main RAM 74 is set to "1", if the state is the first CB state ST2 or the second CB state ST3, the No processing will be performed.

If the current gaming state is not the first CB state ST2 or the second CB state ST3 (step S2302: NO), either the first ending flag 76b or the second ending flag 76c in the game section area 76 of the main side RAM 74 is set to "1". is set (step S2303). As already explained, the first ending flag 76b is set by the main MPU 72 to specify that the number of times the game has been executed in the second section SC2, which is counted using the continuous game number counter 74r, reaches the upper limit number of games. flag. As already explained, the second ending flag 76c indicates to the main MPU 72 that the total number of net increases with restrictions on the number of game media measured using the total number counter 74s is likely to reach the upper limit number of net increases. This is a flag for specifying If "1" is set to either the first ending flag 76b or the second ending flag 76c (step S2303: YES), the processes after step S2304 are not executed. As a result, in a situation where the number of games executed in the second section SC2 reaches the upper limit number of games, or in a situation where there is a high possibility that the total number of net increases with restrictions on the number of game media will reach the upper limit net increase, step S2304 to step The processing for determining whether to shift to AT state ST5 in S2309 and the processing for adding the number of continuous games in AT state ST5 in steps S2310 to S2313 are not executed.

When neither the first ending flag 76b nor the second ending flag 76c is set to "1" (step S2303: NO), the pseudo bonus state flag 77c in the game state area 77 of the main side RAM 74 is set to "1". is set, it is determined whether or not the current gaming state is the pseudo-bonus state ST4 (step S2304). If the current gaming state is the pseudo-bonus state ST4 (step S2304: YES), it is determined whether or not the AT transition confirmation flag 77f provided in the gaming state area 77 of the main side RAM 74 is set to "1". (Step S2305). As already explained, the AT shift determination flag 77f is a flag for the main MPU 72 to specify whether or not the conditions for shifting to the AT state ST5 have already been satisfied in the pseudo-bonus state ST4. If the AT transition determination flag 77f has already been set to "1" (step S2305: YES), that is, if the conditions for transition to the AT state ST5 have already been met in the current pseudo-bonus state ST4, step S2306 After that, the process for determining whether or not to shift to the AT state ST5 is not executed.

If "1" is not set in the AT transition determination flag 77f (step S2305: NO), any one of the index values IV=11 to 15 is won in the winning lottery process (FIG. 18) in this game. On condition that there is (step S2306: YES), AT shift lottery processing is executed (step S2307). In the AT shift lottery process, the AT shift lottery table provided in the main ROM 73 and the lottery counter periodically updated in the main RAM 74 are used to shift to the AT state ST5 after the current pseudo-bonus state ST4 ends. A lottery will decide whether or not to allow it. In the lottery process (Fig. 18) of the role in this game, if the index value IV = 11 is won, there is a 20% probability that the AT transition will be won, and if the index value IV = 12 is won, has a probability of 10% to win the AT transition, and if you win the index value IV = 13, you will win the AT transition with a probability of 40%, and if you win the index value IV = 14, you will have a 30% chance. AT shift wins with a probability, and when the index value IV=15 is won, AT shift wins with a probability of 20%. In this case, an index value IV with a lower probability of winning in the winning lottery process (FIG. 18) has a higher probability of winning an AT transition. As a result, it is possible to increase the advantage of winning an index value IV with a low winning probability in the combination lottery process (FIG. 18). After that, when the AT shift is won (step S2308: YES), the AT shift determination flag 77f is set to "1" (step S2309).

As already explained, the advantageous state processing (FIG. 40) at the start of the game is the pseudo-bonus state ST4 or the AT state ST5 in the advantageous lottery processing (FIG. 38) at the start of the game (step S2102: YES). (step S2103). If the current gaming state is not the pseudo-bonus state ST4 (step S2304: NO), that is, if the current gaming state is the AT state ST5, a CALL command is used to call the program for executing the start-up addition processing. , the process for addition at the start is executed (step S2310). When the program for executing the additional processing at the start is called by the CALL instruction in step S2310, the return address information for returning to the processing of step S2311 following the step S2310 is stored in the stack area of the main RAM 74. be done. Steps S2310 to S2313 are processes for adding the number of continuous games in the AT state ST5. Details of the processing of steps S2310 to S2313 will be described later.

Next, the pseudo-bonus processing executed by the main MPU 72 will be described with reference to the flow chart of FIG. The pseudo-bonus processing is executed at step S1505 in the corresponding processing at the end of the game (FIG. 32). As described above, the corresponding processing at the end of the game is executed after all the reels 32L, 32M, and 32R have stopped rotating in one game, so the pseudo-bonus processing also stops all the reels 32L, 32M, and 32R from rotating in one game. is executed after

In the pseudo-bonus processing, first, it is determined whether or not the value of the bet number setting counter 74b of the main side RAM 74 is "3", thereby determining whether or not the bet number of the current game is "3". (step S2401). If the number of bets for the current game is "2" (step S2401: NO), the processing after step S2402 is not executed. As a result, even if a game with a bet number of "2" is executed in the pseudo-bonus state ST4, the remaining number of continuous games in the pseudo-bonus state ST4 is not subtracted.

In the case of the CB state (the first CB state ST2 or the second CB state ST3), the pseudo-bonus processing (FIG. 41) itself is not executed. The number of games played in the state is not treated as the number of games played in the pseudo-bonus state ST4. Therefore, even if the transition to the CB state occurs in the middle of the pseudo-bonus state ST4, the pseudo-bonus state ST4 is restarted from the state of the remaining number of continuous games immediately before the transition to the CB state after the CB state ends. .

When the number of bets for the current game is "3" (step S2401: YES), the value of the pseudo bonus continuation counter 74t of the main side RAM 74 is subtracted by 1 (step S2402). Thereafter, it is determined whether or not the value of the pseudo bonus continuation counter 74t is "0" (step S2403). When the value of the pseudo-bonus continuation counter 74t is "0" (step S2403: YES), it is determined whether or not "1" is set to the AT transition confirmation flag 77f in the game state area 77 of the main side RAM74. (step S2404).

If the AT transition determination flag 77f is set to "1" (step S2404: YES), it means that the conditions for transition to the AT state ST5 have been met in the current pseudo-bonus state ST4. In this case, first, the pseudo-bonus state flag 77c of the main RAM 74 is cleared to "0" (step S2405). After that, the AT state counter provided in the main side RAM 74 is set with information corresponding to "50", which is the number of initial continuous games of the AT state ST5 (step S2406), and the AT state flag in the game state area 77 of the main side RAM 74 is set. 77d is set to "1" (step S2407), and this pseudo bonus process is terminated.

If the AT transition determination flag 77f is not set to "1" (step S2404: NO), the processing for setting the end preparation state ST6 is executed (step S2408). In the setting process, the pseudo-bonus state flag 77c in the game state area 77 of the main RAM 74 is cleared to "0". Further, in the setting process, the end preparation state flag 77e provided in the game state area 77 of the main side RAM 74 is set to "1". As already explained, the end preparation state flag 77e is a flag for specifying the end preparation state ST6 in the main side MPU 72, and the game state is changed by setting "1" to the end preparation state flag 77e. It becomes end preparation state ST6. After that, the termination preparation completion flag of the main RAM 74 is cleared to "0" (step S2409), and this pseudo bonus process is terminated. As already described, the end preparation completion flag is a flag for the main side MPU 72 to specify whether or not one game has been executed in the end preparation state ST6.

As already described in the end preparation state ST6, if the affirmative determination is made in step S1902 in the second control process (FIG. 36) of the game section, and the end preparation completion flag is not set to "1" (step S1903: NO), after setting the end preparation completion flag to "1", the process for specifying whether or not the ending condition of the second section SC2 is satisfied is executed, and the second control process of the game section in the current game ( FIG. 36) is ended. On the other hand, if the end preparation completion flag is set to "1" (step S1903: YES), a process for ending the second section SC2 and shifting to the first section SC1 is executed (steps S1915 to S1916). ). As a result, the second section SC2 ends when the game following the game in which the pseudo-bonus state ST4 has ended ends.

Next, the AT processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. The process for AT is executed in step S1506 in the corresponding process (FIG. 32) at the end of the game. As already explained, since the corresponding processing at the end of the game is executed after all the reels 32L, 32M, 32R have stopped rotating in one game, the AT processing is also performed after all the reels 32L, 32M, 32R have rotated in one game. Executed after stopping.

In the AT processing, first, it is determined whether or not the value of the bet number setting counter 74b of the main side RAM 74 is "3", thereby determining whether or not the bet number of the current game is "3". (Step S2501). If the number of bets for the current game is "2" (step S2501: NO), the processing after step S2502 is not executed. As a result, even if a game with a bet number of "2" is executed in the AT state ST5, the remaining number of continued games in the AT state ST5 is not subtracted.

Note that the AT process (FIG. 42) itself is not executed in the CB state (first CB state ST2 or second CB state ST3). The number of games played is not treated as the number of games played in AT state ST5. Therefore, even if the AT state ST5 is shifted to the CB state in the middle of the AT state ST5, the AT state ST5 is restarted from the state of the remaining number of continuous games immediately before the shift to the CB state after the end of the CB state.

If the number of bets in this game is "3" (step S2501: YES), subtract 1 from the value of the AT continuation counter 74u of the main side RAM 74 (step S2502), and the value of the AT continuation counter 74u after the subtraction of 1 is "0" (step S2503). When the value of the AT continuation counter 74u is "0" (step S2503: YES), "1" is set to either the first ending flag 76b or the second ending flag 76c in the game state area 77 of the main side RAM74. It is determined whether or not it is set (step S2504). When the values of the first ending flag 76b and the second ending flag 76c are both "0" (step S2504: NO), the AT state flag 77d in the game state area 77 of the main side RAM 74 is cleared to "0" (step S2505 ). This enables the main MPU 72 to grasp that the AT state ST5 has ended.

After that, as in step S1710 of the first control process (FIG. 34) for the game section already described, a CALL command is used to call a subroutine program for unlocked game number lottery processing, thereby executing unlocked game number lottery processing (step S2506). ). As already explained, the number of unlocked games is the number of games required until the transition to the pseudo-bonus state ST4 occurs when the transition to the pseudo-bonus state ST4 is not won in the transition lottery process (step S2112). . In step S2506, when the program of the subroutine of the number-of-release-games lottery process is called by the CALL command, the information of the return address for returning to the process of step S2507, which is the process following step S2506, is stored in the main RAM 74. Stored in the stack area. The content of the number-of-released-games lottery process has already been described with reference to the flowchart of FIG. 35(b).

As already explained, in the number-of-unlocked-games lottery process (FIG. 35(b)), when the value of the determination target counter is "4", the number of unlocked games of "50" is determined. If the number is "3", the number of released games is "200", and if the value of the determination target counter is "2", the number of released games is "400". If the number of unlocked games of "50", "200" and "400" is not won, the number of unlocked games of "600" is won. When the unlocked game number lottery process (FIG. 35(b)) called in step S2506 ends, the process of step S2506 is executed based on the return address information stored in the stack area of the main RAM 74. The process returns to step S2507, which is the next process. In the unlocked game number lottery process (Fig. 35(b)) in step S2506, when the number of unlocked games is "50", the process returns to step S2507 with the value of the determination target counter being "4". If the number of unlocked games is "200", the process returns to step S2507 with the value of the determination target counter being "3", and if the number of unlocked games is "400", the determination target The process returns to step S2507 with the value of the counter being "2", and if the number of unlocked games of "600" is won, the process of step S2507 is performed with the value of the determination target counter being "1". return.

After executing the unlock game number lottery process in step S2506, in steps S2507 and S2508, the same processes as steps S1711 and S1712 of the first control process (FIG. 34) of the game section already described are executed. Specifically, first, processing for setting the number-of-released-games counter is executed (step S2507). As already explained, the number-of-released-games counter is the number of games required to transition to the pseudo-bonus state ST4 in a situation where none of the first to third transition confirmation flags of the main RAM 74 is set to "1". is a counter for the main MPU 72 to specify the number of remaining unlocked games. In the process of setting the unlocked game number counter, the unlocked game number lottery table 73c (FIG. 35(a)) is referred to, and the unlocked game number corresponding to the value of the determination target counter is set in the unlocked game number counter of the main RAM 74. FIG. Specifically, when the value of the determination target counter is "4", the unlocked game number counter is set to "50", and when the value of the determination target counter is "3", the unlocked game number counter is set to "200". " is set to "400" in the unlocked game number counter when the value of the judgment target counter is "2", and "600" is set in the unlocked game number counter when the value of the judgment target counter is "1". ” is set. After that, the value of the determination target counter is cleared to "0" (step S2508), and this AT processing ends.

When "1" is set to either the first ending flag 76b or the second ending flag 76c in the game section area 76 of the main RAM 74 (step S2504: YES), the setting processing of the end preparation state ST6 is executed. (Step S2509). In the process of setting the end preparation state ST6, the AT state flag 77d in the game state area 77 of the main side RAM 74 is cleared to "0". Further, in the setting process of the end preparation state ST6, the end preparation state flag 77e in the game state area 77 of the main side RAM 74 is set to "1". The end preparation state flag 77e is a flag for the main side MPU 72 to specify that it is in the end preparation state ST6. Become. After that, the termination preparation completion flag of the main RAM 74 is cleared to "0" (step S2510), and this AT processing is terminated. As already described, the end preparation completion flag is a flag for the main side MPU 72 to specify whether or not one game has been executed in the end preparation state ST6.

As already explained in the end preparation state ST6, if the affirmative determination is made in step S1902 in the second control process (FIG. 36) of the game section and the end preparation completion flag is not set to "1" (step S1903: NO), after setting the end preparation completion flag to "1", the process for specifying whether or not the ending condition of the second section SC2 is met is executed, and the second control process of the game section in the current game ( FIG. 36) is terminated. On the other hand, if the end preparation completion flag is set to "1" (step S1903: YES), processing for ending the second section SC2 and shifting to the first section SC1 is executed (steps S1915 to S1916). ). As a result, the second section SC2 ends when the game following the game in which the AT state ST5 has ended ends.

Next, prior to the description of the start-up addition process executed by the main MPU 72, the first addition lottery table 73d and the second addition lottery table 73e stored in the main ROM 73 will be described. The first additional lottery table 73d and the second additional lottery table 73e are set as lottery tables to be referred to in the additional lottery. FIG. 43(a) is an explanatory diagram for explaining the contents of the first addition lottery table 73d, and FIG. 43(b) is an explanatory diagram for explaining the contents of the second addition lottery table 73e.

As shown in FIGS. 43A and 43B, the numbers of additional games of 10 games, 20 games and 50 games are set in the first additional lottery table 73d and the second additional lottery table 73e. As shown in FIG. 43(a), when the additional lottery process is executed with the first additional lottery table 73d as a reference lottery table, 10 games are selected with a probability of 1/16, and 10 games are selected with a probability of 1/16. 20 games are selected with a probability of 1/16, 50 games are selected with a probability of 13/16 of being out. As shown in FIG. 43(b), when the additional lottery process is executed with the second additional lottery table 73e as the reference lottery table, 10 games are selected with a probability of 1/8, and 10 games are selected with a probability of 1/8. There is a probability that 20 games will be selected, a 1/8 probability that 50 games will be selected, and a 5/8 probability that you will be out. In this way, the probability of winning the additional number of games of 10 games, 20 games or 50 games in the second additional lottery table 73e is the same as winning the number of additional games of 10 games, 20 games or 50 games in the first additional lottery table 73d. It is set higher than the probability that The second addition lottery table 73e is a lottery table more advantageous for the player than the first addition lottery table 73d.

Next, the processing for addition at the time of start executed by the main MPU 72 will be described with reference to the flowchart of FIG. 43(c). As already described, the start-up addition process is executed at step S2310 in the advantageous state process (FIG. 40) at the start of the game.

In the addition process at the start, it is first determined whether or not any of the index values IV=11 to 15 has been won in the winning lottery process (FIG. 18) in the current game (step S2601). In step S2601, an affirmative determination is made when the value of the index value counter 74f of the main RAM 74 is any one of "11" to "15", and the value of the index value counter 74f is "0" to "10". A negative determination is made when the value is any one of "16" to "17". If a negative determination is made in step S2601, the process for adding a lottery at the start is terminated without executing the process for executing the extra lottery (processes after step S2602). The additional lottery is performed under the condition that any one of the index values IV=11 to 15 is won in the winning lottery process (FIG. 18). Since the addition process at the start (FIG. 43(c)) is a process called in step S2310 of the advantageous state process at the start of the game (FIG. 40), the addition process at the start (FIG. 43(c)) is completed, the process returns to step S2311, which is the process following step S2310. Processing after step S2311 will be described later.

If any of the index values IV = 11 to 15 is won (step S2601: YES), the processes of steps S2602 to S2604 and the number-of-release-games lottery process (Fig. 35(b) )) and steps S1802 to S1807 and steps S2311 to S2313 of the advantageous state processing (FIG. 40) at the start of the game are executed. In the addition lottery, it is determined whether or not the remaining number of continuous games in the AT state ST5 should be added. Choose from games.

Specifically, first, the first addition lottery table 73d stored in the main-side ROM 73 is set as a lottery table to be referenced in the addition lottery (step S2602). After that, it is determined whether or not the index value IV=14 or 15 is won in the lottery process (FIG. 18) of the combination in the current game (step S2603), and the index value IV=14 or 15 is won. If so (step S2603: YES), the lottery table to be referenced in the additional lottery is changed to the second additional lottery table 73e stored in the main ROM 73 (step S2604). On the other hand, in the lottery process (FIG. 18) for the winning combination in the current game, if the index value IV=11 to 13 is won (step S2603: NO), the lottery table to be referred to in the additional lottery is not changed. As already explained, the second additional lottery table 73e is a lottery table more advantageous to the player than the first additional lottery table 73d. In the winning lottery process (FIG. 18), when the first chance replay (IV=14) or the second chance replay (IV=15) is set with the index value IV, the first watermelon (IV=11 ), a lottery table (second additional lottery table 73e) that is more advantageous to the player than the case where the second watermelon (IV=12) or cherry (IV=13) is set to the index value IV is selected. .

If a negative determination is made in step S2603, or if the process of step S2604 is carried out, the program address for executing the process of step S1802 of the unlock game number lottery process (FIG. 35(b)) by a jump command. to execute lottery execution processing in steps S1802 to S1807. When jumping to the program address for executing the process of step S1802 by the jump instruction, the return address information is not stored in the stack area of the main side RAM74. Therefore, the process of step S1802 is executed in a state in which the information of the return address for returning to the process of step S2311 of the advantageous state process (FIG. 40) at the start of the game is stored in the stack area of the main RAM 74. jump to the program address for

Next, after making a negative determination in step S2603 of the start time addition processing (FIG. 43(c)), or after performing the processing of step S2604, the lottery execution processing (steps S1802 to S1807) is executed. I will explain the case where

In step S 1802 , 1-byte lottery numerical information is acquired from the lottery counter that is periodically updated in the main RAM 74 , and the acquired lottery numerical information is set in the random number setting counter in the main RAM 74 . As already explained, the lottery numerical information is numerical information indicating an integer from "0" to "255", and the random number setting counter is a counter in which the lottery numerical information is set. consists of

After that, "4" is set in the determination target counter in the main RAM 74 (step S1803). After that, the determination value set in the lottery table to be referenced (the first additional lottery table 73d or the second additional lottery table 73e) is added to the value of the random number setting counter (step S1804). As shown in FIG. 43(a), "16" is set as the determination value in the first addition lottery table 73d. When the lottery table to be referred to is the first additional lottery table 73d, in step S1804, "16" is added as the determination value to the value of the random number setting counter. As shown in FIG. 43(b), "32" is set as the determination value in the second addition lottery table 73e. When the lottery table to be referred to is the second additional lottery table 73e, in step S1804, "32" is added as the judgment value to the value of the random number setting counter.

Thereafter, it is determined whether or not the value of the random number setting counter after adding the determination value in step S1804 has exceeded "255" (step S1805). If the value of the random number setting counter does not exceed "255" (step S1805: NO), 1 is subtracted from the value of the determination target counter (step S1806). As already described, the processes of steps S1804 to S1807 are repeatedly executed until an affirmative determination is made in step S1805 or step S1807. The number of additional games to be determined is updated in the order of 10 games→20 games→50 games each time the value of the determination target counter is decremented by 1 in step S1806.

Thereafter, it is determined whether or not the value of the determination target counter after subtracting 1 in step S1806 is "1" (step S1807). If a negative determination is made in step S1807, the process advances to step S1804, and the processes of steps S1804 to S1807 are repeatedly executed until an affirmative determination is made in step S1805 or step S1807. Then, if an affirmative determination is made in step S1805 or step S1807, by executing the instruction "RET", based on the information of the return address stored in the stack area of the main RAM 74, at the start of the game 40). Specifically, the process returns to the process of step S2311, which is the process following step S2310 in which the CALL instruction for calling the additional process at start (FIG. 40) is set.

In this way, in step S2310 of the advantageous state processing (FIG. 40) at the start of the game, the additional processing at the start (FIG. 43C) is called, and the step of the AT state processing (FIG. 43C) If an affirmative determination is made in S2601, after executing the processing from step S2602 onwards, the process proceeds to step S1802 of the unlock game number lottery processing (FIG. 35(b)) without executing the command for returning from the subroutine. to jump Therefore, after an affirmative determination is made in step S1805 or step S1807 of the number-of-release-games lottery process (FIG. 35(b)), an instruction to return from the subroutine is executed, whereby the process for addition at start ( The processing returns to step S2311 following step S2310 of the advantageous state processing (FIG. 40) at the start of the game in which the CALL instruction for calling (c) of FIG. 43 is set.

If the number of games to be added is "10", the process returns to step S2311 with the value of the determination counter being "4", and if the number of games to be added is "20", the counter to be determined is "3", the process returns to step S2311, and if the number of additional games of "50" is won, the process returns to step S2311 with the value of the determination target counter being "2". On the other hand, if none of the additional game numbers is won, the process returns to step S2311 with the value of the determination target counter being "1". As already described, even if affirmative determination is made in step S2601 of the additional processing at the start (FIG. 43(c)), the process returns to step S2311 in the advantageous state processing at the start of the game (FIG. 40). However, in this case, the process returns to step S2311 while the value of the determination target counter is "0".

Here, the processing of steps S2311 to S2313 of the advantageous state processing (FIG. 40) at the start of the game will be described. In step S2311, it is determined whether or not the value of the determination target counter in the main RAM 74 is 1 or more. If the value of the determination target counter is "0" (step S2311: NO), that is, if the lottery process (FIG. 18) for the winning combination has not been won with any of the index values IV=11 to 15, Without executing the processing of steps S2312 and S2313, the advantageous state processing at the start of the game is terminated.

If the value of the determination target counter is equal to or greater than "1" (step S2311: YES), the number of continuous games is added (step S2312). In the process of adding the number of continuous games, the number of additional games corresponding to the value of the judgment target counter in the lottery table to be referred to is grasped, and the grasped number of additional games is added to the value of the AT continuation counter 74u in the main side RAM 74. . In step S2312, when the first addition lottery table 73d is selected and when the second addition lottery table 73e is selected, if the value of the determination target counter is "4", the AT continuation counter 74u "10" is added as the number of games to be added to , and if the value of the determination target counter is "3", "20" is added to the AT continuation counter 74u as the number of games to be added, and if the value of the determination target counter is "2" If there is, "50" is added to the AT continuation counter 74u as the number of additional games. On the other hand, when the value of the determination object counter is "1", that is, when the player loses in the additional lottery, the number of additional games is not added to the AT continuation counter 74u. After that, the value of the determination target counter is cleared to "0" (step S2313), and the advantageous state processing (FIG. 40) at the start of the game ends.

Next, the command output processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. Command output processing is executed in step S210 of the timer interrupt processing (FIG. 11).

In the command output process, if the power recovery command flag of the main RAM 74 is set to "1" (step S2701: YES), the power recovery command transmission process for transmitting the power recovery command to the production side MPU 92 is executed (step S2702). Data of the first CB winning data area 74j and the second CB winning data area 74k in the main side RAM 74 are set in the power recovery command. As already explained, the first CB winning data area 74j is an area for storing the first CB winning data indicating that the first CB winning combination has been won, and the second CB winning data area 74k stores the second CB winning data. This is an area for memorizing. When the first CB winning data is included in the power recovery command, the effect side MPU 92 grasps that the power recovery process has been executed in a state where the first CB winning data is stored in the main side RAM 74, When the second CB winning data is included, it is grasped that the power recovery process has been executed while the second CB winning data is stored in the main side RAM74. Further, when the power recovery command does not include the first CB winning data and the second CB winning data, the power recovery process is executed in a state where the main side RAM 74 does not contain the first CB winning data and the second CB winning data. Figure out. After that, the power recovery command flag is cleared to "0" (step S2703), and this command output processing ends.

After making a negative determination in step S2701, if the winning result command flag of the main side RAM 74 is set to "1" (step S2704: YES), the winning result command is transmitted to the effect side MPU 92. Command transmission processing is executed (step S2705). As already explained, the data stored in the first CB winning data area 74j, the second CB winning data area 74k and the winning data area 78 in the main RAM 74 are set in the winning result command. Based on the data set in the winning result command, the performance side MPU 92 grasps whether or not the winning is established this time, and also grasps the type of winning when the winning is established. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are executed so that an effect corresponding to the information grasped from the winning result command is performed. After that, the winning result command flag is cleared to "0" (step S2706), and this command output processing ends.

After making a negative determination in step S2704, if the start command flag of the main RAM 74 is set to "1" (step S2707: YES), or if the end command flag of the main RAM 74 is set to "1" If set (step S2707: NO, step S2708: YES), common command transmission processing is executed (step S2709), and this command output processing ends. In the common command transmission process in step S2709, when the start command flag is set to "1", the start command is transmitted to the effect side MPU 92, and when the end command is set to "1". If there is, a process of transmitting an end command to the effect side MPU 92 is performed.

In the command output process (FIG. 44), when the power recovery command flag is set to "1", the state of the other command flags (starting command flag, winning result command flag, and ending command flag) is Power restoration command transmission processing (step S2702) is executed regardless.

In each game, the period from when the start command flag is set to "1" to when the winning result command flag is set to "1" is the acceleration period of the reels 32L, 32M, and 32R (specifically, about 300 milliseconds). Also, the acceleration period of the reels 32L, 32M, 32R is a period longer than the interrupt period (1.49 milliseconds) of the timer interrupt process (FIG. 11). Therefore, in each game, the start command is transmitted before the winning result command.

In each game, the timing at which the end command flag is set to "1" is a timing after the timing at which the winning result command flag is set to "1". When the command output process (Fig. 44) is executed after the winning result command flag is set to "1" and before the ending command flag is set to "1", the winning result command is output from the ending command. is also sent first. In addition, when the command output process is executed with the winning result command flag and the end time command flag set to "1", the winning result command transmission process is executed and executed after about 1.49 milliseconds. The common command transmission process is executed in the next command output process. In this manner, in each game, commands are transmitted to the effect-side MPU 92 in the order of the command at the start→the command at the time of the winning result→the command at the end.

<Configuration for sending commands>
Next, a configuration for transmitting various commands from the main side MPU 72 to the effect side MPU 92 will be described.

FIG. 45 is an explanatory diagram for explaining the electrical configuration of the main control board 71 and the effect control board 91 for transmitting commands from the main side MPU 72 to the effect side MPU 92 . As already explained, the main control board 71 is provided with the transmission circuit 85 , and the effect control board 91 is provided with the reception circuit 87 . As shown in FIG. 45, the transmission circuit 85 is provided with a transmission standby buffer 112 in which commands to be transmitted to the effect side MPU 92 are set. The transmission standby buffer 112 is a ring buffer consisting of 32 bytes. Among the commands transmitted from the main side MPU 72 to the effect side MPU 92, the command with the largest amount of data is the command at the start and the command at the end, and the data of the command at the start and the command at the end set in the transmission standby buffer 112. The amount is 15 bytes.

When it is time to set a new command while the command being transmitted remains in the transmission standby buffer 112, the new command is placed next to the area in which the command being transmitted is set in the transmission standby buffer 112. It is set in the following areas and enters a transmission standby state. In addition, when it is time to set a new command in a state in which commands being transmitted and commands awaiting transmission exist in the transmission standby buffer 112, the new command is stored in the transmission standby buffer 112 and waiting for transmission. is set in the area after the area in which the command is set, and the transmission standby state is established. The transmission circuit 85 transmits the commands set in the transmission standby buffer 112 to the reception circuit 87 in the order set in the transmission standby buffer 112 . The data capacity of the transmission standby buffer 112 is set larger than the total data capacity of a plurality of commands that can exist in the transmission standby buffer 112 at the same time. Therefore, at the timing when each command is set in the transmission standby buffer 112, an empty area for setting the command is secured.

The transmission circuit 85 is provided with a transmission buffer 111 in which data to be transmitted to the effect side MPU 92 is set. The transmission buffer 111 consists of 1 byte. Commands set in the transmission standby buffer 112 are set in the transmission buffer 111 byte by byte and transmitted to the effect side MPU 92 . Hereinafter, in this specification, 1-byte data included in a command is also referred to as a frame FRm (m is an integer from "1" to "15").

When a command is set in the transmission standby buffer 112, the transmission circuit 85 first transmits 1-byte data (first frame FR1) is set in the transmission buffer 111, and the 1-byte data is transmitted to the MPU 92 on the production side. After that, the transmission circuit 85 sets, in the transmission buffer 111, the 1-byte data (second frame FR2) that is set next to the leading 1-byte data among the multiple-byte data included in the command. , the 1-byte data is transmitted to the effect side MPU 92 . In this manner, the transmission circuit 85 sets data of multiple bytes (multiple frames FRm) included in the command stored in the transmission standby buffer 112 to the transmission buffer 111 until transmission of the entire command is completed. While sequentially updating the 1-byte data (frame FRm) to be executed, the process of transmitting the 1-byte data set in the transmission buffer 111 to the effect side MPU 92 is repeatedly executed.

As shown in FIG. 45, the receiving circuit 87 has a receiving buffer 121 in which 1-byte data received from the transmitting circuit 85 is stored, and a post-reception waiting buffer 122 in which commands received from the main MPU 72 are stored. is provided. The post-reception standby buffer 122 is a 32-byte ring buffer, like the transmission standby buffer 112 in the transmission circuit 85 described above. The storage capacity of the post-reception standby buffer 122 is set to be larger than the total amount of data in a plurality of commands that can exist in the post-reception standby buffer 122 at the same time.

The effect side RAM 94 is provided with a command storage buffer 126 in which commands received from the main side MPU 72 are stored in a state in which they can be used by the effect side MPU 92 . The command storage buffer 126 is a 32-byte ring buffer. The commands stored in the standby buffer 122 after reception are transferred to the command storage buffer 126 and stored in the command storage buffer 126 until the MPU 92 on the production side uses them. The storage capacity of the command storage buffer 126 is set larger than the total amount of data in a plurality of commands that can exist in the command storage buffer 126 at the same time.

After receiving the 1-byte data (frame FRm) stored in the reception buffer 121, the reception circuit 87 sets it in the standby buffer 122 and clears the reception buffer 121 to "0", thereby enabling reception of the next 1-byte data. state. Then, it outputs a receivable signal to the transmission circuit 85 . When the transmission circuit 85 receives the receivable signal and data is set in the transmission buffer 111, the transmission circuit 85 transmits the 1-byte data set in the transmission buffer 111 to the reception circuit 87. do.

A header HD is set in the first frame FR1, which is the first frame of the command transmitted from the master side MPU 72 to the effect side MPU 92, and a footer FT is set in the last frame FRm of the command. there is FIG. 46(a) is an explanatory diagram for explaining the data structure of the header HD, and FIG. 46(b) is an explanatory diagram for explaining the data structure of the footer FT.

As shown in FIG. 46(a), the header HD is 1-byte data consisting of 0th to 7th bits. The 0th to 7th bits of the header HD are set with command identification data that makes it possible to ascertain the type of command. The effect-side MPU 92 grasps the type of the received command based on the command identification data.

Of the 0th to 7th bits of each frame FRm included in the command, the 7th bit is the most significant bit and the 0th bit is the least significant bit. The seventh bit, which is the most significant bit of the header HD (the most significant bit of the command identification data), is a header identification bit that enables identification of the header HD. The header identification bit is always set to "1" regardless of the command type. Of the frames FRm (1-byte data) included in the command, the frame FRm in which the most significant bit (seventh bit) is set to "1" is only the header HD. The reception circuit 87 determines whether or not the most significant bit of the frame FRm stored in the reception buffer 121 is set to "1", thereby grasping whether or not the frame FRm is the header HD. When receiving a plurality of commands from the transmission circuit 85, the reception circuit 87 can grasp the delimiter position of these commands based on the position of the header HD. Note that the header identification bit may be set to "0" and the most significant bit (seventh bit) of the frame FRm other than the header HD may be set to "1". In this configuration, the reception circuit 87 determines whether or not the most significant bit of the frame FRm stored in the reception buffer 121 is set to "0", thereby determining whether or not the frame FRm is the header HD. can be grasped.

As shown in FIG. 46(b), the footer FT is 1-byte data consisting of 0th to 7th bits. The most significant bit of the footer FT is set to "0", and the header HD and the footer FT can be distinguished based on the state of the most significant bit. The identification number data of the slot machine 10 is set in the 0th to 6th bits of the footer FT. The identification number data is numerical information represented by 7 bits other than "0", specifically numerical information of any one of "1" to "127". The receiving circuit 87 determines whether or not identification number data is set in the lower 7 bits (0th to 6th bits) of the frame FRm (1-byte data) stored in the receiving buffer 121. Determine whether the frame FRm is the footer FT. The receiving circuit 87 recognizes the start position of the command by recognizing the header HD, and recognizes the end position of the command by recognizing the footer FT. A series of data starting from the header HD and ending with the footer FT is recognized as one command.

The commands stored in the transmission standby buffer 112 and the frame FRm (1-byte data) stored in the transmission buffer 111 are partially cleared (step S105) or completely cleared (step S105) in the main processing (FIG. 10). S106) is executed.

As already explained, among the plurality of frames FRm included in the command, it is necessary to set "0" to the most significant bit in the frame FRm other than the header HD. When the main MPU 72 transmits a command (specifically, a command at the start and a command at the end) including data in which the most significant bit can be set to "1", the command includes the maximum A highest-order aggregated frame SF in which only upper-bit data is aggregated is set, and the highest-order bits of the plurality of frames are set to "0". As a result, it is possible to set the data in which the most significant bit can be set to "1" while the most significant bit of the frame FRm other than the header HD is set to "0". The most significant bit of the highest-order aggregated frame SF is set to "0", and the header HD and the highest-order aggregated frame SF can be distinguished based on the state of the highest-order bit.

FIG. 46(c) is an explanatory diagram for explaining the setting mode in the main RAM 74 of the storage areas set for the start time command, the end time command and the power recovery command. As shown in FIG. 46(c), a large number of 1-byte storage areas are set in the main RAM 74, and 2-byte addresses are set in a one-to-one correspondence with each of the 1-byte storage areas. ing. The counter and area in which the data is set in the start command are the same as the counter and area in which the data is set in the end command. The counters and areas in which data is set in the start time command and end time command are set in a continuous address range from “0001H” to “000DH” in the main RAM 74 .

Specifically, an AT continuation counter 74u is set in a storage area corresponding to addresses "0001H" to "0002H". As already explained, the AT continuation counter 74u is a counter for specifying the number of remaining continuation games in the AT state ST5 in the main side MPU 72, and the AT continuation counter 74u consists of 2 bytes. The lower 1 byte of the AT continuation counter 74u (hereinafter also referred to as the "lower area of the AT continuation counter 74u") is set in the storage area corresponding to the address "0001H", and the upper 1 byte of the AT continuation counter 74u is stored. (hereinafter also referred to as "the upper area of the AT continuation counter 74u") is set in the storage area corresponding to the address "0002H". In this specification, "B" attached after a numerical value is a symbol indicating that the numerical value is expressed in binary. The number of remaining games in the AT state ST5 stored in the AT continuation counter 74u may be "128" ("0000000010000000B" in binary notation) or more. Therefore, the value of the most significant bit in the lower area of the AT continuation counter 74u may be "1" and the value of the most significant bit may be "0". For example, when the number of remaining games in the AT state ST5 stored in the AT continuation counter 74u is "128", the value of the most significant bit in the lower area of the AT continuation counter 74u becomes "1". When the number of remaining games in the AT state ST5 stored in the counter 74u is "127" ("0000000001111111B" in binary notation), the value of the most significant bit in the lower area of the AT continuation counter 74u is "0". Become. Thus, the lower area of the AT continuation counter 74u is a storage area in which the most significant bit can be set to "1".

As already explained, when the ending condition is satisfied that the number of times the game has been executed since the start of the second section SC2 reaches the upper limit number of games "1500" due to the continuation of the second section SC2. , even in the middle of the AT state ST5, the AT state ST5 is ended in the game in which the ending condition is satisfied, and the second section SC2 is ended, resulting in the first section SC1 and the normal game state ST1. Transition. Also, as already explained, the number of additional games selected in the additional lottery is "10", "20" or "50". Therefore, the number of remaining games in the AT state ST5 stored in the AT continuation counter 74u must be "32768" ("1000000000000000B" in binary notation) or more. "1" is never set. The value of the most significant bit in the upper area of the AT continuation counter 74u is "0", and the upper area of the AT continuation counter 74u is an area in which the most significant bit is not set to "1".

A continuous game number counter 74r is set in a storage area corresponding to addresses "0003H" to "0004H". As already explained, the number-of-continued-games counter 74r counts the number of games executed from the start of the second section SC2 when the second section SC2 continues without intervening the first section SC1. The continuous game number counter 74r consists of 2 bytes. The lower 1 byte of the continuous game number counter 74r (hereinafter also referred to as the "lower area of the continuous game number counter 74r") is set in the storage area corresponding to the address "0003H", and the continuous game number counter 74r The upper 1 byte (hereinafter also referred to as "the upper area of the number-of-continued-games counter 74r") is set in the storage area corresponding to the address "0004H". The number of game executions stored in the continuous game number counter 74r may be "128" ("0000000010000000B" in binary notation) or more. Therefore, the value of the most significant bit in the lower area of the number-of-continued-games counter 74r may be "1" and the value of the most significant bit may be "0". For example, if the number of game executions since the start of the second section SC2 stored in the continuous game number counter 74r is "128", the value of the most significant bit in the lower area of the continuous game number counter 74r is " 1", and when the number of times the game has been executed since the start of the second interval SC2 stored in the continuous game number counter 74r is "127" ("0000000001111111B" in binary notation), the number of continuous games. The value of the most significant bit in the lower area of the counter 74r becomes "0". Thus, the lower area of the continued game number counter 74r is a storage area in which the most significant bit can be set to "1".

As described above, when the ending condition that the number of times the game has been executed since the start of the second section SC2 reaches the upper limit number of games "1500" by continuing the second section SC2 is satisfied, In the game in which the ending condition is established, the second section SC2 ends and the game proceeds to the first section SC1. Therefore, the number of game executions stored in the number-of-continued-games counter 74r must be "32768" ("1000000000000000B" in binary notation) or more, that is, the highest bit in the upper area of the number-of-continued-games counter 74r must be "1". ” is never set. The value of the highest bit in the upper area of the continued game number counter 74r is "0", and the upper area of the continued game number counter 74r is an area in which the highest bit is not set to "1".

A total acquisition number counter 74s is set in a storage area corresponding to addresses "0005H" to "0006H". As already explained, the total acquisition number counter 74s counts the restricted total net increase in the number of game media from the start of the second section SC2 when the second section SC2 continues without intervening the first section SC1. This is a counter for identification by the main MPU 72, and the total acquisition number counter 74s consists of 2 bytes. The lower 1 byte of the total acquisition number counter 74s (hereinafter also referred to as the "lower area of the total acquisition number counter 74s") is set in the storage area corresponding to the address "0005H", and the total acquisition number counter 74s The upper 1 byte (hereinafter also referred to as "the upper area of the total acquisition number counter 74s") is set in the storage area corresponding to the address "0006H". The restricted total net increase in number of game media stored in the total acquisition counter 74s may be "128" ("0000000010000000B" in binary notation) or more. Therefore, the value of the most significant bit in the lower area of the total acquisition number counter 74s may be "1" and the value of the most significant bit may be "0". For example, when the restricted total net increase in the number of gaming media stored in the total win count counter 74s is "128", the value of the most significant bit in the lower area of the total win count counter 74s becomes "1". When the restricted total net increase in the number of game media stored in the total winning number counter 74s is "127" ("0000000001111111B" in binary notation), the value of the most significant bit in the lower area of the total winning number counter 74s is becomes "0". Thus, the lower area of the total acquisition number counter 74s is a storage area in which the most significant bit can be set to "1".

As already explained, if the total number of net increases with restrictions on the number of game media from the start of the second section SC2 reaches the upper limit net increase number of "2400" due to the continuation of the second section SC2, After the second section SC2 is completed, the process shifts to the first section SC1. Therefore, the number of game executions stored in the total win count counter 74s must be "32768" ("1000000000000000B" in binary notation) or more, that is, the highest bit in the upper area of the total win count counter 74s must be "1". ” is never set. The value of the highest bit in the upper area of the total acquisition number counter 74s is "0", and the upper area of the total acquisition number counter 74s is an area in which the highest bit is not set to "1".

As described above, the lower area of the AT continuation counter 74u, the lower area of the continued game number counter 74r, and the lower area of the total winning number counter 74s are the number of games stored in the AT continuation counter 74u, and the number of games stored in the continued game number counter 74r. Depending on the number of games played or the limited total net increase in the number of game media stored in the total winning number counter 74s, the value of the most significant bit is "1" or the value of the most significant bit is "0". This is a storage area in which there are cases where "1" can be set to the most significant bit.

A top-level aggregation area 74v is set in the storage area corresponding to the address "0007H". In the highest aggregate area 74v, when the main side MPU 72 transmits a start time command or an end time command to the effect side MPU 92, data of the highest highest aggregate frame set in the start time command or end time command is set. storage area. The top-level aggregation area 74v consists of 1 byte. "0" or "1" stored in the highest bit (seventh bit) of the storage area corresponding to the addresses "0001H" to "0006H" ” data is aggregated. Specifically, the most significant bit data in the lower area of the AT continuation counter 74u set to the address "0001H" is set to the 0th bit of the highest aggregation area 74v, and set to the address "0002H". The most significant bit data in the upper area of the AT continuation counter 74u is set to the first bit of the highest aggregation area 74v, and the data in the lower area of the continuous game number counter 74r set to the address "0003H" The most significant bit data is set to the second bit of the highest aggregation area 74v, and the highest bit data in the upper area of the continuous game number counter 74r set to the address "0004H" is the highest aggregation area. The data of the most significant bit in the lower area of the total acquisition number counter 74s, which is set to the third bit of 74v and set to the address "0005H", is set to the fourth bit of the highest aggregation area 74v and is set to "0006H". ] is set to the fifth bit of the highest aggregation area 74v. As a result, the most significant bit data in these six areas are aggregated in the highest aggregation area 74v. The 6th and 7th bits in the highest aggregation area 74v are unused bits, and the values of these 6th and 7th bits are "0". The most significant aggregation area 74v is a storage area in which the most significant bit (seventh bit) is not set to "1".

In this way, "0001H" to "0006H" including the lower area of the AT continuation counter 74u, the lower area of the continuous game number counter 74r, and the lower area of the total winning number counter 74s, in which "1" can be set to the most significant bit. Data of "0" or "1" stored in the most significant bit in the six storage areas set in a continuous address range are aggregated into a 1-byte storage area (top aggregation area 74v). . For this reason, compared to the configuration in which a memory area of 2 bytes or more is set in the main RAM 74 in order to set the data "0" or "1" stored in the most significant bit of these six memory areas. Therefore, the data capacity of the storage area provided in the main RAM 74 is reduced for setting the data "0" or "1" stored in the most significant bit of these six storage areas.

The six storage areas are "0001H" to "0006H", including the lower area of the AT continuation counter 74u in which the most significant bit can be set to "1", the lower area of the continued game number counter 74r, and the lower area of the total winning number counter 74s. is set to a continuous address range, the address range of the storage area to be set in the highest-order aggregation area 74v for the data of "0" or "1" stored in the most significant bit is specified. It is possible to simplify the processing configuration for

As described above, the lower area of the AT continuation counter 74u, the lower area of the continued game number counter 74r, and the lower area of the total winning number counter 74s are areas in which the most significant bit can be set to "1", while the AT continuation counter 74u , the upper area of the continuous game number counter 74r, and the upper area of the total winning number counter 74s are areas in which the most significant bit is not set to "1". In the main RAM 74, the lower area and upper area of the AT continuation counter 74u are set in a continuous address range ("0001H" to "0002H"). Further, the lower area and upper area of the continuous game number counter 74r are set to a continuous address range ("0003H" to "0004H"), and the lower area and upper area of the total winning number counter 74s are set to a continuous address range. ("0005H" to "0006H"). Six storage areas set in a continuous address range of "0001H" to "0006H" including the upper area of the AT continuation counter 74u, the upper area of the continuous game number counter 74r, and the upper area of the total winning number counter 74s. The data of "0" or "1" stored in the most significant bit of is aggregated in the highest aggregation area 74v. For this reason, compared to the configuration in which only the storage areas in which the most significant bit can be set to "1" are set in the continuous address range in the main side RAM 74, the number of remaining games in the AT state ST5 and the interval between the first section SC1 are reduced. The number of times the game is executed from the start of the second section SC2 when the second section SC2 continues without intervening, and the number of times when the second section SC2 continues without interposing the first section SC1 It is possible to prevent complication of the processing configuration for grasping the restricted total net increase in the number of game media from the start of the second section SC2.

A bet number setting counter 74b is set in the storage area corresponding to the address "0008H". As already explained, the numerical value information set in the bet number setting counter 74b is "2" or "3". Therefore, the value of the most significant bit of the bet number setting counter 74b is always "0", and the bet number setting counter 74b is a storage area in which the most significant bit is not set to "1". A stop order type counter 74m is set in the storage area corresponding to the address "0009H". As already explained, the numerical information set in the stop order type counter 74m in this embodiment is the stop order type number from "1" to "9" or "0". Therefore, the value of the highest bit of the stop order type counter 74m is always "0", and the stop order type counter 74m is a storage area in which the highest bit is not set to "1". A game state area 77 is set in the storage area corresponding to the address "000AH". As already explained, in the 0th to 5th bits of the game state area 77, the first CB state flag 77a, the second CB state flag 77b, the pseudo bonus state flag 77c, the AT state flag 77d, the end preparation state flag 77e, and the AT transition confirmation The flag 77f is set, and the 6th and 7th bits of the gaming state area 77 are unused bits. The value of the most significant bit of the game state area 77 is always "0", and the game state area 77 is a storage area in which the most significant bit is not set to "1". A game section area 76 is set in the storage area corresponding to the address "000BH". As already explained, the second section flag 76a, the first ending flag 76b and the second ending flag 76c are set in the 0th to 2nd bits of the game section area 76, and the third ~ 7th bit is an unused bit. The value of the most significant bit in the game section area 76 is always "0", and the game section area 76 is a storage area in which the most significant bit is not set to "1". A pseudo bonus continuation counter 74t is set in the storage area corresponding to the address "000CH". As already explained, the pseudo-bonus continuation counter 74t is a counter for the main MPU 72 to specify the remaining number of continuous games in the pseudo-bonus state ST4. The pseudo-bonus continuation counter 74t is set to "50" when the pseudo-bonus state ST4 is the big bonus, and is set to "20" when the pseudo-bonus state ST4 is the regular bonus. The maximum value of the remaining number of continuous games set in the pseudo-bonus continuation counter 74t is "50" ("00110010B" in binary notation), and the value of the most significant bit in the pseudo-bonus continuation counter 74t is always "0". be. Thus, the pseudo bonus continuation counter 74t is a storage area in which the most significant bit is not set to "1". A given number counter 74e is set in the storage area corresponding to the address "000DH". As already explained, the given number of game media set in the given number counter 74e is "1", "2", "5" or "15", and the given number of game media set in the given number counter 74e is "15" ("00001111B" in binary notation). The value of the most significant bit in the given number counter 74e is always "0", and the given number counter 74e is a storage area in which the most significant bit is not set to "1".

In this way, the bet number setting counter 74b, the stop order type counter 74m, the game state area 77, the game section area 76, the pseudo bonus continuation counter 74t and the award number counter are set in the address range of "0008H" to "000DH". 74e is a storage area in which the most significant bit is not set to "1". The main side RAM 74 stores data of the most significant bits of the bet number setting counter 74b, the stop order type counter 74m, the game state area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the award number counter 74e. No storage area is provided.

Among the storage areas of the main side RAM 74 where data is set in the command at the start and the command at the end, the data of the highest bit in the area where "1" can be set to the highest bit (seventh bit) is collected. By providing an upper aggregation area 74v and not providing a storage area where data of the highest bit in the storage area of the main side RAM 74 in which the highest bit is not set to "1" is aggregated , while suppressing the number of storage areas (highest-order aggregation area 74v) set in the main-side RAM 74 to aggregate data of the highest-order bit, Bits of data can be set in the start-time command and the end-time command.

Since the storage area in which data is set in the start command and the end command is set in the continuous address range of "0001H" to "000DH" in the main RAM 74, the storage area in which the data is set in the start command is It is possible to simplify the processing configuration for specifying the address range and the processing configuration for specifying the address range of the storage area in which data is set in the end command.

As shown in FIG. 46(c), among the data set in the command at the start, the data used by the effect-side MPU 92 at the start of the game are the AT continuation counter 74u, the top-level aggregation area 74v, and the number of bets. It is only the data of the setting counter 74b, the stop order type counter 74m and the game state area 77, and the data of the continuous game number counter 74r, the total winning number counter 74s, the game section area 76, the pseudo bonus continuation counter 74t and the award number counter 74e. This data is not used by the effect side MPU 92 at the start of the game. Among the data set in the end command, the data used by the effect side MPU 92 at the end of the game are a continuous game number counter 74r, a total winning number counter 74s, an area for top-level aggregation 74v, and a game state area. 77, game section area 76, pseudo bonus continuation counter 74t and grant number counter 74e data only, AT continuation counter 74u, bet number setting counter 74b and stop order type counter 74m data are sent to production side MPU 92 at the end of the game data that is not used for

In this way, only a part of the storage area of the main side RAM 74 (specifically, the highest level aggregation area 74v and the game state area 77) where the data used by the effect side MPU 92 at the start of the game is stored. , and the storage area of the main side RAM 74 in which data used by the effect side MPU 92 at the end of the game is stored. In this configuration, the storage area in which data is set in the command at the start and the command at the end is the storage area of the main side RAM 74 that stores the data used by the effect side MPU 92 at the start and end of the game. As a result, it is possible to set a storage area in which data is set in the command at the start and a storage area in which data is set in the command at the end in a continuous address range of the main RAM 74 .

In the main RAM 74, the address range of the storage area where the data to be set in the start command is stored (the address range of "0001H" to "000DH") is the data to be set in the end command. Since it is the same as the address range of the storage area (address range of "0001H" to "000DH"), the processing configuration for transmitting the start command and the processing configuration for transmitting the end command should be shared. can be done. As a result, the data capacity of the program for transmitting the command at the start and the command at the end in the main ROM 73 can be reduced.

As described above, the AT continuation counter 74u, the continuation game number counter 74r, and the total winning number counter 74s exist as counters in which the most significant bit of the lower area can be set to "1". The data of the AT continuation counter 74u is data used by the effect side MPU 92 at the start of the game, but is not data used by the effect side MPU 92 at the end of the game. The data of the continuous game number counter 74r and the total winning number counter 74s are data used by the effect side MPU 92 at the end of the game, but are not data used by the effect side MPU 92 at the start of the game. If only the data used by the effect side MPU 92 at the start of the game is set in the start command and only the data used by the effect side MPU 92 at the end of the game is set in the end command, the AT continuation counter In addition to the storage area for setting the most significant bit data in the lower area and upper area of 74u, the lower area and upper area of the continued game number counter 74r and the lower area and upper area of the total winning number counter 74s. It would be necessary to provide a storage area in the main RAM 74 for setting the upper bit data. On the other hand, by setting the data of the AT continuation counter 74u, the continuation game number counter 74r, and the total winning number counter 74s in the start time command and the end time command, the AT continuation counter 74u and the continuation game number counter are set. 74r and total acquisition number counter 74s. can do. As a result, the most significant bit data in the lower area and upper area of the AT continuation counter 74u, the lower area and upper area of the continuous game number counter 74r, and the lower area and upper area of the total winning number counter 74s are set. The data capacity of the side RAM 74 is reduced.

As already explained, data of the first CB winning data area 74j and the second CB winning data area 74k in the main side RAM 74 are set in the power recovery command. As shown in FIG. 46(c), in the main side RAM 74, the first CB winning data area 74j is set to the storage area corresponding to the address "000EH", and the second CB winning data area 74k is set to the storage area corresponding to the address "000FH". It is set in the storage area corresponding to the address. In this way, storage areas for storing data set in commands other than the start time command and the end time command are also set in storage areas corresponding to consecutive addresses in the main RAM 74 . This simplifies the processing for setting the data stored in the first CB winning data area 74j and the second CB winning data area 74k in the power recovery command.

The first CB winning data area 74j and the second CB winning data area 74k in which data is set in the power recovery command are storage areas in which the most significant bit is never set to "1". As shown in FIG. 46(c), the main RAM 74 is not provided with a storage area for collecting the most significant bit data in the first CB winning data area 74j and the second CB winning data area 74k. Therefore, the data capacity of the main side RAM 74 is reduced compared to a configuration in which a storage area is provided for collecting the most significant bit data in the first CB winning data area 74j and the second CB winning data area 74k. ing.

Next, the case where the reception circuit 87 receives the start command will be described. FIG. 47(a) is an explanatory diagram for explaining the data configuration of the command at the start and the command at the end, and FIG. 47(b) is an explanatory diagram for explaining the data configuration of the command at the start after conversion. FIG. 47(c) is an explanatory diagram for explaining the data configuration of the post-conversion completion command. Also, FIG. 48(a) is an explanatory diagram for explaining the conversion mode of the start command, and FIG. 48(b) is an explanatory diagram for explaining the conversion mode of the end command.

The command received by the receiving circuit 87 from the main MPU 72 is stored in the standby buffer 122 after being received. As shown in FIG. 45, the effect side RAM 94 is provided with a pre-conversion area 124 and a post-conversion area 125 . The pre-conversion area 124 is a storage area for storing the start-time command or the end-time command in which the highest aggregated frame SF is set. This is a storage area for converting an end command into a post-conversion start command or a post-conversion end command.

As shown in FIGS. 48A and 48B, the pre-conversion area 124 includes first to fifteenth areas RA1 to RA15, and the post-conversion area 125 includes first to tenth areas RB1 to RB10. is provided. These areas RA1 to RA15 and RB1 to RB10 are storage areas of 1 byte. In the production side RAM 94, the first to fifteenth areas RA1 to RA15 of the pre-conversion area 124 are set in a continuous address range of "α+1" to "α+15". The tenth areas RB1 to RB10 are set in a continuous address range of "β+1" to "β+10".

The total data capacity of the first to fifteenth areas RA1 to RA15 in the pre-conversion area 124 is 15 bytes, and the total data capacity of the first to tenth areas RB1 to RB10 in the post-conversion area 125 is 10 bytes. . As already explained, the maximum data capacity of one command received by the receiving circuit 87 from the transmitting circuit 85 is 15 bytes. The data capacity of the post-conversion start command is 7 bytes, and the data capacity of the post-conversion end command is 10 bytes.

The data configuration of the end command is the same as the data configuration of the start command. In the following, the data configuration of the start command and the end command will be described using the start command as an example.

As shown in FIG. 47(a), the first frame FR1 positioned at the beginning of the start command is set with the data of the header HD indicating that it is the start command, and the 0th to 0th frames of the second frame FR2 are set. The 0th to 6th bits in the lower area of the AT continuation counter 74u are set in the 6th bit, and the 0th to 6th bits in the upper area of the AT continuation counter 74u are set in the 0th to 6th bits of the third frame FR3. Bits 0 to 6 of the fourth frame FR4 are set to bits 0 to 6 in the lower area of the continuous game number counter 74r. The 0th to 6th bits of the frame FR5 are set with the 0th to 6th bits of data in the upper area of the continuous game number counter 74r, and the 0th to 6th bits of the sixth frame FR6 are set to the total number of wins. The 0th to 6th bit data in the lower area of the counter 74s are set, and the 0th to 6th bit data in the upper area of the total acquisition number counter 74s are set in the 0th to 6th bits of the seventh frame FR7. is set, and the data of the top-level aggregation area 74v is set in the eighth frame FR8. As already explained, the data in the topmost aggregation area 74v includes the lower area of the AT continuation counter 74u, the upper area of the AT continuation counter 74u, and the number of continuous games counter in the 0th to 5th bits of the topmost aggregation area 74v. 74r, the upper area of the continuous game number counter 74r, the lower area of the total number of wins counter 74s, and the upper area of the total number of wins counter 74s. Aggregated data.

The data of the bet number setting counter 74b is set in the 9th frame FR9 of the start time command, the data of the stop order type counter 74m is set in the 10th frame FR10, and the game state is set in the 11th frame FR11. The data of the area 77 are set, the data of the game section area 76 are set in the 12th frame FR12, the data of the pseudo bonus continuation counter 74t are set in the 13th frame FR13, and the 14th frame. FR14 is set with the data of the added number counter 74e, and the 15th frame FR15 is set with the data of the footer FT.

When converting the command at start to the command at start after conversion, the MPU 92 on the production side first sets the 0th to 5th bits of the highest integrated frame SF (8th frame FR8) included in the command at start. The data of "0" or "1" is set to the most significant bits of the 2nd to 7th frames FR2 to FR7 corresponding to the 0th to 5th bits. After that, among the 1st to 15th frames FR1 to FR15 included in the command at the start, the frame in which data not used at the start of the game is set and the 8th frame in which the data of the top-level aggregation area 74v are set. The post-conversion start time command is generated by excluding frame FR8. Specifically, the fourth and fifth frames FR4 and FR5 in which the data of the continuous game number counter 74r are set, the sixth and seventh frames FR6 and FR7 in which the data of the total winning number counter 74s are set, An eighth frame FR8 in which the data of the high-level aggregation area 74v is set, a twelfth frame FR12 in which the data of the game section area 76 is set, a thirteenth frame FR13 in which the data of the pseudo-bonus continuation counter 74t is set, And the 14th frame FR14 in which the data of the number of grant counter 74e is set is excluded.

As shown in FIG. 47(b), the post-conversion start command includes data in the header HD, data in the lower area of the AT continuation counter 74u, data in the upper area of the AT continuation counter 74u, and data in the bet number setting counter 74b. , data of the stop order type counter 74m, data of the game state area 77, and data of the footer FT are set. The data in the lower area of the AT continuation counter 74u set in the post-conversion start command is data of the 0th to 7th bits including the most significant bit of the lower area of the AT continuation counter 74u. The data in the upper area of the AT continuation counter 74u set in the hour command is the 0th to 7th bit data including the most significant bit of the upper area of the AT continuation counter 74u.

When the effect-side MPU 92 converts the end-time command into the end-time command after conversion, the effect-side MPU 92 first sets the 0th to 5th bits of the highest aggregated frame SF (eighth frame FR8) included in the end-time command. The data of "0" or "1" is set to the most significant bits of the 2nd to 7th frames FR2 to FR7 corresponding to the 0th to 5th bits. After that, among the 1st to 15th frames FR1 to FR15 included in the command at the time of termination, the frame in which data not used at the end of the game is set and the 8th frame in which the data of the top-level aggregation area 74v are set. A post-conversion termination command is generated by excluding frame FR8. Specifically, the second and third frames FR2 and FR3 in which the data of the AT continuation counter 74u are set, the eighth frame FR8 in which the data of the highest aggregation area 74v are set, and the bet amount setting counter 74b The ninth frame FR9 in which the data is set and the tenth frame FR10 in which the data of the stop order type counter 74m are set are excluded.

As shown in FIG. 47(c), the post-conversion end command includes header HD data, data in the lower area of the continuous game number counter 74r, data in the upper area of the continuous game number counter 74r, and a total winning number counter 74s. data of the lower area of , data of the upper area of the total acquisition number counter 74s, data of the game state area 77, data of the game section area 76, data of the pseudo bonus continuation counter 74t, data of the grant number counter 74e, and footer FT Data is set. The data in the lower area of the continuous game number counter 74r set in the post-conversion termination command is the data of the 0th to 7th bits including the most significant bit of the lower area of the continuous game number counter 74r. The upper area data of the continued game number counter 74r set in the post-end command is data of the 0th to 7th bits including the most significant bit of the upper area of the continued game number counter 74r. Further, the data in the lower area of the total acquisition number counter 74s set in the post-conversion end command is the data of the 0th to 7th bits including the most significant bit in the lower area of the total acquisition number counter 74s. , the data in the upper area of the total acquisition number counter 74s set in the command at the time of completion after conversion is data of the 0th to 7th bits including the most significant bit in the upper area of the total acquisition number counter 74s.

In the effect-side ROM 93, there is a start conversion table that is referred to when converting a start command into a converted start command, and an end conversion table that is referred to when converting an end command into a converted end command. is stored. In the start conversion table, information about frames to be excluded when converting the start command into the post-conversion start command is set. In the end conversion table, information of frames to be excluded when the end command is converted into the post-conversion end command is set. The effect side MPU 92 converts the command at the start into the command at the converted start based on the conversion table at the start, and converts the command at the end into the command at the end after conversion based on the conversion table at the end.

The effect-side MPU 92 sets the start time command or end time command stored in the post-reception waiting buffer 122 in the first to fifteenth areas RA1 to RA15 of the pre-conversion area 124 . As a result, the highest aggregated frame SF is set in the eighth area RA8 of the pre-conversion area 124, as shown in FIGS. After that, the data of "0" or "1" set in the 0th to 5th bits of the highest aggregated frame SF is transferred to the 2nd to 7th frames corresponding to the 0th to 5th bits in the pre-conversion area 124. The most significant bit (seventh bit) of the second to seventh areas RA2 to RA7 in which FR2 to FR7 are set is set. Specifically, the 0th bit data of the eighth area RA8 is set as the most significant bit of the second area RA2, and the 1st bit data of the eighth area RA8 is set as the most significant bit of the third area RA3. , sets the second bit data of the eighth area RA8 to the most significant bit of the fourth area RA4, sets the third bit data of the eighth area RA8 to the most significant bit of the fifth area RA5, and sets the eighth area RA8 to the most significant bit. The data of the 4th bit of RA8 is set to the most significant bit of the sixth area RA6, and the data of the 5th bit of the eighth area RA8 is set to the most significant bit of the seventh area RA7.

A frame in which data "0" or "1" set in the 0th to 5th bits of the highest aggregated frame SF (the eighth frame FR8) is set in the most significant bit in the command at the start or the command at the end. are consecutive second to seventh frames FR2 to FR7. For this reason, a processing configuration for designating a frame in which data "0" or "1" set in the 0th to 5th bits of the highest aggregated frame SF is set in the highest bit is specified by the production side MPU 92. can be simplified.

After that, when the start command is set in the pre-conversion area 124, the first to fifteenth areas RA1 to RA15 of the pre-conversion area 124 are set based on the start conversion table. Of the 15 frames FR1 to FR15, the frames other than the frames to be excluded are transferred to the first to seventh areas RA1 to RA7 of the area 125 after conversion. Specifically, as shown in FIG. 48A, the first area RA1, the second area RA2, the third area RA3, the ninth area RA9, the tenth area RA10, the eleventh area RA11, and the data of the fifteenth area RA15 to the first area RB1, the second area RB2, the third area RA3, the fourth area RB4, the fifth area RB5, the sixth area RB6, and the seventh area RB7 of the post-conversion area 125. Forward. As a result, the command at start can be converted into the command at start after conversion.

When the termination command is set in the pre-conversion area 124, the 1st to 15th frames set in the 1st to 15th areas RA1 to RA15 of the pre-conversion area 124 based on the termination conversion table Of the FR1 to FR15, the frames other than the frames to be excluded are transferred to the first to tenth areas RA1 to RA10 of the post-conversion area 125. FIG. Specifically, as shown in FIG. 48(b), the first area RA1, fourth area RA4, fifth area RA5, sixth area RA6, seventh area RA7, eleventh area RA11, The data of the 12th area RA12, the 13th area RA13, the 14th area RA14 and the 15th area RA15 are converted into the 1st area RB1, the 2nd area RB2, the 3rd area RB3, the 4th area RB4 and the 5th area RB1 of the post-conversion area 125. Transfer to area RB5, sixth area RB6, seventh area RB7, eighth area RB8, ninth area RB9, and tenth area RB10. As a result, the termination command can be converted into the post-conversion termination command.

The effect-side MPU 92 stores the post-conversion start time command or the post-conversion end time command in the command storage buffer 126 . As a result, the effect-side MPU 92 can use the post-conversion start time command or the post-conversion end time command. The post-conversion start time command and the post-conversion end time command are commands in which the most significant bit of the frame FRm other than the header HD can be set to "1". The effect side MPU 92 executes effects based on commands stored in the command storage buffer 126 .

In this manner, the effect-side MPU 92 converts the start command received from the main MPU 72 into the converted start command, and converts the end command received from the main MPU 72 into the converted end command. When the effect-side MPU 92 converts the start-time command or the end-time command received from the main-side MPU 72 into the post-conversion start-time command or the post-conversion end-time command, the effect-side MPU 92 converts the 0th to The data "0" or "1" set in the 5th bit is set in the most significant bit in the 2nd to 7th frames FR2 to FR7 corresponding to the 0th to 5th bits. As a result, while setting the value of the most significant bit in the frame other than the header HD contained in the command at the start or the command at the end transmitted from the master side MPU 72 to the effect side MPU 92 to be "0", the effect side MPU 92 performs the header A post-translation start or post-translation end command may be available in which the most significant bit in non-HD frames may also be set to '1'.

Only some of the 1st to 15th frames FR1 to FR15 included in the start time command are set in the post-conversion start time command. As a result, the master side MPU 72 is configured to transmit a start-time command including data other than the data used by the effect side MPU 92 at the start of the game, while the command is stored in the command storage buffer 126 and used by the effect side MPU 92 . It is possible to suppress the data volume of the post-conversion start command. Further, only some of the first to fifteenth frames FR1 to FR15 included in the end command are set in the post-conversion end command. As a result, the master side MPU 72 is configured to transmit an end-time command including data other than the data used by the effect side MPU 92 at the end of the game, while the data is stored in the command storage buffer 126 and used by the effect side MPU 92 . It is possible to suppress the data volume of the command at the end of conversion after conversion. Therefore, the data capacity of the command storage buffer 126 can be reduced.

Of the 1st to 15th frames FR1 to FR15 included in the start time command, the frames set by the production side MPU 92 in the post-conversion start time command are the 1st to 15th frames FR1 to FR1 included in the end time command. It is different from the frame set in the post-conversion termination command by the effect-side MPU 92 in the FR 15 . For this reason, the address range of the storage area of the main RAM 74 storing the data set in the command at the start transmitted from the main MPU 72 to the effect MPU 92 at the start of the game is the same as the address range from the main MPU 72 to the effect at the end of the game. In a configuration that is the same as the address range of the storage area of the main side RAM 74 in which the data set in the command at the end transmitted to the side MPU 92 is stored, the address range required by the effect side MPU 92 at the start of the game at the start of the game. Only the data that is set between the header HD and the footer FT can be made available to the production side MPU 92 at the time of starting the conversion command, and at the end of the game, the production side MPU 92 can use The MPU 92 on the production side can use the post-conversion completion command in which only the data required for the conversion is set between the header HD and the footer FT.

When the main MPU 72 transmits a command (for example, a power recovery command and a winning result command) containing only data in which "1" is not set to the most significant bit, the frame contained in the command Do not aggregate the most significant bit data in FRm. As already explained, the data of the first CB winning data area 74j and the second CB winning data area 74k are set in the power recovery command. The first CB winning data area 74j and the second CB winning data area 74k are storage areas in which the most significant bit is not set to "1". The main side RAM 74 is not provided with a storage area for collecting the most significant bit data of the first CB winning data area 74j and the second CB winning data area 74k. In addition, the processing for aggregating the most significant bit data of the first CB winning data area 74j and the second CB winning data area 74k is not executed.

In this way, when a command containing only data in which the most significant bit is not set to "1" is transmitted, the data of the most significant bit in the frame included in the command is not aggregated. . For this reason, compared to the configuration that generates the highest aggregated frame SF even for a command that does not set data that can set "1" to the highest bit, the processing configuration for transmitting the command in the main side MPU 72 can be simplified, and the processing load on the main side MPU 72 for transmitting the command can be reduced.

When the production side MPU 92 identifies that the command stored in the post-reception standby buffer 122 does not include the highest aggregated frame SF, the command is transferred to the command storage buffer 126 as it is. Specifically, when the power recovery command is stored in the standby buffer 122 after reception, the power recovery command is transferred as it is to the command storage buffer 126, and the winning result command is stored in the standby buffer 122 after reception. If so, the winning result command is transferred to the command storage buffer 126 as it is. For this reason, compared to the configuration in which the highest-level aggregated frame SF is generated even for a command in which only the frame FRm is set in which the most significant bit is not set to "1", the conversion is performed after the command is received. , the processing load on the effect side MPU 92 can be reduced.

As shown in FIG. 45, the receiving circuit 87 is provided with a first write pointer 127 and a read pointer 128 . The first write pointer 127 and the read pointer 128 consist of 1 byte, and the first write pointer 127 and the read pointer 128 store any integer from "0" to "31". The first write pointer 127 is used when the reception circuit 87 grasps the write destination area in the post-reception standby buffer 122 . When 1-byte data is stored in the reception buffer 121 , the reception circuit 87 grasps the write destination area in the post-reception standby buffer 122 based on the value of the first write pointer 127 and stores the data in the reception buffer 121 . 1-byte data stored in the area is written into the grasped area. Then, 1 is added to the value of the first write pointer 127, and when the value of the first write pointer 127 after the addition of 1 exceeds the maximum value "31", the value of the first write pointer 127 is changed to " 0” clear. After that, the receive buffer 121 is cleared to "0".

The read pointer 128 is used when the production side MPU 92 grasps the beginning of the command stored in the standby buffer 122 after reception. When one or more commands are stored in the standby buffer 122 after reception, the effect-side MPU 92 grasps the head of the command based on the value of the read pointer 128, and also grasps the head of the command based on the data of the footer FT of the command. Grasp the end of the command. When a plurality of commands are stored in the post-reception standby buffer 122, the head of the first command among the plurality of commands stored in the post-reception standby buffer 122 is grasped based on the value of the read pointer 128. At the same time, the end of the command is recognized based on the data of the footer FT of the command.

If the command for which the head and tail are grasped based on the value of the read pointer 128 is the start time command or end time command, the effect side MPU 92 stores the start time command or end time command in the pre-conversion area 124 of the effect side RAM 94. set to Then, the area in which the command at start or end was stored in the wait buffer 122 after reception is cleared to "0", and the value of the read pointer 128 is changed to the end of the command at start or end (footer FT). data) is updated to the value corresponding to the next area. In addition, the effect-side MPU 92, if the command that grasps the beginning and end based on the value of the read pointer 128 is a command other than the command at the start and the command at the end (for example, a winning result command or a return command), the command is stored in the command storage buffer 126 of the effect side RAM 94 . After reception, the area in which the command was stored in the standby buffer 122 is cleared to "0", and the value of the read pointer 128 is set to the next area after the area in which the end of the command (data of the footer FT) was stored. Update the value corresponding to the area. As a result, commands received from the main MPU 72 can be made available to the production MPU 92 in the order in which they are stored in the waiting buffer 122 after reception, that is, in the order in which they are received from the main MPU 72 .

FIG. 49(a) is an explanatory diagram for explaining the contents grasped by the effect side MPU 92 based on the post-conversion start time command, and FIG. It is an explanatory view for explaining the contents to do.

As shown in FIG. 49(a), the effect-side MPU 92 recognizes that it is time to start the game based on the fact that the header HD data indicating that the received command is a start command is set. . The production side MPU 92 grasps that the bet number of the game started this time is "3" or "2" based on the data of the bet number setting counter 74b set in the start time command. . Based on the data of the stop order type counter 74m set in the start time command, the production side MPU 92 grasps whether or not the reels 32L, 32M, 32R are notified of the stop order of the reels 32L, 32M in the image display device 63. , 32R, the type of stop order to be notified is grasped. The effect-side MPU 92 grasps that an AT state win has occurred based on the data of the AT transition determination flag 77f included in the data of the game state area 77 set in the start time command. Based on the data of the AT continuation counter 74u set in the start time command, the effect-side MPU 92 grasps whether or not the number of remaining games to be continued in the AT state ST5 has been increased, and if the increase has occurred. Grasp the number of additional games in the case.

As shown in FIG. 49(b), the effect-side MPU 92 shifts to the first CB state ST2 based on the data of the first CB state flag 77a included in the data of the game state area 77 set in the end command. and the end of the first CB state ST2. The effect-side MPU 92, based on the data of the second CB state flag 77b included in the data of the game state area 77 set in the end command, determines that the transition to the second CB state ST3 has occurred and that the second CB state has occurred. It is recognized that state ST3 has ended. Based on the data of the pseudo-bonus state flag 77c included in the data of the game state area 77 set in the end command, the effect-side MPU 92 determines that it is the start timing of the pseudo-bonus state ST4 and the pseudo-bonus state. It grasps that it is the end timing of ST4. The effect side MPU 92, based on the data of the AT state flag 77d included in the data of the game state area 77 set in the command at the time of completion, determines that the transition to the AT state ST5 has occurred and that the AT state ST5 has occurred. Know that you're done. Based on the data of the second section flag 76a included in the data of the game section area 76 set in the end command, the effect-side MPU 92 determines that the second section SC2 has started and that the second section SC2 has started. know that has ended. Based on the data of the first ending flag 76b included in the data of the game section area 76 set in the end command, the effect side MPU 92 grasps whether or not the effect of the ending period should be started, and ends the ending. When the effect of the period is started, the remaining number of games until the ending condition is satisfied is grasped based on the data of the continuous game number counter 74r set in the end command. Based on the data of the second ending flag 76c included in the data of the game section area 76 set in the end command, the effect-side MPU 92 grasps whether or not the effect of the ending period should be started, and ends the ending. When the performance of the period is started, the limited total net increase number of the remaining game media until the ending condition is satisfied is grasped based on the data of the total acquisition number counter 74s set in the command at the end. The effect-side MPU 92 grasps whether or not game media are given in the game ended this time based on the data of the given number counter 74e set in the command at the end, and gives game media in the game finished this time. In that case, the number of given game media is grasped.

Next, the common command transmission process executed by the main MPU 72 will be described with reference to the flowchart of FIG. As already explained, the common command transmission process is executed when the command flag at the start of the main RAM 74 is set to "1" in the command output process (FIG. 44) (step S2707: YES), or when the main RAM 74 ends. If the hour command flag is set to "1" (step S2708: YES), the process is executed in step S2709. As already described, when the game is started, the start command flag is set to "1" in step S1107 of the lottery result handling process (FIG. 25), and the end command flag is set to end the game. In this case, "1" is set in step S1508 of the corresponding processing (FIG. 32) at the end of the game.

In the common command transmission process, first, the highest level aggregation process is performed (step S2801). In the highest-order aggregation process, the data of "1" or "0" stored in the highest bit (seventh bit) of the storage area set to the addresses of "0001H" to "0006H" in the main RAM 74 is It is transferred to the 0th to 5th bits of the highest level aggregation area 74v. The address range of the storage area of the main-side RAM 74, which is the transfer source in the highest-level aggregation process (step S2801), is a continuous address range of "0001H" to "0006H". In the highest-order aggregation process, the storage areas set at addresses "0001H" to "0006H" are set as the transfer target range, and " "0" or "1" stored in the most significant bit in the transfer source storage area until the data of "0" or "1" is set in the 0th to 5th bits of the most significant aggregation area 74v. The process of transferring data to the transfer destination bit, the process of updating the transfer source storage area, and the process of updating the transfer destination bit are repeatedly executed. The address of the storage area of the transfer source is updated in the order of “0001H”→“0002H”→ . The update is performed in the order of bit -> . . . -> 4th bit -> 5th bit.

FIG. 51 is a flow chart showing the highest level aggregation process (step S2801) executed by the main MPU 72. As shown in FIG.

In the highest level aggregation process, the address of the highest level aggregation area 74v in the main side RAM 74 is set in the transfer destination counter 115 provided in the main side RAM 74 (step S2901). The transfer destination counter 115 is a counter that enables the main MPU 72 to grasp the data transfer destination. The transfer destination counter 115 is set with the address (2 bytes) of the storage area to which the data is to be transferred. By setting the address of the top-level aggregation area 74v in the transfer destination counter 115 in step S2901, the top-level aggregation area 74v can be set as the storage area of the transfer destination.

After that, the highest level aggregation area 74v is cleared to "0" (step S2902), and the value of the bit designation counter 117 provided in the main side RAM 74 is cleared to "0" (step S2903). The bit designation counter 117 is a counter that enables the main side MPU 72 to grasp the transfer destination bit in the transfer destination storage area (top-level aggregation area 74v). Any numerical value information from “0” to “5” is set in the bit designation counter 117 . By clearing the value of the bit designation counter 117 to "0" in step S2903, the 0th bit of the highest level aggregation area 74v can be set as the transfer destination bit.

Thereafter, "0001H", which is the start address of the address range of "0001H" to "0006H", which is the transfer target range in the highest-level aggregation process, is set in the transfer source counter 116 provided in the main RAM 74 (step S2904). The transfer source counter 116 is a counter that enables the main MPU 72 to grasp the address (2 bytes) of the storage area of the transfer source. By setting "0001H" to the transfer source counter 116 in step S2904, the lower area of the AT continuation counter 74u set to the address of "0001H" can be set as the transfer source storage area. Thereafter, "6" is set as the number of data transfers in the transfer number counter 114 (see FIG. 45) provided in the main RAM 74 (step S2905). The "6" is the number of storage areas existing in the transfer target range. The transfer number counter 114 counts the number of times the data stored in the storage area included in the transfer target range in the common command transmission process is transferred to the transmission standby buffer 112, and the number included in the transfer target range in the highest-level aggregation process. This is a counter that enables the main MPU 72 to grasp the number of times the data stored in the most significant bit of the stored storage area is transferred to the most significant aggregation area 74v. The transfer number counter 114 consists of 1 byte.

Thereafter, the most significant bit data in the transfer source storage area is transferred to the transfer destination bit (step S2906). As already explained, the main MPU 72 identifies the storage area of the transfer source based on the address stored in the transfer source counter 116, and based on the address stored in the transfer destination counter 115 and the value of the bit designation counter 117. to specify the destination bit. Thereafter, 1 is subtracted from the value of the transfer number counter 114 (step S2907), and it is determined whether or not the value of the transfer number counter 114 after the subtraction of 1 is "0" (step S2908).

If a negative determination is made in step S2908, the address of the transfer source storage area is updated by adding 1 to the value of the transfer source counter 116 in the main RAM 74 (step S2909). The processing from step S2906 to step S2910 is processing that is repeatedly executed until an affirmative determination is made at step S2908. , the address of the storage area of the transfer source is updated. After that, by adding 1 to the value of the bit designation counter 117 in the main RAM 74, the transfer destination bit in the highest aggregation area 74v is updated (step S2910). In step S2910, the transfer destination bits in the highest level aggregation area 74v are updated in the order of 0th bit→1st bit→...→4th bit→5th bit.

After that, the process proceeds to step S2906, and the processes of steps S2906 to S2910 are repeatedly executed until an affirmative determination is made in step S2908. As a result, the data "0" or "1" stored in the most significant bits of all the storage areas included in the transfer target range is set to the 0th to 5th bits of the most significant aggregation area 74v. be able to. If an affirmative determination is made in step S2908, this top-level aggregation processing ends.

In this way, the transfer target range in the highest-level aggregation process (FIG. 51) is the continuous address range of "0001H" to "0006H" in the main RAM 74. FIG. By repeatedly executing the process of adding 1 to the value of the transfer source counter 116 in the main RAM 74 (the process of step S2909), the storage area of the transfer source can be sequentially updated. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the range to be transferred in the top-level aggregation process (FIG. 51) is the continuous address range of "0001H" to "0006H" in the main RAM 74, the start address of the range to be transferred is stored in the transfer source counter 116 in step S2904. By setting "0001H", which is the number of transfers, to the transfer number counter 114 in step S2905, the transfer target range can be specified. This simplifies the processing configuration for designating the transfer target range.

Returning to the description of the common command transmission processing (FIG. 50), after executing the top-level aggregation processing (FIG. 51) in step S2801, the value of the write pointer 113 (see FIG. 45) provided in the transmission circuit 85 is grasped. By doing so, the write destination area in the transmission standby buffer 112 is grasped (step S2802). The write pointer 113 is set with data for specifying an area to which data is to be written among a plurality of areas existing in the transmission standby buffer 112 . Specifically, the write pointer 113 is set with any numerical value information from “0” to “31”.

Thereafter, it is determined whether or not the command flag at start of the main RAM 74 is set to "1" (step S2803). If the start command flag is set to "1" (step S2803: YES), that is, if it is time to start the game, data in the header HD corresponding to the start command stored in the main ROM 73 is set as the write destination area in the transmission standby buffer 112 grasped in step S2802 (step S2804), and the start command flag is cleared to "0" (step S2805). On the other hand, if the start command flag is not set to "1" (step S2803: NO), that is, if the game is over, the header HD corresponding to the end command stored in the main ROM 73 data is set in the write destination area in the transmission standby buffer 112 grasped in step S2802 (step S2806), and the end command flag of the main RAM 74 is cleared to "0" (step S2807).

If the process of step S2805 or step S2807 has been performed, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S2808). In step S2808, the value of the write pointer 113 is incremented by 1, and when the value of the write pointer 113 after the increment of 1 exceeds the maximum value of "31", the write pointer 113 is cleared to "0".

After that, in the main RAM 74, the start address of the transfer target range for transferring data to the transmission standby buffer 112 when transmitting the command at the start or the command at the end is set in the transfer source counter 116 of the main RAM 74 ( step S2809). The transfer target range in the common command transmission process (FIG. 50) is the address range from "0001H" to "000DH". By setting the address "0001H" in the transfer source counter 116 in step S2809, the lower area of the AT continuation counter 74u can be set as the transfer source storage area. After that, "13" is set in the transfer count counter 114 of the main RAM 74 (step S2810). The "13" is the number of 1-byte storage areas included in the address range of "0001H" to "000DH", which is the transfer target range.

After that, the write destination area of the transmission standby buffer 112 corresponding to the value of the write pointer 113 is grasped, the storage area of the transfer source is grasped based on the address set in the transfer source counter 116, and the transfer source storage area is grasped. The data in the storage area is transferred to the write destination area (step S2811). Thereafter, the most significant bit (seventh bit) in the write destination area is set to "0" (step S2812). As a result, the value of the most significant bit of the second to fourteenth frames FR2 to FR14 can be set to "0", and based on the value of the most significant bit, the header HD and the second to fourteenth frames FR2 to FR14 can be made identifiable.

After that, as in step S2808, the value of the write pointer 113 is updated (step S2813). Specifically, 1 is added to the value of the write pointer 113, and when the value of the write pointer 113 after the addition of 1 exceeds the maximum value of "31", the write pointer 113 is cleared to "0". Thereafter, 1 is subtracted from the value of the transfer number counter 114 in the main RAM 74 (step S2814), and it is determined whether or not the value of the transfer number counter 114 after the subtraction of 1 is "0" (step S2815).

If a negative determination is made in step S2815, that is, if the transfer of the data stored in the 1-byte storage area included in the transfer target range to the transmission standby buffer 112 has not ended, the transfer source By adding 1 to the value of the counter 116, the address of the transfer source storage area is updated (step S2816). The process of steps S2811 to S2816 is a process that is repeatedly executed until an affirmative determination is made in step S2815. ”, the address of the storage area to be the transfer source area is updated.

Thereafter, the process proceeds to step S2811, and the processes of steps S2811 to S2816 are repeatedly executed until an affirmative determination is made in step S2815. As a result, the data stored in all the 1-byte storage areas included in the transfer target range of addresses “0001H” to “000DH” can be set in the transmission standby buffer 112 . If an affirmative determination is made in step S2815, the data of the footer FT stored in the main ROM 73 is set in the write destination area corresponding to the value of the write pointer 113 in the transmission standby buffer 112 ( step S2817). After that, as in steps S2808 and S2813, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S2818), and the common command transmission processing ends. In step S2818, the value of the write pointer 113 is incremented by 1, and when the value of the write pointer 113 after the increment of 1 exceeds the maximum value of "31", the write pointer 113 is cleared to "0".

In this way, the transfer target range in the common command transmission process (FIG. 50) is the continuous address range from "0001H" to "000DH" in the main RAM 74. FIG. By repeatedly executing the process of adding 1 to the value of the transfer source counter 116 in the main RAM 74 (the process of step S2816), the storage area of the transfer source can be sequentially updated. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the transfer target range in the common command transmission process (FIG. 50) is the continuous address range of "0001H" to "000DH" in the main RAM 74, the start address of the transfer target range is set to the transfer source counter 116 in step S2809. is set to "0001H" and "13", which is the number of transfers, is set in the transfer number counter 114 in step S2810, thereby specifying the transfer target range. This simplifies the processing configuration for designating the transfer target range.

Next, the command reception handling process executed by the effect side MPU 92 will be described with reference to the flow chart of FIG. The command reception handling process is repeatedly executed in a relatively short cycle (for example, a cycle of 4 milliseconds) by the effect side MPU 92 .

In the command reception handling process, first, it is determined whether or not the data of the header HD is set in the post-reception waiting buffer 122 in the reception circuit 87 (step S3001). As already explained, the most significant bit (seventh bit) of the frame FRm (1-byte data) included in the various commands received by the effect-side MPU 92 from the main-side MPU 72 is set to "1". FRm is only the first frame FR1 in which the data of the header HD is set. In step S3001, an affirmative determination is made when there is a frame FRm in which "1" is set in the most significant bit.

If the data of the header HD is set in the waiting buffer 122 after reception (step S3001: YES), it is determined whether or not the data of the footer FT is set in the waiting buffer 122 after reception. command has been received (step S3002). If a negative determination is made in step S3002, it means that the command is being received, so this command reception handling process ends without executing the processes after step S3003.

If the data of the footer FT exists in the post-reception standby buffer 122 (step S3002: YES), it becomes an object to be moved from the post-reception standby buffer 122 to the pre-conversion area 124 of the effect-side RAM 94 or the command storage buffer 126. The head and tail of the command (hereinafter also referred to as "command to be moved") are grasped (step S3003). In step S3003, the head of the command to be moved is grasped based on the value of the read pointer 128 in the waiting buffer 122 after reception, and the tail of the command to be moved is grasped based on the data of the footer FT of the command to be moved. Grasp. When a plurality of commands are stored in the post-reception standby buffer 122, based on the value of the read pointer 128, the first command among the plurality of commands stored in the post-reception standby buffer 122 is the command to be moved. becomes.

After that, it is determined whether or not the data of the header HD of the start command is set in the command to be moved grasped in step S3003 (step S3004), and if the data of the header HD of the start command is set (Step S3004: YES) means that the command to be moved is the start command, so the start reception correspondence table is read from the effect side ROM 93 (step S3005). On the other hand, if the data of the header HD of the start command is not set (step S3004: NO), it is determined whether the data of the header HD of the end command is set to the command to be moved grasped in step S3003. (step S3006), and if the data of the header HD of the command at the end is set (step S3006: YES), it means that the command to be moved is the command at the end. The end reception correspondence table is read from the ROM 93 (step S3007).

If the process of step S3005 or step S3007 has been performed, the top setting process is executed (step S3008). In the highest level setting process, "0" or "1" set in the 0th to 5th bits of the highest level aggregated frame SF (eighth frame FR8) included in the received start time command or end time command ” are set in the most significant bits of the second to seventh frames FR2 to FR7 corresponding to the 0th to 5th bits. FIG. 53 is a flow chart showing the highest level setting process (step S3008).

In the highest-level setting process, the first to fifteenth frames FR1 to FR15 of the start command or the end command, which are commands to be moved in the post-reception waiting buffer 122, are transferred to the first to first frames of the pre-conversion area 124 in the effect-side RAM 94. 15 areas RA1 to RA15 are set (step S3101). As a result, the top aggregated frame SF is set in the eighth area RA8 in both cases in which the start command is set in the pre-conversion area 124 and the end command is set in the pre-conversion area 124. state.

After that, the post-reception standby buffer 122 is cleared (step S3102). In the post-reception standby buffer 122 clearing process, the area in which the start command or the end command, which is the command to be moved, was stored in the post-reception standby buffer 122 is cleared to "0". As a result, an empty area for storing the next command can be secured in the waiting buffer 122 after reception. After that, the value of the read pointer 128 in the standby buffer 122 after reception is updated to the value corresponding to the storage area next to the storage area in which the last command (data of the footer FT) of the start command or end command was stored. (Step S3103).

Thereafter, the address (2 bytes) of the eighth area RA8 of the pre-conversion area 124 is set in the effect-side transfer source counter provided in the effect-side RAM 94 (step S3104). The performance-side transfer source counter is a counter that enables the performance-side MPU 92 to grasp the storage area of the data transfer source. The production side transfer source counter consists of 2 bytes. By setting the address of the eighth area RA8 in the effect side transfer source counter in step S3104, the eighth area RA8 in which the highest aggregated frame SF is set can be used as the transfer source storage area.

Thereafter, the value of the effect side bit designation counter provided in the effect side RAM 94 is cleared to "0" (step S3105). The effect side bit designation counter is a counter that enables the effect side MPU 92 to grasp the transfer source bit in the transfer source storage area. The production side bit designation counter consists of 1 byte. By clearing the value of the effect side bit designation counter to "0" in step S3105, the 0th bit in the eighth area RA8 of the pre-conversion area 124 can be used as the transfer source bit.

Thereafter, the address (2 bytes) of the second area RA2 in the pre-conversion area 124 is set in the effect-side transfer destination counter provided in the effect-side RAM 94 (step S3106). The performance-side transfer destination counter is a counter that enables the performance-side MPU 92 to grasp the storage area of the transfer destination. The production side transfer destination counter consists of 1 byte. By setting the address of the second area RA2 in the effect-side transfer destination counter in step S3106, the second area RA2 can be used as the transfer destination storage area.

After that, the data "0" or "1" stored in the transfer source bit is transferred to the most significant bit in the transfer destination storage area (step S3107). As already explained, the effect-side MPU 92 specifies the transfer source storage area based on the address stored in the effect-side transfer source counter, and specifies the transfer source storage area based on the value of the effect-side bit designation counter. Specifies the source bit in . Also, the effect-side MPU 92 specifies the storage area of the transfer destination based on the address stored in the effect-side transfer destination counter.

After that, by determining whether or not the value of the effect side bit designation counter is "5", the transfer source bit is the 5th bit of the 8th area RA8 in the pre-conversion area 124, and the data is transferred in step S3107. is performed (step S3108). When a negative determination is made in step S3108, the transfer source bit in the eighth area RA8 of the pre-conversion area 124 is updated by adding 1 to the value of the effect side bit designation counter (step S3109). The processing from step S3107 to step S3110 is processing that is repeatedly executed until an affirmative determination is made at step S3108. , the source bit in the eighth area RA8 is updated.

After that, the address of the transfer destination storage area in the pre-conversion area 124 is updated by adding 1 to the effect side transfer destination counter (step S3110). In step S3110, in the pre-conversion area 124, the transfer destination storage areas are updated in the order of second area RA2→third area RA3→fourth area RA4→fifth area RA5→sixth area RA6→seventh area RA7. be done.

If the transfer source bit and the transfer destination storage area are updated in steps S3109 and S3110, the process advances to step S3107, and the processes of steps S3107 to S3110 are repeatedly executed until an affirmative determination is made in step S3108. . As a result, data aggregated into the 0th to 5th bits of the highest aggregated frame SF before transmission of the command at the start or the command at the end in the main MPU 72 is transferred to the highest bits of the corresponding 2nd to 7th frames FR2 to FR7. can be returned to If an affirmative determination is made in step S3108, the highest setting processing is terminated.

In this way, in the highest order setting process (FIG. 53), the data "0" or "1" stored in the 0th to 5th bits of the highest order aggregated frame SF are set to the highest order bit. The address of RA7 is a continuous address range from "α+2" to "α+7". By repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S3110), the transfer destination storage area can be sequentially updated. This simplifies the processing configuration for sequentially updating the transfer destination storage area.

The value of the effect-side bit designation counter in the effect-side RAM 94 is the data "0" or "1" stored in any of the 0th to 5th bits of the highest aggregate frame SF to the maximum value in the storage area of the transfer destination. One is added each time the process of transferring to the upper bit (the process of step S3107) is executed. Therefore, by referring to the value of the rendering-side bit designation counter, the data "0" or "1" set in any of the 0th to 5th bits of the highest aggregated frame SF can be changed to the 0th to 5th bits. It is possible to grasp the number of times of transfer to the second to seventh frames FR2 to FR7 corresponding to any of the fifth bits. As a result, it is possible to simplify the processing configuration for ascertaining the number of transfers by the effect-side MPU 92 .

Returning to the description of the command reception handling process (FIG. 52), after executing the highest level setting process in step S3008, the command conversion process is executed (step S3009). If the command received this time is a start command, in the command conversion processing in step S3009, among the data stored in the pre-conversion area 124, the header HD data, the footer FT data, and the data sent to the effect-side MPU 92 at the start of the game. By extracting the data to be used and transferring them to the first to seventh areas RB1 to RB7 of the post-conversion area 125, the post-conversion start command is set in the post-conversion area 125. FIG. On the other hand, if the command received this time is an end command, in the command conversion processing in step S3009, among the data stored in the pre-conversion area 124, the header HD data, the footer FT data, and the effect side command at the end of the game. By extracting the data to be used by the MPU 92 and transferring it to the post-conversion area 125 , the post-conversion end command is set in the post-conversion area 125 . FIG. 54 is a flow chart showing command conversion processing (step S3009) executed by the effect side MPU 92. FIG.

In the command conversion process, first, the address ("α+1") of the first area RA1 in the pre-conversion area 124 is set in the effect-side transfer source counter (step S3201). As a result, the first area RA1 of the pre-conversion area 124 can be used as the transfer source storage area. After that, the address ("β+1") of the first area RB1 in the post-conversion area 125 is set in the effect-side transfer destination counter (step S3202). As a result, the first area RB1 in the post-conversion area 125 can be used as the transfer source storage area. After that, the data stored in the transfer source storage area is transferred to the transfer destination storage area (step S3203). As already explained, the effect-side MPU 92 can specify the transfer source storage area based on the address stored in the effect-side transfer source counter, and can specify the transfer source storage area based on the address stored in the effect-side transfer destination counter. can be used to specify the storage area of the transfer destination.

Thereafter, it is determined whether or not the transfer source storage area is the fifteenth area RA15 in the pre-conversion area 124 (step S3204). At step S3204, affirmative determination is made when the address ("α+15") of the fifteenth area RA15 in the pre-conversion area 124 is stored in the performance-side transfer source counter. The fifteenth area RA15 is provided in the footer FT regardless of whether the command set in the pre-conversion area 124 is the start command or the end command is set in the pre-conversion area 124. This is the area where data is set.

If a negative determination is made in step S3204, that is, if the conversion of the command has not been completed, 1 is added to the effect side transfer source counter to update the address of the transfer source storage area (step S3205). ). The processing from step S3205 to step S3206 is processing that is repeatedly executed until a negative determination is made at step S3206. Update the address of the storage area of the transfer source. As a result, the transfer source storage areas in the pre-conversion area 124 are updated in the order of the first area RA1→second area RA2→fourteenth area RA14→fifteenth area RA15.

After that, referring to the read start reception correspondence table or end reception correspondence table, it is determined whether or not the transfer source storage area updated in step S3205 is an exclusion target area (step S3206). ). As already explained, the start reception correspondence table stores the fourth to seventh areas RA4 to RA7 in which the third to sixth frames FR3 to FR6 are stored and the highest aggregated frame SF as areas to be excluded. An eighth area RA8 is set, and twelfth to fourteenth areas RA12 to RA14 are set to store tenth to twelfth frames FR10 to FR12. In addition, in the termination reception correspondence table, the second and third areas RA2 and RA3 in which the first and second frames FR1 and FR2 are stored, and the highest aggregated frame SF are stored as areas to be excluded. An eighth area RA8 and ninth to tenth areas RA9 to RA10 storing seventh to eighth frames FR7 to FR8 are set.

If an affirmative determination is made in step S3206, the process advances to step S3205, and the processes of steps S3205 to S3206 are repeatedly executed until a negative determination is made in step S3206. As a result, even when areas to be excluded exist consecutively in the pre-conversion area 124, the data stored in the consecutive areas to be excluded are transferred to the post-conversion area 125. You can prevent it from slipping.

When a negative determination is made in step S3206, the address of the transfer destination storage area is updated by adding 1 to the value of the performance side transfer destination counter (step S3207). The processing from step S3203 to step S3207 is processing that is repeatedly executed until an affirmative determination is made at step S3204. , update the address of the storage area of the transfer source. As a result, in the post-conversion area 125, the transfer destination storage areas are updated in the order of the first area RB1→second area RB2→...→ninth area RB9→tenth area RB10. After that, the process proceeds to step S3203, and the processes of steps S3203 to S3207 are repeatedly executed until an affirmative determination is made in step S3204. As a result, of the data set in the pre-conversion area 124 , the data set in areas not subject to exclusion are transferred to the post-conversion area 125 , and the post-conversion start time command or the post-conversion end time command is transferred to the post-conversion area 125 . A command can be set. If an affirmative determination is made in step S3204, that is, if command conversion is completed, this command conversion process is terminated.

In this way, the update of the transfer source storage area in the pre-conversion area 124 is performed in a manner excluding areas to be excluded. On the other hand, when the transfer destination storage area in the post-conversion area 125 is updated, the storage area set next to the current transfer destination storage area in the post-conversion area 125 becomes the post-update transfer destination storage area. is done in As a result, when a start command is received, data to be used by the effect-side MPU 92 at the start of the game can be extracted from the start command and set as the post-conversion start command. is received, the data to be used by the effect side MPU 92 at the end of the game can be extracted from the command at the end and set as the command at the end after conversion.

Returning to the description of the command reception handling process (FIG. 52), after executing the command conversion process in step S3009, by grasping the value of the second write pointer 129 (see FIG. 45) provided in the effect side RAM 94 The write destination area in the command storage buffer 126 is grasped (step S3010). The second write pointer 129 is set with data for specifying an area to which data is to be written among the plurality of areas existing in the command storage buffer 126 . Specifically, the second write pointer 129 is set with any numerical value information from “0” to “31”.

Thereafter, the post-conversion start command or the post-conversion end command stored in the post-conversion area 125 is set in the write destination area in the command storage buffer 126 ascertained in step S3010 (step S3011). As a result, the post-conversion start time command or the post-conversion end time command is stored in the command storage buffer 126, and the effect side MPU 92 can use the post-conversion start time command or the post-conversion end time command. can do.

After that, the value of the second write pointer 129 is updated (step S3012). In step S3012, when the data of the post-conversion start command is written in the command storage buffer 126 in step S3011, the value of the second write pointer 129 is incremented by "7", which is the data capacity of the post-conversion start command. If the data of the post-conversion end command is written in the command storage buffer 126 in step S3011, the value of the second write pointer 129 is incremented by "10", which is the data capacity of the post-conversion end command. In step S3012, if the calculation result of adding "7" or "10" exceeds the maximum value of "63", a value smaller than the calculation result by "64" is set in the second write pointer 129. be in a state where For example, if the calculation result of adding "7" or "10" is "64" which exceeds the maximum value "63", "0" which is "64" less than the calculation result ("64") is set in the second write pointer 129 .

After that, if the command stored in the command storage buffer 126 in step S3011 is the post-conversion start time command (step S3013: YES), the start time reception flag provided in the production side RAM 94 is set to "1" ( step S3014). The reception flag at the start is a flag that enables the production side MPU 92 to grasp that the command at the start has been received from the main side MPU 72 . By setting the start reception flag to "1" in step S3014, the processes after step S3302 are executed in the start reception handling process (FIG. 55) to be described later.

If the command stored in the command storage buffer 126 in step S3011 is not the post-conversion start command (step S3013: NO), that is, if the command stored in the command storage buffer 126 in step S3011 is the post-conversion end command , "1" is set to the completion reception flag provided in the effect side RAM 94 (step S3015). The termination time reception flag is a flag that enables the production side MPU 92 to grasp that the termination time command has been received from the main side MPU 72 . By setting "1" to the reception flag at the end in step S3015, the processes after step S3502 are executed in the reception at the end processing (FIG. 57) to be described later. If the process of step S3014 or step S3015 has been performed, the pre-conversion area 124 and post-conversion area 125 are cleared to "0" (step S3016), and this command reception handling process ends.

If the command recognized as the command to be moved in step S3003 is neither the start command nor the end command (step S3004: NO, step S3006: NO), the command to be moved is the winning result command. It is determined whether or not data in the header HD indicating that is set (step S3017). When the data of the header HD indicating that the command to be moved is a winning result command is set (step S3017: YES), the command is stored by grasping the value of the second write pointer 129 in the effect side RAM 94. The write destination area in the buffer 126 is grasped (step S3018), and the winning result command stored in the waiting buffer 122 after reception is set in the write destination area in the command storage buffer 126 grasped in step S3018 (step S3019). ). As a result, the winning result command is stored in the command storage buffer 126, so that the effecting MPU 92 can use the winning result command.

After that, the value of the second write pointer 129 is updated (step S3020). At step S3020, the value of the second write pointer 129 is incremented by "5", which is the data capacity of the winning result command written to the command storage buffer 126 at step S3019. In step S3020, when the calculation result of the calculation for adding "5" exceeds the maximum value "63", a value smaller than the calculation result by "64" is set in the second write pointer 129. . For example, when the calculation result of adding "5" is "64" which exceeds the maximum value "63", "0" which is "64" smaller than the calculation result ("64") is the second write. It is assumed that the pointer 129 is set.

After that, the post-reception waiting buffer 122 is cleared (step S3021). In the clearing process of the post-reception standby buffer 122 in step S3021, the area in which the winning result command was stored in the post-reception standby buffer 122 is cleared to "0". As a result, an empty area for storing the next command can be secured in the waiting buffer 122 after reception. After that, the value of the read pointer 128 in the waiting buffer 122 after reception is updated to the value corresponding to the area next to the area in which the end of the winning result command (data of the footer FT) was stored (step S3022).

After that, the winning result reception flag provided in the effect-side RAM 94 is set to "1" (step S3023), and this command reception handling process is terminated. The winning result reception flag is a flag that allows the production side MPU 92 to grasp that the winning result command has been received. When the winning result reception flag is set to "1" in step S3023, the processes after step S3402 are executed in the later-described winning result reception handling process (FIG. 56).

If a negative determination is made in step S3017, other command reception handling processing is executed (step S3024), and this command reception handling processing ends. In the other command reception processing in step S3024, first, the value of the second write pointer 129 in the effect-side RAM 94 is grasped to grasp the write destination area in the command storage buffer 126. command (for example, a power recovery command) is set as a command to be moved. After that, similarly to steps S3012 and S3020, the value of the second write pointer 129 is updated. After that, the area in which the command to be moved was stored in the waiting buffer 122 after reception is cleared to "0". As a result, an empty area for storing the next command can be secured in the waiting buffer 122 after reception. After that, the value of the read pointer 128 in the waiting buffer 122 after reception is updated to the value corresponding to the area next to the area in which the end of the command to be moved (data of the footer FT) was stored.

Next, the start reception handling process executed by the effect side MPU 92 will be described with reference to the flow chart of FIG. The receiving process at the start is repeatedly executed in a relatively short cycle (for example, a cycle of 4 milliseconds) by the effect side MPU 92 .

In the start reception handling process, if the start reception flag of the effect-side RAM 94 is set to "1" (step S3301: YES), the post-conversion start time command stored in the command storage buffer 126 is set. The data of the bet number setting counter 74b is set in the effect side bet number counter provided in the effect side RAM 94 (step S3302). The production side bet number counter is a counter that allows the production side MPU 92 to grasp the number of bets (“2” or “3”) for the current game. By setting the data of the bet number setting counter 74b set in the post-conversion start time command in step S3302 to the production side bet number counter, the production side MPU 92 can grasp the bet number of this game. can be done.

After that, the current game state is grasped (step S3303). The production side RAM 94 stores a production side first CB state flag, a production side second CB state flag, a production side pseudo bonus state flag, a production side AT state flag, a production side end preparation state flag, a first CB internal state flag, and a second CB internal state. A flag is provided. The effect-side first CB state flag is a flag that enables the effect-side MPU 92 to grasp that the game state is the first CB state ST2, and the effect-side second CB state flag is the effect that the game state is the second CB state ST3. The effect-side pseudo-bonus state flag is a flag that enables the effect-side MPU 92 to grasp that the game state is the pseudo-bonus state ST4, and the effect-side AT state flag is the game. It is a flag that enables the production side MPU 92 to grasp that the state is the AT state ST5, and the production side end preparation state flag is a flag that enables the production side MPU 92 to grasp that the game state is the end preparation state ST6. The first CB internal state flag is a flag that enables the production side MPU 92 to grasp that it is the first CB internal state in which the corresponding first CB winning has not been established after the occurrence of the first CB winning, and the second CB internal state. The flag is a flag that makes it possible for the effect-side MPU 92 to grasp that the second CB is in an internal state in which the corresponding second CB winning has not been established after the occurrence of the second CB winning. In step S3303, when the effect side first CB state flag is set to "1", it is grasped that it is the first CB state ST2, and when the effect side second CB state flag is set to "1", the 2 CB state ST3 is grasped, and when the production side pseudo bonus state flag is set to "1", it is grasped that it is a pseudo bonus state ST4, and "1" is set to the production side AT state flag. When it is in the AT state ST5, it is grasped that it is in the AT state ST5, and when the effect side end preparation state flag is set to "1", it is grasped that it is in the end preparation state ST6. Also, when the values of these five flags are all "0", it is understood that the game state is the normal game state ST1. Furthermore, when the first CB internal state flag is set to "1", it is recognized that it is in the first CB internal state, and when the second CB internal state flag is set to "1", the second CB internal state is detected. understand the state.

After that, an effect start process is executed (step S3304). In the effect start process, the upper lamp 61, the speaker 62 and the image display device 63 are used to execute the effect corresponding to the game state grasped in step S3303 and the bet number set in the effect side bet number counter in step S3302. A performance data table is read out from the performance side ROM 93 . Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read performance data table. In the effect start processing in step S3304, when the ending period flag provided in the effect side RAM 94 is set to "1", the effect data table for executing the effect corresponding to the ending period is read from the effect side ROM 93. The ending period flag is a flag that enables the effect-side MPU 92 to grasp that the ending effect of the second section SC2 is being executed. The ending period flag is set to "1" in step S3608 of the second section corresponding processing (FIG. 58) described later.

In the effect start process in step S3304, if the gaming state is the pseudo-bonus state ST4, it is provided in the effect-side RAM 94 on the condition that the value of the number-of-continued-game non-display flag provided in the effect-side RAM 94 is "0". The number of remaining continuous games in the pseudo-bonus state ST4 is grasped by referring to the pseudo-bonus state counter on the effecting side, and display data for displaying the grasped remaining number of continuing games on the image display device 63 is displayed as an image. Output to the display device 63 . The number-of-continued-games non-display flag is a flag that enables the effect-side MPU 92 to grasp that the display indicating the number of remaining continued games in the pseudo-bonus state ST4 is not executed. When the pseudo-bonus state ST4 is started in a state in which one of the ending flags 76b and 76c in the main RAM 74 is set to "1", the pseudo-bonus state handling process, which will be described later, is set to the number-of-continued-games non-display flag. "1" is set in step S3707 (FIG. 59). The effect-side pseudo-bonus continuation counter is a counter that enables the effect-side MPU 92 to grasp the remaining number of continuous games in the pseudo-bonus state ST4. Data of the pseudo-bonus continuation counter 74t, which is set in the post-conversion termination command, is set in steps S3704 and S3709 of the pseudo-bonus state handling process (FIG. 59) described later. be. The number of continuous games in the second section SC2 is equal to or greater than the reference number of games (specifically "1450"), or the total net increase in number of game media with restrictions in the second section SC2 is the reference acquisition number (specifically "2150") or more, in the case of shifting to the pseudo-bonus state ST4, the continuation of the second section SC2 is performed before the remaining number of continuous games in the pseudo-bonus state ST4 becomes "0". The number of games reaches the upper limit number of games (specifically "1500") or the total number of net additions with restrictions on the number of game media in the second section SC2 reaches the upper limit number of net additions (specifically "2400") Therefore, the pseudo-bonus state ST4 may end with the end of the second section SC2. In this case, by not displaying the number of remaining games to be continued in the pseudo-bonus state ST4, the pseudo-bonus state ST4 ends when the ending condition of the second section SC2 is satisfied. It is possible to prevent the player from feeling uncomfortable.

In the effect start process in step S3304, when the game state is the AT state ST5, by referring to the effect-side AT continuation counter provided in the effect-side RAM 94, the number of remaining continuous games in the AT state ST5 is grasped, Display data for displaying the grasped remaining number of continuous games on the image display device 63 is output to the image display device 63 . The effect-side AT continuation counter is a counter that allows the effect-side MPU 92 to grasp the number of remaining continuous games in the AT state ST5. The AT continuation counter on the effect side is set with the data of the AT continuation counter 74u, which is set in the post-conversion termination command in steps S3807 and S3812 of the AT state handling process (FIG. 60) described later.

After that, by referring to the effect side AT state flag, it is determined whether or not the game state is AT state ST5 (step S3305), and if the game state is AT state ST5 (step S3305: YES), the effect The value of the AT continuation counter on the effect side in the side RAM 94 is grasped (step S3306). After that, the value of the AT continuation counter 74u is grasped based on the data of the AT continuation counter 74u set in the post-conversion start time command (step S3307). After that, it is determined whether or not the number of remaining games to be continued in the AT state ST5 has been increased (step S3308). In step S3308, the value of the AT continuation counter 74u grasped in step S3307 is calculated to subtract the value of the effect side AT continuation counter grasped in step S3306. It is determined that an addition has occurred (step S3308: YES). As already explained, there are "10", "20" and "50" as the number of games to be added in the addition lottery for the remaining number of continuous games in the AT state ST5.

If an extra win has occurred (step S3308: YES), the number of extra winning games that have occurred this time is grasped based on the result of the computation performed in step S3308 (step S3309). After that, an additional effect setting process is executed (step S3310). In the add-on effect setting process, the effect data table for executing the add-on effect corresponding to the number of add-on games grasped in step S3309 on the image display device 63 is read from the effect-side ROM 93 . Then, display control of the image display device 63 is executed according to the read effect data table. When the additional effect is executed, a cut-in image corresponding to the number of additional games is displayed on the image display device 63 during execution of the effect started in the effect start process in step S3304. As a result, the player is notified of the number of additional games.

If a negative determination is made in step S3308, or if the process of step S3310 is performed, the data of the AT continuation counter 74u set in the post-conversion start time command is set in the AT continuation counter on the production side ( step S3311). As a result, the effect-side MPU 92 can grasp the number of remaining continuous games in the AT state ST5.

If the game state is not the AT state ST5 (step S3305: NO), it is determined whether or not the game state is the pseudo bonus state ST4 by referring to the effect-side pseudo-bonus state flag (step S3312). When the gaming state is the pseudo bonus state ST4 (step S3312: YES), it is determined whether or not the effect executed flag provided in the effect side RAM 94 is set to "1" (step S3313). The effect executed flag is a flag for making it possible for the effect side MPU 92 to grasp whether or not the AT transition fixed effect has already been executed in the present pseudo bonus state ST4. The effect executed flag is cleared to "0" at step S3715 of the pseudo-bonus state handling process (FIG. 59) to be described later when the pseudo-bonus state ST4 ends.

If "1" is not set to the effect executed flag (step S3313: NO), the AT transition confirmation flag 77f included in the data of the gaming state area 77 set in the post-conversion start time command Based on the data, it is determined whether or not the transition to the AT state ST5 is confirmed (step S3314), and if the transition to the AT state ST5 is confirmed (step S3314: YES), the AT transition confirmation effect is set. Processing is executed (step S3315). In the setting processing of the AT transition confirmation effect, the effect data table for executing the AT transition confirmation effect notifying that the transition to the AT state ST5 is confirmed is read from the effect side ROM 93 . Then, display control of the image display device 63 is started according to the read effect data table. When the AT transition confirmation effect is executed, a cut-in image notifying that the transition to the AT state ST5 is confirmed is displayed on the image display device 63 during the execution of the effect started in step S3304. As a result, the player can be notified that the transition to the AT state ST5 has been confirmed. After that, "1" is set to the effect executed flag of the effect side RAM 94 (step S3316). As a result, it is possible to prevent the AT shift finalization effect from being executed twice or more in duplicate until the current pseudo-bonus state ST4 ends.

When the process of step S3311 is executed, when the affirmative determination is made in step S3313, when the negative determination is made in step S3314, or when the process of step S3316 is performed, the image display device 63 It is determined whether or not the game is a game in which stop order notification for notifying the stop order of 32L, 32M, and 32R is performed (step S3317). In step S3317, the value of the stop order type counter 74m is grasped based on the data of the stop order type counter 74m set in the post-conversion start time command, and the value of the stop order type counter 74m is changed from "1" to "9". , it is determined that the game is a game in which stop order notification is executed (step S3317: YES). As already explained, in the game in which the image display device 63 notifies the stop order, one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m, and the image display device 63 The value of the stop order type counter 74m becomes "0" in the game in which the stop order notification is not performed at .

If the game is one in which stop order notification is executed by the image display device 63 (step S3317: YES), the game is executed by the image display device 63 based on the value of the stop order type counter 74m ascertained in step S3317. The type of stop order notification is grasped (step S3318), and stop order notification start processing is executed (step S3319). In the stop order notification start processing, the notification data table for executing the stop order notification of the type ascertained in step S3318 on the image display device 63 is read from the effect-side ROM 93 . Then, the display control of the image display device 63 is started according to the read notification data table.

If a negative determination is made in step S3312, if a negative determination is made in step S3317, or if the process of step S3319 is performed, the reception flag at the start of the effect side RAM 94 is cleared to "0" ( Step S3320), the start-time reception handling process is terminated.

In this way, the effect-side MPU 92 converts the start time command received from the main side MPU 72 into the converted start time command, and performs processing for executing the effect of the game started this time based on the converted start time command. to run. As already explained with reference to FIG. 47(b), in the after-conversion start command, the data of the AT continuation counter 74u, the bet number setting counter 74b, the stop order type counter 74m and the game state area 77 in the main side RAM 74 are included. is set. When the start command is received, the data of the AT continuation counter 74u, the bet number setting counter 74b, the stop order type counter 74m, and the game state area 77 can be used. Compared to the configuration in which the data of the number setting counter 74b, the stop order type counter 74m, and the game state area 77 are received by two or more commands, the number of command transmissions from the main side MPU 72 to the effect side MPU 92 can be reduced. can. As a result, the processing load for the master side MPU 72 to transmit commands to the effect side MPU 92 can be reduced, and the processing load when the effect side MPU 92 executes the processing corresponding to the command received from the master side MPU 72 can be reduced. can be mitigated.

Next, the winning result reception handling process executed by the effect side MPU 92 will be described with reference to the flowchart of FIG. The winning result reception handling process is repeatedly executed by the effect side MPU 92 at a relatively short cycle (for example, a cycle of 4 milliseconds).

In the winning result reception handling process, when the winning result reception flag of the effect-side RAM 94 is set to "1" (step S3401: YES), the winning result command stored in the command storage buffer 126 is set to Based on the data in the 1CB winning data area 74j, it is determined whether or not the first CB winning data is set in the main RAM 74 (step S3402). When the first CB winning data is set (step S3402: YES), based on the data in the winning data area 78 in the main RAM 74 set in the winning result command, the first CB winning data It is determined whether or not the corresponding first CB winning has been established (step S3403), and if the first CB winning has not been established (step S3403: NO), the first CB internal state flag in the effect side RAM 94 is set to "1". is set (step S3404). As a result, the effect-side MPU 92 can be made aware of the internal state of the first CB. On the other hand, when the first CB winning is established (step S3403: YES), the first CB internal state flag in the effect-side RAM 94 is cleared to "0" (step S3405). As a result, the effect-side MPU 92 can grasp that the internal state of the first CB has ended.

If a negative determination is made in step S3402, the second CB winning data is stored in the main RAM 74 based on the data in the second CB winning data area 74k set in the winning result command stored in the command storage buffer 126. is set (step S3406). When the second CB winning data is set (step S3406: YES), based on the data in the winning data area 78 in the main RAM 74 set in the winning result command, the second CB winning data It is determined whether or not the corresponding second CB winning has been established (step S3407), and if the second CB winning has not been established (step S3407: NO), the second CB internal state flag in the effect side RAM 94 is set to "1". is set (step S3408). As a result, the effect-side MPU 92 can be made aware of the internal state of the second CB. On the other hand, when the second CB winning is established (step S3407: YES), the second CB internal state flag in the effect-side RAM 94 is cleared to "0" (step S3409). As a result, the effect-side MPU 92 can grasp that the internal state of the second CB has ended.

When the process of step S3404 is performed, when the process of step S3405 is performed, when a negative determination is performed in step S3406, when the process of step S3408 is performed, or when the process of step S3409 is performed, The winning result reception flag of the effect-side RAM 94 is cleared to "0" (step S3410), and the main winning result reception handling process ends.

Next, the termination reception handling process executed by the effect side MPU 92 will be described with reference to the flow chart of FIG. The termination reception handling process is repeatedly executed in a relatively short cycle (for example, a cycle of 4 milliseconds) by the effect side MPU 92 .

In the reception processing at the end, when the reception flag at the end of the effect side RAM 94 is set to "1" (step S3501: YES), the second section corresponding processing is executed (step S3502). FIG. 58 is a flow chart showing the second section handling process (step S3502).

In the second section corresponding process, it is determined whether or not the effect side second section flag provided in the effect side RAM 94 is set to "1" (step S3601). The effect side second section flag is a flag that enables the effect side MPU 92 to grasp that the game section is the second section SC2. If "1" is not set in the effect-side second section flag (step S3601: NO), the data of the game section area 76 set in the post-conversion termination command stored in the command storage buffer 126 Based on the data of the second section flag 76a included in , it is determined whether or not the game section is the second section SC2 (step S3602). When the effect side second section flag is not set to "1" and the second section flag 76a of the main side RAM 74 is set to "1" (step S3601: NO, step S3602: If YES), it means that it is time to start the second section SC2, so the effect-side second section flag is set to "1" (step S3603). As a result, the effect-side MPU 92 can grasp that the game section is the second section SC2.

If an affirmative determination is made in step S3601, similar to step S3602, based on the data of the second section flag 76a included in the data of the game section area 76 set in the post-conversion end command , determines whether or not the game section is the second section SC2 (step S3604). If an affirmative determination is made in step S3604, that is, if the current game is executed in a state where the game section is the second section SC2, and the second section SC2 continues even after the end of the current game, an effect It is determined whether or not the ending period flag in the side RAM 94 is set to "1" (step S3605). As already explained, the ending period flag is a flag that enables the effect-side MPU 92 to grasp that the ending effect of the second section SC2 is being executed.

If a negative determination is made in step S3605, based on the data of the first ending flag 76b and the second ending flag 76c included in the data of the game section area 76 set in the post-conversion end command , and determines whether or not "1" is set in any of the ending flags 76b, 76c in the main RAM 74 (step S3606). If one of the ending flags 76b, 76c is set to "1" (step S3606: YES), the AT state included in the data of the game state area 77 set in the post-conversion end command Based on the data of the flag 77d, it is determined whether or not it is in the AT state ST5 (step S3607). If it is in the AT state ST5 (step S3607: YES), the ending period flag of the effect-side RAM 94 is set to "1" (step S3608), and the process for the second section ends. By setting the ending period flag to "1", it is possible to start the effect for the ending period in the effect start process in step S3304 of the start reception handling process (FIG. 55) already described. On the other hand, if it is not the AT state ST5 (step S3607: NO), the ending wait flag provided in the effect side RAM 94 is set to "1" (step S3609), and the second section corresponding processing is terminated. The ending standby flag is a flag that allows the effect-side MPU 92 to grasp that the effect of the ending period should be started at the timing of shifting to the AT state ST5. If the ending wait flag is set to "1" in step S3609, the effect of the ending period is started at the timing of shifting to the AT state ST5.

When the effect side second section flag is set to "1" and the second section flag 76a is not set to "1" (step S3601: YES, step S3604: NO) , it means that it is the end timing of the second section SC2, so a second section initialization effect setting process is executed (step S3610). In the setting process of the second section initialization effect, display data for performing display corresponding to the initialization of the second section SC2 on the image display device 63 is output to the image display device 63 . After that, the effect side second section flag is cleared to "0" (step S3611). As a result, the effect-side MPU 92 can grasp that the game section has become the first section SC1. After that, the ending period flag of the effect-side RAM 94 is cleared to "0" (step S3612), and the process for the second interval ends. At step S3612, the ending period flag is cleared to "0" so that the effect for the ending period is not executed.

Returning to the explanation of the termination reception handling process (FIG. 57), after the second section handling process is executed in step S3502, the pseudo bonus state handling process is executed (step S3503). FIG. 59 is a flow chart showing pseudo-bonus state handling processing.

In the pseudo-bonus state handling process, if the effect-side pseudo-bonus state flag in the effect-side RAM 94 is not set to "1" (step S3701: NO), the data in the game state area 77 set in the post-conversion termination command is displayed. Based on the data of the pseudo-bonus state flag 77c included in , it is determined whether or not it is the pseudo-bonus state ST4 (step S3702). When the effect side pseudo-bonus state flag is not set to "1" and the pseudo-bonus state flag 77c of the main side RAM 74 is set to "1" (step S3701: NO, step S3702: If YES), it means that it is time to shift to the pseudo-bonus state ST4, so the setting processing of the pseudo-bonus state start effect is executed (step S3703). In the process of setting the pseudo-bonus state start effect, the effect data table for executing the pseudo-bonus state start effect indicating the transition to the pseudo-bonus state ST4 by the upper lamp 61, the speaker 62 and the image display device 63 is stored in the effect-side ROM 93. read from Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read performance data table.

Thereafter, the data of the pseudo-bonus continuation counter 74t set in the post-conversion termination command is set in the pseudo-bonus continuation counter on the performance side provided in the performance-side RAM 94 (step S3704). As already explained, the effect-side pseudo-bonus continuation counter is a counter that allows the effect-side MPU 92 to grasp the remaining number of continuous games in the pseudo-bonus state ST4. The pseudo-bonus continuation counter on the effect side is used to display the remaining number of continuous games in the pseudo-bonus state ST4 on the image display device 63 in the effect start process in step S3304 of the already-described start reception handling process (FIG. 55). Referenced when executing a process. Thereafter, "1" is set to the effect side pseudo bonus state flag in the effect side RAM 94 (step S3705). As a result, the effect-side MPU 92 can grasp that the game state is the pseudo-bonus state ST4 and the game section is the pseudo-bonus state ST4.

After that, based on the data of the first ending flag 76b and the second ending flag 76c included in the data of the game section area 76 set in the post-conversion end command, one of the ending flags 76b and 76c is set to " 1” is set (step S3706). When at least one of the first ending flag 76b and the second ending flag 76c in the main RAM 74 is set to "1" (step S3706: YES), the continuous game count non-display flag in the effect RAM 94 is set to "1". ” is set (step S3707). As already explained, the number-of-continued-games non-display flag is a flag that enables the effect-side MPU 92 to grasp that the display indicating the number of remaining continued games in the pseudo-bonus state ST4 is not executed. In the game in the pseudo-bonus state ST4, when the value of the number-of-continued-games non-display flag is "0", a display indicating the number of remaining continuous games in the pseudo-bonus state ST4 and the number of game media acquired in the pseudo-bonus state ST4 is displayed. The display shown is performed on the image display device 63 . Further, in the game in the pseudo-bonus state ST4, when the number of continued games non-display flag is set to "1", the image display device 63 displays the number of game media acquired in the pseudo-bonus state ST4. On the other hand, the display indicating the remaining number of continuous games in the pseudo-bonus state ST4 is not performed.

When the effect side pseudo-bonus state flag is set to "1" and the pseudo-bonus state flag 77c of the main side RAM 74 is set to "1" (step S3701: YES, step S3708: YES), that is, if the current game is executed in the pseudo-bonus state ST4 and the pseudo-bonus state ST4 continues even after the end of the current game, the pseudo-bonus continuation counter 74t set in the post-conversion termination command is set in the pseudo-bonus continuation counter on the presentation side, the value of the pseudo-bonus continuation counter on the presentation side is updated (step S3709). After that, update processing of the pseudo-bonus provision number counter provided in the effect side RAM 94 is executed (step S3710). The pseudo-bonus given number counter is a counter that enables the effect-side MPU 92 to grasp the number of game media acquired in the pseudo-bonus state ST4. In step S3710, the process of updating the pseudo-bonus grant counter updates the number of grants of game media in the current game based on the data of the grant counter 74e set in the post-conversion termination command, is added to the pseudo-bonus grant number counter of the effect side RAM 94.例文帳に追加As a result, the effect-side MPU 92 can grasp the number of game media acquired in the pseudo-bonus state ST4. After that, the display indicating the number of game media acquired in the pseudo-bonus state ST4 displayed on the image display device 63 is updated (step S3711). In step S3711, the display data corresponding to the value of the pseudo-bonus provision number counter updated in step S3710 is output to the image display device 63. FIG.

When "1" is set to the effect side pseudo-bonus state flag and "1" is not set to the pseudo-bonus state flag 77c of the main side RAM 74 (step S3701: YES, step S3708: If NO), it means that the pseudo-bonus state ST4 has ended, so a setting process of the pseudo-bonus state end effect is executed (step S3712). In the processing for setting the pseudo-bonus state end effect, the effect data table for executing the pseudo-bonus state end effect indicating the end of the pseudo-bonus state ST4 by the upper lamp 61, the speaker 62 and the image display device 63 is stored in the effect-side ROM 93. read from Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read effect data table.

After that, the production side pseudo bonus state flag is cleared to "0" (step S3713). As a result, the effect-side MPU 92 can grasp that the pseudo-bonus state ST4 has ended. After that, the value of the dummy bonus continuation counter on the effect side is cleared to "0" (step S3714), and the effect executed flag in the effect side RAM 94 is cleared to "0" (step S3715). After that, the continuous game count non-display flag of the effect side RAM 94 is cleared to "0" (step S3716), and the pseudo bonus grant number counter of the effect side RAM 94 is cleared to "0" (step S3717).

Thereafter, based on the data of the end preparation state flag 77e included in the data of the game state area 77 set in the post-conversion end time command, it is determined whether or not the state is the end preparation state ST6 (step S3718). If it is the end preparation state ST6 (step S3718: YES), the effect side end preparation state flag of the effect side RAM 94 is set to "1" (step S3719). As a result, the effect-side MPU 92 can grasp that the game state is the ready-to-end state.

When a negative determination is made in step S3706, when the process of step S3707 is performed, when the process of step S3711 is performed, when a negative determination is performed in step S3718, or when the process of step S3719 is performed , the process advances to step S3521 of the termination reception handling process (FIG. 57). On the other hand, if a negative determination is made in steps S3701 and S3702, this pseudo bonus state handling process is terminated, and the process advances to step S3504 of the termination reception handling process (FIG. 57).

Returning to the explanation of the termination reception handling process (FIG. 57), in step S3504, the AT status handling process is executed. FIG. 60 is a flow chart showing AT state handling processing.

In the AT state correspondence process, if the effect side AT state flag of the effect side RAM 94 is not set to "1" (step S3801: NO), the data of the game state area 77 set in the post-conversion end command Based on the data of the AT state flag 77d, it is determined whether or not the AT state is ST5 (step S3802). When the effect side AT state flag is not set to "1" and the AT state flag 77d of the main side RAM 74 is set to "1" (step S3801: NO, step S3802: YES) Since it means that it is time to shift to the AT state ST5, the processing of steps S3803 to S3808 is executed. Specifically, it is determined whether or not the ending standby flag of the effect side RAM 94 is set to "1" (step S3803), and if the ending standby flag is set to "1" (step S3803: YES). , the ending period flag of the effect side RAM 94 is set to "1" (step S3804). As a result, the effect during the ending period can be executed. Thus, when the first ending flag 76b or the second ending flag 76c of the main side RAM 74 is set to "1" while the ending effect is not being executed and the game state is not the AT state ST5. After that, the ending effect is started with the shift to the AT state ST5 as a trigger. After that, the ending standby flag of the production side RAM 94 is cleared to "0" (step S3805).

When a negative determination is made in step S3803, or when the processing of step S3805 is executed, setting processing of AT state start effect is executed (step S3806). In the AT state start effect setting process, the effect data table for executing the AT state start effect indicating that the AT state ST5 has started in the upper lamp 61, the speaker 62 and the image display device 63 is read from the effect-side ROM 93. . Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read performance data table.

After that, the data of the AT continuation counter 74u set in the post-conversion termination command is set in the performance-side AT continuation counter in the performance-side RAM 94 (step S3807). As already explained, the effect-side AT continuation counter is a counter that enables the effect-side MPU 92 to grasp the remaining number of continuous games in the AT state ST5. The AT continuation counter on the production side performs processing for displaying the remaining number of continuous games in the AT state ST5 on the image display device 63 in the production start processing in step S3304 of the already explained start reception handling processing (FIG. 55). It is referred to when doing. After that, the production side AT state flag is set to "1" (step S3808). As a result, the effect-side MPU 92 can grasp that the game state is the AT state ST5.

When "1" is set to the effect side AT state flag and "1" is set to the AT state flag 77d of the main side RAM 74 (step S3801: YES, step S3809: YES) That is, when the current game is executed in the AT state ST5 and the AT state ST5 is continued even after the end of the current game, based on the data of the grant number counter 74e set in the post-conversion termination command, , the number of game media to be given in the game to end this time is grasped (step S3810), and setting processing for displaying the number of given game media is executed (step S3811). In the processing for setting display of the number of awarded game media, if the number of awarded game media ascertained in step S3810 is 1 or more, a data table for displaying corresponding to the number of awarded game media on the image display device 63 is displayed on the production side. Read from the ROM 93 . Then, display control of the image display device 63 is started according to the read effect data table. Thereafter, by setting the data of the AT continuation counter 74u set in the post-conversion termination command to the AT continuation counter on the production side, the value of the AT continuation counter on the production side is updated (step S3812).

When the effect side AT state flag of the effect side RAM 94 is set to "1" and the AT state flag 77d of the main side RAM 74 is not set to "1" (step S3801: YES, step In S3809: NO), since it means that the AT state ST5 has ended, the AT state end effect setting process is executed (step S3813). In the AT state end effect setting process, the effect data table for executing the AT state end effect indicating that the AT state ST5 is ended by the upper lamp 61, the speaker 62 and the image display device 63 is read from the effect side ROM 93. Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read performance data table. After that, the production side AT state flag is cleared to "0" (step S3814). As a result, the effect-side MPU 92 can grasp that the AT state ST5 has ended. After that, the value of the AT continuation counter on the production side is cleared to "0" (step S3815).

After that, based on the data of the end preparation state flag 77e included in the data of the game state area 77 set in the post-conversion end time command, it is determined whether or not the state is the end preparation state ST6 (step S3816). If it is the end preparation state ST6 (step S3816: YES), the effect side end preparation state flag of the effect side RAM 94 is set to "1" (step S3817). As a result, the effect-side MPU 92 can grasp that the game state is the end preparation state ST6.

When the process of step S3808 is performed, when the process of step S3812 is performed, when a negative determination is performed in step S3816, or when the process of step S3817 is performed, reception handling processing at termination (FIG. 57) to step S3521. On the other hand, if a negative determination is made in steps S3801 and S3802, this AT state handling process is terminated, and the process advances to step S3505 of the termination reception handling process (FIG. 57).

Returning to the explanation of the termination reception handling process (FIG. 57), in steps S3505 to S3511, the first CB status handling process is executed. In the first CB state correspondence processing (step S3505 to step S3511), it is first determined whether or not the effect side first CB state flag of the effect side RAM 94 is set to "1" (step S3505), and the effect side first CB state flag is determined. is not set to "1" (step S3505: NO), based on the data of the first CB state flag 77a contained in the data of the game state area 77 set in the post-conversion end command , the first CB state ST2 (step S3506). If "1" is not set to the effect side AT state flag of the effect side RAM 94 and "1" is set to the first CB state flag 77a of the main side RAM 74 (step S3505: NO, Step S3506: YES) means that it is time to shift to the first CB state ST2, so the setting processing of the first CB state start effect is executed (step S3507). In the processing for setting the first CB state start effect, the effect data table for executing the first CB state start effect indicating that the first CB state ST2 has started in the upper lamp 61, the speaker 62 and the image display device 63 is set on the effect side. Read from the ROM 93 . Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read performance data table. After that, the effect side first CB state flag is set to "1" (step S3508). As a result, the effect-side MPU 92 can grasp that the game state is the first CB state ST2.

If "1" is set to the effect side first CB state flag of the effect side RAM 94 and "1" is not set to the first CB state flag 77a of the main side RAM 74 (step S3505: YES , step S3509: NO), since it means that the first CB state ST2 has ended, the setting processing of the first CB state end effect is executed (step S3510). In the setting processing of the first CB state end effect, the effect data table for executing the first CB state end effect indicating that the first CB state ST2 has ended is stored in the effect side ROM 93 by the upper lamp 61, the speaker 62 and the image display device 63. read from Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read effect data table. Thereafter, the production side first CB state flag is cleared to "0" (step S3511). As a result, the effect-side MPU 92 can grasp that the first CB state ST2 has ended.

If negative determinations are made in steps S3505 and S3506, second CB state handling processing is executed in steps S3512 to S3518. In the second CB state corresponding processing (step S3512 to step S3518), it is first determined whether or not the effect side second CB state flag of the effect side RAM 94 is set to "1" (step S3512), and the effect side second CB state flag is determined. is not set to "1" (step S3512: NO), based on the data of the second CB state flag 77b included in the data of the game state area 77 set in the post-conversion end command , second CB state ST3 (step S3513). If the effect side second CB state flag of the effect side RAM 94 is not set to "1" and the second CB state flag 77b of the main side RAM 74 is set to "1" (step S3512: NO , step S3513: YES) means that it is time to shift to the second CB state ST3, so the second CB state start effect setting process is executed (step S3514). In the second CB state start effect setting processing, the effect data table for executing the second CB state start effect indicating that the second CB state ST3 has started in the upper lamp 61, the speaker 62 and the image display device 63 is set on the effect side. Read from the ROM 93 . Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read effect data table. After that, the effect side second CB state flag is set to "1" (step S3515). As a result, the effect-side MPU 92 can grasp that the game state is the second CB state ST3.

If "1" is set to the effect side second CB state flag of the effect side RAM 94 and "1" is not set to the second CB state flag 77b of the main side RAM 74 (step S3512: YES , step S3516: NO), which means that the second CB state ST3 has ended, so the second CB state end effect setting process is executed (step S3517). In the setting processing of the second CB state end effect, the effect data table for executing the second CB state end effect indicating that the second CB state ST3 has ended is stored in the effect side ROM 93 by the upper lamp 61, the speaker 62 and the image display device 63. read from Then, light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are started according to the read performance data table. Thereafter, the effect side second CB state flag is cleared to "0" (step S3518). As a result, the effect-side MPU 92 can grasp that the second CB state ST3 has ended.

When negative determinations are made in steps S3512 and S3513, it is determined whether or not the effect side end preparation state flag of the effect side RAM 94 is set to "1" (step S3519). As already explained, the end preparation state ST6 ends when one game is played. When the production side end preparation state flag is set to "1" (step S3519: YES), that is, when the current game is executed in the end preparation state ST6, the end preparation state ST6 is entered after the end of the current game. is completed, the production side end preparation state flag is cleared to "0" (step S3520). As a result, the MPU 92 on the production side can grasp that the end preparation state ST6 has ended.

If the process of step S3508 is performed, if the determination is affirmative in step S3509, if the process of step S3511 is performed, if the process of step S3515 is performed, if the determination is affirmative in step S3516, step If the process of S3518 has been performed, if a negative determination is made in step S3519, or if the process of step S3520 has been performed, the process proceeds to step S3521. Also, as already explained, if a negative determination is made in step S3706 of the pseudo-bonus state handling process (FIG. 59), if the process of step S3707 is carried out, if the process of step S3711 is carried out, then in step S3718 If a negative determination is made, or if the process of step S3719 is carried out, the process also proceeds to step S3521 of the termination reception handling process (FIG. 57). Furthermore, as already described, when the process of step S3808 of the AT state handling process (FIG. 60) is performed, when the process of step S3812 is performed, when a negative determination is made in step S3816, or when a negative determination is made in step S3817 If the process has been performed, the process proceeds to step S3521 of the process for reception at termination (FIG. 57). In step S3521, the reception flag at the end of the effect side RAM 94 is cleared to "0", and the reception corresponding processing at the end is ended.

In this way, the effect-side MPU 92 converts the end command received from the main MPU 72 into the post-conversion end command, and executes processing for executing the effect based on the post-conversion end command. As already explained with reference to FIG. 47(c), the post-conversion end command includes the continuous game number counter 74r, the total winning number counter 74s, the game state area 77, the game section area 76, and the pseudo bonus in the main RAM 74. The data of the continuation counter 74t and the number-of-givens counter 74e are set. The data of the continuous game number counter 74r, the total win number counter 74s, the game state area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the award number counter 74e can be used when the end command is received. Therefore, the data of the continuous game number counter 74r, the total winning number counter 74s, the game state area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the awarded number counter 74e are received by two or more commands. By comparison, it is possible to reduce the number of command transmissions from the main side MPU 72 to the effect side MPU 92 . As a result, the processing load for the master side MPU 72 to transmit commands to the effect side MPU 92 can be reduced, and the processing load when the effect side MPU 92 executes the processing corresponding to the command received from the master side MPU 72 can be reduced. can be mitigated.

As described above, "0001H" to "0006H" including the lower area of the AT continuation counter 74u, the lower area of the continuous game number counter 74r, and the lower area of the total winning number counter 74s in which "1" can be set to the highest bit The data of "0" or "1" stored in the most significant bit of the six storage areas set in a continuous address range are aggregated into a 1-byte storage area (top aggregation area 74v). . For this reason, compared to the configuration in which two or more byte storage areas are set in the main RAM 74 in order to set the data "0" or "1" stored in the most significant bit of these six storage areas. Therefore, the data capacity of the storage area provided in the main RAM 74 is reduced for setting the data "0" or "1" stored in the most significant bit of these six storage areas.

Six storage areas, including the lower area of the AT continuation counter 74u in which "1" can be set to the highest bit, the lower area of the continuous game number counter 74r, and the lower area of the total winning number counter 74s, are "0001H" to "0006H". is set in the continuous address range, the address range of the storage area to be set in the highest-order aggregation area 74v for the data of "0" or "1" stored in the most significant bit is specified. It is possible to simplify the processing configuration for

Storage areas set in the address range of "0008H" to "000DH" (bet number setting counter 74b, stop order type counter 74m, game state area 77, game section area 76, pseudo bonus continuation counter 74t and grant number counter 74e ) is a storage area in which the most significant bit is not set to "1". The most significant bit in the storage area corresponding to the address of "0001H" to "0006H" among the storage areas set in the address range of "0001H" to "000DH" where the data is set in the command at the start and the command at the end In the configuration provided with the highest-order aggregation area 74v in which data "0" or "1" stored in the There is no storage area for setting the data "0" stored in . For this reason, while suppressing the number of storage areas (highest-order aggregation area 74v) set in the main RAM 74 to aggregate data of the highest-order bit, The most significant bit data can be set in the command at the start and the command at the end.

Since the storage area in which data is set in the start command and the end command is set in the continuous address range of "0001H" to "000DH" in the main RAM 74, the storage area in which the data is set in the start command is It is possible to simplify the processing configuration for specifying the address range and the processing configuration for specifying the address range of the storage area in which data is set in the end command.

Only a part of the storage area of the main side RAM 74 (specifically, the highest level aggregation area 74v and the game state area 77) storing data used by the effect side MPU 92 at the start of the game is This is a configuration common to the storage area of the main side RAM 74 in which data used by the effect side MPU 92 is stored. In this configuration, the storage area in which data is set in the command at the start and the command at the end is the storage area of the main side RAM 74 that stores the data used by the effect side MPU 92 at the start and end of the game. As a result, it is possible to set a storage area in which data is set in the command at the start and a storage area in which data is set in the command at the end in a continuous address range of the main RAM 74 .

In the main RAM 74, the address range of the storage area where the data to be set in the start command is stored (the address range of "0001H" to "000DH") is the data to be set in the end command. Since it is the same as the address range of the storage area (address range of "0001H" to "000DH"), the processing configuration for transmitting the start command and the processing configuration for transmitting the end command should be shared. can be done. As a result, the data capacity of the program for transmitting the command at the start and the command at the end in the main ROM 73 can be reduced.

There are an AT continuation counter 74u, a continuation game number counter 74r, and a total winning number counter 74s as counters in which the most significant bit of the lower area can be set to "1". The data of the AT continuation counter 74u is data used by the effect side MPU 92 at the start of the game, but is not data used by the effect side MPU 92 at the end of the game. The data of the continuous game number counter 74r and the total winning number counter 74s are data used by the effect side MPU 92 at the end of the game, but are not data used by the effect side MPU 92 at the start of the game. If only the data used by the effect side MPU 92 at the start of the game is set in the start command and only the data used by the effect side MPU 92 at the end of the game is set in the end command, the AT continuation counter In addition to the storage area for setting the most significant bit data in the lower area and upper area of 74u, the lower area and upper area of the continued game number counter 74r and the lower area and upper area of the total winning number counter 74s. It would be necessary to provide a storage area in the main RAM 74 for setting the data of the upper bits. On the other hand, by setting the data of the AT continuation counter 74u, the continuation game number counter 74r, and the total winning number counter 74s in the start time command and the end time command, the AT continuation counter 74u and the continuation game number counter are set. 74r and total acquisition number counter 74s. can do. As a result, the most significant bit data in the lower area and upper area of the AT continuation counter 74u, the lower area and upper area of the continuous game number counter 74r, and the lower area and upper area of the total winning number counter 74s are set. The data capacity of the side RAM 74 is reduced.

The effect side MPU 92 converts the start time command received from the main side MPU 72 into the converted start time command, and converts the end time command received from the main side MPU 72 into the converted end time command. When the effect-side MPU 92 converts the start-time command or the end-time command received from the main-side MPU 72 into the post-conversion start-time command or the post-conversion end-time command, the effect-side MPU 92 converts the 0th to The data "0" or "1" set in the 5th bit is set in the most significant bit in the 2nd to 7th frames FR2 to FR7 corresponding to the 0th to 5th bits. As a result, while setting the value of the most significant bit in the frame other than the header HD contained in the command at the start or the command at the end transmitted from the master side MPU 72 to the effect side MPU 92 to be "0", the effect side MPU 92 performs the header A post-translation start or post-translation end command may be available in which the most significant bit in non-HD frames may also be set to '1'.

A frame in which data "0" or "1" set in the 0th to 5th bits of the highest aggregated frame SF (the eighth frame FR8) is set in the most significant bit in the command at the start or the command at the end. are consecutive second to seventh frames FR2 to FR7. For this reason, a processing configuration for designating a frame in which data "0" or "1" set in the 0th to 5th bits of the highest aggregated frame SF is set in the highest bit is specified by the production side MPU 92. can be simplified.

Only some of the 1st to 15th frames FR1 to FR15 included in the start time command are set in the post-conversion start time command. As a result, the master side MPU 72 is configured to transmit a start-time command including data other than the data used by the effect side MPU 92 at the start of the game, while the command is stored in the command storage buffer 126 and used by the effect side MPU 92 . It is possible to suppress the data volume of the post-conversion start command. Further, only some of the first to fifteenth frames FR1 to FR15 included in the end command are set in the post-conversion end command. As a result, the master side MPU 72 is configured to transmit an end-time command including data other than the data used by the effect side MPU 92 at the end of the game, while the data is stored in the command storage buffer 126 and used by the effect side MPU 92 . It is possible to suppress the data volume of the command at the end of conversion after conversion. Therefore, the data capacity of the command storage buffer 126 can be reduced.

Of the 1st to 15th frames FR1 to FR15 included in the start time command, the frames set by the production side MPU 92 in the post-conversion start time command are the 1st to 15th frames FR1 to FR1 included in the end time command. It is different from the frame set in the post-conversion termination command by the effect-side MPU 92 in the FR 15 . For this reason, the address range of the storage area of the main RAM 74 storing the data set in the command at the start transmitted from the main MPU 72 to the effect MPU 92 at the start of the game is the same as the address range from the main MPU 72 to the effect at the end of the game. In a configuration that is the same as the address range of the storage area of the main side RAM 74 in which the data set in the command at the end transmitted to the side MPU 92 is stored, the address range required by the effect side MPU 92 at the start of the game at the start of the game. Only the data that is set between the header HD and the footer FT can be made available to the production side MPU 92 at the time of starting the conversion command, and at the end of the game, the production side MPU 92 can use The MPU 92 on the production side can use the post-conversion completion command in which only the data required for the conversion is set between the header HD and the footer FT.

The transfer target range in the highest-level aggregation process (FIG. 51) is the continuous address range of “0001H” to “0006H” in the main RAM 74 . By repeatedly executing the process of adding 1 to the value of the transfer source counter 116 in the main RAM 74 (the process of step S2909), the storage area of the transfer source can be sequentially updated. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the transfer target range in the highest-level aggregation process (FIG. 51) is the continuous address range of "0001H" to "0006H" in the main RAM 74, the start address of the transfer target range is set to the transfer source counter 116 in step S2904. is set to "0001H", and "6", which is the number of transfers, is set in the transfer number counter 114 in step S2905. This simplifies the processing configuration for designating the transfer target range.

The transfer target range in the common command transmission process (FIG. 50) is the continuous address range of “0001H” to “000DH” in the main RAM 74 . By repeatedly executing the process of adding 1 to the value of the transfer source counter 116 in the main RAM 74 (the process of step S2816), the storage area of the transfer source can be sequentially updated. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the transfer target range in the common command transmission process (FIG. 50) is the continuous address range of "0001H" to "000DH" in the main RAM 74, the start address of the transfer target range is set to the transfer source counter 116 in step S2809. is set to "0001H" and "13", which is the number of transfers, is set in the transfer number counter 114 in step S2810, thereby specifying the transfer target range. This simplifies the processing configuration for designating the transfer target range.

The addresses of the areas RA2 to RA7 in which the data "0" or "1" stored in the 0th to 5th bits of the highest-order aggregated frame SF are set to the highest-order bits in the highest-order setting process (FIG. 53) are It is a continuous address range from "α+2" to "α+7". By repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S3110), the transfer destination storage area can be sequentially updated. This simplifies the processing configuration for sequentially updating the transfer destination storage area.

The value of the effect-side bit designation counter in the effect-side RAM 94 is the data "0" or "1" stored in any one of the 0th to 5th bits of the highest aggregate frame SF to the maximum value in the storage area of the transfer destination. One is added each time the process of transferring to the upper bit (the process of step S3107) is executed. Therefore, by referring to the value of the rendering-side bit designation counter, the data "0" or "1" set in any of the 0th to 5th bits of the highest aggregated frame SF can be changed to the 0th to 5th bits. The number of transfers to the second to seventh frames FR2 to FR7 corresponding to any of the fifth bits can be grasped. As a result, it is possible to simplify the processing configuration for ascertaining the number of transfers by the effect-side MPU 92 .

By transferring the data of some of the first to fifteenth frames FR1 to FR15 included in the start time command or end time command set in the pre-conversion area 124 to the post-conversion area 125, the start time command Alternatively, when the end command is converted to the post-conversion start command or the post-conversion end command, the transfer source storage area in the pre-conversion area 124 is updated in a manner excluding the area to be excluded. On the other hand, when the transfer destination storage area in the post-conversion area 125 is updated, the storage area set next to the current transfer destination storage area in the post-conversion area 125 becomes the post-update transfer destination storage area. is done in As a result, when a start command is received, data to be used by the effect-side MPU 92 at the start of the game can be extracted from the start command and set as the post-conversion start command. is received, the data to be used by the effect side MPU 92 at the end of the game can be extracted from the command at the end and set as the command at the end after conversion.

The effect side MPU 92 converts the start time command received from the main side MPU 72 into a converted start time command, and executes processing for executing the effect of the game started this time based on the converted start time command. Data of an AT continuation counter 74u, a bet number setting counter 74b, a stop order type counter 74m and a game state area 77 in the main side RAM 74 are set in the post-conversion start time command. When the start command is received, the data of the AT continuation counter 74u, the bet number setting counter 74b, the stop order type counter 74m, and the game state area 77 can be used. Compared to the configuration in which the data of the number setting counter 74b, the stop order type counter 74m, and the game state area 77 are received by two or more commands, the number of command transmissions from the main side MPU 72 to the effect side MPU 92 can be reduced. can. As a result, the processing load for the master side MPU 72 to transmit commands to the effect side MPU 92 can be reduced, and the processing load when the effect side MPU 92 executes the processing corresponding to the command received from the master side MPU 72 can be reduced. can be mitigated.

The effect side MPU 92 converts the end command received from the main side MPU 72 into a post-conversion end command, and executes processing for executing the effect based on the post-conversion end command. Data of a continuous game number counter 74r, a total winning number counter 74s, a game state area 77, a game section area 76, a pseudo-bonus continuation counter 74t, and a given number counter 74e in the main side RAM 74 are set in the post-conversion end command. there is The data of the continuous game number counter 74r, the total win number counter 74s, the game state area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the award number counter 74e can be used when the end command is received. Therefore, the data of the continuous game number counter 74r, the total winning number counter 74s, the game state area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the awarded number counter 74e are received by two or more commands. By comparison, it is possible to reduce the number of command transmissions from the main side MPU 72 to the effect side MPU 92 . As a result, the processing load for the master side MPU 72 to transmit commands to the effect side MPU 92 can be reduced, and the processing load when the effect side MPU 92 executes the processing corresponding to the command received from the master side MPU 72 can be reduced. can be mitigated.

<Configuration of main side MPU 72>
Next, the configuration of the main MPU 72 will be described. FIG. 61(a) is an explanatory diagram for explaining the configuration of the main MPU 72. FIG.

As shown in FIG. 61(a), the main MPU 72 has W register 101a, A register 101b, B register 102a, C register 102b, D register 103a, E register 103b, H register 104a and L register 104b as general purpose registers. It has These eight general purpose registers are 1-byte registers. These general-purpose registers can also be used as pair registers by combining two corresponding general-purpose registers. Specifically, the W register 101a and A register 101b can be combined to be used as a 2-byte WA register 101, and the B register 102a and C register 102b can be combined to be used as a 2-byte BC register 102. be able to. The D register 103a and E register 103b can be combined to be used as a 2-byte DE register 103, and the H register 104a and L register 104b can be combined to be used as a 2-byte HL register 104. .

The main MPU 72 has a program counter PC. The program counter PC stores the storage address of the next instruction to be fetched by the main MPU 72, and its value is incremented by 1 each time one byte of the instruction is fetched. In the main MPU 72, the program stored in the main ROM 73 moves from a lower address (smaller program address) to a higher address (larger program address), except when a jump instruction or a call instruction is executed. Orders are processed in order.

As shown in FIG. 61(a), the main MPU 72 has a zero flag ZF, a carry flag CF and a jump flag JF. The zero flag ZF consists of 1 bit. The zero flag ZF is a flag that becomes "1" when the content of the register after the operation is "0", and becomes "0" when the content of the register after the operation is not "0". Carry flag CF consists of 1 bit. The carry flag CF becomes "1" when a carry occurs from the most significant bit (the 7th bit in the 0th to 7th bits) during the execution of the ADD instruction (addition instruction), which is an 8-bit operation instruction. In addition, it becomes "0" when no carry occurs from the most significant bit (seventh bit). Also, the carry flag CF is set when the most significant bit (the 7th bit among the 0th to 7th bits) is borrowed during the execution of the SUB instruction (subtraction instruction), which is an 8-bit operation instruction. It becomes "1", and becomes "0" when there is no borrowing to the most significant bit (seventh bit). Jump flag JF is a flag that takes the same value as zero flag ZF or carry flag CF depending on the executed instruction. The jump flag JF consists of 1 bit. The jump flag JF takes the same value as the zero flag ZF when the OUT instruction, which is an output instruction, the XOR instruction, which is an exclusive OR operation instruction, and the LD instruction, which is a transfer instruction, are executed. Specifically, the value of the jump flag JF is "1" when the value of the zero flag ZF is "1", and is "0" when the value of the zero flag ZF is "0". On the other hand, the jump flag JF takes the same value as the value of the carry flag CF when the CP instruction, which is a comparison instruction, and the SUB instruction, which is a subtraction instruction, are executed. Specifically, the value of the jump flag JF is "1" when the value of the carry flag CF is "1", and is "0" when the value of the carry flag CF is "0". . The jump flag JF is referenced in a JRS instruction, which will be described later.

FIG. 61(b) is an explanatory diagram for explaining how data and programs are set in the main ROM 73. As shown in FIG. As shown in FIG. 61(b), the main-side ROM 73 is assigned addresses from "9000H" to "9EFFH". A number of 1-byte areas are provided in the main ROM 73, and a 2-byte address is set for each 1-byte area.

In the main-side ROM 73, data used for executing various processes are collectively stored in areas of consecutive addresses in the address range of "9000H" to "98FFH". In addition, the address range of "9900H" to "9902H" which is continuous with the address range of "9000H" to "98FFH" is the address of an unused area where no data is stored, followed by "9903H". Programs for executing various processes are collectively stored in areas of successive addresses in the address range of .about.9EFFH. Further, the address range of "9F00H" to "9F02H" which is continuous with the address range of "9903H" to "9EFFH" is an address of an unused area where no data is stored. The relationship between data, programs, and addresses as described above is set in both physical addresses in the main ROM 73 and logical addresses on the memory map recognized by the main MPU 72 .

In the main-side ROM 73, data and programs are stored in areas of different ranges of addresses regardless of the execution order of processing, so that the work of distinguishing and checking data and programs can be performed efficiently. can be done. In addition, since the address range of an unused area in which no data is stored is set between the address range of the area in which the data is stored and the address range of the area in which the program is stored, the data It becomes easy to grasp the boundary between the address range and the address range of the program in the checking work.

Next, prior to the description of the program content of the power-off standby process executed by the main MPU 72 (FIG. 62(b)), the jump instruction including the JRS instruction set in the power-off standby process program will be described. .

FIG. 62(a) is an explanatory diagram for explaining the types of jump instructions executed by the main MPU 72. FIG. As shown in FIG. 62(a), JP instruction, JR instruction and JRS instruction exist as jump instructions executed by the main MPU 72. FIG. As shown in FIG. 61( a ), the main MPU 72 has a JP execution circuit 105 , a JR execution circuit 106 and a JRS execution circuit 107 . The JP execution circuit 105 is a dedicated circuit for executing JP instructions, the JR execution circuit 106 is a dedicated circuit for executing JR instructions, and the JRS execution circuit 107 is a dedicated circuit for executing JRS instructions. .

As shown in FIG. 62(a), the JP instruction is an instruction that designates the entire 2-byte program address (absolute address) that is the jump destination and jumps to the jump destination program address. The word length of the JP instruction (the data capacity of the machine language) is 3 bytes, and the machine language of the JP instruction contains the entire 2-byte program address specifying the jump destination. By using the JP instruction, regardless of the program address where the JP instruction is set, any of the addresses included in the address range ("9903H" to "9EFFH") where the program is stored in the main ROM 73 You can also jump to the address of

JR and JRS instructions specify a 2-byte program address as a jump destination by using difference information from the program address where the JR or JRS instruction is set. This is an instruction to jump to The word length of the JR instruction (the data capacity of the machine language) is 2 bytes, and the machine language of the JR instruction contains 1-byte data that designates part of the jump destination program address. In the JR instruction, difference information from the program address where the JR instruction is set is set with a total of 8 bits, ie, 1 sign bit and 7 numerical value bits. In the JR instruction, the jump destination program address (2 bytes) is relatively specified based on the program address set in the JR instruction and the difference information (8 bits) set in the JR instruction. In this way, the data capacity of the information (difference information) set in the JR instruction to specify the 2-byte jump destination program address is suppressed to 8 bits, and the data capacity of the machine language of the JR instruction is reduced to has been reduced. Therefore, by using the JR instruction with a word length of 2 bytes, the data capacity of the machine language of the jump instruction for jumping to the program address of the jump destination is reduced compared to the case of using the JP instruction with a word length of 3 bytes. can be reduced. The range that can be jumped by the JR instruction is the range from "(program address where the relevant JR instruction is set)+2-128" to "(program address where the relevant JR instruction is set)+2+127". Of these, "+2" corresponds to the word length (2 bytes) of the JR instruction itself, and "-128 to 127" is a numerical range that can be specified with a total of 8 bits, 1 sign and 7 bits. be.

In the JRS instruction, information on the difference from the program address where the JRS instruction is set is set with a total of 5 bits, ie, 1 sign bit and 4 numerical value bits. In the JRS instruction, the jump destination program address (2 bytes) is relatively specified based on the program address where the JRS instruction is set and the difference information (5 bits) set in the JRS instruction. In this way, the data capacity of the information (difference information) set in the JRS instruction to specify the 2-byte jump destination program address is suppressed to 5 bits, and the machine language data capacity of the JRS instruction is reduced to has been reduced. Therefore, by using the JRS instruction with a word length of 1 byte, it is possible to jump to the program address of the jump destination compared to using the JP instruction with a word length of 3 bytes or the JR instruction with a word length of 2 bytes. It is possible to reduce the data volume of the machine language of the jump instruction. The range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". Of these, "+1" corresponds to the word length (1 byte) of the JRS instruction itself, and "-16 to 15" is a numerical range that can be specified with a total of 5 bits, 1 sign and 4 bits. be.

The JP instruction and the JR instruction include a conditional jump that jumps on the condition that the flag to be referenced is in a predetermined state, and an unconditional jump that jumps unconditionally without referring to the state of the flag. . The JP instruction and the JR instruction refer to the zero flag ZF or the carry flag CF. The main MPU 72 outputs a JP instruction that jumps on the condition that the value of the zero flag ZF is "1", a JP instruction that jumps on the condition that the value of the zero flag ZF is "0", and a carry flag CF value of " A JP instruction that jumps on the condition that the value of the carry flag CF is "1" and a JP instruction that jumps on the condition that the value of the carry flag CF is "0" can be executed. In addition, the main MPU 72 outputs a JR instruction that jumps on the condition that the value of the zero flag ZF is "1", a JR instruction that jumps on the condition that the value of the zero flag ZF is "0", and the value of the carry flag CF. A JR instruction that jumps on the condition that is "1" and a JR instruction that jumps on the condition that the value of the carry flag CF is "0" can be executed.

The word length of the JRS instruction (1 byte) is short compared to the word length of the JP instruction (3 bytes) and the word length of the JR instruction (2 bytes). In order to make it possible to shorten the word length, the JRS instruction is provided with only a conditional jump that jumps on the condition that the referenced flag is in a predetermined state. There is no unconditional jump that jumps unconditionally. Also, in order to shorten the word length, the flags to be referenced in the JRS instruction are limited to the jump flag JF only. The main MPU 72 can execute a JRS instruction that jumps on the condition that the value of the jump flag JF is "1" and a JRS instruction that jumps on the condition that the value of the jump flag JF is "0". can.

The value of the jump flag JF is maintained even if the JRS instruction is executed. The value of the jump flag JF does not change before and after the JRS instruction is executed. Therefore, while maintaining the value of the jump flag JF before the execution of the JRS instruction, a jump is made to the program address of the jump destination set in the JRS instruction, and based on the value of the jump flag JF before the execution of the JRS instruction. The instruction set at the jump destination program address can be executed.

Next, the program contents of the power-off standby process executed by the main MPU 72 will be described with reference to the explanatory diagram of FIG. 62(b). As already described, the power-off standby process is executed in step S119 of the main process (FIG. 10), and is executed in step S308 of the power failure process (FIG. 12). As shown in FIG. 62(b), "1001" to "1002" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

As shown in FIG. 62(b), the command "OUT (WDTCLR0), 18H" is set at the line number "1001". "OUT" is an OUT instruction as an output instruction. "WDTCLR0" is a 1-byte port number for outputting initial value data from the main MPU 72 to the watchdog timer 86a, and "18H" is the initial value ("24") set to the watchdog timer 86a. 1-byte numerical information indicating By executing the instruction "OUT (WDTCLR0), 18H" at the line number "1001", the initial value "18H" ("24") is set to the watchdog timer 86a. As a result, the watchdog timer 86a can be initialized and returned to a state in which the time required for the watchdog timer 86a to underflow is 240 milliseconds.

As already explained, the watchdog timer 86a is a down counter that is updated by subtracting 1 at a predetermined cycle (specifically, once every 10 milliseconds). The watchdog timer 86a underflows if the initial value is not set for 240 milliseconds. A reset signal is output to the input port of the MPU 72 when the watchdog timer 86a underflows. When the reset signal is received, the MPU 72 starts processing for resetting the program.

The command "JRS 0, ADR101" is set at the line number "1002". "JRS" is a conditional jump instruction with a word length of 1 byte. "0" is the contents of setting the condition that the value of the jump flag JF is "0" as a condition for jumping to the program address of the jump destination. "ADR101" designates the program address where the instruction "OUT (WDTCLR0), 18H" of the line number "1001" is set as the jump destination program address. The instruction at line number "1002" is set to the program address "ADR102." As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". . As shown in FIG. 62(b), an OUT instruction with a word length of 3 bytes is set in line number "1001". "ADR101" is "(ADR102)+1-4" and can be specified as a jump destination program address in the JRS instruction based on the program address (ADR102) where the JRS instruction of line number "1002" is set. A program address that is in range. At line number "1002", a jump is made to the program address of line number "1001" where the instruction "OUT (WDTCLR0), 18H" is set on condition that the value of the jump flag JF is "0".

FIG. 62(c) is an explanatory diagram for explaining the state of the jump flag JF after the instruction "OUT (WDTCLR0), 18H" is executed at the line number "1001". As already explained, the jump flag JF after execution of the OUT instruction takes the same value as the value of the zero flag ZF. When the OUT instruction "OUT (WDTCLR0), 18H" is executed at the line number "1001", the value of the zero flag ZF becomes "0". Therefore, the state of the jump flag JF after execution of the OUT instruction becomes "0", which is the same as the value of the zero flag ZF. Jump to line number "1001". Then, the commands of line numbers "1001" to "1002" are repeatedly executed until the supply of operating power to the main MPU 72 is stopped. As a result, the process of setting the initial value to the watchdog timer 86a can be repeatedly executed. The interval at which the initial value is set to the watchdog timer 86a in the power-off standby process is the time required from when the initial value is set to the watchdog timer 86a until the value of the watchdog timer 86a underflows (specifically, is 240 ms). As a result, it is possible to prevent the value of the watchdog timer 86a from underflowing and activating the processing for resetting the program of the main MPU 72. FIG.

A JRS instruction with a word length of 1 byte is set as an instruction for jumping from the program address (“ADR102”) of line number “1002” to the program address (“ADR101”) of line number “1001”. Therefore, a JR instruction with a word length of 2 bytes or a JP instruction with a word length of 3 bytes is set as an instruction for jumping from the program address of line number "1002" to the program address of line number "1001". It is possible to reduce the data volume of the program for the power-off standby process compared to the configuration in which the

As already explained, the JRS instruction only provides a conditional jump that jumps on the condition that the flag to be referenced is in a predetermined state. No jumps provided. The JRS instruction set at line number "1002" is a conditional jump instruction that jumps to the program address at line number "1001" on the condition that the value of the jump flag JF is "0". In the processing, the state of the jump flag JF always becomes "0" after the OUT instruction of the line number "1001" is executed. Therefore, it is possible to repeatedly execute the instructions set to the line numbers "1001" to "1002" while using the JRS instruction, which is a conditional jump instruction with a short word length. .

<Structure for external output of AT status signal>
Next, a configuration for externally outputting the AT state signal will be described. The slot machine 10 sends various signals including an AT state signal (specifically, an AT state signal, a pseudo-bonus state signal, an input number signal and a payout number signal) to the hall computer HC located outside the slot machine 10. ). A hall computer HC is a management computer installed in a game hall. The AT state signal is a signal that enables the hall computer HC to grasp that the current gaming state of the slot machine 10 is the AT state ST5. At the end of the AT state ST5, the AT state signal is lowered from the HI state to the LOW state.

FIG. 63(a) is an explanatory diagram for explaining a configuration for performing external output from the slot machine 10 to the hall computer HC. As shown in FIG. 63( a ), the main MPU 72 has an output port 108 . The slot machine 10 has an external terminal board 109 for outputting various signals to the outside. The external terminal plate 109 is provided with an AT state signal terminal 109a for externally outputting an AT state signal. The output port 108 is electrically connected to the AT state signal terminal 109a. The main MPU 72 outputs an AT state signal to the hall computer HC via the AT state signal terminal 109a.

When the hall computer HC detects that the AT state signal input from the slot machine 10 rises from the LOW state to the HI state, it recognizes that the AT state ST5 has started, and changes the AT state signal from the HI state to the LOW state. When the fall to the state is detected, it is recognized that the AT state ST5 has ended. In the hall computer HC, when the AT state signal input from the slot machine 10 is in the HI state, it is recognized that the game state is in the AT state ST5, and when the AT state signal is in the LOW state, A configuration may be adopted in which it is grasped that the game state is not the AT state ST5.

The hall computer HC transmits information to the data counter DC installed in the game hall based on the signal received from the slot machine 10 . The data counter DC is mounted above the corresponding slot machine 10, and the data counter DC displays the number of game executions after the start of the non-AT state. The non-AT state ends when the game state shifts to the AT state ST5, and starts when the AT state ST5 ends. The AT state signal terminal 109a may be electrically connected to the data counter DC, and the main MPU 72 may externally output the AT state signal to the data counter DC.

Next, the external output setting process executed by the main MPU 72 will be described with reference to the flowchart of FIG. 63(b). The external output setting process is executed in step S411 of the normal process (FIG. 13).

In the external output setting process, an AT state signal setting process for setting the state of the AT state signal is executed (step S3901). FIG. 63(c) is an explanatory diagram for explaining the relationship between the value of the AT state flag 77d, the value of the AT state signal counter 74w, and the AT state signal. In the AT state signal setting process in step S3901 of the external output setting process (FIG. 63(b)), the AT state flag 77d of the main RAM 74 is set to "1" and the value of the AT state signal counter 74w is set to "0". , that is, when the AT state signal start-up process is not performed after the game state shifts to the AT state ST5, the AT state signal from LOW state to HI state. After that, the AT state signal counter 74w is set to "1". As a result, the main MPU 72 can recognize that the AT state signal is in the HI state. The state where the AT state flag 77d is set to "1" and the value of the AT state signal counter 74w is "0" is a state that occurs when the AT state ST5 is started. In the AT state signal setting process in step S3901, when "1" is set in the AT state flag 77d of the main RAM 74 and the AT state signal counter 74w, a process for changing the state of the AT state signal is executed. do not. Thereby, the HI state of the AT state signal is maintained. The state in which the AT state flag 77d and the AT state signal counter 74w are set to "1" is a state that occurs when the AT state ST5 continues.

In the AT state signal setting process in step S3901, when the value of the AT state flag 77d of the main RAM 74 is "0" and the value of the AT state signal counter 74w is "1", that is, when the AT state ST5 is finished. If the AT state signal has not been set to fall from HI state, the AT state signal is raised from HI state to LOW state by executing the AT state signal fall processing. After that, the value of the AT state signal counter 74w is cleared to "0". This enables the main MPU 72 to recognize that the AT state signal is in the LOW state. The state where the value of the AT state flag 77d is "0" and the value of the AT state signal counter 74w is "1" is a state that occurs when the AT state ST5 ends. In the AT state signal setting process in step S3901, when the AT state flag 77d of the main RAM 74 and the AT state signal counter 74w are "0", the process for changing the state of the AT state signal is not executed. . Thereby, the LOW state of the AT state signal is maintained. The state in which the values of the AT state flag 77d and the AT state signal counter 74w are "0" is a state that occurs when the state (non-AT state) where the gaming state is not the AT state ST5 continues.

Returning to the description of the external output setting process (FIG. 63(b)), after the AT state signal setting process is executed in step S3901, other signal setting processes are executed (step S3902), and this external output setting process is executed. exit. In other signal setting processing in step S3902, processing for setting the state of the pseudo-bonus state signal output to the hall computer HC via the external terminal board 109 is executed. The pseudo-bonus state signal is a signal that enables the hall computer HC to grasp whether or not the gaming state is the pseudo-bonus state ST4. The main MPU 72 raises the pseudo-bonus state signal from the LOW state to the HI state when the pseudo-bonus state ST4 starts, and changes the pseudo-bonus state signal from the HI state to the LOW state when the pseudo-bonus state ST4 ends. Stand down.

Next, the program contents of the AT state signal setting process executed by the main MPU 72 will be described with reference to the explanatory diagram of FIG. 64(a). The AT state signal setting process is executed in step S3901 of the external output setting process (FIG. 63(b)). As shown in FIG. 64(a), "1101" to "1117" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

As shown in FIG. 64(a), the command "LD A, (YGJTAR)" is set at the line number "1101". "LD" is an LD instruction as an 8-bit transfer instruction, and "A" is the content specifying the A register 101b as the transfer destination. "YGJTAR" is the address (2 bytes) of the game state area 77 in the main side RAM 74; "(YGJTAR)" is the content specifying the gaming state area 77 as the transfer source. By executing the command "LD A, (YGJTAR)" at the line number "1101", the data in the gaming state area 77 is transferred to the A register 101b.

The command "AND A, 08H" is set at the line number "1102". "AND" is an AND instruction for calculating a logical product of 8-bit data, and "A" is the A register 101b. As described above, the data of the gaming state area 77 is set in the A register 101b by executing the LD instruction of line number "1101". As already explained with reference to FIG. 31(b), the AT state flag 77d is set in the third bit of the game state area 77. FIG. "08H" is mask data "00001000B" for masking with "0" bits other than the third bit in which the data of the AT state flag 77d is set among the data stored in the A register 101b. By executing the instruction "AND A, 08H" at the line number "1102", the AND operation of the data stored in the A register 101b and the mask data is executed, and the result of the operation is A Stored in the register 101b. The value of the A register 101b becomes "08H" when the AT state flag 77d is set to "1", and becomes "00H" when the value of the AT state flag 77d is "0". .

The command "CP A, 08H" is set at the line number "1103". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "08H" is 1-byte numerical information. By executing the instruction "CP A, 08H" at the line number "1103", an operation is performed to subtract "08H" from the value of the A register 101b. The value of the carry flag CF is set to "1" when the 7th bit of the 7 bits is borrowed, and when the most significant bit is not borrowed in the operation, the carry flag CF is set to "1". becomes "0". As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. As described above, after execution of the instruction "AND A, 08H" at line number "1102", the value of the A register 101b is "08H" if the AT status flag 77d is set to "1". In addition, when the value of the AT state flag 77d is "0", it is "00H". When the AT status flag 77d is set to "1", the instruction "CP A, 08H" is executed at the line number "1103", thereby resetting "08H" stored in the A register 101b. Therefore, the value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0" without borrowing to the most significant bit. On the other hand, when the value of the AT status flag 77d is "0", the command "CP A, 08H" is executed at the line number "1103", thereby "00H" stored in the A register 101b , the value of the carry flag CF becomes "1" and the value of the jump flag JF also becomes "1". The operation result of subtracting "08H" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 08H" is executed, the value of the A register 101b does not change.

The command "JRS 0, ADR113" is set at the line number "1104". "JRS" is a conditional jump instruction with a word length of 1 byte. "0" is the contents of setting the condition that the value of the jump flag JF is "0" as a condition for jumping. "ADR113" is the contents of specifying "ADR113" which is the program address where the LD instruction of line number "1111" is set as the jump destination program address. The JRS instruction at line number "1104" is set to a program address of "ADR111." In the JRS instruction of line number "1104", a 2-byte jump destination program The address (ADR 113) is relatively specified. Compared to the structure using the JP instruction with a word length of 3 bytes or the JR instruction with a word length of 2 bytes, the jump to the jump destination program address is performed using the JRS instruction with a word length of 1 byte. The machine language data capacity of the jump instruction for jumping to the previous program address is reduced. As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". . As shown in FIG. 64(a), instructions (LD instruction at line number "1105", line number " 1106” CP instruction, RET instruction on line number “1107”, CALL instruction on line number “1108”, XOR instruction on line number “1109” and JRS instruction on line number “1110”) total word length is 11 bytes. is. "ADR113" is "(ADR111)+1+11", and is a program address that can be specified as a jump destination program address in the JRS instruction based on the program address (ADR111) where the JRS instruction of line number "1104" is set. is. By executing the instruction "JRS 0, ADR113" at the line number "1104", the program address "ADR113" at the line number "1111" is executed on condition that the value of the jump flag JF is "0". jump to Specifically, when "1" is set in the AT state flag 77d, the command "JRS 0, ADR113" is executed at the line number "1104", and the line number "ADR113" is executed. 1111” program address. On the other hand, when the value of the AT status flag 77d is "0", even if the instruction "JRS 0, ADR113" is set in the line number "1104", the program address does not jump and the next line is executed. Proceed to number "1105".

Commands set to line number "1105" to line number "1110" are commands to be executed in a state (non-AT state) where the gaming state is not AT state ST5. The command "LD A, (AJSGCNT)" is set at the line number "1105". "LD" is an LD instruction as an 8-bit transfer instruction, and "A" is the content specifying the A register 101b as the transfer destination. "AJSGCNT" is the address (2 bytes) of the AT state signal counter 74w in the main RAM 74; "(AJSGCNT)" is the content specifying the AT state signal counter 74w as the transfer source. By executing the instruction "LD A, (AJSGCNT)" at line number "1105", the data of the AT state signal counter 74w is transferred to the A register 101b. As already explained, the value of the AT state signal counter 74w is "1" when the AT state signal is in the HI state, and is "0" when the AT state signal is in the LOW state.

The command "CP A, 01H" is set at the line number "1106". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "01H" is 1-byte numerical information. By executing the instruction "CP A, 01H" at the line number "1106", an operation is performed to subtract "01H" from the value of the A register 101b. The value of the carry flag CF is set to "1" when the 7th bit of the 7 bits is borrowed, and when the most significant bit is not borrowed in the operation, the carry flag CF is set to "1". becomes "0". As described above, after the command "LD A, (AJSGCNT)" at line number "1105" is executed, the data ("00H" or "01H") of the AT state signal counter 74w is set in the A register 101b. there is When the value of the AT state signal counter 74w is "1", the command "CP A, 01H" is executed at the line number "1106", thereby resetting "01H" stored in the A register 101b. Since the operation of subtracting "01H" from is performed, there is no borrowing to the most significant bit, and the value of the carry flag CF becomes "0". On the other hand, when the value of the AT status flag 77d is "0", the instruction "CP A, 01H" is executed at the line number "1106", thereby "00H" stored in the A register 101b is executed. , so that the most significant bit is borrowed and the value of the carry flag CF becomes "1".

A command "RET C" is set at the line number "1107". "RET" is an instruction to return from the subroutine, and "C" is the contents of setting the condition that the value of the carry flag CF is "1" as a condition for returning from the subroutine. As described above, when the value of the AT state signal counter 74w is "0", the carry flag CF is set to "1" by executing the instruction "CP A, 01H" at the line number "1106". It has become. Therefore, when the value of the AT state signal counter 74w is "0", the command "RET C" is executed at line number "1107", thereby returning to step S1411 of the port output process (FIG. 28). , the AT state signal setting process called is terminated, and the process returns to step S1411 which is set next to the AT state signal setting process. In this way, when the value of the AT state flag 77d is "0" and the value of the AT state signal counter 74w is "0", the state where the game state is not the AT state ST5 (non-AT state) continues. Therefore, the AT state signal setting process is terminated without changing the LOW state of the AT state signal. On the other hand, as described above, when the value of the AT state signal counter 74w is "1", the value of the carry flag CF is changed by executing the instruction "CP A, 01H" at the line number "1106". "0". Therefore, even if the command "RET C" is set in the line number "1107", the subroutine will not return, and the process will proceed to the next line number "1108". Thus, when the value of the AT state flag 77d is "0" and the value of the AT state signal counter 74w is "1", the process ( This means that the processing of line number "1108" (to be described later) has not yet been executed. The state in which the value of the AT state flag 77d is "0" and the value of the AT state signal counter 74w is "1" is a state that occurs at the end of the AT state ST5.

The command "CALL AJSGTSSR" is set at the line number "1108". "AJSGTSSR" is AT state signal fall processing, and "CALL" is a CALL instruction for calling a subroutine for the AT state signal fall processing. At line number "1108", the command "CALL AJSGTSSR" is executed to cause the AT state signal to fall. In the AT state signal fall processing, processing for changing the AT state signal from the HI state to the LOW state is executed. When the AT state signal fall processing is completed, the process proceeds to the line number "1109" set next to the line number "1108" that called the AT state signal fall processing.

The command "XOR A, A" is set at the line number "1109". "XOR" is an exclusive OR instruction called an XOR instruction, and "A" before and after the comma designates the A register 101b. By executing "XOR A, A" at line number "1109", the operation result of the exclusive OR of the value of the A register 101b and the value of the A register 101b is specified by "A" before the comma. is set in the A register 101b. Specifically, regardless of the value of the A register 101b, "00H" is set in the A register 101b. That is, the A register 101b is cleared to "0". In the AT state signal setting process, data in the A register 101b is set in the AT state signal counter 74w of the main side RAM 74 at line number "1116" to be described later. The A register 101b is a register in which data to be set in the AT state signal counter 74w is set, and an instruction "XOR A, A" is an instruction for clearing the A register 101b to "0". As described above, the operation result of the operation performed by the instruction "XOR A, A" is "0". Also, as already explained, the jump flag JF takes the same value as the zero flag ZF when the XOR instruction is executed. Therefore, by executing the instruction "XOR A, A" at the line number "1109", the value of the zero flag ZF becomes "1" and the value of the jump flag JF becomes "1".

The command "JRS 1, ADR114" is set at the line number "1110". "JRS" is a conditional jump instruction with a word length of 1 byte; specifies the program address of line number "1116" of "ADR114" as a jump destination. The instruction "JRS 1, ADR114" at line number "1110" is set to the program address "ADR112". As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". . As shown in FIG. 64(a), instructions set at program addresses between program addresses "ADR112" and "ADR114" (LD instruction at line number "1111", CP instruction, RET instruction of line number "1113", CALL instruction of line number "1114" and LD instruction of line number "1115") total word length is 11 bytes. "ADR114" is "(ADR112)+1+11", and is a program address that can be specified as a jump destination program address in the JRS instruction based on the program address (ADR112) where the JRS instruction of line number "1110" is set. is. As described above, by executing the instruction "XOR A, A" at line number "1109", the value of the zero flag ZF becomes "1" and the value of the jump flag JF also becomes "1". Therefore, by executing the instruction "XOR A, A" at line number "1109" and then executing the instruction "JRS 1, ADR114" at line number "1110", "ADR112" is executed. It is possible to always jump from the program address of line number "1110" to the program address of line number "1116" of "ADR114".

As already explained, the JRS instruction with a word length of 1 byte includes a conditional jump that jumps to the program address of the jump destination under the condition that the value of the jump flag JF is either "1" or "0". Only instructions are provided. In the state where the instruction "XOR A, A" is executed at line number "1109" and the value of the jump flag JF is "1", the instruction "JRS 1, ADR114" is executed at line number "1110". By adopting the configuration for execution, it is possible to reliably jump from line number "1110" to line number "1116". As described above, the instruction "XOR A, A" set at line number "1109" causes the data in the A register 101b set in the AT state signal counter 74w at line number "1116" to be described later to be "0". ” is an order to clear. Then, the instruction "XOR A, A" set at line number "1109" uses the JRS instruction with a word length of 1 byte at line number "1110" to perform "ADR114" at line number "1116". It is also an instruction that makes it possible to jump reliably to a program address. The data capacity of the program for executing the AT state signal setting process is reduced by consolidating these two roles into the XOR instruction of line number "1109".

The instruction set at line number "1111" is executed when line number "1104" is jumped to line number "1111". As already explained, when the AT status flag 77d is set to "1", the command "JRS 0, ADR113" is executed at the line number "1104", and the line number "ADR113" is executed. 1111” program address. Instructions set in line numbers "1111" to "1115" are executed in the AT state ST5.

At the line number "1111", the command "LD A, (AJSGCNT)" is set, similarly to the line number "1105". By executing the instruction "LD A, (AJSGCNT)" at line number "1111", the data of the AT state signal counter 74w is transferred to the A register 101b. As already explained, the value of the AT state signal counter 74w is "1" when the AT state signal is in the HI state, and is "0" when the AT state signal is in the LOW state.

At the line number "1112", the command "CP A, 01H" is set, similarly to the line number "1106". By executing the instruction "CP A, 01H" at the line number "1112", an operation of subtracting "1" from the value of the A register 101b is performed. If the value of the A register 101b before the subtraction of 1 is "0", that is, if the value of the AT state signal counter 74w is "0", the most significant bit (the 0th to 7th bits) 7 bits) occurs and the value of the carry flag CF becomes "1". On the other hand, if the value of the A register 101b before the subtraction of 1 is "1" or more, that is, if the value of the AT state signal counter 74w is "1", the most significant bit (0th to 7th 7th bit), the value of the carry flag CF becomes "0". The result of the operation of subtracting "1" from the value of the A register 101b is never written to the A register 101b, and even if the instruction "CP A, 01H" is executed, the value of the A register 101b does not change.

The command "RET NC" is set at the line number "1113". "RET" is an instruction to return from the subroutine, and "NC" is the contents of setting the condition that the value of the carry flag CF is "0" as a condition for returning from the subroutine. As described above, when the value of the AT state signal counter 74w is "1", the value of the carry flag CF is set to "0" by executing the instruction "CP A, 01H" at the line number "1112". It has become. Therefore, when the value of the AT state signal counter 74w is "1", the currently called subroutine is terminated by executing the command "RET NC" at line number "1113". Returns to the processing that is set after the processing that called the subroutine. Specifically, the process returns to step S3902, which is the process following step S3901 in the external output setting process (FIG. 63(b)). Thus, when the value of the AT state flag 77d is "1" and the value of the AT state signal counter 74w is "1", it means that the AT state ST5 is continued. is in the HI state, the AT state signal setting process is terminated. On the other hand, as described above, when the value of the AT state signal counter 74w is "0", the value of the carry flag CF is changed to " 1”. Therefore, even if the command "RET NC" is set in the line number "1113", the subroutine will not be returned, and the process will proceed to the next line number "1114". Thus, when the value of the AT state flag 77d is "1" and the value of the AT state signal counter 74w is "0", the AT state signal rises after the game state shifts to the AT state ST5. This means that the process to raise the AT state (the process of line number "1114" to be described later) has not yet been executed. A state in which the value of the AT state flag 77d is "1" and the value of the AT state signal counter 74w is "0" is a state that occurs at the start of the AT state ST5.

The command "CALL AJSGTASR" is set at the line number "1114". "AJSGTASR" is an AT state signal rising process, and "CALL" is a CALL instruction for calling a subroutine for the AT state signal rising process. At line number "1114", the command "CALL AJSGTASR" is executed to start up the AT state signal. In the process for raising the AT state signal, a process for changing the AT state signal from the LOW state to the HI state is executed. When the AT state signal start-up process is completed, the process proceeds to the line number "1115" next to the line number "1114" that called the AT state signal start-up process.

The command "LD A, 01H" is set at the line number "1115". "LD" is an LD instruction as an 8-bit transfer instruction, "A" is the content specifying the A register 101b as the transfer destination, and "01H" is 1-byte numerical information indicating "1". By executing the instruction "LD A, 01H" at the line number "1115", "01H" is set in the A register 101b.

The instruction set at line number "1116" is executed when jumping from the program address ("ADR112") at line number "1110" to the program address ("ADR114") at line number "1116" or at line number "1115". ” is executed when the LD instruction is executed. The command "LD (AJSGCNT), A" is set at the line number "1116". "LD" is an LD instruction as an 8-bit transfer instruction, "(AJSGCNT)" is the content specifying the AT state signal counter 74w as the transfer destination, and "A" is the content specifying the A register 101b as the transfer source. is. When jumping from the program address of line number "1110" to the program address of line number "1116", that is, when the AT state ST5 ends, the A register 101b is cleared to "0" at line number "1109". Therefore, the AT state signal counter 74w of the main side RAM 74 is set to "0" by executing the instruction "LD (AJSGCNT), A" at the line number "1116". This enables the main MPU 72 to recognize that the AT state signal is in the LOW state. On the other hand, when the instruction of line number "1115" is executed, that is, when the AT state ST5 starts, "1" is set in the A register 101b at line number "1115". 1116", the AT state signal counter 74w is set to "1" by executing the command "LD (AJSGCNT), A". This enables the main MPU 72 to grasp that the AT state signal is in the HI state.

The command "RET" is set at the line number "1117". "RET" is a return instruction from a subroutine. By executing the command "RET" at line number "1117", the currently called subroutine is terminated and the process set next to the process that called the subroutine is returned to. Specifically, the process returns to step S3902, which is set following the process of step S3901 in the external output setting process (FIG. 63(b)).

FIG. 64(b) is set to jump from the program address of line number "1110" of "ADR112" to the program address of line number "1116" of "ADR114" in the AT state signal setting process (FIG. 64(a)). FIG. 64(c) is an explanatory diagram for explaining the jump instruction that is executed, and FIG. 64(c) is a comparative example of the AT state signal setting processing, from the program address of line number "1110" of "ADR112" to the line number of "ADR114". 1116" is an explanatory diagram for explaining a jump instruction set for jumping to a program address of "1116".

As already explained, the JRS instruction requires that the flag to be referred to be in a predetermined state (the value of the jump flag JF is "1" or the value of the jump flag JF is "0"). Only a conditional jump that jumps as is prepared, and an unconditional jump that jumps unconditionally without referring to the state of the flag is not prepared. As described above, the instruction "JRS 1, ADR114" set at the line number "1110" is executed by the program "ADR114" at the line number "1116" on the condition that the value of the jump flag JF is "1". This is an instruction to jump to an address. If the value of the jump flag JF is "0", the jump condition is not satisfied even if the instruction "JRS 1, ADR114" is set at the line number "1110", so the jump is made to the program address "ADR114". It advances to the next line number "1111" without doing. In the AT state signal setting process (FIG. 64(a)) in this embodiment, the value of the jump flag JF becomes "1" by executing the instruction "XOR A, A" at the line number "1109". In this configuration, the instruction "JRS 1, ADR114" at the line number "1110" is executed while the value of the jump flag JF is "1". As a result, the JRS instruction, which is a conditional jump instruction set at line number "1110", is used to move the program from the program address of line number "1110" of "ADR112" to the program of line number "1116" of "ADR114". You can always jump to an address.

In order to always jump from the program address of line number "1110" to the program address of line number "1116", it is conceivable to set the JR instruction or JP instruction, which is an unconditional jump instruction, to line number "1110". For example, if the JR instruction "JR ADR114" is set to line number "1110" as shown in FIG. 64(c), the word length of the jump instruction set to line number "1110" becomes 2 bytes. Also, although illustration is omitted, if the JP instruction "JP ADR114" is set to the line number "1110", the word length of the jump instruction set to the line number "1110" becomes 3 bytes. The command "XOR A, A" set in line number "1109" is a command for creating 1-byte data "00H" to be set in the AT state signal counter 74w in line number "1116". , the jump instruction set to the line number "1110" is a necessary instruction regardless of whether it is a JRS instruction (word length 1 byte), a JR instruction (word length 2 bytes), or a JP instruction (word length 3 bytes). . In the AT state signal setting process (Fig. 64(a)), the command "XOR A, A" and the command "JRS 1, ADR114" are set in consecutive line numbers "1109" and "1110". Because of the configuration, the word length of the jump instruction set at line number "1110" is suppressed to 1 byte, and any jump instruction is set at line number "1110". Using the instruction "XOR A, A", it is possible to always jump from the program address of line number "1110" to the program address of line number "1116". As a result, the data volume of the program (FIG. 64(a)) for executing the AT state signal setting process can be reduced.

<Program content of lottery result correspondence processing>
Next, prior to the description of the program contents (see FIG. 66) of the lottery result handling process (FIG. 25) executed by the main MPU 72, the value of the index value counter 74f in the main RAM 74 in the lottery result handling process is " The details of processing for determining whether or not the value is included in the numerical range of 1 to 9 will be described. As already explained, the lottery result handling process is executed in step S914 of the combination lottery process (FIG. 18).

In the following description, the numerical range of "1" to "9", which is the object of judgment in determining whether the value of the index value counter 74f is included in the numerical range of "1" to "9" Also called "range". As already explained, in a game in which the pseudo-bonus state ST4 or AT state ST5 is set and the number of bets is "3", an index value of one of "1" to "9" is selected in the winning lottery process (FIG. 18). Under the condition that the IV is won, one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m. Then, based on the fact that one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m, the combined display section 66 displays the reels 32L, 32M, and 32R corresponding to the stop order. is executed, the stop order notification of the reels 32L, 32M, and 32R is executed on the image display device 63 . The determination target range (“1” to “9”) is the pseudo-bonus state ST4 or AT state ST5, and the number of bets in the current game is “3”. This is the range of the index values IV for which the image display device 63 is to perform stop order notification.

The main MPU 72 first transfers the data of the index value counter 74f in the main RAM 74 to the A register 101b. After that, by executing the command "ADD A, F6H" at line number "1213" of the lottery result handling process (FIG. 66), which will be described later, "246" is added to the value of the A register 101b. The A register 101b is a 1-byte register, and the maximum value of numerical information stored in the A register 101b is "255". "246" added to the value of the A register 101b is the maximum value of the judgment range ("1" to "9") from the maximum value of "255" in the 1-byte numerical information stored in the A register 101b. This is numerical information obtained by subtracting "9".

FIG. 65 is an explanatory diagram for explaining the relationship between the value of the A register 101b before adding "246" and the value of the A register 101b and the value of the carry flag CF after adding "246". As shown in FIG. 65, when the value of the A register 101b before adding "246" is any of "0" to "9", that is, when the value of the A register 101b before adding "246" is If the value is less than or equal to "9", which is the maximum value of the determination target range ("1" to "9"), during the execution of the operation of adding "246" to the A register 101b, from the most significant bit (7th bit) Carry-over does not occur. Therefore, the value of the carry flag CF after adding "246" becomes "0". Then, the 1-byte numerical information (“246” to “255”) stored in the A register 101b before execution of the operation of adding “246” is changed to A The value is larger than the 1-byte numerical information (“0” to “9”) stored in the register 101b.

If the value of the A register 101b before adding "246" is any of "10" to "17", that is, if the value of the A register 101b before adding "246" is within the determination range ("1" to "9"), if the value is greater than "9", which is the maximum value of A carry occurs. Therefore, the value of the carry flag CF after adding "246" becomes "1". Then, the 1-byte numerical information (“0” to “7”) stored in the A register 101b before execution of the operation of adding “246” is changed to A The value is smaller than the 1-byte numerical information (“10” to “17”) stored in the register 101b.

If the value of the A register 101b before adding "246" is any of the range "1" to "9" to be determined, it will be stored in the A register 101b after the addition of "246". The 1-byte numerical information contained therein is one of "247" to "255". In this way, when the value of the A register 101b before adding "246" is any of "1" to "9", which is the determination target range, after the addition of "246" is completed, A The 1-byte numerical information stored in the register 101b has a value of "247" or more.

If the value of the A register 101b before adding "246" is "0" that is not included in the determination target determination ("1" to "9"), the value of the A register 101b after the addition of "246" The 1-byte numerical information stored in is "246". Also, if the value of the A register 101b before adding "246" is any of "10" to "17" that is not included in the determination target determination ("1" to "9"), "246" is After the addition operation is completed, the 1-byte numerical information stored in the A register 101b is one of "0" to "7". In this way, the value of the A register 101b before adding "246" is either "0" or "10" to "17" that is not included in the determination target determination ("1" to "9"). In this case, the 1-byte numerical information stored in the A register 101b becomes a value less than "247" after the operation of adding "246" is completed.

As described above, the 1-byte numerical information stored in the A register 101b after executing the operation of adding "246" is equal to the 1-byte numerical information stored in the A register 101b before executing the operation of adding "246". If the numerical information is any of "1" to "9" included in the judgment target range, it will be a value of "247" or more, and before executing the operation to add "246", the A register If the 1-byte numerical information stored in 101b is any of "0" and "10" to "17" that are not included in the determination target range, the value is less than "247". Therefore, by determining whether or not the value of the A register 101b is greater than or equal to "247" after executing the operation of adding "246", the number of determinations is suppressed to one while the value of the index value counter 74f is increased. is included in the determination target range of "1" to "9".

Next, the program contents of the lottery result handling process (FIG. 25) executed by the main MPU 72 will be described with reference to the explanatory diagram of FIG. As already explained, the lottery result handling process is executed in step S914 of the winning lottery process (FIG. 18). The processing contents of the lottery result correspondence processing are as explained with reference to the flowchart of FIG. As shown in FIG. 66, "1201" to "1219" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

At the line number "1201", a command "LD A, (YGJTAR)" is set, like the line number "1101" of the AT state signal setting process (FIG. 64(a)) already described. "LD" is an LD instruction as an 8-bit transfer instruction, and "A" is the content specifying the A register 101b as the transfer destination. "YGJTAR" is the address (2 bytes) of the game state area 77 in the main RAM 74, and "(YGJTAR)" is the content specifying the game state area 77 as the transfer source. By executing the command "LD A, (YGJTAR)" at the line number "1201", the data in the gaming state area 77 is transferred to the A register 101b.

The command "AND A, 04H" is set at the line number "1202". "AND" is an AND instruction for calculating a logical product of 8-bit data, and "A" is the A register 101b. As described above, the data of the gaming state area 77 is set in the A register 101b by executing the LD command of line number "1201". As already explained with reference to FIG. 31(b), the second bit of the game state area 77 is provided with a pseudo-bonus state flag 77c. "04H" is mask data "00000100B" for masking with "0" bits other than the second bit in which the data of the pseudo-bonus status flag 77c is set among the data stored in the A register 101b. be. By executing the instruction "AND A, 04H" at the line number "1202", the AND operation of the data stored in the A register 101b and the mask data is executed, and the result of the operation is A Stored in the register 101b. The value of the A register 101b is "04H" when the pseudo-bonus state flag 77c is set to "1", and is "00H" when the value of the pseudo-bonus state flag 77c is "0". becomes.

The command "CP A, 04H" is set at the line number "1203". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "04H" is 1-byte numerical information indicating "4". By executing the instruction "CP A, 04H" at the line number "1203", an operation is performed to subtract "04H" from the value of the A register 101b. The value of the carry flag CF is set to "1" when the 7th bit of the 7 bits is borrowed, and when the most significant bit is not borrowed in the operation, the carry flag CF is set to "1". becomes "0". As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. When "1" is set in the pseudo-bonus status flag 77c, an operation is performed to subtract "04H" from "04H" stored in the A register 101b, so that the most significant bit is borrowed. Therefore, the value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0". On the other hand, when the value of the pseudo-bonus status flag 77c is "0", an operation is performed to subtract "04H" from "00H" stored in the A register 101b, so that the most significant bit is borrowed. As a result, the value of the carry flag CF becomes "1" and the value of the jump flag JF also becomes "1".

The command "JRS 0, ADR123" is set at the line number "1204". "JRS" is a conditional jump instruction with a word length of 1 byte; It specifies "ADR123" which is the program address where the LD instruction of line number "1209" is set as the jump destination program address. The instruction at line number "1204" is set to the program address "ADR121". In the JRS instruction of line number "1204", a 2-byte jump destination program Address (ADR 123) is relatively specified. Compared to the structure using the JP instruction with a word length of 3 bytes or the JR instruction with a word length of 2 bytes, the jump to the jump destination program address is performed using the JRS instruction with a word length of 1 byte. The machine language data capacity of the jump instruction for jumping to the previous program address is reduced. As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". . As shown in FIG. 66, instructions set at program addresses between the program addresses "ADR121" and "ADR123" (LD instruction at line number "1205", AND instruction, CP instruction of line number '1207' and JRS instruction of line number '1208') total word length is 8 bytes. "ADR123" is "(ADR121)+1+8", and is a program address that can be specified as a jump destination program address in the JRS instruction based on the program address (ADR121) where the JRS instruction of line number "1204" is set. is. By executing the instruction "JRS 0, ADR123" at the line number "1204", a jump is made to the program address of the line number "1209" on condition that the value of the jump flag JF is "0". As described above, when the pseudo bonus status flag 77c is set to "1", the value of the jump flag JF is set to "0" by executing the instruction of the line number "1203". Therefore, by executing the instruction "JRS 0, ADR123" at the line number "1204", the program jumps to the program address "ADR123" at the line number "1209". On the other hand, as described above, when the value of the pseudo-bonus status flag 77c is "0", the value of the jump flag JF is set to "1" by executing the instruction of the line number "1203". Therefore, even if the instruction "JRS 0, ADR123" is set in the line number "1204", the program address does not jump, and the program proceeds to the next line number "1205".

The commands of line number "1205" to line number "1208" are commands executed when the gaming state is not the pseudo-bonus state ST4. In line numbers "1205" to "1207", commands similar to line numbers "1101" to "1103" of the already described AT state signal setting process (FIG. 64(a)) are set. . Specifically, the command "LD A, (YGJTAR)" is set at the line number "1205". "LD" is an LD instruction as an 8-bit transfer instruction, "A" is the content specifying the A register 101b as the transfer destination, and "(YGJTAR)" is the content specifying the game state area 77 as the transfer source. be. By executing the command "LD A, (YGJTAR)" at the line number "1205", the data in the gaming state area 77 is transferred to the A register 101b.

The command "AND A, 08H" is set at the line number "1206". "AND" is an AND instruction for calculating a logical product of 8-bit data, and "A" is the A register 101b. As described above, the data of the gaming state area 77 is set in the A register 101b by executing the LD command of line number "1205". As already explained with reference to FIG. 31(b), the third bit of the game state area 77 is provided with an AT state flag 77d. "08H" is mask data "00001000B" for masking with "0" bits other than the third bit in which the data of the AT state flag 77d is set among the data stored in the A register 101b. . By executing the instruction "AND A, 08H" at the line number "1206", the AND operation of the data stored in the A register 101b and the mask data is executed, and the result of the operation is A Stored in the register 101b. The value of the A register 101b becomes "08H" when the AT state flag 77d is set to "1", and becomes "00H" when the value of the AT state flag 77d is "0". .

The command "CP A, 08H" is set at the line number "1207". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "08H" is 1-byte numerical information. By executing the instruction "CP A, 08H" at the line number "1207", an operation is performed to subtract "08H" from the value of the A register 101b. The value of the carry flag CF is set to "1" when the 7th bit of the 7 bits is borrowed, and when the most significant bit is not borrowed in the operation, the carry flag CF is set to "1". becomes "0". As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. When "1" is set in the AT state flag 77d, the operation of subtracting "08H" from "08H" stored in the A register 101b is performed, so that the most significant bit is borrowed. The value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0". On the other hand, when the value of the AT state flag 77d is "0", an operation of subtracting "08H" from "00H" stored in the A register 101b is performed, so that the most significant bit is borrowed. Then, the value of the carry flag CF becomes "1" and the value of the jump flag JF also becomes "1".

The command "JRS 1, ADR125" is set at the line number "1208". "JRS" is a conditional jump instruction with a word length of 1 byte; It specifies "ADR125", which is the program address at which the JRS instruction of line number "1215" is set as the jump destination program address. The instruction at line number "1208" is set to the program address "ADR122". In the JRS instruction of line number "1208", a 2-byte jump destination program The address (ADR 125) is relatively specified. Compared to the structure using the JP instruction with a word length of 3 bytes or the JR instruction with a word length of 2 bytes, the jump to the jump destination program address is performed using the JRS instruction with a word length of 1 byte. The machine language data capacity of the jump instruction for jumping to the previous program address is reduced. As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". . As shown in FIG. 66, instructions set at program addresses between the program addresses "ADR122" and "ADR125" (LD instruction at line number "1209", CP instruction, JRS instruction of line number '1211', LD of line number '1212', ADD instruction of line number '1213' and CP instruction of line number '1214') total word length is 13 bytes. "ADR125" is "(ADR122)+1+13", which is a program address that can be specified as a jump destination program address for the JRS instruction based on the program address (ADR122) where the JRS instruction of line number "1208" is set. be. By executing the instruction "JRS 1, ADR125" at the line number "1208", a jump is made to the line number "1215" on condition that the value of the jump flag JF is "1". As described above, when the value of the AT state flag 77d is "0", the value of the jump flag JF is "1" by executing the instruction of the line number "1207". Therefore, the instruction "JRS 1, ADR125" is executed at line number "1208" to jump to the program address "ADR125" at line number "1215". On the other hand, as described above, when the AT state flag 77d is set to "1", the value of the jump flag JF becomes "0" by executing the instruction of the line number "1207". Therefore, even if the instruction "JRS 1, ADR125" is set in the line number "1208", the program address does not jump, and the program proceeds to the next line number "1209".

The command set to line number "1209" jumps to line number "1209" by the JRS command of line number "1204", or jumps to line number "1208" where the JRS command is set. Executed when the next line number "1209" is reached. Specifically, the instruction set in the line number "1209" is the pseudo bonus state ST4 in which "1" is set in the pseudo bonus state flag 77c or "1" is set in the AT state flag 77d. It is executed in AT state ST5.

The command "LD A, (BTSSCNT)" is set at the line number "1209". "LD" is an LD instruction as an 8-bit data transfer instruction, and "A" is the A register 101b. "BTSSCNT" is the address (2 bytes) of the bet number setting counter 74b in the main side RAM 74, and "(BTSSCNT)" is the content specifying the bet number setting counter 74b as the transfer source. By executing the instruction "LD A, (BTSSCNT)" at the line number "1209", the data stored in the bet number setting counter 74b is transferred to the A register 101b. As a result, when the number of bets in the current game is "3", "03H" is set in the A register 101b, and when the number of bets in the current game is "2", the A register 101b "02H" is set.

The command "CP A, 03H" is set at the line number "1210". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "03H" is 1-byte numerical information indicating "3". By executing the instruction "CP A, 03H" at the line number "1210", an operation is performed to subtract "03H" from the value of the A register 101b. The value of the carry flag CF is set to "1" when the 7th bit of the 7 bits is borrowed, and when the most significant bit is not borrowed in the operation, the carry flag CF is set to "1". becomes "0". As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. When the number of bets in the current game is "3", the operation of subtracting "03H" from "03H" stored in the A register 101b is performed. Therefore, the value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0". On the other hand, if the number of bets in the current game is "2", an operation of subtracting "03H" from "02H" stored in the A register 101b is performed, so that the highest bit is borrowed. Then, the value of the carry flag CF becomes "1" and the value of the jump flag JF also becomes "1". The calculation result of subtracting "03H" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 03H" is executed, the value of the A register 101b does not change.

The command "JRS 1, ADR126" is set at the line number "1211". "JRS" is a conditional jump instruction with a word length of 1 byte; It specifies "ADR126" which is the program address where the LD instruction of line number "1218" is set as the jump destination program address. The instruction at line number "1211" is set to the program address "ADR124". In the JRS instruction of line number "1211", a 2-byte jump destination program The address (ADR 126) is relatively specified. Compared to the structure using the JP instruction with a word length of 3 bytes or the JR instruction with a word length of 2 bytes, the jump to the jump destination program address is performed using the JRS instruction with a word length of 1 byte. The machine language data capacity of the jump instruction for jumping to the previous program address is reduced. As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". . As shown in FIG. 66, instructions set at program addresses between the program addresses "ADR124" and "ADR126" (LD instruction at line number "1212", ADD instruction, CP instruction of line number "1214", JRS instruction of line number "1215", LD instruction of line number "1216" and LD instruction of line number "1217") are 14 bytes in total. "ADR126" is "(ADR124)+1+14", which is a program address that can be specified as a jump destination program address in the JRS instruction based on the program address (ADR124) where the JRS instruction of line number "1211" is set. is. By executing the instruction "JRS 1, ADR126" at the line number "1211", a jump is made to the line number "1218" on condition that the value of the jump flag JF is "1". As described above, when the number of bets in the current game is "2", the value of the jump flag JF is "1" by executing the command of line number "1210". Therefore, the instruction "JRS 1, ADR126" is executed at line number "1211" to jump to the program address "ADR126" at line number "1218". On the other hand, as described above, when the number of bets in the current game is "3", the value of the jump flag JF becomes "0" by executing the command of the line number "1210". Therefore, even if the instruction "JRS 1, ADR126" is set in the line number "1211", the program address does not jump, and the program proceeds to the next line number "1212".

The command of line number "1212" is executed when the player is in the pseudo-bonus state ST4 or the AT state ST5 and the number of bets in the current game is "3". An instruction "LD A, (INDXCNT)" is set at the line number "1212". "LD" is an LD instruction as an 8-bit data transfer instruction, and "A" is the A register 101b. "INDXCNT" is the address (2 bytes) of the index value counter 74f in the main RAM 74, and "(INDXCNT)" is the content specifying the index value counter 74f as the transfer source. By executing the instruction "LD A, (INDXCNT)" at the line number "1209", the data of the index value counter 74f is transferred to the A register 101b. As a result, when any of the index values IV of "1" to "17" is won in the winning lottery process (FIG. 18), the index value IV is set in the A register 101b, In the lottery process (FIG. 18), "0" is set in the A register 101b when none of the index values IV is won.

The command "ADD A, F6H" is set at the line number "1213". "ADD" is an ADD instruction as an addition instruction for 8-bit data, "A" is the A register 101b, and "F6H" is 1-byte numerical data indicating "246". As already explained, "246" is obtained by subtracting "9", which is the maximum value of the determination target range ("1" to "9"), from "255", which is the maximum value in 1-byte numerical information. Numeric value. By executing the instruction "ADD A, F6H" at the line number "1213", an operation is performed to add "246" to the value of the A register 101b, and the result of the operation is written to the A register 101b. . When a carry from the most significant bit (7th bit) occurs in the operation, the carry flag CF is set to "1", and a carry from the most significant bit (7th bit) in the operation is If not, the value of the carry flag CF becomes "0". As already described with reference to FIG. 65, by executing the instruction "ADD A, F6H" at line number "1213", if the value of the index value counter 74f is "0", the A register 101b is "246" and the value of the index value counter 74f is within the range of "1" to "9" for determination, the value of the A register 101b is "247" to "255". In either case, if the value of the index value counter 74f is within the determination range of "10" to "17", the value of the A register 101b is within the range of "0" to "7". In this way, when the value of the index value counter 74f is within the determination target range of "1" to "9", the value of the A register 101b becomes "247" or more, and the index value counter If the value of 74f is either "0" or "10" to "17" which are not included in the determination target range, the value of the A register 101b becomes less than "247".

The command "CP A, F7H" is set at the line number "1214". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "F7H" is 1-byte numerical information indicating "247". By executing the instruction "CP A, F7H" at the line number "1214", an operation of subtracting "F7H" from the value of the A register 101b is performed. The value of the carry flag CF is set to "1" when the 7th bit of the 7 bits is borrowed, and when the most significant bit is not borrowed in the operation, the carry flag CF is set to "1". becomes "0". As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. If the value of the index value counter 74f is within the determination target range of "1" to "9", an operation is performed to subtract "247" from a value greater than or equal to "247". Therefore, the value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0". On the other hand, if the value of the index value counter 74f is either "0" or "10" to "17" which is not included in the determination target range, "247" is subtracted from the value less than "247". Since the operation is performed, the most significant bit is borrowed, the value of the carry flag CF becomes "1", and the value of the jump flag JF also becomes "1".

The command set at line number "1215" is jumped to line number "1215" by the JRS command at line number "1208", or when the CP command at line number "1214" is executed and line number "1215" is Executed when proceeding to First, the case where the CP instruction of line number "1214" is executed and then the instruction of line number "1215" is executed will be described.

The command "JRS 1, ADR 126" is set to the line number "1215" in the same way as the line number "1211". "JRS" is a conditional jump instruction with a word length of 1 byte; It specifies "ADR126" which is the program address where the LD instruction of line number "1218" is set as the jump destination program address. As described above, the instruction at line number "1215" is set to the program address "ADR125". In the JRS instruction of line number "1215", a 2-byte jump destination program The address (ADR 126) is relatively specified. Compared to the structure using the JP instruction with a word length of 3 bytes or the JR instruction with a word length of 2 bytes, the jump to the jump destination program address is performed using the JRS instruction with a word length of 1 byte. The machine language data capacity of the jump instruction for jumping to the previous program address is reduced. As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". . As shown in FIG. 66, an instruction set at a program address existing between program addresses "ADR125" and "ADR126" (LD instructions at line numbers "1216" and "1217") The total word length of is 6 bytes. "ADR126" is "(ADR125)+1+6", and is a program address that can be specified as a jump destination program address in the JRS instruction based on the program address (ADR125) where the JRS instruction of line number "1215" is set. is. By executing the instruction "JRS 1, ADR126" at the line number "1215", a jump is made to the line number "1218" on condition that the value of the jump flag JF is "1". As described above, if the value of the index value counter 74f is either "0" or "10" to "17" that is not included in the determination target range ("1" to "9"), the line number " 1214" is executed, the value of the jump flag JF becomes "1". Therefore, the instruction "JRS 1, ADR126" is executed at line number "1215" to jump to the program address "ADR126" at line number "1218". On the other hand, as described above, when the value of the index value counter 74f is within the determination range of "1" to "9", the instruction of line number "1214" is executed to set the jump flag JF. is "0". Therefore, even if the instruction "JRS 1, ADR126" is set in the line number "1215", the program address does not jump, and the program proceeds to the next line number "1216".

Next, the case where the JRS instruction of line number "1208" jumps to line number "1215" and then the instruction of line number "1215" is executed will be described. As already explained, the instruction "JRS 1, ADR125" is set at the line number "1208", and on the condition that the value of the jump flag JF is "1", the program address of the line number "1215" is set. to jump Specifically, when the value of the pseudo-bonus state flag 77c is "0", the instructions of line numbers "1205" to "1208" are executed, and when the value of the AT state flag 77d is "0" jump from the program address (ADR122) of line number "1208" to the program address (ADR125) of line number "1215". As already explained, the execution of the JRS instruction does not change the state of the jump flag JF. Therefore, when the JRS instruction of line number "1208" jumps to line number "1215" and then the instruction of line number "1215" is executed, the value of the jump flag JF is always "1". , the execution of the instruction "JRS 1, ADR126" at line number "1215" always jumps to the program address at line number "1218".

In this way, when the gaming state is neither the pseudo-bonus state ST4 nor the AT state ST5, the command "JRS 1, ADR125" is executed at the line number "1208" and the line number "ADR125" is executed. By jumping to the program address "1215" and executing the instruction "JRS 1, ADR126" at the line number "1215", the program always jumps to the program address "ADR126" at the line number "1218". The JRS command of line number "1215" is a game in which the pseudo-bonus state ST4 or AT state ST5 and the number of bets is "3". This is an instruction for jumping to the program address of line number "1218" when the index value IV is not won, and on the condition that the value of the jump flag JF is "1", lines from line number "1208" are executed. This is also an instruction for always jumping to the program address of line number "1218" when jumping to the program address of number "1215". Therefore, in a game in which the pseudo-bonus state ST4 or AT state ST5 is set and the number of bets is "3", an index value IV of "1" to "9" is won in the winning lottery process (FIG. 18). As a separate instruction from the instruction for jumping to the program address of line number "1218" if there is not Compared to the configuration in which an instruction to always jump to the program address numbered "1218" is set, the data capacity of the program stored in the main ROM 73 for executing the lottery result handling process (FIG. 66) is reduced. is reduced.

The command of line number "1216" is a game in which the value of the index value counter 74f is in the range of "1" to "9" to be judged in a game in which the pseudo bonus state ST4 or AT state ST5 is set and the number of bets is "3". is executed if either At the line number "1216", the command "LD A, (INDXCNT)" is set, like the line number "1212". "LD" is an LD instruction as an 8-bit transfer instruction, "A" is the A register 101b, and "(INDXCNT)" is the content specifying the index value counter 74f as the transfer source. By executing the instruction "LD A, (INDXCNT)" at line number "1216", the data of the index value counter 74f is transferred to the A register 101b. Since the instruction of line number "1216" is an instruction executed when the value of the index value counter 74f is within the determination target range of "1" to "9", "1" is stored in the A register 101b. to "9" is set.

A command "LD (TJSBCNT), A" is set at the line number "1217". "LD" is the LD instruction as an 8-bit transfer instruction, and "A" is the A register 101b. "TJSBCNT" is the address (2 bytes) of the stop order type counter 74m in the main RAM 74, and "(TJSBCNT)" is the content specifying the stop order type counter 74m as the transfer destination. By executing the instruction "LD (TJSBCNT), A" at the line number "1217", the data of the A register 101b is transferred to the stop order type counter 74m. As a result, one of the stop order type numbers "1" to "9" can be set in the stop order type counter 74m.

As described above, in a game in which the pseudo-bonus state ST4 or AT state ST5 is set and the number of bets is "3", the index value IV , one of the stop order number from "1" to "9" is set in the stop order counter 74m. Then, as already explained, the reels 32L, 32M and 32R are displayed on the shared display unit 66 based on the fact that one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m. is executed, and the stop order notification of the reels 32L, 32M, and 32R is executed on the image display device 63. FIG.

The instruction set at line number "1218" is a line number " 1218" program address (ADR126), or when the LD instruction is executed at line number "1217" to proceed to line number "1218". Specifically, when the gaming state is neither the pseudo-bonus state ST4 nor the AT state ST5, the JRS command of line number "1208" jumps to the program address (ADR125) of line number "1215" and the line The JRS command with number "1215" always jumps to the program address (ADR126) at line number "1218". If the player is in the pseudo-bonus state ST4 or AT state ST5 and the number of bets in the current game is "2", the JRS command of line number "1211" jumps to the program address (ADR126) of line number "1218". . Pseudo-bonus state ST4 or AT state ST5, the number of bets in the current game is "3", and no index value IV of "1" to "9" has been won in the winning lottery process (FIG. 18). In this case, the JRS instruction of line number "1215" jumps to the program address (ADR126) of line number "1218". Pseudo-bonus state ST4 or AT state ST5, the number of bets in this game is "3", and an index value IV of "1" to "9" is won in the lottery process (Fig. 18) If so, set any one of the stop order type numbers "1" to "9" in the stop order type counter 74m, and then proceed to line number "1218".

A command "LD (KSJCAR), 01H" is set at the line number "1218". "LD" is an LD instruction as an 8-bit transfer instruction, and "01H" is 1-byte numerical information "1". "KSJCAR" is the address (2 bytes) of the starting command area provided in the main RAM 74; The starting command area is a 1-byte storage area in which a starting command flag is set, and the starting command flag is set in the least significant bit (0th bit) of the starting command area. Also, the 1st to 7th bits in the command area at start are unused. "(KSJCAR)" is the content specifying the command area at the start of the main RAM 74 as the transfer destination. By executing the command "LD (KSJCAR), 01H" at the line number "1218", "01H" is set in the starting command area of the main RAM 74. FIG. As a result, "1" can be set in the start command flag of the main RAM 74. FIG. As already explained, by setting the start command flag to "1", the process of transmitting the start command to the effect side MPU 92 in the common command transmission process (FIG. 50) is executed.

The command "RET" is set at the line number "1219". "RET" is a return instruction from a subroutine. By executing the command "RET" at the line number "1219", the lottery result handling process (FIG. 66) called in step S914 of the combination lottery process (FIG. 18) ends. As already explained, in the winning lottery process (FIG. 18), when the lottery result handling process is executed in step S914, the lottery process (FIG. 18) for the winning combination ends and the normal process (FIG. 13) is performed. , the process proceeds to the reel control process in step S408.

FIG. 67(a) is an explanatory diagram for explaining the program contents of the first comparative example of the lottery result handling process. As shown in FIG. 67(a), "8001" to "8020" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

In the first comparative example of the lottery result handling process, the index value counter 74f determines whether the value of the index value counter 74f is within the determination target range of "1" to "9". data in the A register 101b, a process of determining whether or not the value of the A register 101b is equal to or greater than "1" which is the minimum value of the determination target range, and a process of determining whether the value of the A register 101b is "1". , and determining whether or not the value of the A register 101b is equal to or less than "9", which is the maximum value of the determination target range.

As shown in FIG. 67(a), the row number "8001" to row number "8011" in the first comparative example of the lottery result handling process are replaced with the row number "1201" of the already explained lottery result handling process (FIG. 66). ” to line number “1211” are set. At the line number "8012" in the first comparative example of the lottery result handling process, the command "LD A, (INDXCNT)" is set, like the line number "1212" of the lottery result handling process (FIG. 66). ing. The data of the index value counter 74f is set in the A register 101b by executing the instruction "LD A, (INDXCNT)" at the line number "8012".

The command "CP A, 01H" is set at the line number "8013". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "01H" is the minimum value of the determination target range ("1" to "9"). ” is 1-byte numerical information. By executing the instruction "CP A, 01H" at the line number "8013", an operation is performed to subtract "01H" from the value of the A register 101b. The value of the carry flag CF is set to "1" when the 7th bit of the 7 bits is borrowed, and when the most significant bit is not borrowed in the operation, the carry flag CF is set to "1". becomes "0". As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. When the value of the index value counter 74f is "1" or more, an operation is performed to subtract "1" from the value of "1" or more. The value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0". On the other hand, when the value of the index value counter 74f is "0", the operation of subtracting "1" from "0" is performed. When it becomes "1", the value of the jump flag JF also becomes "1". The operation result of subtracting "01H" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 01H" is executed, the value of the A register 101b does not change.

The command "JRS 1, ADR807" is set at the line number "8014". "JRS" is a conditional jump instruction with a word length of 1 byte; It specifies "ADR807", which is the program address where the LD instruction of line number "8019" is set as the jump destination program address. The instruction at line number "8014" is set to the program address "ADR805". In the JRS instruction of line number "8014", a 2-byte jump destination program The address (ADR 807) is relatively specified. ADR807 is "(ADR805)+1+9", which is a program address that can be specified as a jump destination program address in the JRS instruction with reference to the program address (ADR805) where the JRS instruction of line number "8014" is set. . By executing the instruction "JRS 1, ADR807" at the line number "8014", a jump is made to the line number "8019" on condition that the value of the jump flag JF is "1". Specifically, when the value of the index value counter 74f is "0", that is, the value of the index value counter 74f is smaller than "1", which is the minimum value of the determination target range ("1" to "9"). , the instruction "JRS 1, ADR807" is executed at line number "8014" to jump to the program address "ADR807" at line number "8019". On the other hand, if the value of the index value counter 74f is greater than or equal to "1", which is the minimum value of the determination target range ("1" to "9"), the command "JRS 1, ADR807" is placed at the line number "8014". is set, the program address does not jump and proceeds to the next line number "8015".

The command "CP A, 0AH" is set at the line number "8015". "CP" is a CP instruction as a comparison instruction for 8-bit data, "A" is the A register 101b, and "0AH" is the maximum value of the determination target range ("1" to "9"). is 1-byte numerical information indicating "10" which is "1" larger than ". By executing the instruction "CP A, 0AH" at the line number "8015", an operation is performed to subtract "0AH" from the value of the A register 101b. The value of the carry flag CF is set to "1" when the 7th bit of the 7 bits is borrowed, and when the most significant bit is not borrowed in the operation, the carry flag CF is set to "1". becomes "0". As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. When the value of the index value counter 74f is "10" or more, an operation is performed to subtract "10" from the value of "10" or more. The value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0". On the other hand, if the value of the index value counter 74f is less than "10", that is, if the value of the index value counter 74f is less than or equal to "9", which is the maximum value of the determination target range, the value less than "10" Since the operation of subtracting "10" is performed, the value of the carry flag CF becomes "1" and the value of the jump flag JF also becomes "1" due to the borrowing to the most significant bit.

The command "JRS 0, ADR807" is set at the line number "8016". "JRS" is a conditional jump instruction with a word length of 1 byte; It specifies "ADR807", which is the program address where the LD instruction of line number "8019" is set as the jump destination program address. The instruction at line number "8016" is set to the program address "ADR806". In the JRS instruction of line number "8016", a 2-byte jump destination program The address (ADR 807) is relatively specified. ADR807 is "(ADR806)+1+6", which is a program address that can be specified as a jump destination program address in the JRS instruction with reference to the program address (ADR806) where the JRS instruction of line number "8016" is set. . By executing the instruction "JRS 0, ADR807" at the line number "8016", a jump is made to the line number "8019" on condition that the value of the jump flag JF is "0". Specifically, when the value of the index value counter 74f is "10" or more, that is, the value of the index value counter 74f is greater than "9", which is the maximum value of the determination target range ("1" to "9"). If it is a large value, the instruction "JRS 0, ADR807" is executed at line number "8016" to jump to the program address "ADR807" at line number "8019". On the other hand, if the value of the index value counter 74f is less than "10", that is, if the value of the index value counter 74f is equal to or less than "9", which is the maximum value of the determination target range ("1" to "9"), , even if the instruction "JRS 0, ADR807" is set at line number "8016", the program address does not jump and proceeds to the next line number "8017".

Line numbers "8017" to "8020" are set with commands similar to line numbers "1216" to "1219" of the lottery result handling process (FIG. 66). The instructions set in line numbers "8017" to "8018" are executed when the value of the index value counter 74f is within the determination target range of "1" to "9". By executing the instruction "LD A, (INDXCNT)" at the line number "8017", the data of the index value counter 74f (numerical information "1" to "9") is stored in the A register 101b. transferred. By executing the instruction "LD (TJSBCNT), A" at the line number "8018", the data of the A register 101b is set in the stop order type counter 74m. As a result, one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m. By executing the instruction "LD (KSJCAR), 01H" at the line number "8019", "01H" is transferred to the starting command area of the main RAM 74, and "1" is set to the starting command flag of the main RAM 74. ” is set. By executing the command "RET" at the line number "8020", the first comparative example (FIG. 67(a)) of the lottery result handling process ends.

FIG. 67(b) shows the index value IV in the determination target range (“1” to “9”) in the lottery result handling process (FIG. 66) and the first comparative example of the lottery result handling process (FIG. 67(a)). FIG. 11 is an explanatory diagram for explaining a command set for executing a process of setting a stop order type number in a stop order type counter 74m on condition that a prize is won;

In the lottery result handling process (FIG. 66), the instruction for executing the process of setting the stop order type number in the stop order type counter 74m on the condition that the index value IV in the determination target range is won is the row number. "1212" to line number "1217" are set. Also, in the first comparative example of the lottery result handling process (FIG. 67(a)), the process of setting the stop order type number to the stop order type counter 74m on the condition that the index value IV in the determination target range is won. are set in line numbers "8012" to "8018". In the first comparative example (FIG. 67(a)) of the lottery result handling process, three 3-byte LD instructions are set in line number "8012" to line number "8018", and a 2-byte CP instruction is set. Two are set, and two 1-byte JRS instructions are set. The total word length of the instructions set from line number "8012" to line number "8018" is 15 bytes. On the other hand, three 3-byte LD instructions and one 2-byte ADD instruction are set in line numbers "1212" to "1217" of the lottery result handling process (FIG. 66). , one 2-byte CP instruction is set, and one 1-byte JRS instruction is set. The total word length of the instructions set from line number "1212" to line number "1217" is 14 bytes.

As already explained, the lottery result handling process (FIG. 66) sets the value of the A register 101b, in which the data of the index value counter 74f is set, to the determination target range from "255", which is the maximum value in the 1-byte numerical information. A process of adding "246", which is a value calculated by subtracting "9", which is the maximum value of ("1" to "9"), and adding "246" to the A register 101b a process of determining whether or not the stored 1-byte numerical information is greater than or equal to "247" which is a value calculated by adding "246" to "1" which is the minimum value of the determination target range; , is a processing configuration for performing As a result, the value of the A register 101b in which the data of the index value counter 74f is set is within the determination target range ("1" to "9 ”), and a process of determining whether the value of the A register 101b is equal to or less than “9”, which is the maximum value of the determination target range. and, in comparison with the processing configuration for performing The total word length can be reduced. Therefore, it is possible to reduce the data volume of the program stored in the main ROM 73 for executing the lottery result handling process (FIG. 66).

The number of jump instructions (JRS instructions) set in line number "1212" to line number "1217" in the lottery result response process (Fig. 66) is the same as in the first comparative example of the lottery result response process (Fig. 67(a) ) is smaller than the number of jump instructions (JRS instructions) set in line numbers "8012" to "8018". By reducing the number of jump instructions, the risk of unused programs can be reduced.

FIG. 68(a) is for explaining the jump instruction set for jumping from the program address "ADR122" and the program address "ADR125" to the program address "ADR126" in the lottery result handling process (FIG. 66). is an explanatory diagram of . As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set) + 1-16" to "(the program address where the JRS instruction is set) + 1 + 15". . As shown in FIG. 66, "ADR126" is "(ADR122)+1+20", and with the program address (ADR122) at which the JRS instruction of line number "1208" is set as a reference, the jump destination program A program address that cannot be specified as an address.

In the lottery result handling process (FIG. 66), the JRS instruction to jump is set to the program addresses "ADR122" and "ADR125" on the condition that the value of the jump flag JF is "1". In the lottery result correspondence process (FIG. 66), the program address (ADR122) where the JRS instruction of line number "1208" is set is used as a reference, utilizing the fact that the state of the jump flag JF does not change even if the JRS instruction is executed. jumps to "ADR125", which is a program address that can be specified as the program address of the jump destination in the JRS instruction, and jumps to the program address "ADR126" by the JRS instruction set to the program address of "ADR125". is.

As already explained, the JRS command of line number "1215" is "1" in the winning lottery process (FIG. 18) in a game in which the pseudo-bonus state ST4 or AT state ST5 is set and the number of bets is "3". This is an instruction for jumping to the program address of the line number "1218" when the index value IV of "9" is not won, and is executed on the condition that the value of the jump flag JF is "1". This is also an instruction to always jump to the program address of line number "1218" when jumping from number "1208" to the program address of line number "1215".

FIG. 68(b) explains the jump instruction set to jump from the program address "ADR122" and the program address "ADR125" to the program address "ADR126" in the second comparative example of the lottery result handling process. It is an explanatory diagram for. As already explained, the range that can be jumped by the JR instruction is the range from "(the program address where the relevant JR instruction is set) + 2 - 128" to "(the program address where the relevant JR instruction is set) + 2 + 127". . As described above, "ADR126" is "(ADR122)+1+20" and is a program address that can be specified as a jump destination program address in a JR instruction with ADR122 as a reference. In the second comparative example of the lottery result handling process (FIG. 68(b)), the command "JRC, ADR126" is set at the program address "ADR122". "JR" is a jump instruction with a word length of 2 bytes, "C" is a jump condition that the carry flag CF is set to "1", and "ADR126" is It is the contents of designating the program address "ADR126" as the jump destination program address. As already explained, in the JR instruction, based on the program address (ADR122) set in the JR instruction and the difference information (8 bits) set in the JR instruction, a 2-byte jump destination program address (ADR 126) is relatively specified. Further, as already explained, when the CP instruction is executed, the value of the jump flag JF becomes the same as the value of the carry flag CF. In the second comparative example of the lottery result handling process (FIG. 68(b)), the instruction "JRC, ADR126" is set at the program address "ADR122", so the carry flag CF is set to "1". on the condition that the program address "ADR125" is skipped and the program address "ADR126" is directly jumped to.

As described above, the JRS command of line number "1215" is "1" to "1" in the lottery process (Fig. Direct jump from line number "1208" to line number "1218" because it is an instruction to jump to the program address of line number "1218" when index value IV of "9" is not won. Even in such a configuration, the JRS instruction of the line number "1215" cannot be omitted.

As shown in FIG. 68(b), in the second comparative example (FIG. 68(b)) of the lottery result handling process, the program address "ADR122" and the program address "ADR125" are jumped to the program address "ADR126". The total word length of the jump instructions set for is 3 bytes. On the other hand, as shown in FIG. 68(a), it is set to jump from the program address "ADR122" and the program address "ADR125" to the program address "ADR126" in the lottery result handling process (FIG. 66). The total word length of the jump instructions being executed is 2 bytes.

As described above, the lottery result handling process (FIG. 66) sets the JRS instruction to jump to the program addresses "ADR122" and "ADR125" on the condition that the value of the jump flag JF is "1". , the state of the jump flag JF does not change even if the JRS instruction is executed. A process of jumping to the program address of line number "1215" by an instruction and reliably jumping to the program address of line number "1218" by a JRS instruction with a word length of 1 byte set to the jump destination line number "1215". Configuration. As a result, as in the second comparative example (FIG. 68(b)) of the lottery result handling process, the word length is 2 bytes on the condition that the carry flag CF is set to "1" at the line number "1208". Compared to the processing configuration that directly jumps to the line number "1218" by the JR instruction, the jump instruction set to jump from the program address "ADR122" and the program address "ADR125" to the program address "ADR126" Word length can be reduced. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 for executing the lottery result handling process (FIG. 66).

<Contents of program for additional processing at start>
Next, prior to the description of the program contents (see FIG. 69(b)) of the additional processing at start (FIG. 43(c)) executed by the main MPU 72, the index of the main RAM 74 in the additional processing at start The contents of processing for determining whether the value of the value counter 74f is any one of "11" to "15" will be described.

In the following description, the numerical range of "11" to "15", which is the object of determination in determining whether or not the value of the index value counter 74f is included in the numerical range of "11" to "15", is referred to as the "first It is also referred to as “the lottery target range”. In determining whether or not the value of the index value counter 74f is included in the numerical range of "14" to "15", the numerical range of "14" to "15" to be determined is determined by the "second lottery Also called "coverage". As already explained, the add-on processing at the start is executed in the AT state ST5. In addition, as already explained, in the process for addition at the start, first if the index value IV in the first lottery target range ("11" to "15") is won in the role lottery process (Fig. 18) The first additional lottery table 73d (Fig. 43(a)) is selected as the lottery table to be referred to, and the index value of the second lottery target range ("14" to "15") is selected in the winning lottery process (Fig. 18). When IV is won, the lottery table to be referred to is changed to the second add-on lottery table 73e (FIG. 43(b)) which is more advantageous for the player than the first add-on lottery table 73d. Then, in the winning lottery process (FIG. 18), if any of the index values IV of "11" to "13" which are within the range of the first lottery and are not within the range of the second lottery are won, the An additional lottery is executed based on the 1 additional lottery table 73d. In addition, in the winning lottery process (FIG. 18), if the index value IV of "14" or "15", which is the first lottery target range and the second lottery target range, is won, the second additional lottery An additional lottery is executed based on the table 73e.

The main MPU 72 first transfers the data of the index value counter 74f in the main RAM 74 to the A register 101b. After that, by executing the command "SUB A, 0BH" at line number "1302" of the process for addition at start (Fig. 69(b)), which will be described later, "11" is subtracted from the value of the A register 101b. perform calculations. The "11" subtracted from the value of the A register 101b is the minimum value of the first lottery target range ("11" to "15"). The operation of subtracting "11" is a numerical range ("0" to "255") that can represent the minimum value ("11") of the first lottery target range ("11" to "15") with 8 bits. ) to the minimum value (“0”). By this calculation, the first lottery target range is shifted to the smaller side by "11". By the operation of subtracting "11", the maximum value ("15") of the first lottery target range shifts to the smaller side by "11" and becomes "4". Details of the SUB instruction of line number "1302" will be described later.

FIG. 69(a) is for explaining the relationship between the value of the A register 101b before the subtraction of "11", the value of the A register 101b after the subtraction of "11", and the value of the carry flag CF after the subtraction of "11". It is an explanatory diagram. As shown in FIG. 69(a), when the value of the A register 101b before subtracting "11" is any one of "11" to "17", that is, when the value of the A register 101b before subtracting "11" is the 1 If the minimum value of the lottery target range (“11” to “15”) is “11” or more, the most significant bit of the A register 101b during the execution of the operation of subtracting “11” from the value of the A register 101b (7th bit among 0th to 7th bits) is not borrowed. Therefore, the value of the carry flag CF after the subtraction of "11" becomes "0". The 1-byte numerical information (“0” to “6”) stored in the A register 101b after the operation of subtracting “11” is The value is smaller than the 1-byte numerical information (“11” to “17”) stored in 101b.

If the value of the A register 101b before subtracting "11" is any one of "0" to "10", that is, the value of the A register 101b before subtracting "11" is the minimum of the first lottery target range. If the value is smaller than the value of "11" (a value of "10" or less), the most significant bit of the A register 101b (the 0th to the 7th bit in the 7th bit). Therefore, the value of the carry flag CF after subtraction of "11" becomes "1". The 1-byte numerical information (“245” to “255”) stored in the A register 101b after the operation of subtracting “11” is The value is greater than the 1-byte numerical information (“0” to “10”) stored in 101b.

If the value of the A register 101b before the subtraction of "11" is any of the first lottery target range of "11" to "15", it will be stored in the A register 101b after the operation of subtracting "11" The 1-byte numerical information contained therein is one of "0" to "4". In this way, when the value of the A register 101b before the subtraction of "11" is included in the first lottery target range, the 1 byte stored in the A register 101b after the operation of subtracting "11" is completed. becomes a value less than "5".

If the value of the A register 101b before subtracting "11" is any of "0" to "10" that is not included in the first lottery target range ("11" to "15"), "11" The 1-byte numerical information stored in the A register 101b after the subtraction operation is completed is any one of "245" to "255". Also, if the value of the A register 101b before the subtraction of "11" is "16" or "17" that is not included in the first lottery target range, it is stored in the A register 101b after the operation of subtracting "11" is completed. The 1-byte numerical information contained in the data is "5" or "6". In this way, if the value of the A register 101b before the subtraction of "11" is any of "0" to "10" and "16" to "17" that are not included in the first lottery target range, " After the operation of subtracting "11" is completed, the 1-byte numerical information stored in the A register 101b becomes a value of "5" or more.

As described above, the 1-byte numerical information stored in the A register 101b after the operation of subtracting "11" is such that the value of the A register 101b before the subtraction of "11" is included in the first lottery target range. If there is, the value is less than "5", and the value of the A register 101b before subtraction of "11" is not included in the first lottery target range "0" to "10" and "16" to "17" , the value is "5" or more. Therefore, by determining whether or not the 1-byte numerical information stored in the A register 101b is less than "5" after executing the operation of subtracting "11", the number of determinations is suppressed to one. Meanwhile, it is possible to determine whether or not the value of the index value counter 74f is included in the first lottery object range of "11" to "15".

As shown in FIG. 69(a), the value of the index value counter 74f is included in the first lottery target range ("11" to "15") and the second lottery target range ("14" to "15"). ), the 1-byte numerical information stored in the A register 101b after the operation of subtracting "11" is changed from "0" to " 2” (a value less than “3”). On the other hand, if the value of the index value counter 74f is "14" or "15" which is included in the first lottery target range ("11" to "15") and is also included in the second lottery target range. , and "11" are subtracted, the 1-byte numerical information stored in the A register 101b becomes "3" or "4" (a value equal to or greater than "3"). Therefore, after determining that the value of the index value counter 74f is included in the first lottery object range of "11" to "15", the 1-byte numerical information stored in the A register 101b is "3". By determining whether or not it is less than 1, it is determined whether or not the value of the index value counter 74f is included in the second lottery target range of "14" to "15" while suppressing the number of determination times to one. It can be performed.

In order to specify that the index value IV is included in the second lottery target range ("14" to "15"), the index value IV before subtraction of "11" is the minimum value of the second lottery target range. Considering the configuration for determining whether or not it is "14" or more, the boundary value when determining whether or not the index value IV is included in the second lottery target range ("14" to "15") is It becomes "14". On the other hand, after performing a calculation (calculation to subtract "11") to change the first lottery target range ("11" to "15") to the side smaller by "11", the value after the calculation is A configuration for determining whether or not the minimum value (“14”) of the second lottery target range (“14” to “15”) is “3” or more, which is a value that is changed to the smaller side by “11” By doing so, the boundary value when determining whether or not the index value IV is included in the second lottery target range (“14” to “15”) is set to “3” which is a value smaller than “14”. can do. The number of bits required to represent the boundary value (“3”) when determining whether or not the value obtained by shifting the index value IV to the smaller side by “11” is greater than or equal to “3” is “2”. , and the number of bits is necessary to represent the boundary value ("14") when determining whether the index value IV before change is equal to or greater than "14", which is the minimum value of the second lottery target range. number of bits ("4"). In this way, in the configuration in which the index value IV is subtracted by "11" in order to specify that the index value IV is included in the first lottery target range, the index value IV is reduced by "11". In order to represent the boundary value in the determination by using the value after the variation to determine whether the index value before the variation is included in the second lottery target range. can be reduced. Thereby, the data capacity for storing the boundary value can be reduced.

Next, the program contents of the process for addition at start (FIG. 43(c)) executed by the main MPU 72 will be described with reference to the explanatory diagram of FIG. 69(b). As already explained, the addition processing at the start is executed in step S2310 of the advantageous state processing (FIG. 40) at the start of the game. The details of the processing for addition at the time of start have already been described with reference to the flowchart of FIG. 43(c). As shown in FIG. 69(b), "1301" to "1309" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

At the line number "1301", a command "LD A, (INDXCNT)" is set, like the line number "1212" of the lottery result handling process (FIG. 66). "LD" is an LD instruction as a transfer instruction for 8-bit data, "A" is the A register 101b, and "(INDXCNT)" is the content specifying the index value counter 74f of the main RAM 74 as the transfer source. . The data of the index value counter 74f is transferred to the A register 101b by executing the instruction "LD A, (INDXCNT)" at the line number "1301". As a result, when any of the index values IV of "1" to "17" is won in the winning lottery process (FIG. 18), the index value IV is set in the A register 101b, In the lottery process (FIG. 18), "0" is set in the A register 101b when none of the index values IV is won.

The command "SUB A, 0BH" is set at the line number "1302". "SUB" is a SUB instruction as an 8-bit data subtraction instruction, "A" is the A register 101b, and "0BH" is the minimum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating "11". By executing the instruction "SUB A, 0BH" at line number "1302", an operation is performed to subtract "11" from the value of the A register 101b, and the result of this operation is written to the A register 101b. . When a carry flag CF is set to "1" when a borrow occurs in the most significant bit (7th bit) in the operation, the carry flag CF is set to "1", and If no borrowing occurs, the value of the carry flag CF becomes "0". As already explained with reference to FIG. 69(a), when the value of the index value counter 74f is included in the first lottery target range ("11" to "15"), the value of the A register 101b is " 5" and the value of the index value counter 74f is not included in the first lottery target range ("11" to "15") "0" to "10" and "16" to "17" , the value of the A register 101b is "5" or more. Further, as already described with reference to FIG. 69(a), the value of the index value counter 74f is included in the first lottery target range ("11" to "15") and the second lottery target range (" 14” to “15”), the value of the A register 101b becomes less than “3” and the value of the index value counter 74f. is included in the first lottery target range ("11" to "15") and is "14" or "15" which is also included in the second lottery target range, the value of the A register 101b is It becomes a value of "3" or more.

The command "CP A, 05H" is set at the line number "1303". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "05H" is the maximum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating a value (“5”) that is “1” larger than “4”, which is a value calculated by subtracting “11” from “15”. By executing the instruction "CP A, 05H" at the line number "1303", an operation of subtracting "5" from the value of the A register 101b is performed. If the value of the A register 101b before the subtraction of "5" is less than "5", that is, if the value of the index value counter 74f is included in the first lottery target range ("11" to "15") , the value of the carry flag CF becomes "1" due to borrowing to the most significant bit (the 7th bit among the 0th to 7th bits) in the calculation. On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or more, that is, the value of the index value counter 74f is not included in the first lottery target range ("11" to "15"). 0" to "10" and "16" to "17", no borrowing to the most significant bit (7th bit in 0th to 7th bits) occurs in the calculation Therefore, the value of the carry flag CF becomes "0". The operation result of subtracting "5" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 05H" is executed, the value of the A register 101b does not change. Therefore, the data stored in the A register 101b by subtracting "11" at line number "1302" can also be used at line number "1306", which will be described later.

A command "RET NC" is set at the line number "1304". "RET" is a RET instruction as an instruction to return from a subroutine, and "NC" is a content that sets the condition that the value of the carry flag CF is "0" as a condition for returning from the subroutine. . By executing the instruction "RET NC" at the line number "1304", the step of the advantageous state processing (FIG. 40) at the start of the game is performed on the condition that the value of the carry flag CF is "0". The process for addition at the start called in S2310 is ended, and the process returns to step S2311 following step S2310. As described above, the value of the index value counter 74f is any of "0" to "10" and "16" to "17" that are not included in the first lottery target range ("11" to "15"). In this case, the value of carry flag CF becomes "0" by executing the instruction of line number "1303". Therefore, by executing the command "RET NC" at the line number "1304", the addition process at the start is terminated, and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). . On the other hand, as described above, when the value of the index value counter 74f is included in the first lottery target range (“11” to “15”), the instruction of line number “1303” is executed to carry The value of the flag CF becomes "1". Therefore, even if the command "RET NC" is set in the line number "1304", the processing for addition at start will not end, and the process will proceed to the next line number "1305".

The command of line number "1305" is executed when the AT state ST5 is set and the index value IV of the first lottery target range ("11" to "15") is won in the winning lottery process (FIG. 18). executed. The command "LD HL, KSADD01" is set at the line number "1305". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD01" is the start address of the first addition lottery table 73d in the main ROM 73. be. The start address of the first addition lottery table 73d is transferred to the HL register 104 by executing the instruction "LD HL, KSADD01" at the line number "1305". As a result, the first additional lottery table 73d can be set as the lottery table to be referenced in the additional lottery. In this way, when the AT state ST5 is reached and the index value IV in the first lottery target range ("11" to "15") is won in the role lottery process (FIG. 18), the reference target A first additional lottery table 73d is set as the lottery table.

The command "CP A, 03H" is set at the line number "1306". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "03H" is the minimum value of the second lottery target range ("14" to "15"). This is 1-byte numerical information indicating a value (“3”) calculated by subtracting “11” from “14”. As described above, the A register 101b stores 1-byte numerical information calculated by subtracting "11" from the row number "1302". Since the instruction of line number "1306" is executed when the index value IV in the first lottery target range ("11" to "15") is won in the winning lottery process (Fig. 18), the A register The value of 101b is one of "0" to "4". By executing the instruction "CP A, 03H" at the line number "1306", an operation of subtracting "3" from the value of the A register 101b is performed. As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. If the value of the A register 101b before the subtraction of "3" is less than "3", that is, the value of the index value counter 74f is "11" which is not included in the second lottery target range ("14" to "15"). to "13", the carry flag CF is set to "1" by borrowing to the most significant bit (the 7th bit among the 0th to 7th bits) in the operation. At the same time, the value of the jump flag JF also becomes "1". On the other hand, when the value of the A register 101b before the subtraction of "3" is "3" or more, that is, when the value of the index value counter 74f is "14" or "15" included in the second lottery target range. , the value of the carry flag CF becomes "0" and the value of the jump flag JF is changed to is also "0". As described above, the index value before the change is included in the second lottery target range ("14" to "15") by using the value after the index value IV is changed to the smaller side by "11". By adopting a configuration in which determination is made to specify that, the number of bits for representing the boundary value (“3”) in the determination can be reduced. Thereby, the data capacity for storing the boundary value can be reduced.

The command "JRS 1, ADR132" is set at the line number "1307". "JRS" is a conditional jump instruction with a word length of 1 byte; This is the contents of setting the program address of line number "1309" of "ADR132" as the jump destination. The instruction at line number "1307" is set to the program address "ADR131". As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set) + 1-16" to "(the program address where the JRS instruction is set) + 1 + 15". . As shown in FIG. 69(b), the word length of the instruction (the LD instruction of line number "1308") set at the program address existing between the program addresses "ADR131" and "ADR132" is 3 bytes. "ADR132" is "(ADR131)+1+3", and is a program address that can be specified as a jump destination program address in the JRS instruction based on the program address (ADR131) where the JRS instruction of line number "1307" is set. is.

As described above, the value of the index value counter 74f is included in the first lottery target range (“11” to “15”) and is not included in the second lottery target range (“14” to “15”). If it is any one of "11" to "13", the value of jump flag JF becomes "1" by executing the instruction of line number "1306". Therefore, the instruction "JRS 1, ADR132" is executed at line number "1307" to jump to the program address "ADR132" at line number "1309". On the other hand, as described above, the value of the index value counter 74f is included in the first lottery target range (“11” to “15”) and is also included in the second lottery target range (“14” to “15”). If it is "14" or "15", the value of the jump flag JF becomes "0" by executing the instruction of the line number "1306". Therefore, even if the instruction "JRS 1, ADR132" is set in the line number "1307", the program address does not jump, and the program proceeds to the next line number "1308".

The command of line number "1308" is executed when the AT state is ST5 and the index value IV of the second lottery target range ("14" to "15") is won in the winning lottery process (FIG. 18). executed. A command "LD HL, KSADD02" is set at the line number "1308". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD02" is the second addition lottery table 73e (Fig. 43 ( b)) is the starting address. The start address of the second addition lottery table 73e is transferred to the HL register 104 by executing the instruction "LD HL, KSADD02" at the line number "1308". As a result, the lottery table to be referred to can be changed from the first additional lottery table 73d to the second additional lottery table 73e, which is more advantageous to the player than the first additional lottery table 73d. In this way, when the AT state ST5 and the index value IV of the second lottery target range ("14" to "15") are won in the role lottery process (FIG. 18), the additional lottery A second additional lottery table 73e is set as a lottery table to be referred to.

The instruction set to line number "1309" is jumped to line number "1309" by the JRS instruction of line number "1307", or when the LD instruction of line number "1308" is executed, line number "1309" Executed when proceeding to Specifically, in the AT state ST5, it is included in the first lottery target range ("11" to "15") and the second lottery target range ("14" to "15"), jumps to the program address of line number "1309" by the JRS command of line number "1307" and jumps to the program address of line number "1309" the instruction is executed. In addition, in the AT state ST5, in the winning lottery process (FIG. 18), it is included in the first lottery target range ("11" to "15") and the second lottery target range ("14" to "15") ), the instruction of line number "1309" is executed after executing the LD instruction of line number "1308".

The command "JP ADR133" is set at the line number "1309". "JP" is a JP instruction as an unconditional jump instruction with a word length of 3 bytes, and "ADR133" is set with an instruction for executing the processing of step S1802 in the unlock game number lottery processing (FIG. 35(b)). program address (2 bytes). By executing the instruction "JP ADR133" at the line number "1309", the program jumps to the program address "ADR133". Then, by executing the processes of steps S1802 to S1807 of the number-of-release-games lottery process (FIG. 35(b)), an extra lottery for the remaining number of continuous games in the AT state ST5 is executed. As already explained, it is in the AT state ST5 and is included in the first lottery target range ("11" to "15") in the role lottery process (Fig. 18) and the second lottery target range ("14" to "15"), the additional lottery is executed with the first additional lottery table 73d set as the lottery table to be referred to. In addition, it is in the AT state ST5 and is included in the first lottery target range ("11" to "15") in the role lottery process (Fig. 18) and is included in the second lottery target range ("14" to "15"). )), the additional lottery is executed with the second additional lottery table 73e set as the lottery table to be referred to.

The JP instruction at line number "1309" is an instruction for jumping to the program address "ADR133" after changing the lottery table to be referenced at line number "1308" to the second additional lottery table 73e. This instruction enables a jump to the program address of "ADR133" without fail when the JRS instruction of number "1307" jumps to the program address of line number "1309". For this reason, after changing the lottery table to be referred to at line number "1308" to the second additional lottery table 73e, an instruction different from the instruction for jumping to the program address "ADR133" is executed at line number "1307". In contrast to the configuration in which an instruction is set to ensure jumping to the program address "ADR133" when jumping with the JRS instruction of , the main-side ROM 73 is stored in order to execute the additional processing at the start. The data capacity of the program can be reduced.

As already described, in the number-of-released-games lottery process (FIG. 35), after setting the number-of-released-games lottery table 73c as the lottery table to be referenced in step S1801, steps S1802 to S1807 are executed without calling the subroutine program. Lottery execution processing is executed. The lottery execution process (steps S1802 to step S1807) is a process executed after the process of step S1801 is executed in the number-of-released-games lottery process (FIG. 35). ) is executed when jumping is performed by the JP instruction of line number “1309”. If the lottery execution process (steps S1802 to S1807) is a common subroutine called in the number-of-released-games lottery process (FIG. 35) and the start-up addition process (FIG. 69(b)), the number of unlocked games In the lottery process (FIG. 35), it is necessary to set a CALL instruction (3 bytes) for calling the lottery execution process after the instruction for executing the process of step S1801. In this configuration, a CALL instruction is set in place of the JP instruction at the line number "1309" of the start-up addition processing (FIG. 69(b)), but the word length (3 bytes) of the CALL instruction is It is the same as the word length (3 bytes) of the JP instruction. For this reason, if a common subroutine called lottery execution processing is called in the unlocked game number lottery process (FIG. 35) and the addition process at the start (FIG. 69(b)), then the unlocked game number lottery process (FIG. 35) The data capacity of the program stored in the main ROM 73 increases by the amount of the set CALL command in order to execute the number-of-release-games lottery process (FIG. 35) and the extra process at the start (FIG. 69(b)). end up

In this embodiment, by executing the JP command "JP ADR133" at the line number "1309" of the process for addition at the start (FIG. 69(b)), the cancellation game number lottery process (FIG. 35(b)) is executed. The process configuration jumps to the program address (ADR133) where the command for executing the process of step S1802 is set, and the process of step S1801 is executed in the unlock game number lottery process (FIG. 35(b)). In this processing configuration, the processing of step S1802 is executed without calling the subroutine program when the subroutine program is called. For this reason, compared to a configuration in which a common subroutine called lottery execution processing is called in the number-of-released-games lottery process (FIG. 35) and the addition-at-start process (FIG. 69B), the number-of-release-games lottery process (FIG. ) and the processing for addition at the start (FIG. 69(b)), the data capacity of the program stored in the main ROM 73 can be reduced.

FIG. 70(a) is an explanatory diagram for explaining the contents of a program in the first comparative example of the addition processing at the start. As shown in FIG. 70(a), "8101" to "8110" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

In the first comparative example of the addition processing at the start, in order to determine whether or not the value of the index value counter 74f is a value included in the first lottery target range ("11" to "15"), A process of setting the data of the index value counter 74f in the A register 101b, a process of determining whether or not the value of the A register 101b is equal to or greater than "11", which is the minimum value of the first lottery target range, and the A register. A processing configuration for determining whether or not the value of the A register 101b is equal to or less than "15", which is the maximum value of the first lottery target range, when it is determined that the value of 101b is equal to or greater than "11". is. In addition, in the first comparative example of the addition processing at the start, when the value of the index value counter 74f is within the first lottery target range, the value of the index value counter 74f is within the second lottery target range ("14" to "15"), the process of determining whether the value of the A register 101b is equal to or greater than "14", which is the minimum value of the second lottery target range. Configuration.

As shown in FIG. 70(a), the line number "8101" in the first comparative example of the additional processing at start is similar to the line number "1301" in the additional processing at start (FIG. 69(b)). , an instruction "LD A, (INDXCNT)" is set. The data of the index value counter 74f is transferred to the A register 101b by executing the instruction "LD A, (INDXCNT)" at the line number "8101". As a result, when any of the index values IV of "1" to "17" is won in the winning lottery process (FIG. 18), the index value IV is set in the A register 101b, In the lottery process (FIG. 18), "0" is set in the A register 101b when none of the index values IV is won.

The command "CP A, 0BH" is set at the line number "8102". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "0BH" is the minimum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating "11". By executing the instruction "CP A, 0BH" at the line number "8102", an operation of subtracting "11" from the value of the A register 101b is performed. As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. If the value of the A register 101b before the subtraction of "11" is any one of "0" to "10", that is, the value of the index value counter 74f is the minimum of the first lottery target range ("11" to "15"). If it is less than the value "11", then the most significant bit (the 7th bit among the 0th to 7th bits) is borrowed in the operation, and the value of the carry flag CF becomes "1". At the same time, the value of the jump flag JF also becomes "1". On the other hand, if the value of the A register 101b before the subtraction of "11" is any one of "11" to "17", that is, if the value of the index value counter 74f is "11" or more, the maximum Since there is no borrowing to the upper bit (the 7th bit among the 0th to 7th bits), the value of the carry flag CF becomes "0" and the value of the jump flag JF also becomes "0". The operation result of subtracting "11" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 0BH" is executed, the value of the A register 101b does not change. The data transferred from the index value counter 74f to the A register 101b at line number "8101" is also used at line number "8104" to be described later.

A command "RET C" is set at the line number "8103". "RET" is a RET instruction to return from the subroutine, and "C" is a condition for returning from the subroutine that the carry flag CF is set to "1". be. By executing the instruction "RET C" at the line number "8103", the first comparative example of the add-on process at the start ends on the condition that the carry flag CF is set to "1". Specifically, when the value of the index value counter 74f is any one of "0" to "10", the carry flag CF is set to "1". End the comparative example. On the other hand, if the value of the index value counter 74f is any one of "11" to "17", the value of the carry flag CF is "0", so the first comparative example of the add-on processing at the start ends. and proceed to the next line number "8104".

The command "CP A, 10H" is set at the line number "8104". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "10H" is the maximum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating "16" which is "1" larger than "15". As described above, the A register 101b stores the data transferred from the index value counter 74f to the A register 101b at the line number "8101". By executing the instruction "CP A, 10H" at the line number "8104", an operation of subtracting "16" from the value of the A register 101b is performed. As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. Further, the instruction of line number "8104" is executed under the condition that the value of the index value counter 74f is any one of "11" to "17". If the value of the A register 101b before the subtraction of "16" is less than "16", that is, if the value of the index value counter 74f is within the first lottery target range of "11" to "15" , the value of the carry flag CF becomes "1" and the value of the jump flag JF becomes "1" as a result of borrowing to the most significant bit (the 7th bit among the 0th to 7th bits) in this operation. becomes. On the other hand, if the value of the A register 101b before the subtraction of "16" is "16" or more, that is, if the value of the index value counter 74f is "16" or "17" which is not included in the first lottery object determination. , the value of the carry flag CF becomes "0" and the value of the jump flag JF is changed to is also "0". The operation result of subtracting "16" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 10H" is executed, the value of the A register 101b does not change. The data transferred from the index value counter 74f to the A register 101b at line number "8101" is also used at line number "8107" to be described later.

A command "RET NC" is set at the line number "8105". "RET" is a RET instruction as an instruction to return from a subroutine, and "NC" is a content that sets the condition that the value of the carry flag CF is "0" as a condition for returning from the subroutine. . By executing the instruction "RET NC" at the line number "8105", the add-on processing at the start is completed on condition that the value of the carry flag CF is "0". Specifically, when the value of the index value counter 74f is "16" or "17", the value of the carry flag CF is "0", so the addition process at the start ends. On the other hand, if the value of the index value counter 74f is within the first lottery target range of "11" to "15", the value of the carry flag CF is "1", so the process returns from the subroutine. , and proceed to the next line number "8106".

At the line number "8106", a command "LD HL, KSADD01" is set, like the line number "1305" of the process for addition at start (Fig. 69(b)). The start address of the first addition lottery table 73d is transferred to the HL register 104 by executing the instruction "LD HL, KSADD01" at the line number "8106". As a result, the first additional lottery table 73d is set as the lottery table to be referred to.

The command "CP A, 0EH" is set at the line number "8107". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "0EH" is the minimum value of the second lottery target range ("14" to "15"). This is 1-byte numerical information indicating "14". As described above, the A register 101b stores the data transferred from the index value counter 74f to the A register 101b at the line number "8101". By executing the instruction "CP A, 0EH" at the line number "8107", an operation of subtracting "14" from the value of the A register 101b is performed. As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. Further, the command of line number "8107" is executed under the condition that the value of the index value counter 74f is any one of "11" to "15", which is the first lottery target range. If the value of the A register 101b before the subtraction of "14" is less than "14", that is, the value of the index value counter 74f is included in the first lottery target range ("11" to "15") and the second If it is any of "11" to "13" that is not included in the lottery target range ("14" to "15"), the highest bit in the calculation (0th to 7th bits) 7th bit), the value of the carry flag CF becomes "1" and the value of the jump flag JF also becomes "1". On the other hand, if the value of the A register 101b before the subtraction of "14" is "14" or more, that is, if the value of the index value counter 74f is included in the second lottery target range ("14" or "15") , the value of the carry flag CF becomes "0" and the value of the jump flag JF is changed to is also "0".

In line numbers "8108" to "8110", commands similar to line numbers "1307" to "1309" of the process for addition at start (FIG. 69(b)) are set. As described above, if the value of the index value counter 74f is any of "11" to "13" which is included in the first lottery target range and is not included in the second lottery target range, the row The value of the jump flag JF is set to "1" by executing the instruction numbered "8107". Therefore, by executing the instruction "JRS 1, ADR812" at the line number "8108", the program address "ADR811" at the line number "8108" is changed to the program address "ADR812" at the line number "8110". jump to On the other hand, as described above, when the value of the index value counter 74f is "14" or "15" which is included in the second lottery target range, the instruction of the line number "8107" is executed to jump. The value of the flag JF is "0". Therefore, even if the instruction "JRS 1, ADR812" is set in the line number "8108", the program address does not jump, and the program proceeds to the next line number "8109". The start address of the second addition lottery table 73e is transferred to the HL register 104 by executing the instruction "LD HL, KSADD02" at the line number "8109". As a result, the lottery table to be referenced in the additional lottery is changed to the second additional lottery table 73e. In this way, when the AT state ST5 and the index value IV of the second lottery target range ("14" to "15") are won in the role lottery process (FIG. 18), the additional lottery A second additional lottery table 73e is set as a lottery table to be referred to. By executing the instruction "JP ADR133" at the line number "8110", the program jumps to the program address "ADR133".

FIG. 70(b) is a first comparative example of the addition processing at the start and the addition processing at the start, and selects the command set to select the first addition lottery table 73d and the second addition lottery table 73e. FIG. 10 is an explanatory diagram for explaining instructions set for the purpose; In the process for addition at the start (FIG. 69(b)), the command for selecting the first addition lottery table 73d on the condition that the index value IV in the first lottery target range is won is the line number "1301". ” to line number “1305”. In addition, in the first comparative example (FIG. 70(a)) of the addition process at the start, the condition for selecting the first addition lottery table 73d is that the index value IV in the first lottery target range is won. The instructions are set to line number "8101" to line number "8106".

As shown in FIG. 70(b), there are two 3-byte LD instructions at line numbers "8101" to "8106" in the first comparative example (FIG. 70(a)) of the addition process at the start. Two 2-byte CP instructions are set, and two 1-byte RET instructions are set. The total word length of the instructions set from line number "8101" to line number "8106" is 12 bytes. On the other hand, two 3-byte LD instructions are set in line number "1301" to line number "1305" of the process for addition at start (FIG. 69(b)), and two 3-byte SUB instructions are set. is set, one 2-byte CP instruction is set, and one 1-byte RET instruction is set. The total word length of the instructions set from line number "1301" to line number "1305" is 11 bytes.

As already explained, the addition processing at the start (FIG. 69(b)) is the first lottery target range (“11” to “15”) from the value of the A register 101b in which the data of the index value counter 74f is set. ), and the value of the A register 101b after subtracting "11" is subtracted from "15", which is the maximum value of the first lottery target range. and determining whether or not the value is less than "5", which is "1" greater than the value calculated by the calculation. As a result, the value of the A register 101b, in which the data of the index value counter 74f is set, is the minimum value of the first lottery object range, as in the first comparative example (FIG. 70(a)) of the addition process at the start. A process of determining whether or not the value of the A register 101b is equal to or greater than a certain "11" and a process of determining whether or not the value of the A register 101b is equal to or less than "15", which is the maximum value of the first lottery target range, are performed. Compared to the processing configuration, it is possible to reduce the total word length of instructions set in the program for determining whether the value of the index value counter 74f is included in the first lottery target range. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 in order to execute the process for addition at start (FIG. 69(b)).

In the addition process at the start (FIG. 69(b)), when the value of the index value counter 74f is any one of "11" to "13", the first addition lottery table is set as the lottery table to be referred to, and The command for setting the second additional lottery table as the lottery table to be referred to when the value of the index value counter 74f is "14" or "15" is set to line number "1301" to line number "1308". It is In addition, in the first comparative example (FIG. 70(a)) of the addition process at the start, when the value of the index value counter 74f is any one of "11" to "13", the lottery table to be referred to is the first lottery table. The command for setting the additional lottery table and setting the second additional lottery table as the reference target lottery table when the value of the index value counter 74f is "14" or "15" is given from line numbers "8101" to It is set to line number "8109". Three 3-byte LD instructions are set in line numbers "8101" to line number "8109" in the first comparative example (FIG. 70(a)) of the addition process at the start, and three 3-byte CP instructions are set. are set, two 1-byte RET instructions are set, and one 1-byte JRS instruction is set. The total word length of the instructions set from line number "8101" to line number "8109" is 18 bytes. On the other hand, three 3-byte LD instructions are set in line number "1301" to line number "1308" of the process for addition at start (FIG. 69(b)), and 2-byte SUB instruction is set, two 2-byte CP instructions are set, one 1-byte RET instruction is set, and one 1-byte JRS instruction is set. The total word length of the instructions set from line number "1301" to line number "1308" is 17 bytes.

As already explained, the addition processing at the start (FIG. 69(b)) is the first lottery target range (“11” to “15”) from the value of the A register 101b in which the data of the index value counter 74f is set. ), and the value of the A register 101b after subtracting "11" is subtracted from "15", which is the maximum value of the first lottery target range. A process of determining whether or not it is less than "5", which is a value "1" larger than the value calculated by the calculation, and the value of the A register 101b after subtracting "11" is the second lottery target range (“14” to “15”), which is the minimum value of “14” minus “11”, which is the value calculated by subtracting “3” or more; Configuration. As a result, the value of the A register 101b, in which the data of the index value counter 74f is set, becomes the first lottery object range ("11"), as in the first comparative example of the addition processing at the start (FIG. 70(a)). to "15"), and whether or not the value of the A register 101b is equal to or less than "15", which is the maximum value of the first lottery target range. and a process of determining whether the value of the A register 101b is equal to or greater than "14", which is the minimum value of the second lottery target range ("14" to "15"). Compared to the processing configuration, when the value of the index value counter 74f is any one of "11" to "13", the first additional lottery table is set as the lottery table to be referred to, and the value of the index value counter 74f is In order to set the second additional lottery table as the lottery table to be referred to in the case of "14" or "15", the total word length of the instructions set in the program can be reduced. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 in order to execute the process for addition at start (FIG. 69(b)).

FIG. 71(a) is a jump instruction set to jump from the program address "ADR131" and the program address "ADR132" to the program address "ADR133" in the process for addition at the start (FIG. 69(b)). It is an explanatory view for explaining. As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". . "ADR133" is a program address in which a command for executing the process of step S1802 of the number-of-release-games lottery process (FIG. 35(b)) is set, and the JRS command of line number "1307" is set. This is a program address that cannot be specified as a jump destination program address in the JRS instruction based on the program address (ADR131) where the JRS instruction is located. "ADR133" is a program address that cannot be specified as a jump destination program address in a JRS instruction based on the program address (ADR132) of line number "1309".

As already explained, the range that can be jumped by the JR instruction is the range from "(the program address where the relevant JR instruction is set) + 2 - 128" to "(the program address where the relevant JR instruction is set) + 2 + 127". . "ADR133" is a program address that cannot be specified as a jump destination program address in the JR instruction based on the program address (ADR131) of line number "1307", and is a program address (ADR132) of line number "1309" that cannot be specified as a reference. This is a program address that cannot be specified as a jump destination program address in the JR instruction.

In the process for addition at the start (Fig. 69(b)), the command "JP ADR133" is set in the line number "1309". As already explained, the JP instruction is a jump instruction with a word length of 3 bytes that designates the entire jump destination program address (2 bytes). Therefore, by using the JP instruction, it is possible to jump from the program address "ADR132" where the JP instruction of line number "1309" is set to the program address "ADR133". 69(b)) sets a JRS instruction with a word length of 1 byte to the line number "1307", and sets the line number "1307" on the condition that the value of the jump flag JF is "1". ” to the program address (ADR132) of the line number “1309”, and jumps to the program address “ADR133” using the JP instruction set in the program address of the jump destination.

FIG. 71(b) explains a jump instruction set for jumping from the program address "ADR131" and the program address "ADR132" to the program address "ADR133" in the second comparative example of the addition process at the start. It is an explanatory view for doing. In the second comparative example (FIG. 71(b)) of the addition process at the start, the instruction "JP C, ADR133" is set at the program address "ADR131". "JP" is a jump instruction with a word length of 3 bytes, "C" is a jump condition that the carry flag CF is set to "1", and "ADR133" is This is the contents of designating the program address "ADR133" as the jump destination program address. As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. In the second comparative example (FIG. 71(b)) of the add-on processing at the start, since the instruction "JRC, ADR133" is set at the program address "ADR131", the carry flag CF is set to "1". on the condition that the program address "ADR132" is skipped and the program address "ADR133" is directly jumped to.

As described above, the JP command of line number "1309" is in AT state ST5 and is included in the second lottery target range ("14" to "15") in the winning lottery process (FIG. 18). After changing the lottery table to be referenced in the additional lottery at line number "1308" to the second additional lottery table 73e on the condition that the value IV is won, jump to the program address "ADR133". is an order. Therefore, even in a configuration in which line number "1307" directly jumps to the program address "ADR133", the JP instruction at line number "1309" cannot be omitted.

As shown in FIG. 71(b), in the second comparative example (FIG. 71(b)) of the additional processing at the start, a jump from the program address "ADR131" and the program address "ADR132" to the program address "ADR133" is performed. The total word length of the jump instruction set to do is 6 bytes. On the other hand, as shown in FIG. 71(a), in the process for addition at the start (FIG. 69(b)), a jump is made from the program address "ADR131" and the program address "ADR132" to the program address "ADR133". The total word length of the jump instruction set to do is 4 bytes.

As described above, the superimposing process at the start (FIG. 69(b)) is performed by executing a JRS command with a word length of 1 byte on the condition that the value of the jump flag JF is "1" at the line number "1307". This is a processing configuration for jumping to "1309" and jumping to the program address "ADR133" using the JP instruction set in the jump destination line number "1309". As a result, as in the second comparative example (FIG. 71(b)) of the addition processing at the start, the word length is 3 on the condition that the carry flag CF is set to "1" at the line number "1307". Jump set to jump from the program address "ADR131" and the program address "ADR132" to the program address "ADR133" compared to the processing configuration that jumps directly to the program address "ADR133" by the byte JP instruction. The total instruction word length can be reduced. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 in order to execute the process for addition at start (FIG. 69(b)).

According to this embodiment detailed above, the following excellent effects are obtained.

The main MPU 72 recognizes that it is the execution period of the stop order correspondence display on the combined display unit 66 based on the value of the stop order type counter 74m being any one of "1" to "9", and stops. Based on the fact that no stop order number from "1" to "9" is set in the order type counter 74m, it is determined that it is not the execution period of the stop order correspondence display. The slot machine 10 has a configuration in which, during execution of the game, display corresponding to the stop order based on the value of the stop order type counter 74m or display of the awarded number based on the value of the awarded number counter 74e is executed on the combined display unit 66. A flag that enables the main side MPU 72 to grasp that the unit 66 should execute the stop order display and the state that the given number display should be executed is defective. For this reason, compared to the configuration having the flag, the dual-use display unit 66 can display a state in which the display corresponding to the stop order and a state in which the awarded number is displayed are executed during the execution of the game. The data capacity of the main RAM 74 can be reduced.

In a game in which display corresponding to the stop order on the dual-use display unit 66 and notification of the stop order on the image display device 63 are executed, any one of "1" to "9" won in the winning lottery process (FIG. 18) is displayed. The index value IV is stored in the index value counter 74f, and the index value IV of any one of "1" to "9" stored in the index value counter 74f is directly used as the stop order type number and stored in the stop order type counter 74m. is set to For this reason, compared to the configuration in which the data of the stop order type number set in the stop order type counter 74m is different from the data of the index value IV that was won in the winning lottery process (FIG. 18), The processing configuration for setting the stop order type number in the order type counter 74m is simplified.

In the winning determination process (FIG. 26), when a minor winning combination is established, the timing at which the processing in step S1205 for setting the award number corresponding to the minor winning combination in the award number counter 74e is executed is the stop order type counter 74m. is cleared to "0" before the timing at which the processing of step S1208 is executed. When the stop order type counter 74m is cleared to "0" while the stop order correspondence display is being performed on the dual use display unit 66, the display content of the dual use display unit 66 is switched from the stop order correspondence display to the given number display. If the processing configuration is such that the stop order type counter 74m is cleared to "0" before setting the number of grants corresponding to the small win achieved this time to the number counter 74e of grants, the stop order corresponding display on the combined display unit 66 is finished. There is a risk that "0" will be displayed between the start and the start of display of the award number corresponding to the small winning combination established this time. When the display contents on the dual-purpose display unit 66 are switched twice in a short time (for example, about 3 milliseconds) in the order of display corresponding to the stop order→“00”→display corresponding to the number of game media to be given, the manager of the game hall or confuse the player. On the other hand, the processing configuration is such that the stop order type counter 74m is cleared to "0" in a state in which the number of awarded game media corresponding to the minor win achieved this time is set in the awarded number counter 74e. It is possible to smoothly switch the display content on the display unit 66 from the stop order correspondence display to the given number display.

In a state in which the game is being executed and the combined display unit 66 is displaying the awarded number based on the value of the awarded number counter 74e, any one of "1" to "9" is displayed on the stop order type counter 74m. By performing the process of setting the stop order type number (the process of step S1105 in the lottery result correspondence process (FIG. 25)), the display content on the combined display unit 66 can be switched from the given number display to the stop order correspondence display. can. For this reason, in addition to the process of setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m, as a separate process from this process, the display content on the combined display unit 66 is given. Compared to the configuration in which the processing for switching from the display of the assigned number based on the value of the number counter 74e to the display corresponding to the stop order is set, the stop order type counter 74m can display any one of "1" to "9" in the stop order. It is possible to simplify the processing configuration for setting the type number and switching the display content on the dual-purpose display unit 66 from display of the assigned number to display corresponding to the stop order.

A process of clearing the value of the stop order type counter 74m to "0" in a state where the game is being executed and the stop order display is being executed on the combined display unit 66 (in the prize determination process (FIG. 26) By performing the process of step S1208), the display content on the combined display unit 66 can be switched from the display corresponding to the order of stop to the display of the given number based on the value of the given number counter 74e. Therefore, in addition to the process of clearing the value of the stop order type counter 74m to "0", as a separate process from this process, the display content on the combined display unit 66 is changed from the display corresponding to the stop order to the value of the given number counter 74e. The value of the stop order type counter 74m is cleared to "0" and the display content on the combined display unit 66 is changed from the display corresponding to the stop order to the display of the number of grants compared to the configuration in which the processing for switching to the display of the number of grants is set based on The processing configuration for switching to can be simplified.

The main MPU 72 recognizes that it is the execution period of the ratio display on the dual-purpose display unit 66 based on the calculation result data of any one of "0" to "100" being set in the ratio display counter 74n. , it is determined that it is not the execution period of the ratio display based on the fact that the calculation result data of "0" to "100" is not set in the ratio display counter 74n. In a configuration in which the ratio display based on the value of the ratio display counter 74n or the award number display based on the value of the award number counter 74e is performed on the dual-use display unit 66 during a period in which the game is not being executed, the slot machine 10 can be used for dual-purpose display. A flag that enables the main side MPU 72 to grasp that the unit 66 should execute the ratio display and the state that the given number display should be executed is defective. For this reason, compared to the configuration having the flag, a state in which the ratio display is performed and a state in which the awarded number is displayed on the dual-purpose display unit 66 during a period in which the game is not performed are generated. Therefore, the data capacity of the main RAM 74 can be reduced.

While the game is not being executed and the combined display unit 66 is displaying the awarded number based on the value of the awarded number counter 74e, any one of "0" to "100" is displayed on the ratio display counter 74n. (processing of step S1305 in the management process (FIG. 27)) for setting the calculation result data in (1), the display content on the dual-use display unit 66 can be switched from the display of the given number to the display of the ratio. For this reason, in addition to the process of storing the calculation result data in the ratio display counter 74n, as a separate process from this process, the display content on the combined display unit 66 is changed from the given number display to the ratio display based on the value of the given number counter 74e. Compared to the configuration in which the processing for switching to is set, the processing configuration for storing the calculation result data in the ratio display counter 74n and switching the display content on the dual-use display unit 66 from the given number display to the ratio display is simplified. can be

A process of setting the ratio display counter 74n to the initial value "255" (management process (Fig. 27) 3), the display content on the combined display unit 66 can be switched from the ratio display to the given number display based on the value of the given number counter 74e. For this reason, in addition to the process of setting the initial value to the ratio display counter 74n, as a separate process from this process, a process of switching the display content on the combined display unit 66 from the ratio display to the given number display is set. Compared to the configuration, the processing configuration for setting the initial value to the ratio display counter 74n and switching the display content on the dual-purpose display unit 66 from the ratio display to the given number display can be simplified.

The calculation result data of the stay ratio of the second section SC2 is set in the ratio display counter 74n when the ratio display start operation is performed while the game is not being executed. Even in a state where the ratio display is not executed on the dual-purpose display unit 66, the calculation for calculating the stay ratio of the second section SC2 is performed, and the calculation result data is stored in the main side RAM 74. As a result, the ratio In addition to the display counter 74n, it is necessary to provide the main RAM 74 with a counter for storing the calculation result data. On the other hand, since the calculation result data is set to the ratio display counter 74n only during the period when the ratio display is executed on the dual-purpose display unit 66, the calculation result data is stored on the main side. The data capacity of the storage area provided in the RAM 74 can be reduced.

A period during which one of the stop order classification numbers "1" to "9" is set in the stop order classification counter 74m, and one of calculation result data "0" to "100" is set in the ratio display counter 74n. It is a period that does not overlap with the period that is specified. For this reason, the condition for executing the stop order corresponding display and the condition for executing the ratio display on the combined display unit 66 are not satisfied at the same time. This eliminates the need for a flag that enables the main MPU 72 to grasp that the dual-use display unit 66 is in a state in which the stop order correspondence display should be executed and the state in which the ratio display should be executed. Compared to the configuration provided, it is possible to reduce the data capacity of the main side RAM 74 for generating the state in which the display corresponding to the stop order and the state in which the ratio display is performed on the combined display unit 66. can.

A continuous address range of "0001H" to "0006H" including the lower area of the AT continuation counter 74u, the lower area of the continuous game number counter 74r, and the lower area of the total winning number counter 74s, in which "1" can be set to the highest bit. The data of "0" or "1" stored in the most significant bits of the six storage areas set to . For this reason, compared to the configuration in which a memory area of 2 bytes or more is set in the main RAM 74 in order to set the data "0" or "1" stored in the most significant bit of these six memory areas. Therefore, the data capacity of the storage area provided in the main RAM 74 is reduced for setting the data "0" or "1" stored in the most significant bit of these six storage areas.

Six storage areas, including the lower area of the AT continuation counter 74u in which "1" can be set to the highest bit, the lower area of the continuous game number counter 74r, and the lower area of the total winning number counter 74s, are "0001H" to "0006H". is set in the continuous address range, the address range of the storage area to be set in the highest-order aggregation area 74v for the data of "0" or "1" stored in the most significant bit is specified. It is possible to simplify the processing configuration for

Storage areas set in the address range of "0008H" to "000DH" (bet number setting counter 74b, stop order type counter 74m, game state area 77, game section area 76, pseudo bonus continuation counter 74t and grant number counter 74e ) is a storage area in which the most significant bit is not set to "1". The most significant bit in the memory area corresponding to the addresses "0001H" to "0006H" among the memory areas set in the address range "0001H" to "000DH" in which the data is set in the command at the start and the command at the end In the configuration provided with the highest-order aggregation area 74v in which the data "0" or "1" stored in the There is no storage area for setting the data "0" stored in . For this reason, while suppressing the number of storage areas (top-level aggregation area 74v) set in the main-side RAM 74 to aggregate data of the highest-order bit, The most significant bit data can be set in the start command and the end command.

Since the storage area in which data is set in the start command and the end command is set in the continuous address range of "0001H" to "000DH" in the main RAM 74, the storage area in which the data is set in the start command is It is possible to simplify the processing configuration for specifying the address range and the processing configuration for specifying the address range of the storage area in which data is set in the end command.

Only a part of the storage area of the main side RAM 74 (specifically, the highest level aggregation area 74v and the game state area 77) storing data used by the effect side MPU 92 at the start of the game is This is a configuration common to the storage area of the main side RAM 74 in which data used by the effect side MPU 92 is stored. In this configuration, the storage area in which data is set in the command at the start and the command at the end is the storage area of the main side RAM 74 that stores the data used by the effect side MPU 92 at the start and end of the game. As a result, it is possible to set a storage area in which data is set in the command at the start and a storage area in which data is set in the command at the end in a continuous address range of the main RAM 74 .

In the main RAM 74, the address range of the storage area where the data to be set in the start command is stored (the address range of "0001H" to "000DH") is the data to be set in the end command. Since it is the same as the address range of the storage area (address range of "0001H" to "000DH"), the processing configuration for transmitting the start command and the processing configuration for transmitting the end command should be shared. can be done. As a result, the data capacity of the program for transmitting the command at the start and the command at the end in the main ROM 73 can be reduced.

There are an AT continuation counter 74u, a continuation game number counter 74r, and a total winning number counter 74s as counters in which the most significant bit of the lower area can be set to "1". The data of the AT continuation counter 74u is data used by the effect side MPU 92 at the start of the game, but is not data used by the effect side MPU 92 at the end of the game. The data of the continuous game number counter 74r and the total winning number counter 74s are data used by the effect side MPU 92 at the end of the game, but are not data used by the effect side MPU 92 at the start of the game. If only the data used by the effect side MPU 92 at the start of the game is set in the start command and only the data used by the effect side MPU 92 at the end of the game is set in the end command, the AT continuation counter In addition to the storage area for setting the most significant bit data in the lower area and upper area of 74u, the lower area and upper area of the continued game number counter 74r and the lower area and upper area of the total winning number counter 74s. It would be necessary to provide a storage area in the main RAM 74 for setting the upper bit data. On the other hand, by setting the data of the AT continuation counter 74u, the continuation game number counter 74r, and the total winning number counter 74s in the start time command and the end time command, the AT continuation counter 74u and the continuation game number counter are set. 74r and total acquisition number counter 74s. can do. As a result, the most significant bit data in the lower area and upper area of the AT continuation counter 74u, the lower area and upper area of the continuous game number counter 74r, and the lower area and upper area of the total winning number counter 74s are set. The data capacity of the side RAM 74 is reduced.

The effect side MPU 92 converts the start time command received from the main side MPU 72 into the converted start time command, and converts the end time command received from the main side MPU 72 into the converted end time command. When the effect-side MPU 92 converts the start-time command or the end-time command received from the main-side MPU 72 into the post-conversion start-time command or the post-conversion end-time command, the effect-side MPU 92 converts the 0th to The data "0" or "1" set in the 5th bit is set in the most significant bit in the 2nd to 7th frames FR2 to FR7 corresponding to the 0th to 5th bits. As a result, while setting the value of the most significant bit in the frame other than the header HD contained in the command at the start or the command at the end transmitted from the master side MPU 72 to the effect side MPU 92 to "0", the effect side MPU 92 performs the header A post-translation start or post-translation end command may be available in which the most significant bit in non-HD frames may also be set to '1'.

A frame in which data "0" or "1" set in the 0th to 5th bits of the highest aggregated frame SF (the eighth frame FR8) is set in the most significant bit in the command at the start or the command at the end. are consecutive second to seventh frames FR2 to FR7. For this reason, a processing configuration for designating a frame in which data "0" or "1" set in the 0th to 5th bits of the highest aggregated frame SF is set in the highest bit is specified by the production side MPU 92. can be simplified.

Only some of the first to fifteenth frames FR1 to FR15 included in the start command are set in the post-conversion start command. As a result, the master side MPU 72 is configured to transmit a start-time command including data other than the data used by the effect side MPU 92 at the start of the game, while the data is stored in the command storage buffer 126 and used by the effect side MPU 92 . It is possible to suppress the data volume of the post-conversion start command. Further, only some of the first to fifteenth frames FR1 to FR15 included in the end command are set in the post-conversion end command. As a result, the master side MPU 72 is configured to transmit an end command including data other than the data used by the effect side MPU 92 at the end of the game. It is possible to suppress the data volume of the command at the end of conversion after conversion. Therefore, the data capacity of the command storage buffer 126 can be reduced.

Of the 1st to 15th frames FR1 to FR15 included in the start time command, the frames set by the production side MPU 92 in the post-conversion start time command are the 1st to 15th frames FR1 to FR1 included in the end time command. It is different from the frame set in the post-conversion termination command by the effect-side MPU 92 in the FR 15 . For this reason, the address range of the storage area of the main RAM 74 storing the data set in the command at the start transmitted from the main MPU 72 to the effect MPU 92 at the start of the game is the same as the address range from the main MPU 72 to the effect at the end of the game. In a configuration that is the same as the address range of the storage area of the main side RAM 74 in which the data set in the command at the end transmitted to the side MPU 92 is stored, the address range required by the effect side MPU 92 at the start of the game at the start of the game. Only the data that is set between the header HD and the footer FT can be made available to the production side MPU 92 at the time of starting the conversion command, and at the end of the game, the production side MPU 92 can use The MPU 92 on the production side can use the post-conversion completion command in which only the data required for the conversion is set between the header HD and the footer FT.

The transfer target range in the highest-level aggregation process (FIG. 51) is the continuous address range of “0001H” to “0006H” in the main RAM 74 . By repeatedly executing the process of adding 1 to the value of the transfer source counter 116 in the main RAM 74 (the process of step S2909), the storage area of the transfer source can be updated sequentially. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the transfer target range in the highest-level aggregation process (FIG. 51) is the continuous address range of "0001H" to "0006H" in the main RAM 74, the start address of the transfer target range is set to the transfer source counter 116 in step S2904. is set to "0001H", and "6", which is the number of transfers, is set in the transfer number counter 114 in step S2905. This simplifies the processing configuration for designating the transfer target range.

The transfer target range in the common command transmission process (FIG. 50) is the continuous address range of “0001H” to “000DH” in the main RAM 74 . By repeatedly executing the process of adding 1 to the value of the transfer source counter 116 in the main RAM 74 (the process of step S2816), the storage area of the transfer source can be sequentially updated. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the transfer target range in the common command transmission process (FIG. 50) is a continuous address range of "0001H" to "000DH" in the main RAM 74, the start address of the transfer target range is set to the transfer source counter 116 in step S2809. is set to "0001H" and "13", which is the number of transfers, is set to the transfer number counter 114 in step S2810, thereby specifying the transfer target range. This simplifies the processing configuration for designating the transfer target range.

The addresses of the areas RA2 to RA7 in which the data "0" or "1" stored in the 0th to 5th bits of the highest-order aggregated frame SF are set to the highest-order bits in the highest-order setting process (FIG. 53) are It is a continuous address range from "α+2" to "α+7". By repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S3110), the transfer destination storage area can be sequentially updated. This simplifies the processing configuration for sequentially updating the transfer destination storage area.

The value of the effect-side bit designation counter in the effect-side RAM 94 is the data "0" or "1" stored in any one of the 0th to 5th bits of the highest aggregate frame SF to the maximum value in the storage area of the transfer destination. One is added each time the process of transferring to the upper bit (the process of step S3109) is executed. Therefore, by referring to the value of the rendering-side bit designation counter, the data "0" or "1" set in any of the 0th to 5th bits of the highest aggregated frame SF can be changed to the 0th to 5th bits. The number of transfers to the second to seventh frames FR2 to FR7 corresponding to any of the fifth bits can be grasped. As a result, it is possible to simplify the processing configuration for ascertaining the number of transfers by the effect-side MPU 92 .

By transferring the data of some frames among the first to fifteenth frames FR1 to FR15 included in the start time command or the end time command set in the pre-conversion area 124 to the post-conversion area 125, the start time command Alternatively, when the end command is converted to the post-conversion start command or the post-conversion end command, the transfer source storage area in the pre-conversion area 124 is updated in a manner excluding the area to be excluded. On the other hand, when the transfer destination storage area in the post-conversion area 125 is updated, the storage area set next to the current transfer destination storage area in the post-conversion area 125 becomes the post-update transfer destination storage area. is done in As a result, when a start command is received, data to be used by the effect-side MPU 92 at the start of the game can be extracted from the start command and set as the post-conversion start command. is received, data to be used by the effect-side MPU 92 at the end of the game can be extracted from the command at the end and set as the command at the end after conversion.

The effect side MPU 92 converts the start time command received from the main side MPU 72 into a converted start time command, and executes processing for executing the effect of the game started this time based on the converted start time command. Data of an AT continuation counter 74u, a bet number setting counter 74b, a stop order type counter 74m and a game state area 77 in the main side RAM 74 are set in the post-conversion start time command. When the start command is received, the data of the AT continuation counter 74u, the bet number setting counter 74b, the stop order type counter 74m, and the game state area 77 can be used. Compared to the configuration in which the data of the number setting counter 74b, the stop order type counter 74m, and the game state area 77 are received by two or more commands, the number of command transmissions from the main side MPU 72 to the effect side MPU 92 can be reduced. can. As a result, the processing load for the master side MPU 72 to transmit commands to the effect side MPU 92 can be reduced, and the processing load when the effect side MPU 92 executes the processing corresponding to the command received from the master side MPU 72 can be reduced. can be mitigated.

The effect side MPU 92 converts the end command received from the main side MPU 72 into a post-conversion end command, and executes processing for executing the effect based on the post-conversion end command. Data of a continuous game number counter 74r, a total winning number counter 74s, a game state area 77, a game section area 76, a pseudo-bonus continuation counter 74t, and a given number counter 74e in the main side RAM 74 are set in the post-conversion end command. there is The data of the continuous game number counter 74r, the total win number counter 74s, the game state area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the award number counter 74e can be used when the end command is received. Therefore, the data of the continuous game number counter 74r, the total winning number counter 74s, the game state area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the awarded number counter 74e are received by two or more commands. By comparison, it is possible to reduce the number of command transmissions from the main side MPU 72 to the effect side MPU 92 . As a result, the processing load for the master side MPU 72 to transmit commands to the effect side MPU 92 can be reduced, and the processing load when the effect side MPU 92 executes the processing corresponding to the command received from the master side MPU 72 can be reduced. can be mitigated.

The JRS instruction indicates that the flag to be referenced is in a predetermined state (the value of the jump flag JF is "1" or the value of the jump flag JF is "0"). Only conditional jumps that jump as conditions are prepared, and unconditional jumps that jump unconditionally without referring to the state of the flag are not prepared. The JRS instruction set at line number "1002" in the power-off standby process (FIG. 62(b)) jumps to the program address at line number "1001" on condition that the value of the jump flag JF is "0". However, in the power-off standby process, the value of the jump flag JF always becomes "0" after the OUT instruction "OUT (WDTCLR0), 18H" of the line number "1001" is executed. Therefore, it is possible to repeatedly execute the instructions set to the line numbers "1001" to "1002" while using the JRS instruction, which is a conditional jump instruction with a short word length. .

In the power-off standby process (FIG. 62(b)), the word length is set to 1 byte. Therefore, a JR instruction with a word length of 2 bytes or a JP instruction with a word length of 3 bytes is set as an instruction for jumping from the program address of line number "1002" to the program address of line number "1001". It is possible to reduce the data volume of the program for the power-off standby process compared to the configuration in which the

JRS instructions with a word length of 1 byte only provide conditional jump instructions that jump to the destination program address on condition that the value of the jump flag JF is either "1" or "0". do not have. In the AT state signal setting process (FIG. 64(a)), the value of the zero flag ZF is set to "1" and the value of the jump flag JF is set to "1" by executing the instruction "XOR A, A" at the line number "1109". The value becomes "1". After that, by executing the instruction "JRS 1, ADR114" at the line number "1110" next to the line number "1109" while the value of the jump flag JF is "1", the line number "1110" is executed. ” to the program address of line number “1116” of “ADR114”. The instruction "XOR A, A" set at the line number "1109" clears the data of the A register 101b set in the AT state signal counter 74w at the jump destination line number "1116" to "0". It is an order for Then, the instruction "XOR A, A" set at line number "1109" uses the JRS instruction with a word length of 1 byte at line number "1110" to perform "ADR114" at line number "1116". It is also an instruction that makes it possible to jump reliably to a program address. The data capacity of the program for executing the AT state signal setting process is reduced by consolidating these two roles into the XOR instruction of line number "1109".

In order to always jump from the program address of line number "1110" to the program address of line number "1116", it is conceivable to set the JR instruction or JP instruction, which is an unconditional jump instruction, to line number "1110". If a JR instruction with a word length of 2 bytes or a JP instruction with a word length of 3 bytes is set to the line number "1110", the word length of the jump instruction for jumping from the line number "1110" to the line number "1116" increases. In the AT state signal setting process (Fig. 64(a)), the command "XOR A, A" and the command "JRS 1, ADR114" are set in consecutive line numbers "1109" and "1110". By this configuration, the word length of the jump instruction set at line number "1110" is suppressed to 1 byte, and the program address at line number "1110" is always jumped to the program address at line number "1116". is possible.

In the lottery result handling process (FIG. 66), the value of the A register 101b in which the data of the index value counter 74f is set is changed from the maximum value "255" in the 1-byte numerical information to the determination target range ("1" to A process of adding "246", which is a value calculated by subtracting "9", which is the maximum value of "9"), and 1 stored in the A register 101b after adding "246" A processing configuration for determining whether or not the numerical information of a byte is equal to or greater than "247", which is a value calculated by adding "246" to "1", which is the minimum value of the determination target range. is. As a result, the value of the A register 101b in which the data of the index value counter 74f is set is within the determination target range ("1" to "9 ”), and a process of determining whether the value of the A register 101b is equal to or less than “9”, which is the maximum value of the determination target range. and, in comparison with the processing configuration for performing The total word length can be reduced. Therefore, it is possible to reduce the data volume of the program stored in the main ROM 73 for executing the lottery result handling process (FIG. 66).

The value of the A register 101b, in which the data of the index value counter 74f is set, is changed from "255", which is the maximum value in the 1-byte numerical information, to " A process of adding "246", which is the value calculated by subtracting "9", and the 1-byte numerical information stored in the A register 101b after adding "246" is the minimum value of the determination target range. and determining whether or not the value is equal to or greater than "247", which is a value calculated by adding "246" to the value "1". As in the first comparative example (FIG. 67(a)), the value of the A register 101b in which the data of the index value counter 74f is set is the minimum value of the determination target range ("1" to "9"). 1” or more, and a processing configuration for determining whether the value of the A register 101b is equal to or less than “9”, which is the maximum value of the determination target range. Thus, the number of jump instructions (JRS instructions) can be reduced. This reduces the risk of unused programs.

In the lottery result handling process (FIG. 66), a JRS instruction is set to jump to the program addresses "ADR122" and "ADR125" on the condition that the value of the jump flag JF is "1", and the JRS instruction is executed. Using the fact that the state of the jump flag JF does not change even if it is executed, the line number is changed by a JRS instruction with a word length of 1 byte on the condition that the value of the jump flag JF is "1" at line number "1208". It is a processing configuration that jumps to the program address of "1215" and reliably jumps to the program address of line number "1218" by the JRS command with a word length of 1 byte set to the jump destination line number of "1215". As a result, as in the second comparative example (FIG. 68(b)) of the lottery result handling process, the word length is 2 bytes on the condition that the carry flag CF is set to "1" at the line number "1208". Compared to the processing configuration that directly jumps to the line number "1218" by the JR instruction, the jump instruction set to jump from the program address "ADR122" and the program address "ADR125" to the program address "ADR126" Word length can be reduced. Therefore, it is possible to reduce the data volume of the program stored in the main ROM 73 for executing the lottery result handling process (FIG. 66).

69(b)) is the minimum value of the first lottery target range ("11" to "15") from the value of the A register 101b in which the data of the index value counter 74f is set. The value of the A register 101b after subtracting "11" is calculated by subtracting "11" from "15", which is the maximum value of the first lottery target range. It is a processing configuration for performing a process of determining whether or not the value is less than "5", which is a value "1" larger than the value. As a result, the value of the A register 101b, in which the data of the index value counter 74f is set, is the minimum value of the first lottery object range, as in the first comparative example (FIG. 70(a)) of the addition process at the start. A process of determining whether or not the value of the A register 101b is equal to or greater than a certain "11" and a process of determining whether or not the value of the A register 101b is equal to or less than "15", which is the maximum value of the first lottery target range, are performed. Compared to the processing configuration, it is possible to reduce the total word length of instructions set in the program for determining whether the value of the index value counter 74f is included in the first lottery target range. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 in order to execute the process for addition at start (FIG. 69(b)).

69(b)) is the minimum value of the first lottery target range ("11" to "15") from the value of the A register 101b in which the data of the index value counter 74f is set. The value of the A register 101b after subtracting "11" is calculated by subtracting "11" from "15", which is the maximum value of the first lottery target range. A process of determining whether or not it is less than "5", which is a value "1" greater than the value, and the value of the A register 101b after subtracting "11" is the second lottery target range ("14" to and determining whether or not it is equal to or greater than "3" which is a value calculated by subtracting "11" from "14" which is the minimum value of "15"). As a result, the value of the A register 101b, in which the data of the index value counter 74f is set, becomes the first lottery object range ("11"), as in the first comparative example of the addition processing at the start (FIG. 70(a)). to "15"), and whether or not the value of the A register 101b is equal to or less than "15", which is the maximum value of the first lottery target range. and a process of determining whether the value of the A register 101b is equal to or greater than "14", which is the minimum value of the second lottery target range ("14" to "15"). Compared to the processing configuration, when the value of the index value counter 74f is any one of "11" to "13", the first additional lottery table is set as the lottery table to be referred to, and the value of the index value counter 74f is In order to set the second additional lottery table as the lottery table to be referred to in the case of "14" or "15", the total word length of the instructions set in the program can be reduced. As a result, it is possible to reduce the data volume of the program stored in the main ROM 73 in order to execute the process for addition at start (FIG. 69(b)).

In a configuration in which a calculation is performed to subtract "11" from the index value IV in order to specify that the index value IV is included in the first lottery target range, the index value IV is changed to the smaller side by "11" The subsequent value is used to determine whether the index value before the change is included in the second lottery target range. After performing the calculation (calculation to subtract "11") to change the first lottery target range ("11" to "15") to the side smaller by "11", the value after the calculation is the second lottery target range (“14” to “15”), the minimum value (“14”) is shifted to the smaller side by “11”, and it is determined whether or not it is “3” or more. The boundary value when determining whether or not the value IV is included in the second lottery target range ("14" to "15") is set to a value smaller than the minimum value ("14") for the second lottery target determination. can be "3". The number of bits required to represent the boundary value (“3”) when determining whether or not the value obtained by shifting the index value IV to the smaller side by “11” is greater than or equal to “3” is “2”. , and the number of bits is necessary to represent the boundary value ("14") when determining whether the index value IV before change is equal to or greater than "14", which is the minimum value of the second lottery target range. number of bits ("4"). This makes it possible to reduce the number of bits for representing the boundary value in the determination performed to specify that the index value IV is included in the second lottery target range. Therefore, the data capacity for storing the boundary value can be reduced.

69(b)), the jump flag JF at line number "1307" is set to "1". This processing configuration jumps to the program address "ADR133" using the JP instruction set to the line number "1309" of the jump destination. As a result, as in the second comparative example (FIG. 71(b)) of the addition processing at the start, the word length is 3 on the condition that the carry flag CF is set to "1" at the line number "1307". Jump set to jump from the program address "ADR131" and the program address "ADR132" to the program address "ADR133" compared to the processing configuration that jumps directly to the program address "ADR133" by the byte JP instruction. The total instruction word length can be reduced. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 in order to execute the process for addition at start (FIG. 69(b)).

By executing the JP instruction "JP ADR133" at the line number "1309" of the process for addition at the start (Fig. 69(b)), the process of step S1802 of the unlock game number lottery process (Fig. 35(b)) is executed. The processing configuration jumps to the program address (ADR133) where the command to be executed is set, and the program of the subroutine when the processing of step S1801 is executed in the unlock game number lottery processing (FIG. 35(b)). This is a processing configuration for executing the processing of step S1802 without calling the . For this reason, compared to a configuration in which a common subroutine called lottery execution processing is called in the number-of-released-games lottery process (FIG. 35) and the addition-at-start process (FIG. 69B), the number-of-release-games lottery process (FIG. ) and the processing for addition at the start (FIG. 69(b)), the data volume of the program stored in the main ROM 73 can be reduced.

<Second embodiment>
In this embodiment, when the main MPU 72 sets the command at the start or the command at the end in the transmission standby buffer 112, it is possible to transfer data by specifying the start address and the end address of the transfer target range in the main RAM 74. This is different from the first embodiment. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

FIG. 72(a) is an explanatory diagram for explaining the configuration of the main RAM 74 in this embodiment. As shown in FIG. 72( a ), the main RAM 74 is provided with an end position counter 131 . The end position counter 131 is a counter that enables the main MPU 72 to grasp the end address (2 bytes) of the transfer target range in the common command transmission process (FIG. 72(b)) and the highest-level aggregation process (FIG. 73), which will be described later. is. The end position counter 131 consists of 2 bytes.

As in the first embodiment, the transfer target range in the common command transmission process (FIG. 72(b)) is the continuous address range of "0001H" to "000DH" in the main RAM 74, and the highest level aggregation process (FIG. 73) is a continuous address range of “0001H” to “0006H” in the main RAM 74 . The end address of the transfer target range in the common command transmission process (FIG. 72(b)) is "000DH", and the end address of the transfer target range in the highest level aggregation process (FIG. 73) is "0006H".

FIG. 72(b) is a flow chart showing the common command transmission process executed by the main MPU 72. FIG. As already described in the first embodiment, the common command transmission process is performed when the start command flag of the main RAM 74 is set to "1" in the command output process (FIG. 44) (step S2707: YES). , or when "1" is set in the end command flag of the main RAM 74 (step S2708: YES), it is executed in step S2709. As already described, when the game is started, the start command flag is set to "1" in step S1107 of the lottery result handling process (FIG. 25), and the end command flag is set to end the game. In this case, "1" is set in step S1508 of the corresponding processing (FIG. 32) at the end of the game.

In the common command transmission process, first, the highest level aggregation process is executed (step S4001). FIG. 73 is a flow chart showing the highest level aggregation processing.

In the highest level aggregation process, the same processes as steps S2901 to S2904 of the highest level aggregation process (FIG. 51) in the first embodiment are executed in steps S4101 to S4104. Specifically, the address of the highest level aggregation area 74v in the main RAM 74 is set in the transfer destination counter 115 of the main RAM 74 (step S4101). As a result, the top-level aggregation area 74v can be set as the transfer destination storage area. After that, the highest level aggregation area 74v is cleared to "0" (step S4102), and the value of the bit designation counter 117 in the main side RAM 74 is cleared to "0" (step S4103). As a result, the 0th bit of the top-level aggregation area 74v can be set as the transfer destination bit. Thereafter, "0001H", which is the start address of the transfer target range ("0001H" to "0006H") in the top-level aggregation process (FIG. 73), is set in the transfer source counter 116 in the main RAM 74 (step S4104). As a result, the lower area of the AT continuation counter 74u set at the address "0001H" can be set as the transfer source storage area.

Thereafter, "0006H", which is the end address of the transfer target range ("0001H" to "0006H") in the top-level aggregation process (FIG. 73), is set in the end position counter 131 in the main RAM 74 (step S4105). This allows the main MPU 72 to grasp the end address. Thereafter, the most significant bit data in the transfer source storage area is transferred to the transfer destination bit (step S4106). As already described in the first embodiment, the main MPU 72 identifies the storage area of the transfer source based on the address stored in the transfer source counter 116, and the address and address stored in the transfer destination counter 115. A transfer destination bit is specified based on the value of the bit specification counter 117 .

Thereafter, it is determined whether or not the address set in the transfer source counter 116 is the end address ("0006H") set in the end position counter 131 in step S4105 (step S4107). If the address set in the transfer source counter 116 is not the end address (“0006H”) (step S4107: NO), 1 is added to the value of the transfer source counter 116 to update the transfer source storage area. (Step S4108). The processing of steps S4106 to S4109 is processing that is repeatedly executed until an affirmative determination is made in step S4107. 0006H”, the address of the transfer source storage area is updated.

Thereafter, the transfer destination bit is updated by adding 1 to the value of the bit designation counter 117 (step S4109). In step S4109, the transfer destination bits are updated in the order of 0th bit→1st bit→2nd bit→3rd bit→4th bit→5th bit in the top-level aggregation area 74v. After that, the process proceeds to step S4106, and the processes of steps S4106 to S4109 are repeatedly executed until an affirmative determination is made in step S4107. As a result, the most significant bit data in the storage area included in the transfer target range (“0001H” to “0006H”) can be set to the 0th to 5th bits of the most significant aggregation area 74v.

In this way, in the top-level aggregation process (FIG. 73), the start address (“0001H”) and end address (“0006H”) of the transfer target range (“0001H” to “0006H”) are set, and the transfer source is stored. Until the address of the area becomes the end address, the process of transferring the most significant bit data in the transfer source storage area to the transfer destination bit (step S4106), the process of updating the address of the transfer source storage area (step S4108). (processing of step S4109) and the processing of updating the transfer destination bit (processing of step S4109) are repeatedly executed. This simplifies the processing configuration for setting the most significant bit data in the transfer target range storage area to the most significant aggregation area 74v.

Returning to the description of the common command transmission process (FIG. 72(b)), after executing the top-level aggregation process (FIG. 73) in step S4001, in steps S4002 to S4009, common command transmission in the first embodiment The same processing as steps S2802 to S2809 of the processing (FIG. 50) is executed. Specifically, first, the value of the write pointer 113 (FIG. 45) in the transmission circuit 85 is grasped to grasp the write destination area in the transmission waiting buffer 112 (step S4002). After that, if the start command flag of the main RAM 74 is set to "1" (step S4003: YES), that is, if it is time to start the game, the start command stored in the main ROM 73 is executed. The data of the corresponding header HD is set in the write destination area grasped in step S4002 (step S4004), and the start command flag is cleared to "0" (step S4005). On the other hand, if the start time command flag is not set to "1" (step S4003: NO), that is, if the game is over, the header HD corresponding to the end command stored in the main ROM 73 is set in the write destination area grasped in step S4002 (step S4006), and the end command flag of the main RAM 74 is cleared to "0" (step S4007).

If the process of step S4005 or step S4007 has been performed, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4008). In step S4008, the value of the write pointer 113 is incremented by 1, and when the value of the write pointer 113 after the increment of 1 exceeds the maximum value of "31", the write pointer 113 is cleared to "0". After that, in the main RAM 74, the start address of the transfer target range for transferring data to the transmission standby buffer 112 when transmitting the command at the start or the command at the end is set in the transfer source counter 116 of the main RAM 74 ( step S4009). As already explained, the transfer target range in the common command transmission process (FIG. 50) is the address range from "0001H" to "000DH". By setting the address "0001H" in the transfer source counter 116 in step S4009, the lower area of the AT continuation counter 74u can be set as the transfer source storage area. Thereafter, "000DH" is set as the end address to the end position counter 131 in the main RAM 74 (step S4010). "000DH" is the final address of the transfer target range from "0001H" to "000DH".

Thereafter, the data stored in the transfer source storage area is transferred to the write destination area corresponding to the value of the write pointer 113 in the transmission standby buffer 112 (step S4011). As already described in the first embodiment, the main MPU 72 identifies the transfer source storage area based on the address stored in the transfer source counter 116 . Thereafter, the most significant bit (seventh bit) in the write destination area is set to "0" (step S4012). As a result, the value of the most significant bit of the second to fourteenth frames FR2 to FR14 in the command at the start or the command at the end can be set to "0", and the data of the header HD is set to the first frame FR1. and the second to fourteenth frames FR2 to FR14.

After that, as in step S4008, the value of the write pointer 113 is updated (step S4013). Thereafter, it is determined whether or not the data of the transfer source counter 116 is the end address ("000DH") set in the end position counter 131 in step S4010 (step S4014). If not (step S4014: NO), the transfer source storage area is updated by adding 1 to the value of the transfer source counter 116 (step S4015). The processing of steps S4011 to S4015 is processing that is repeatedly executed until an affirmative determination is made in step S4014. ”, the address of the storage area to be the transfer source area is updated.

Thereafter, the process proceeds to step S4011, and the processes of steps S4011 to S4015 are repeatedly executed until an affirmative determination is made in step S4014. As a result, the data in the storage area included in the transfer target range (“0001H” to “000DH”) can be set in the transmission standby buffer 112 . If an affirmative determination is made in step S4014, that is, if the transfer of the data stored in the storage area included in the transfer target range to the transmission standby buffer 112 is completed, the write pointer is set in the transmission standby buffer 112. The data of the footer FT stored in the main ROM 73 is set in the write destination area corresponding to the value of 113 (step S4016). After that, as in steps S4008 and S4013, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4017), and the common command transmission processing ends.

In this way, in the common command transmission process (FIG. 72(b)), the start address (“0001H”) and the end address (“000DH”) of the transfer target range (“0001H” to “000DH”) are stored in the main RAM 74. and transfer the data stored in the transfer source storage area to the write destination area in the transmission standby buffer 112 until the address of the transfer source storage area becomes the end address (step S4011), write The process of updating the previous area (process of step S4013) and the process of updating the address of the transfer source storage area (process of step S4015) are repeatedly executed. As a result, the processing configuration for setting the data stored in the storage area of the transfer target range to the transmission standby buffer 112 can be simplified.

According to this embodiment detailed above, the following excellent effects are obtained.

The transfer target range in the highest level aggregation process (FIG. 73) is set to continuous addresses (addresses “0001H” to “0006H”) in the main RAM 74 . In the top-level aggregation process (FIG. 73), the start address (“0001H”) and end address (“0006H”) of the transfer target range (“0001H” to “0006H”) are set, and the address of the transfer source storage area is The process of transferring the most significant bit data in the transfer source storage area to the transfer destination bit until the end address is reached (step S4106), the process of updating the address of the transfer source storage area (step S4108), And the process of updating the transfer destination bit (the process of step S4109) is repeatedly executed. This simplifies the processing configuration for setting the most significant bit data in the transfer target range storage area to the most significant aggregation area 74v.

The transfer target range in the common command transmission process (FIG. 72(b)) is set to consecutive addresses (addresses “0001H” to “000DH”) in the main RAM 74 . In the common command transmission process (FIG. 72(b)), the start address (“0001H”) and end address (“000DH”) of the transfer target range (“0001H” to “000DH”) are set in the main RAM 74, and the transfer is performed. The process of transferring the data stored in the transfer source storage area to the write destination area in the transmission standby buffer 112 until the address of the original storage area becomes the end address (process of step S4011); The process of updating (process of step S4013) and the process of updating the address of the transfer source storage area (process of step S4015) are repeatedly executed. As a result, the processing configuration for setting the data stored in the storage area of the transfer target range to the transmission standby buffer 112 can be simplified.

<Third Embodiment>
This embodiment differs from the first embodiment in that, in addition to the command at the start and the command at the end, there is a BB shift command as a command for consolidating the data stored in the most significant bit. are doing. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

As the game state, in addition to the normal game state ST1, the first CB state ST2, the second CB state ST3, the pseudo-bonus state ST4, the AT state ST5 and the end preparation state ST6 already described in the first embodiment, the first BB state and A second BB state exists. As already explained in the first embodiment, the main ROM 73 stores a winning combination lottery table (FIG. 19) for three-coin bet and a winning combination lottery table (FIG. 20) for two-coin betting. In addition to the index values IV of "1" to "17" already described in the first embodiment, the combination lottery table for betting 3 cards and the combination lottery table for betting 2 cards in the present embodiment include An index value IV of "18" to which the 1BB winning data is set and an index value IV of "19" to which the second BB winning data is set are set. The probability of winning the 1st BB and the probability of winning the 2nd BB on the combination lottery table when 3 cards are bet are approximately 1/437, respectively, and the 1st BB winning occurs on the combination lottery table when 2 cards are bet. The probability and the probability of the 2nd BB winning occurring are each about 1/437.

In the winning lottery process (FIG. 18), when the index value IV ("18") in which the first BB winning data is set is won, the first BB winning data is set in the main side RAM 74, and the second BB winning data is set in the main side RAM 74. The second BB winning data is set in the main side RAM 74 when the winning is won at the index value IV (“19”) to which the winning data is set. When the first BB winning data is set in the main side RAM 74, the game state shifts to the first BB state by establishing the first BB winning, and when the second BB winning data is set in the main side RAM 74, When the 2BB winning is established, the game state shifts to the 2BB state. If the game ends without the first BB winning in a state in which the first BB winning data is set in the main side RAM 74, the first BB winning data is carried over to the next and subsequent games, and the second BB winning data is stored in the main side RAM 74. When the game ends without the 2nd BB winning in a state where the winning data is set, the 2nd BB winning data is carried over to the next and subsequent games. The first BB winning data set in the main side RAM 74 is cleared to "0" when the first BB winning is established or when the all clearing process (step S106) is executed in the main process (FIG. 10), The 2nd BB winning data set in the main RAM 74 is cleared to "0" when the 2nd BB winning is established or when the all clearing process (step S106) is executed in the main process (FIG. 10).

In the first BB state or the second BB state, one game can be executed when the number of game media bet is "3". In the first BB state or the second BB state, the net increase expected value of game media in one game is a value greater than "0". The first BB state ends when the total number of paid out game media in the first BB state reaches the end reference number of "300", and the second BB state ends when the number of paid out game media in the second BB state reaches 300. reaches the end reference number of "150".

As already described with reference to FIG. 31(b) in the first embodiment, the game state area 77 is provided in the main side RAM 74. As shown in FIG. In this embodiment, the 6th bit of the gaming state area 77 is provided with a BB state flag. The BB state flag is a flag that enables the main MPU 72 to recognize that the gaming state is the first BB state or the second BB state. The BB state flag is set to "1" when transitioning to the first BB state or the second BB state, and is cleared to "0" when the first BB state or the second BB state ends. The main MPU 72 recognizes that the game state is the first BB state or the second BB state based on the fact that the BB state flag is set to "1". As already described in the first embodiment, the data stored in the gaming state area 77 are set to the command at the start and the command at the end. The effect-side MPU 92 grasps that the game state is the first BB state or the second BB state based on the data in the game state area 77 set in the start time command and the end time command.

FIG. 74(a) is an explanatory diagram for explaining the configuration of the main RAM 74 in this embodiment. As shown in FIG. 74(a), the main RAM 74 is provided with a limit number counter 74x, an interval game number counter 74y, a replay establishment number counter 74z, a cherry establishment number counter 74α, and a BB top aggregation area 74β. there is These limit number counter 74x, interval game number counter 74y, replay establishment number counter 74z, cherry establishment number counter 74α and BB top aggregation area 74β are produced by the main side MPU 72 when the first BB prize or the second BB prize is established. This is a storage area in which data is set in the BB shift command sent to the side MPU 92 . Details of the BB transition command will be described later.

The limit number counter 74x determines whether the total number of payouts of game media in the first BB state or the second BB state has reached the end reference number ("300" in the first BB state, "150" in the second BB state). It is a counter that enables the master side MPU 72 to grasp whether or not. When the 1st BB winning is established, the limited number counter 74x is set to "300", and when the 2nd BB winning is established, the limited number counter 74x is set to "150". The limit number counter 74x consists of 2 bytes. As shown in FIG. 74(a), the address "0021H" in the main RAM 74 is set to the lower area (lower 1-byte area) of the limit number counter 74x, and the address "0022H" is set to A high-order area (high-order 1-byte area) of the limit number counter 74x is set. When "300" ("0000000100101100B" in binary notation) is set in the limit number counter 74x, the value of the most significant bit in the lower area and upper area of the limit number counter 74x becomes "0". Also, when "150" ("0000000010010110B" in binary notation) is set in the limit number counter 74x, the value of the most significant bit in the lower area of the limit number counter 74x becomes "1". The value of the most significant bit in the upper area of is "0". The lower area of the limit number counter 74x is a storage area in which "1" can be set to the most significant bit, and the upper area of the limit number counter 74x is a storage area in which "1" is not set to the most significant bit.

The interval game number counter 74y is a counter that allows the main MPU 72 to grasp the number of games that have been executed in a state where a state other than the BB state (first BB state or second BB state) continues. The interval game number counter 74y consists of 2 bytes. Numerical information of any one of "0" to "65535" is set in the interval game number counter 74y. The main MPU 72 clears the value of the interval game number counter 74y to "0" based on the end of the first BB state or the second BB state, and the game starts in a game state that is neither the first BB state nor the second BB state. 1 is added to the value of the interval game number counter 74y based on the execution. However, if the game is executed in a state that is neither the first BB state nor the second BB state and the maximum value of the interval game number counter 74y is set to "65535", the interval game number The state in which the maximum value ("65535") is set in the counter 74y is maintained. Since the interval game number counter 74y counts the number of games in a numerical range of "0" to "65535" ("1111111111111111B" in binary notation), the lower area and upper area of the interval game number counter 74y are the most significant bits. is a storage area in which "1" can be set.

The replay establishment number counter 74z is a counter that enables the main MPU 72 to grasp the number of replay wins established in a situation where a state other than the BB state (first BB state or second BB state) continues. The replay establishment number counter 74z consists of 2 bytes. Numerical information of any one of "0" to "65535" is set in the replay establishment number counter 74z. The main MPU 72 clears the value of the replay establishment number counter 74z to "0" based on the end of the first BB state or the second BB state, and normal replay is performed in a game state that is neither the first BB state nor the second BB state. The value of the replay establishment number counter 74z is incremented by 1 based on the winning, first chance replay winning or second chance replay winning. However, in a state where the game state is neither the first BB state nor the second BB state and the maximum value "65535" is set in the replay establishment counter 74z, the normal replay win, the first chance replay win or the second chance replay win When the chance replay win is established, the state in which the maximum value ("65535") is set in the replay establishment number counter 74z is maintained. Since the replay success counter 74z counts the number of successful replay wins within a numerical range of "0" to "65535" ("1111111111111111B" in binary notation), the lower area and upper area of the replay success counter 74z are: This is a storage area in which the most significant bit can be set to "1".

The cherry winning number counter 74α is a counter that enables the main MPU 72 to grasp the number of cherry wins that are established in a situation where a state other than the BB state (first BB state or second BB state) continues. The cherry establishment number counter 74α consists of 1 byte. Numerical information of one of "0" to "255" is set in the number-of-cherries-established counter 74α. The main MPU 72 clears the value of the cherry establishment number counter 74α to "0" based on the end of the first BB state or the second BB state, and also wins a cherry prize in a game state that is neither the first BB state nor the second BB state. is established, the value of the cherry establishment number counter 74α is incremented by one. However, if a cherry win is established in a state in which the game state is neither the first BB state nor the second BB state and the maximum value "255" is set in the cherry success counter 74α, the number of cherry successes is determined. The state in which the maximum value (“255”) is set in the counter 74α is maintained. Since the value of the cherry completion counter 74α may be "128" ("0000000010000000B" in binary notation) or more, the cherry completion counter 74α is a storage area in which the most significant bit can be set to "1".

The BB top-level aggregation area 74β includes the lower area and upper area of the limit number counter 74x set in the continuous address range of "0021H" to "0027H", the lower area and upper area of the interval game number counter 74y, and the replay The data "0" or "1" stored in the lower area and upper area of the success number counter 74z and the most significant bit (the 7th bit in the 0th to 7th bits) of the cherry success number counter 74α are aggregated. storage area. The BB top-level aggregation area 74β consists of 1 byte. The most significant bit data in the lower area of the limit number counter 74x is set to the 0th bit of the BB highest order aggregate area 74β, and the most significant bit data in the upper area of the limit number counter 74x is set to the BB highest order aggregate area 74β. , and the most significant bit data in the lower area of the interval game number counter 74y is set to the second bit of the BB highest aggregation area 74β, and the most significant bit in the upper area of the interval game number counter 74y. is set to the 3rd bit of the BB highest aggregation area 74β, and the data of the highest bit in the lower area of the replay establishment counter 74z is set to the 4th bit of the BB highest aggregation area 74β, and the replay is established. The most significant bit data in the upper area of the number counter 74z is set to the fifth bit of the BB highest aggregation area 74β. bits are set. The value of the highest bit (seventh bit) of the BB highest-order aggregation area 74β is always "0", and the BB highest-order aggregation area 74β is a storage area in which the highest bit is not set to "1".

The BB top-level aggregation area 74β is set to an address of "0028H" which is continuous in the address range of "0021H" to "0027H". Data is stored in the storage area of the main RAM 74 due to the configuration in which the target storage area in which the data is set in the BB transition command in the main RAM 74 is set in the continuous address range of "0021H" to "0028H". It is possible to simplify the processing configuration for setting the data stored in the BB transition command.

As described above, when the first BB prize or the second BB prize is established, the main side MPU 72 transmits the BB shift command to the effect side MPU 92 . The BB transition command is a command for making the effect-side MPU 92 grasp that the first BB state or the second BB state is started. As described above, the BB shift command is set with the data stored in the limit number counter 74x, the interval game number counter 74y, the replay establishment number counter 74z, the cherry establishment number counter 74α, and the BB top-level aggregation area 74β. there is When the effect-side MPU 92 recognizes that the value of the limit number counter 74x is "300" based on the BB transition command received from the main-side MPU 72, the upper part is set so that the start effect of the first BB state is executed. Light emission control of the lamp 61, sound output control of the speaker 62, and display control of the image display device 63 are executed, and the value of the limit number counter 74x is "150" based on the BB shift command received from the main side MPU 72. When it is grasped, the light emission control of the upper lamp 61, the sound output control of the speaker 62, and the display control of the image display device 63 are executed so that the start effect of the second BB state is executed.

The effect-side ROM 93 stores two types of light emission data tables for executing light emission control of the upper lamp 61 in the start effect of the first BB state, and executes sound output control of the speaker 62 in the start effect of the first BB state. Two types of sound data tables are stored for the purpose of the first BB state, and two types of image data tables are stored for executing the display control of the image display device 63 in the start rendering of the first BB state. When executing the start effect of the first BB state, the effect-side MPU 92 selects the light emission data table using the data of the interval game number counter 74y set in the BB transition command, and is set in the BB transition command. The sound data table is selected using the data of the replay establishment number counter 74z, and the image data table is selected using the data of the cherry establishment number counter 74α set in the BB shift command. Then, based on the selected light emission data table, sound data table and image data table, the upper lamp 61, the speaker 62 and the image display device 63 execute the first BB state start effect. Thus, the first BB state start effect can be executed in a mode corresponding to the value of the interval game number counter 74y, the value of the replay establishment number counter 74z, and the value of the cherry establishment number counter 74α.

The effect-side ROM 93 stores two types of light emission data tables for executing light emission control of the upper lamp 61 in the start effect of the second BB state, and executes sound output control of the speaker 62 in the start effect of the second BB state. Two kinds of sound data tables are stored for the purpose of the second BB state, and two kinds of image data tables are stored for executing the display control of the image display device 63 in the start rendering of the second BB state. When executing the start effect of the second BB state, the effect-side MPU 92 selects the light emission data table using the data of the interval game number counter 74y set in the BB transition command, and is set in the BB transition command. The sound data table is selected using the data of the replay establishment number counter 74z, and the image data table is selected using the data of the cherry establishment number counter 74α set in the BB shift command. Then, based on the selected light emission data table, sound data table and image data table, the upper lamp 61, the speaker 62 and the image display device 63 execute the second BB state start effect. Thus, the second BB state start effect can be executed in a mode corresponding to the value of the interval game number counter 74y, the value of the replay establishment number counter 74z, and the value of the cherry establishment number counter 74α.

When the BB shift command is transmitted, the data stored in the most significant bit of the storage area set in the address range of "0021H" to "0027H" in the main side RAM 74 is set in the BB highest order aggregation area 74β. At the same time, the data stored in the storage area set in the address range of “0021H” to “0028H” in the main RAM 74 is set in the transmission standby buffer 112 . Further, as already explained in the first embodiment, when the command at the start or the command at the end is transmitted, the maximum of the storage area set in the address range of "0001H" to "0006H" in the main RAM 74 is The data stored in the upper bits is set in the highest-order aggregation area 74v, and the data stored in the storage area set in the address range of "0001H" to "000DH" in the main RAM 74 is transmitted. It is set in the waiting buffer 112 .

The command at the start, the command at the end, and the BB transition command are transmitted to the effect side MPU 92 by executing a common command transmission process (FIG. 74(b)), which will be described later. In the common command transmission process, in the command output process in step S211 of the timer interrupt process (FIG. 11), if the command flag at the start of the main RAM 74 is set to "1", the command flag at the end of the main RAM 74 is set to It is executed when "1" is set or when the BB transition command flag provided in the main RAM 74 is set to "1". The BB transition command flag is a flag that enables the main MPU 72 to recognize that the transition to the first BB state or the second BB state has occurred. The BB shift command flag is set to "1" when the condition for shifting to the first BB state or the second BB state is satisfied.

In the game in which the 1st BB prize or the 2nd BB prize is established, the period from when the start command flag is set to "1" to when the BB transition command flag is set to "1" is the reel 32L, 32M, 32R. This period is longer than the acceleration period (specifically, 0.3 seconds). Also, the acceleration period of the reels 32L, 32M, 32R is longer than the interrupt period (1.49 milliseconds) of the timer interrupt process (FIG. 11). In this game, the BB shift command flag is set to "1" after the processing for transmitting the start command in the common command transmission processing is executed, so both the start command flag and the BB shift command flag The common command transmission process is never executed while "1" is set.

In the common command transmission process, the main MPU 72 recognizes that the start command will be transmitted when the start command flag is set to "1", and when the BB shift command flag is set to "1". It knows to send a BB transition command if there is. Also, the main MPU 72 understands that the BB transition command is to be transmitted when the value of the BB transition command flag is "0" and the end time command flag is set to "1". When the common command transmission process is executed with the BB transition command flag and the command flag at the end set to "1", the process for transmitting the BB transition command is executed, resulting in approximately 1.49 milliseconds. In the next common command transmission process executed seconds later, the process for transmitting the termination command is executed. In this way, in a game in which the first BB prize or the second BB prize is established, commands are transmitted to the effect side MPU 92 in the order of the start command→BB transition command→end command.

Next, the common command transmission processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. 74(b).

In the common command transmission process, steps S4201 and S4202 are similar to steps S2801 and S2802 of the common command transmission process (FIG. 50) in the first embodiment. Specifically, first, top-level aggregation processing is executed (step S4201). FIG. 75 is a flow chart showing the highest level aggregation processing.

In the top-level aggregation process, a transfer destination setting process is executed (step S4301). In the transfer destination setting process, the address of the highest level aggregation area 74v in the main RAM 74 is set in the transfer destination counter 115 of the main RAM 74 when the command at the start or the command at the end is transmitted. As a result, the top-level aggregation area 74v can be set as the transfer destination storage area. Also, when transmitting the BB shift command, the address of the BB top-level aggregation area 74β in the main side RAM 74 is set in the transfer destination counter 115 . As a result, the BB top-level aggregation area 74β can be set as the transfer destination storage area. As described above, the main MPU 72 understands that the start command will be transmitted when the start command flag is set to "1", and when the BB shift command flag is set to "1" to send a BB transition command to. Also, the main MPU 72 understands that the BB transition command is to be transmitted when the value of the BB transition command flag is "0" and the end time command flag is set to "1".

After that, the transfer destination storage area is cleared to "0" (step S4302). In step S4302, if the top-level aggregation area 74v is set as the transfer destination storage area in step S4301, the top-level aggregation area 74v is cleared to "0". When the area 74β is set as the transfer destination storage area, the BB top-level aggregation area 74β is cleared to "0". After that, the value of the bit designation counter 117 in the main RAM 74 is cleared to "0" (step S4303), similarly to step S2903 of the highest level aggregation process (FIG. 51) in the first embodiment. As a result, the 0th bit of the highest-order aggregation area 74v can be set as the transfer destination bit when transmitting the start time command or the end time command, and the transfer destination bit can be set when transmitting the BB transition command. , the 0th bit of the BB top-level aggregation area 74β can be set.

After that, start address setting processing for the highest level aggregation is executed (step S4304). In the top-level aggregation start address setting process, the start address of the transfer target range in the top-level aggregation process is set in the transfer source counter 116 of the main RAM 74 . Specifically, when the command at the start or the command at the end is transmitted, the transfer target range in the highest-level aggregation process is the address range of "0001H" to "0006H", and the start address of the transfer target range "0001H" ” is set in the transfer source counter 116 . Further, when the BB shift command is transmitted, the range of addresses to be transferred in the highest-level aggregation process is the range of addresses from "0021H" to "0027H", and the start address of the range to be transferred, "0021H", is sent to the transfer source counter 116. set.

After that, transfer count setting processing for top-level aggregation is executed (step S4305). In the transfer count setting process for the highest level aggregation, when sending a start command or an end command, the number of storage areas included in the transfer target range ("0001H" to "0006H") in the highest level aggregation process. A certain "6" is set in the transfer number counter 114 as the number of transfers. When transmitting the BB shift command, the number of transfer times counter 114 is set to "7", which is the number of storage areas included in the transfer target range ("0021H" to "0027H") in the highest-level aggregation process. set.

After that, in steps S4306 to S4310, the same processes as steps S2906 to S2910 of the highest level aggregation process (FIG. 51) in the first embodiment are executed. Specifically, the most significant bit data in the transfer source storage area is transferred to the transfer destination bit (step S4306). The main MPU 72 identifies the storage area of the transfer source based on the address stored in the transfer source counter 116, and determines the transfer destination bit based on the address stored in the transfer destination counter 115 and the value of the bit designation counter 117. identify. Thereafter, 1 is subtracted from the value of the transfer number counter 114 (step S4307), and it is determined whether or not the value of the transfer number counter 114 after the subtraction of 1 is "0" (step S4308).

If a negative determination is made in step S4308, the address of the transfer source storage area is updated by adding 1 to the value of the transfer source counter 116 (step S4309). The processing of steps S4306 to S4310 is repeatedly executed until an affirmative determination is made in step S4308. In step S4309, when transmitting a command at the start or a command at the end, the address of the transfer source storage area is updated in the order of "0001H"→"0002H"→...→"0005H"→"0006H". Further, when the BB shift command is transmitted, the address of the transfer source storage area is updated in the order of "0021H"→"0022H"→...→"0026H"→"0027H".

Thereafter, the transfer destination bit in the transfer destination storage area is updated by adding 1 to the value of the bit designation counter 117 in the main RAM 74 (step S4310). In step S4310, when transmitting the command at the start or the command at the end, the transfer destination bits in the top-level aggregation area 74v are updated in the order of 0th bit → 1st bit → ... → 4th bit → 5th bit. be. Further, when the BB shift command is transmitted, the transfer destination bits in the BB top-level aggregation area 74β are updated in the order of 0th bit → 1st bit → . . . → 5th bit → 6th bit.

Thereafter, the process proceeds to step S4306, and the processes of steps S4306 to S4310 are repeatedly executed until an affirmative determination is made in step S4308. As a result, when transmitting a command at the start or a command at the end, the data stored in the most significant bits of the six storage areas included in the address range of "0001H" to "0006H" are used for the highest aggregation. It can be set to the 0th to 5th bits of the area 74v, and the most significant bits of the seven storage areas included in the address range of "0021H" to "0027H" when the BB transition command is transmitted. The stored data can be set in the 0th to 6th bits of the BB highest aggregation area 74β. If an affirmative determination is made in step S4308, this top-level aggregation processing ends.

In this way, as commands for aggregating the data stored in the most significant bit, the command at the start and the command at the end, and the command at the start and the command at the end are aggregating the data stored in the most significant bit. In a configuration where there are BB transition commands with different address ranges (transfer target range in the highest-level aggregation process) to be performed, the transfer target range in the highest-level aggregation process according to the type of command to be sent By changing the information on the start address and the number of transfers, the address range of "0001H" to "0006H" is set when sending a command at the start or a command at the end using the common highest-level aggregate processing. The data stored in the most significant bit of the stored storage area can be aggregated into the highest aggregation area 74v, and when the BB shift command is transmitted, the address range of "0021H" to "0027H" can be aggregated. The data stored in the most significant bit of the set storage area can be aggregated into the BB highest aggregation area 74β. For this reason, as a separate process from the process of aggregating the data stored in the most significant bit when transmitting the command at the start or the command at the end, the data stored in the most significant bit is stored in the most significant bit when the BB transition command is transmitted. To reduce the data capacity of the program stored in the main ROM 73 for executing the process of aggregating the data stored in the most significant bit compared to the configuration provided with the process of aggregating the data stored in the can be done.

When the command at the start or the command at the end is transmitted, the transfer target range in the highest-level aggregation process is the continuous address range of “0001H” to “0006H” in the main RAM 74 . Further, when the BB shift command is transmitted, the transfer target range in the highest-level aggregation process is the continuous address range of “0021H” to “0027H” in the main RAM 74 . By repeatedly executing the process of adding 1 to the value of the transfer source counter 116 in the main RAM 74 (the process of step S4309), the storage area of the transfer source can be sequentially updated. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the transfer target range in the highest-level aggregation process is a continuous address range in the main RAM 74, the start address of the transfer target range is set in the transfer source counter 116 in step S4304, and the transfer count counter is set in step S4305. By setting information on the number of transfers in 114, the transfer target range can be specified. This simplifies the processing configuration for designating the transfer target range in the highest-level aggregation processing.

Returning to the description of the common command transmission process (FIG. 74(b)), after the top-level aggregation process is executed in step S4201, the value of the write pointer 113 in the transmission circuit 85 is grasped, and the writing in the transmission standby buffer 112 is performed. The previous area is grasped (step S4202), and header setting processing is executed (step S4203). In the header setting process, if the start command flag is set to "1", the data of the header HD corresponding to the start command stored in the main ROM 73 is written to the write destination area ascertained in step S4202. set. If the BB shift command flag is set to "1", the header HD data corresponding to the BB shift command stored in the main ROM 73 is set in the write destination area ascertained in step S4202. Furthermore, when the value of the BB shift command flag is "0" and the end command flag is set to "1", the data of the header HD corresponding to the end command stored in the main ROM 73 is The write destination area determined in step S4202 is set.

Thereafter, as in step S2808 of the common command transmission processing (FIG. 50) in the first embodiment, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4204). . In step S4204, step S4209 to be described later, and step S4214 to be described later, the value of the write pointer 113 is incremented by one. Clear the pointer 113 to "0".

After that, start address setting processing is executed (step S4205). In the start address setting process, when transmitting the start time command or the end time command, "0001H", which is the start address of the transfer target range ("0001H" to "000DH") in the common command transmission process, is set in the main side RAM 74. In addition to setting in the transfer source counter 116, when transmitting the BB transition command, the start address of the transfer target range (“0021H” to “0028H”) in the common command transmission process, “0021H”, is transferred to the main side RAM 74. It is set in the original counter 116 .

After that, transfer count setting processing is executed (step S4206). In the number-of-transfers setting process, when transmitting the command at the start or the command at the end, the number of storage areas included in the transfer target range ("0001H" to "000DH") in the common command transmission process, which is "13 ” as the number of transfers is set in the transfer counter 114 of the main RAM 74, and when the BB shift command is sent, it is included in the transfer target range (“0021H” to “0028H”) in the common command sending process. The transfer number counter 114 is set to "8", which is the number of storage areas, as the number of transfers.

After that, in steps S4207 to S4214, the same processing as steps S2811 to S2818 of the common command transmission processing (FIG. 50) in the first embodiment is executed. Specifically, the write destination area of the transmission standby buffer 112 corresponding to the value of the write pointer 113 is grasped, the transfer source storage area is grasped based on the address set in the transfer source counter 116, and the relevant storage area is grasped. The data in the transfer source storage area is transferred to the write destination area (step S4207). Thereafter, the most significant bit (seventh bit) in the write destination area is set to "0" (step S4208). As a result, when a command at the start or a command at the end is transmitted, the value of the most significant bit in the 2nd to 14th frames FR2 to FR14 of the command at the start or the command at the end can be set to "0". In addition, it is possible to distinguish between the header HD and the second to fourteenth frames FR2 to FR14 based on the value of the most significant bit. Further, when transmitting a BB transition command, the value of the most significant bit in the second to ninth frames FR2 to FR9 of the BB transition command can be set to "0", and based on the value of the most significant bit header HD and the second to ninth frames FR2 to FR9.

After that, as in step S4204, the value of the write pointer 113 is updated (step S4209), and the value of the transfer number counter 114 is decremented by 1 (step S4210). Then, it is determined whether or not the value of the transfer number counter 114 after subtracting 1 is "0" (step S4211). If a negative determination is made in step S4211, that is, if the transfer of the data stored in the 1-byte storage area included in the transfer target range to the transmission standby buffer 112 has not ended, the transfer source By adding 1 to the value of the counter 116, the address of the transfer source storage area is updated (step S4212). The processing from step S4207 to step S4212 is repeatedly executed until an affirmative determination is made in step S4211. In step S4212, when transmitting a command at the start or a command at the end, the storage area to be the transfer source area is stored in the order of "0001H"→"0002H"→"0003H"→...→"000CH"→"000DH". When sending a BB shift command, the transfer source storage area is updated in the order of "0021H"→"0022H"→"0023H"→...→"0027H"→"0028H". Update your address.

Thereafter, the process proceeds to step S4207, and the processes of steps S4207 to S4212 are repeatedly executed until an affirmative determination is made in step S4211. As a result, when transmitting a command at the start or a command at the end, the data stored in the 14 storage areas included in the address range of "0001H" to "000DH" are set in the transmission standby buffer 112. In addition, when transmitting the BB shift command, the data stored in the eight storage areas included in the address range of "0021H" to "0028H" can be set in the transmission standby buffer 112. can.

If an affirmative determination is made in step S4211, the data of the footer FT stored in the main ROM 73 is set in the write destination area corresponding to the value of the write pointer 113 in the transmission standby buffer 112 (step S4213). ), similar to steps S4204 and S4209, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4214).

After that, the command flag clearing process is executed (step S4215), and the common command transmission process ends. In the command flag clearing process in step S4215, if the start command flag is set to "1", the start command flag is cleared to "0". If the BB shift command flag is set to "1", the BB shift command flag is cleared to "0". Furthermore, when the value of the BB shift command is "0" and the end command flag is set to "1", the end command flag is cleared to "0". In the command flag clearing process (step S4215), only the BB transition command flag is cleared to "0" when the BB transition command flag and the termination command flag are set to "1". The state in which the command flag is set to "1" is maintained. As a result, it is possible to execute the processing for transmitting the termination command in the next common command transmission processing which is executed approximately 1.49 milliseconds later.

In this way, the start command and end command and the start command and end command are different in the address range to which data is set in the command in the main RAM 74 (the transfer target range in the common command transmission process). In a configuration in which a BB transition command exists, by varying the start address of the transfer target range and the transfer count information in the common command transmission process according to the type of the command to be transmitted, the common common command transmission process is used to set the data stored in the storage area set in the address range of "0001H" to "000DH" in the transmission standby buffer 112 when transmitting the command at the start or the command at the end. In addition, when the BB shift command is transmitted, the data stored in the storage area set in the address range of "0021H" to "0028H" can be set in the transmission standby buffer 112. FIG. For this reason, as a separate process from the process of setting the data of the main RAM 74 in the transmission standby buffer 112 when transmitting the command at the start or the command at the end, when transmitting the BB transition command, the main Compared to the configuration in which the processing of setting the data of the side RAM 74 is provided, the data capacity of the program stored in the main side ROM 73 for executing the processing of setting the data of the main side RAM 74 in the transmission standby buffer 112 is reduced. can be reduced.

When transmitting the command at the start or the command at the end, the transfer target range in the common command transmission process is the continuous address range of “0001H” to “000DH” in the main RAM 74 . Further, when the BB shift command is transmitted, the transfer target range in the common command transmission process is the continuous address range of “0021H” to “0028H” in the main side RAM 74 . Since the transfer target range in the common command transmission process is a continuous address range in the main RAM 74, by repeatedly executing the process of adding 1 to the value of the transfer source counter 116 in the main RAM 74 (the process of step S4212), the transfer source can be updated sequentially. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the transfer target range in the common command transmission process is a continuous address range in the main RAM 74, the start address of the transfer target range is set in the transfer source counter 116 in step S4205, and the transfer count counter is set in step S4206. By setting information on the number of transfers in 114, the transfer target range can be specified. This simplifies the processing configuration for designating the transfer target range in the common command transmission processing.

According to this embodiment detailed above, the following excellent effects are obtained.

Commands at the start and at the end of commands for which the data stored in the most significant bits are aggregated, and the commands at the start and the commands at the end are the objects for which the data stored in the most significant bits are aggregated. In a configuration where there are BB transition commands with different address ranges (transfer target range in the highest-level aggregation process), the start address of the transfer target range in the highest-level aggregation process and By varying the information on the number of transfers, the memory set in the address range of "0001H" to "0006H" is used when transmitting the command at the start or the command at the end using the common highest-level aggregate processing. The data stored in the most significant bit of the area can be aggregated into the highest aggregation area 74v, and the address range of "0021H" to "0027H" is set when the BB shift command is transmitted. The data stored in the most significant bit of the storage area can be aggregated in the BB highest aggregation area 74β. For this reason, as a separate process from the process of consolidating the data stored in the most significant bit when transmitting the command at the start or the command at the end, when the BB transition command is transmitted, the data stored in the most significant bit is To reduce the data capacity of the program stored in the main ROM 73 for executing the process of aggregating the data stored in the most significant bit compared to the configuration provided with the process of aggregating the data stored in the can be done.

The command at the start and the command at the end, and the command at the start and the command at the end are BB transition commands in which the address range for which data is set in the command in the main RAM 74 (transfer target range in the common command transmission process) is different. is present, the common command transmission process can be used by changing the start address of the transfer target range and the number of times of transfer in the common command transmission process according to the type of command to be transmitted. , when transmitting the command at the start or the command at the end, the data stored in the storage area set in the address range of "0001H" to "000DH" can be set in the transmission standby buffer 112, When transmitting the BB shift command, the data stored in the storage area set in the address range of "0021H" to "0028H" can be set in the transmission standby buffer 112. FIG. For this reason, as a separate process from the process of setting the data of the main RAM 74 in the transmission standby buffer 112 when transmitting the command at the start or the command at the end, when transmitting the BB transition command, the main Compared to the configuration in which the processing of setting the data of the side RAM 74 is provided, the data capacity of the program stored in the main side ROM 73 for executing the processing of setting the data of the main side RAM 74 in the transmission standby buffer 112 is reduced. can be reduced.

<Fourth Embodiment>
In this embodiment, the data table (common data table 73f, which will be described later) stored in the main ROM 73 is used to grasp the storage area of the main RAM 74 to which data is to be set for the command at the start and the command at the end. is different from the first embodiment. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

As already described in the first embodiment, data stored in a plurality of storage areas in the main RAM 74 are set in the command at the start and the command at the end. In the present embodiment, at least part of the storage areas to which data is set in the start command and end command are not set in a continuous address range in the main RAM 74 . FIG. 76 is an explanatory diagram for explaining the common data table 73f stored in the main ROM 73 in this embodiment. The common data table 73f is a data table that enables the main MPU 72 to grasp the address of the storage area of the main RAM 74 to which data is to be set in the command at the start and the command at the end. The common data table 73f is referred to when transmitting the start time command and the end time command.

As shown in FIG. 76(a), the common data table 73f is set in a continuous address range from "9101H" to "911AH" in the main ROM 73. As shown in FIG. A large number of 1-byte storage areas are set in the main ROM 73, and 2-byte addresses are set in one-to-one correspondence with each of the 1-byte storage areas. A 1-byte storage area in the main ROM 73 is specified by a 2-byte address. As already described in the first embodiment, a large number of 1-byte storage areas are set in the main RAM 74, and a 2-byte address is assigned to each 1-byte storage area in a one-to-one correspondence. is set. A 1-byte storage area in the main RAM 74 is specified by a 2-byte address.

The address of the lower area of the AT continuation counter 74u is set in the 2-byte storage area corresponding to the addresses "9101H" to "9102H", and the 2-byte storage area corresponding to the addresses "9103H" to "9104H". The address of the upper area of the AT continuation counter 74u is set in the area, and the address of the lower area of the continuous game number counter 74r is set in the 2-byte storage area corresponding to the addresses "9105H" to "9106H". In the 2-byte storage area corresponding to the addresses "9107H" to "9108H", the upper area address of the continuous game number counter 74r is set, and the addresses corresponding to the addresses "9109H" to "910AH" are set. In the 2-byte storage area, the address of the lower area of the total acquisition number counter 74s is set, and in the 2-byte storage area corresponding to the addresses "910BH" to "910CH", the upper area of the total acquisition number counter 74s is set. are set, and the addresses of the top-level aggregation area 74v are set in the 2-byte storage area corresponding to the addresses of "910DH" to "910EH", and the addresses of "910FH" to "9110H" are set. The address of the bet number setting counter 74b is set in the 2-byte storage area corresponding to , and the address of the stop order type counter 74m is set in the 2-byte storage area corresponding to the addresses "9111H" to "9112H". The address of the game state area 77 is set in the 2-byte storage area corresponding to the addresses "9113H" to "9114H", and the 2-byte memory area corresponding to the addresses "9115H" to "9116H" is set. The address of the game section area 76 is set in the storage area of , and the address of the pseudo bonus continuation counter 74t is set in the 2-byte storage area corresponding to the addresses of "9117H" to "9118H". 9119H" to "911AH", the address of the number of grant counter 74e is set in the 2-byte storage area corresponding to the address.

In the main-side ROM 73, since the addresses of the storage areas in which the data is set in the command at the start and the command at the end are set in a continuous address range of "9101H" to "911AH", the data in these storage areas are transmitted. The processing configuration for specifying the addresses of these storage areas when setting them in the standby buffer 112 can be simplified.

As in the first embodiment, the upper and lower areas of the AT continuation counter 74u, the lower and upper areas of the continuous game number counter 74r, and the lower and upper areas of the total winning number counter 74s. The data are aggregated in the 0th to 5th bits of the highest aggregation area 74v in the main RAM 74. FIG. In the main-side ROM 73, the lower area and upper area of the AT continuation counter 74u in which the data of the most significant bit is aggregated in the highest aggregation area 74v, the lower area and upper area of the continuous game number counter 74r, and the total winning number counter 74s. The addresses of the lower area and the upper area are set in a continuous address range of "9101H" to "910CH". For this reason, when setting the most significant bit data in these lower area and upper area to the 0th to 5th bits of the highest aggregation area 74v, processing for specifying the addresses of these lower area and upper area Configuration can be simplified.

In a configuration in which data is set in the command at the start and data is set in the command at the end while referring to the data table (common data table 73f) stored in the main-side ROM 73, when setting data in the command at the start: The data table to be referred to and the data table to be referred to when data is set in the termination command are common. Therefore, it is possible to reduce the data capacity of the data table stored in the main-side ROM 73 in order to perform the process of setting data in the start time command and the end time command.

The storage area of the main RAM 74 in which data is set in the start command is the same as the storage area of the main RAM 74 in which data is set in the end command. As a result, the data table referred to when setting data in the start command and the data table referred to when setting data in the end command can be a common data table (common data table 73f). .

FIG. 76(b) is an explanatory diagram for explaining the configuration of the main RAM 74. As shown in FIG. As shown in FIG. 76B, the main RAM 74 is provided with a transfer source address counter 132 and an end address counter 133 . The transfer source address counter 132 is a counter that enables the main side MPU 72 to grasp the address of the main side ROM 73 in which the address of the transfer source storage area in the main side RAM 74 is set. The transfer source address counter 132 consists of 2 bytes.

The end address counter 133 is a counter that enables the master side MPU 72 to grasp the end address of the range to be transferred in the common command transmission process (FIG. 77) and the highest level aggregation process (FIG. 78) which will be described later. The transfer target range in the common command transmission process (FIG. 77) is the address range from "9101H" to "911AH" in the common data table 73f, and the end address of the transfer target range is "9119H". As described above, the given number counter 74e is set at the end of the transfer target range, and "9119H" is the head of the address range from "9119H" to "911AH" in which the address of the given number counter 74e is set. is the address. The transfer target range in the highest level aggregation process (FIG. 78) is the address range from "9101H" to "910CH" in the common data table 73f, and the end address of the transfer target range is "910BH". As described above, the upper area of the total acquisition number counter 74s is set at the end of the transfer target range, and "910BH" is the address of the upper area of the total acquisition number counter 74s. This is the top address in the address range of "910CH".

Next, the common command transmission processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. As already described in the first embodiment, the common command transmission process is performed when the start command flag of the main RAM 74 is set to "1" in the command output process (FIG. 44) (step S2707: YES). , or when "1" is set in the end command flag of the main RAM 74 (step S2708: YES), it is executed in step S2709. As already described, when the game is started, the start command flag is set to "1" in step S1107 of the lottery result handling process (FIG. 25), and the end command flag is set to end the game. In this case, "1" is set in step S1508 of the corresponding processing (FIG. 32) at the end of the game.

In the common command transmission process, first, the common data table 73f stored in the main ROM 73 is read (step S4401). After that, the highest level aggregation process is executed (step S4402). FIG. 78 is a flow chart showing the highest level aggregation process executed by the main MPU 72. FIG.

In the highest level aggregation process, first, the address of the highest level aggregation area 74v of the main side RAM 74 is set in the transfer destination counter 115 of the main side RAM 74 (step S4501). As a result, the highest level aggregation area 74v can be set as the transfer destination storage area. After that, the highest level aggregation area 74v is cleared to "0" (step S4502), and the value of the bit designation counter 117 in the main side RAM 74 is cleared to "0" (step S4503). As a result, the 0th bit of the top-level aggregation area 74v can be set as the transfer destination bit.

Thereafter, "9101H", which is the start address of the transfer target range ("9101H" to "910CH") of the highest-level aggregation process (FIG. 78), is set in the transfer source address counter 132 (step S4504). As a result, the lower area of the AT continuation counter 74u can be grasped as the storage area of the transfer source based on the addresses set to the addresses "9101H" to "9102H" in the common data table 73f. Thereafter, "910BH", which is the end address of the transfer target range ("9101H" to "910CH") of the highest-level aggregation process (FIG. 78), is set in the end address counter 133 of the main RAM 74 (step S4505).

Thereafter, the most significant bit data in the transfer source storage area is transferred to the transfer destination bit (step S4506). In step S4506, based on the data of the storage area corresponding to the address set in the transfer source address counter 132 in the common data table 73f, the address of the transfer source storage area in the main RAM 74 is specified, and the transfer destination counter 115 and the value of the bit designation counter 117, the transfer destination bit is specified. Thereafter, it is determined whether or not the data in the transfer source address counter 132 is the end address set in the end address counter 133 in step S4505 (step S4507).

If the data in the transfer source address counter 132 is not the end address (step S4507: NO), the transfer source storage area is updated by adding 2 to the value of the transfer source address counter 132 (step S4508). The processing of steps S4506 to S4509 is processing that is repeatedly executed until an affirmative determination is made in step S4507. , the addresses stored in the transfer source address counter 132 are updated. After that, by adding 1 to the value of the bit designation counter 117, the transfer destination bit in the top-level aggregation area 74v is updated (step S4509). In step S4509, the transfer destination bits in the highest level aggregation area 74v are updated in the order of 0th bit→1st bit→...→4th bit→5th bit.

After that, the process advances to step S4506, and the processes of steps S4506 to S4509 are repeatedly executed until an affirmative determination is made in step S4507. As a result, the data of the most significant bit in the storage area grasped based on the addresses set in the address range of "9101H" to "910CH" in the common data table 73f is transferred to the 0th to th of the most significant aggregation area 74v. Can be set to 5 bits. If an affirmative determination is made in step S4507, this top-level aggregation processing ends.

As already explained, in the main ROM 73, the lower area and upper area of the AT continuation counter 74u in which the most significant bit data is aggregated in the highest aggregation area 74v, the lower area and upper area of the continuous game number counter 74r, and The addresses of the lower area and upper area of the total acquisition number counter 74s are set in a continuous address range of "9101H" to "910CH". For this reason, after setting the start address (“9101H”) of the transfer target range (“9101H” to “910CH”) of the highest-level aggregation process (FIG. 78) in the transfer source address counter 132, the highest address in the transfer source storage area is set. A process of transferring the upper bit data to the transfer destination bit (process of step S4506), a process of adding 2 to the value of the transfer source address counter 132 and updating the transfer source storage area (process of step S4508), and bit designation By repeatedly executing the process of adding 1 to the value of the counter 117 and updating the transfer destination bit (the process of step S4509), the maximum storage area in the storage area of the main RAM 74 specified by the address set in the transfer target range. High-order bit data can be aggregated in the highest-order aggregation area 74v. As a result, the most significant bit data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continuous game number counter 74r, and the lower and upper areas of the total winning number counter 74s are transferred to the highest aggregation area. The processing configuration for consolidating to 74v is simplified.

Returning to the description of the common command transmission process (FIG. 77), after executing the top-level aggregation process in step S4402, in steps S4403 to S4409, the steps of the common command transmission process (FIG. 50) in the first embodiment Processing similar to that of steps S2802 to S2808 is executed. Specifically, the write destination area in the transmission standby buffer 112 is grasped by grasping the value of the write pointer 113 (FIG. 45) in the transmission circuit 85 (step S4403). After that, if the start command flag of the main RAM 74 is set to "1" (step S4404: YES), that is, if it is time to start the game, the start command stored in the main ROM 73 is executed. The data of the corresponding header HD is set in the write destination area grasped in step S4403 (step S4405), and the start command flag is cleared to "0" (step S4406). On the other hand, if the start command flag is not set to "1" (step S4404: NO), that is, if the game is over, the header HD corresponding to the end command stored in the main ROM 73 data is set in the write destination area ascertained in step S4403 (step S4407), and the end command flag of the main RAM 74 is cleared to "0" (step S4408).

If the process of step S4406 or step S4408 has been performed, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4409). In step S4409, the value of the write pointer 113 is incremented by 1, and when the value of the write pointer 113 after the increment of 1 exceeds the maximum value of "31", the write pointer 113 is cleared to "0".

Thereafter, "9101H", which is the start address of the transfer target range ("9101H" to "911AH") in the common command transmission process (FIG. 77), is set in the transfer source address counter 132 (step S4410). Thus, based on the addresses set in the address range of "9101H" to "9102H" in the common data table 73f, it is possible to recognize the lower area of the AT continuation counter 74u as the transfer source storage area. Thereafter, "9119H", which is the end address of the transfer target range ("9101H" to "911AH") in the common command transmission process (FIG. 77), is set in the end address counter 133 (step S4411).

After that, the data stored in the transfer source storage area is transferred to the write destination area in the transmission standby buffer 112 (step S4412). In step S4412, the address of the transfer source storage area in the main RAM 74 is specified based on the data of the storage area corresponding to the address set in the transfer source address counter 132 in the common data table 73f. Thereafter, the most significant bit (seventh bit) in the write destination area is set to "0" (step S4413). As a result, the value of the most significant bit of the second to fourteenth frames FR2 to FR14 can be set to "0", and based on the value of the most significant bit, the header HD and the second to fourteenth frames FR2 to FR14 can be made identifiable.

After that, as in step S4409, the value of the write pointer 113 is updated (step S4414). Specifically, 1 is added to the value of the write pointer 113, and when the value of the write pointer 113 after the addition of 1 exceeds the maximum value of "31", the write pointer 113 is cleared to "0". Thereafter, it is determined whether or not the data in the transfer source address counter 132 is the end address ("9119H") set in the end address counter 133 in step S4411 (step S4415).

If the data in the transfer source address counter 132 is not the end address (step S4415: NO), 2 is added to the value of the transfer source address counter 132 to grasp the storage area of the transfer source in the common data table 73f. The referenced address is updated (step S4416). Thereby, the transfer source storage area in the main RAM 74 can be updated. The processing of steps S4412 to S4416 is processing that is repeatedly executed until an affirmative determination is made in step S4415. , the addresses stored in the transfer source address counter 132 are updated.

After that, the process proceeds to step S4412, and the processes of steps S4412 to S4416 are repeatedly executed until an affirmative determination is made in step S4415. As a result, the data stored in the storage area of the main RAM 74 corresponding to the addresses set in the address range of "9101H" to "911AH" in the common data table 73f can be set in the transmission standby buffer 112. .

If an affirmative determination is made in step S4415, in steps S4417 and S4418, the same processing as steps S2817 and S2818 of the common command transmission processing (FIG. 50) in the first embodiment is executed. Specifically, the data of the footer FT stored in the main ROM 73 is set in the write destination area corresponding to the value of the write pointer 113 in the transmission standby buffer 112 (step S4417). After that, as in steps S4409 and S4414, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4418), and the common command transmission processing ends.

As already explained, the address of the storage area of the main RAM 74 to which the data is set in the command at the start and the command at the end is set in the continuous address range of "9101H" to "911AH" in the common data table 73f. It is Therefore, after the start address (“9101H”) of the transfer target range (“9101H” to “911AH”) in the common command transmission process (FIG. 77) is set in the transfer source address counter 132, the data in the transfer source storage area is transferred to the write destination area in the transmission standby buffer 112 (step S4412), the process of updating the write destination area (step S4414), and the value of the transfer source address counter 132 is incremented by 2. By repeatedly executing the process of updating the original storage area, the data stored in the storage area of the main RAM 74 specified by the address set in the transfer target range can be set in the transmission standby buffer 112. can. This simplifies the processing configuration for setting the data stored in the storage area of the main RAM 74 as the start command and the end command.

According to this embodiment detailed above, the following excellent effects are obtained.

In a configuration in which data is set in the command at the start and data is set in the command at the end while referring to the data table (common data table 73f) stored in the main-side ROM 73, when setting data in the command at the start: The data table to be referred to and the data table to be referred to when data is set in the termination command are common. Therefore, it is possible to reduce the data capacity of the data table stored in the main-side ROM 73 in order to perform the process of setting data in the start time command and the end time command.

The storage area of the main RAM 74 in which data is set in the start command is the same as the storage area of the main RAM 74 in which data is set in the end command. As a result, the data table referred to when setting data in the start command and the data table referred to when setting data in the end command can be a common data table (common data table 73f). .

In the main side ROM 73, the lower area and upper area of the AT continuation counter 74u in which the data of the most significant bit is aggregated in the highest aggregation area 74v, the lower area and upper area of the continuous game number counter 74r, and the total winning number counter 74s The addresses of the lower area and the upper area are set in a continuous address range of "9101H" to "910CH". For this reason, after setting the start address (“9101H”) of the transfer target range (“9101H” to “910CH”) of the highest-level aggregation process (FIG. 78) in the transfer source address counter 132, the highest address in the transfer source storage area is set. A process of transferring the upper bit data to the transfer destination bit (process of step S4506), a process of adding 2 to the value of the transfer source address counter 132 and updating the transfer source storage area (process of step S4508), and bit designation By repeatedly executing the process of adding 1 to the value of the counter 117 and updating the transfer destination bit (the process of step S4509), the maximum storage area in the storage area of the main RAM 74 specified by the address set in the transfer target range. High-order bit data can be aggregated in the highest-order aggregation area 74v. As a result, the most significant bit data in the lower and upper areas of the AT continuation counter 74u, the lower and upper areas of the continuous game number counter 74r, and the lower and upper areas of the total winning number counter 74s are transferred to the highest aggregation area. The processing configuration for consolidating to 74v is simplified.

The addresses of the storage areas of the main RAM 74 to which data is set in the start command and the end command are set in the continuous address range of "9101H" to "911AH" in the common data table 73f. Therefore, after the start address (“9101H”) of the transfer target range (“9101H” to “911AH”) in the common command transmission process (FIG. 77) is set in the transfer source address counter 132, the data in the transfer source storage area is transferred to the write destination area in the transmission standby buffer 112 (step S4412), the process of updating the write destination area (step S4414), and the value of the transfer source address counter 132 is incremented by 2. By repeatedly executing the process of updating the original storage area, the data stored in the storage area of the main RAM 74 specified by the address set in the transfer target range can be set in the transmission standby buffer 112. can. This simplifies the processing configuration for setting the data stored in the storage area of the main RAM 74 as the start command and the end command.

<Fifth Embodiment>
In this embodiment, of the data stored in the storage area of the main side RAM 74 grasped based on the common data table 73f, only the data required by the effect side MPU 92 at the start of the game is set as the start command. In addition, of the data stored in the storage area of the main side RAM 74 grasped based on the common data table 73f, only the data required by the effect side MPU 92 at the end of the game is set as the end command. is different from the fourth embodiment. The configuration different from that of the fourth embodiment will be described below. Note that the description of the same configuration as that of the fourth embodiment is basically omitted.

FIG. 79(a) shows the addresses of the storage areas of the main RAM 74 that store the data set in the command at the start, out of the address range in which the common data table 73f of the main ROM 73 is set. FIG. 79B is an explanatory diagram for explaining the address range in which the addresses of the storage area of the main RAM 74 storing the data set in the command at the end are set, and FIG. FIG. 79(c) is an explanatory diagram for explaining the data structure of the command, and FIG. 79(c) is an explanatory diagram for explaining the data structure of the end command.

As shown in FIG. 79(a), the common data table 73f has a first setting range and a second setting range, and a first exclusion range and a second exclusion range. The first set range and the second set range are address ranges in which the addresses of the storage areas of the main RAM 74 in which the data set in the start command are stored are set. The first set range is the address range from "9101H" to "9104H", and the second set range is the address range from "910DH" to "9114H". The first exclusion range and the second exclusion range are address ranges in which addresses of storage areas of the main-side RAM 74 to which data is not set in the start command are set. The first exclusion range is the address range from "9105H" to "910CH", and the second exclusion range is the address range from "9115H" to "911AH".

As shown in FIG. 79(b), the command at the start includes addresses set in the first set range (“9101H” to “9104H”) and the second set range (“910DH” to “9114H”). The data of the lower area of the AT continuation counter 74u, the upper area of the AT continuation counter 74u, the uppermost area of the AT continuation counter 74u, the highest aggregate area 74v, the bet number setting counter 74b, the stop order type counter 74m, and the game state area 77 are set. . These data are data required by the effect side MPU 92 at the start of the game.

In this way, only the data required by the effect side MPU 92 at the start of the game is set in the start command, thereby reducing the data capacity of the start command transmitted from the main side MPU 72 to the effect side MPU 92. can be reduced. In addition, the process of extracting only the data required by the performance side MPU 92 at the start of the game from the data set in the start time command by the performance side MPU 92 receiving the start time command can be eliminated. This makes it possible to reduce the processing load of the effect-side MPU 92 when the command at start is received.

As shown in FIG. 79(a), the common data table 73f includes a third set range and a fourth set range, as well as a third exclusion range and a fourth exclusion range. The third set range and the fourth set range are address ranges in which the addresses of the storage areas of the main RAM 74 in which the data set in the termination command are stored are set. The third set range is the address range from "9105H" to "910EH", and the fourth set range is the address range from "9113H" to "911AH". The third exclusion range and the fourth exclusion range are address ranges in which addresses of storage areas of the main-side RAM 74 in which no data is set in the end command are set. The third exclusion range is the address range from "9101H" to "9104H", and the fourth exclusion range is the address range from "910FH" to "9112H".

As shown in FIG. 79(c), the end command includes addresses set in the third set range (“9105H” to “910EH”) and the fourth set range (“9113H” to “911AH”). A lower area of the continuous game number counter 74r, a higher area of the continued game number counter 74r, a lower area of the total winning number counter 74s, a higher area of the total winning number counter 74s, a top aggregation area 74v, and a gaming state. Data are set for the area 77, the game section area 76, the pseudo bonus continuation counter 74t, and the award number counter 74e. These data are data required by the effect side MPU 92 at the end of the game.

In this way, only the data required by the effect side MPU 92 at the end of the game is set in the end command, thereby reducing the data capacity of the end command transmitted from the main side MPU 72 to the effect side MPU 92. can be reduced. In addition, the process of extracting only the data required by the performance side MPU 92 at the end of the game out of the data set in the command at the end by the performance side MPU 92 receiving the command at the end can be made unnecessary. This makes it possible to reduce the processing load of the effect-side MPU 92 when receiving the end command.

FIG. 80(a) is an explanatory diagram for explaining the electrical configuration of the main control board 71 and the effect control board 91 for transmitting commands from the main side MPU 72 to the effect side MPU 92. FIG. As shown in FIG. 80(a), the effect side RAM 94 is provided with a top setting area 134. As shown in FIG. The highest level setting area 134 performs processing for setting the data of the 0th to 5th bits in the highest level aggregated frame SF set in the start time command or the end time command in the frame corresponding to the 0th to 5th bits. This is a storage area used for execution.

FIG. 80(b) is an explanatory diagram for explaining the configuration of the top setting area 134. As shown in FIG. As shown in FIG. 80(b), the highest setting area 134 is provided with first to eleventh areas RC1 to RC11. The first to eleventh areas RC1 to RC11 are storage areas consisting of 1 byte. The total data capacity of the first to eleventh areas RC1 to RCA11 in the highest setting area 134 is 11 bytes. In the effect-side RAM 94, the first to eleventh areas RC1 to RC11 of the highest setting area 134 are set in a continuous address range of "γ+1" to "γ+11".

As shown in FIG. 79(b), the start command consists of eight frames (first to eighth frames FR1 to FR8). The effect-side MPU 92 sets the first to eighth frames FR1 to FR8 of the received starting time command in the first to eighth areas RC1 to RC8 of the highest setting area . The second frame FR2 in which the data in the lower area of the AT continuation counter 74u in the main RAM 74 is set is set in the second area RC2, and the third frame FR3 in which the data in the upper area of the AT continuation counter 74u is set. The highest aggregated frame SF (fourth frame FR4) set in the third area RC3 and in which the data of the highest aggregated area 74v is set is set in the fourth area RC4. As already explained in the first embodiment, the data "0" or "1" stored in the most significant bit (seventh bit) of the lower area of the AT continuation counter 74u in the main RAM 74 is The "0" data set in the 0th bit of the frame SF and stored in the most significant bit of the upper area of the AT continuation counter 74u is set in the first bit of the highest aggregated frame SF. The effect-side MPU 92 sets the 0th bit data in the fourth area RC4 to the most significant bit of the second area RC2, and sets the 1st bit data in the fourth area RC4 to the most significant bit of the third area RC3. By setting, a post-conversion start command is generated. Then, the generated post-conversion start command is stored in the command storage buffer 126 . As a result, the effect-side MPU 92 can be put into a state in which the post-conversion start time command can be used.

As shown in FIG. 79(c), the end command consists of 11 frames (1st to 11th frames FR1 to FR11). The effect-side MPU 92 sets the first to eleventh frames FR1 to FR11 of the received termination command in the first to eleventh areas RC1 to RC11 of the highest setting area 134 . The second frame FR2 in which the data of the lower area of the continuous game number counter 74r in the main RAM 74 is set is set in the second area RC2, and the third frame in which the data of the upper area of the continuous game number counter 74r is set. FR3 is set in the third area RC3, and the fourth frame FR4 in which the data of the lower area of the total acquisition number counter 74s is set is set in the fourth area RC4, and the data of the upper area of the total acquisition number counter 74s is set. The fifth frame FR5 in which the data of the highest level aggregation area 74v is set is set in the fifth area RC5, and the highest level aggregated frame SF (sixth frame FR6) in which the data of the highest level aggregation area 74v is set is set in the sixth area RC6. As already explained in the first embodiment, the data "0" or "1" stored in the most significant bit (seventh bit) of the lower area of the continuous game number counter 74r in the main RAM 74 is the most significant bit. The data "0" stored in the most significant bit of the upper area of the number-of-continued-games counter 74r is set to the second bit of the aggregated frame SF, and is set to the third bit of the most significant aggregated frame SF. , the data "0" or "1" stored in the most significant bit of the lower area of the total acquired number counter 74s is set to the fourth bit of the highest aggregated frame SF, and the uppermost bit of the total acquired number counter 74s Data "0" stored in the most significant bit of the area is set to the fifth bit of the most significant aggregated frame SF. The effect-side MPU 92 sets the second bit data in the sixth area RC6 as the most significant bit of the second area RC2, and sets the third bit data in the sixth area RC6 as the most significant bit of the third area RC3. By setting the data of the 4th bit in the sixth area RC6 as the most significant bit of the fourth area RC4 and the data of the 5th bit in the sixth area RC6 as the most significant bit of the fifth area RC5, Generate command at end after conversion. Then, the generated post-conversion termination command is stored in the command storage buffer 126 . As a result, the effect-side MPU 92 can be put into a state in which the post-conversion termination command can be used.

Next, the common command transmission processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. As already described in the first embodiment, the common command transmission process is performed when the start command flag of the main RAM 74 is set to "1" in the command output process (FIG. 44) (step S2707: YES). , or when "1" is set in the end command flag of the main RAM 74 (step S2708: YES), it is executed in step S2709. As already described, when the game is started, the start command flag is set to "1" in step S1107 of the lottery result handling process (FIG. 25), and the end command flag is set to end the game. In this case, "1" is set in step S1508 of the corresponding processing (FIG. 32) at the end of the game.

In the common command transmission process, steps S4601 to S4605 are similar to steps S4401 to S4405 of the common command transmission process (FIG. 77) in the fourth embodiment. Specifically, first, the common data table 73f stored in the main-side ROM 73 is read (step S4601), and the top-level aggregation process is executed (step S4602). In the top-level aggregation process, as already described in the fourth embodiment with reference to the flowchart of FIG. The data of the most significant bit in the storage area of the master side RAM 74 grasped is set to the 0th to 5th bits of the most significant aggregation area 74v. The top-level aggregation process (step S4602) is executed both when the start command is transmitted and when the end command is transmitted.

As already explained, in the main side RAM 74, as storage areas in which the most significant bit data is set in the highest aggregation area 74v, the lower area and upper area of the AT continuation counter 74u, the lower area and upper area of the continuous game number counter 74r, and There is an upper area and an area below and above the total win counter 74s. Of the six storage areas, the storage area where data is set in the command at the start is the lower area and upper area of the AT continuation counter 74u, and the storage area where data is set in the command at the end is the number of continued games counter. 74r, and the lower and upper areas of the total win counter 74s. In this way, among the six storage areas for which the most significant bit data is aggregated in the highest aggregation area 74v, data is set in the storage area in which data is set in the command at the start and in the command at the end. In a configuration in which the storage areas are different, the most significant bit data in the six storage areas are aggregated into the highest aggregation area 74v in both cases of transmitting the command at the start and the command at the end. This is the configuration in which processing (the highest-level aggregation processing in step S4602) is executed. Therefore, when the start command is transmitted, the most significant bit data is set in the highest aggregation area 74v for only the storage area in which the data is set in the start command among the six storage areas. At the same time, when the termination command is to be transmitted, a process of setting the most significant bit data to the highest aggregation area 74v for only the storage area for which the data is set in the termination command among the six storage areas is executed. Compared with the configuration, the processing configuration of the processing for setting the most significant bit data in the most significant aggregation area 74v can be simplified.

After that, the value of the write pointer 113 (FIG. 45) in the transmission circuit 85 is grasped to grasp the write destination area in the transmission standby buffer 112 (step S4603). After that, if the starting command flag in the main RAM 74 is set to "1" (step S4604: YES), that is, if it is time to start the game, the starting command stored in the main ROM 73 is used. The data of the header HD indicating that there is data is set in the write destination area ascertained in step S4603 (step S4605). Thereafter, "9101H", which is the top address of the first set range ("9101H" to "9104H"), is set in the transfer source address counter 132 in the main RAM 74 (step S4606). As a result, the lower area of the AT continuation counter 74u in the main RAM 74 can be set as the transfer source storage area.

If "1" is not set in the start time command flag (step S4604: NO), the data of the header HD indicating the end time command stored in the main ROM 73 is grasped in step S4603. The area to be written is set (step S4607). Thereafter, "9105H", which is the top address of the third set range ("9105H" to "910EH"), is set in the transfer source address counter 132 in the main RAM 74 (step S4608). As a result, the lower area of the continuous game number counter 74r in the main RAM 74 can be set as the transfer source storage area.

When the process of step S4606 or step S4608 is performed, the value of the write pointer 113 is updated to update the value of the transmission standby buffer 112 as in step S4409 of the common command transmission process (FIG. 77) in the fourth embodiment. is updated (step S4609). In step S4609, the value of the write pointer 113 is incremented by 1, and when the value of the write pointer 113 after the increment of 1 exceeds the maximum value of "31", the write pointer 113 is cleared to "0".

After that, in steps S4610 to S4612, the same processing as steps S4012 to S4014 of the common command transmission processing (FIG. 77) in the fourth embodiment is executed. Specifically, first, the data in the transfer source storage area is transferred to the write destination area in the transmission standby buffer 112 (step S4610). In step S4610, the address of the transfer source storage area in the main RAM 74 is specified based on the data of the storage area corresponding to the address set in the transfer source address counter 132 in the common data table 73f. Thereafter, the most significant bit (seventh bit) in the write destination area is set to "0" (step S4611). As a result, when a command at start is transmitted, the value of the most significant bit of the second to seventh frames FR2 to FR7 of the command at start can be set to "0", and based on the value of the most significant bit header HD and the second to seventh frames FR2 to FR7. Further, when transmitting a termination command, the value of the most significant bit of the second to tenth frames FR2 to FR10 of the termination command can be set to "0", and based on the value of the most significant bit The header HD can be made identifiable from the second to tenth frames FR2 to FR10.

After that, as in step S4609, the value of the write pointer 113 is updated (step S4612). Specifically, 1 is added to the value of the write pointer 113, and when the value of the write pointer 113 after the addition of 1 exceeds the maximum value of "31", the write pointer 113 is cleared to "0". After that, by adding "2" to the value of the transfer source address counter 132, the address referred to for grasping the storage area of the transfer source in the common data table 73f is updated (step S4613). Thereby, the transfer source storage area in the main RAM 74 can be updated.

After that, if "1" is set in the start-time command flag of the main RAM 74 (step S4614: YES), the data in the transfer source address counter 132 is the first exclusion range ("9105H" to "910CH"). (step S4615). If the data of the transfer source address counter 132 is "9105H" (step S4615: YES), the transfer source address counter 132 stores "910DH", which is the leading address of the second set range ("910DH" to "9114H"). is set (step S4616). As a result, the transfer source storage area can be updated to the highest level aggregation area 74v. Also, it is possible to prevent the data stored in the storage area of the main RAM 74, which is grasped based on the address set in the first exclusion range of the common data table 73f, from being set in the start command. If the data of the transfer source address counter 132 is not "9105H" (step S4615: NO), the data of the transfer source address counter 132 is the start address of the second exclusion range ("9115H" to "911AH") 9115H" (step S4617).

If the process of step S4616 has been performed, or if a negative determination is made in step S4617, the process advances to step S4610, and the processes of steps S4610 to S4617 are repeatedly executed until an affirmative determination is made in step S4617. As a result, the data stored in the storage area of the main RAM 74 specified based on the addresses set in the first set range and the second set range of the common data table 73f can be set in the transmission standby buffer 112. can be done. Therefore, it is possible to set only the data required by the effect side MPU 92 in the transmission waiting buffer 112 at the start of the game.

If an affirmative determination is made in step S4617, that is, the data stored in the storage area of the main-side RAM 74 specified based on the addresses set in the first set range and the second set range are transferred to the transmission standby buffer 112. , the command flag at start of the main RAM 74 is cleared to "0" (step S4618).

If "1" is not set in the start-time command flag of the main RAM 74 (step S4614: NO), the data in the transfer source address counter 132 is the top of the fourth exclusion range ("910FH" to "9112H"). It is determined whether or not the address is "910FH" (step S4619). If the data of the transfer source address counter 132 is "910FH" (step S4619: YES), the transfer source address counter 132 stores "9113H", which is the top address of the fourth set range ("9113H" to "911AH"). is set (step S4620). As a result, the transfer source storage area can be updated to the gaming state area 77 . Also, it is possible to prevent the data stored in the storage area of the main RAM 74, which is grasped based on the address set in the fourth exclusion range of the common data table 73f, from being set in the end command. If the data of the transfer source address counter 132 is not "910FH" (step S4619: NO), it is determined whether or not the data of the transfer source address counter 132 is "911BH" (step S4621). "911BH" is the address next to "911AH" which is the last address of the fourth set range ("9113H" to "911AH").

If the process of step S4620 is performed, or if a negative determination is made in step S4621, the process proceeds to step S4610, and steps S4610 to S4614 and steps S4619 to S4621 are performed until an affirmative determination is made in step S4621. Execute the process repeatedly. As a result, the data stored in the storage area of the main RAM 74 specified based on the addresses set in the third set range and the fourth set range of the common data table 73f can be set in the transmission standby buffer 112. can be done. Therefore, it is possible to set only the data required by the effect side MPU 92 in the transmission waiting buffer 112 when the game ends.

If an affirmative determination is made in step S4621, that is, the data stored in the storage area of the main side RAM 74 specified based on the addresses set in the third set range and the fourth set range are transferred to the transmission standby buffer 112. , the end command flag in the main RAM 74 is cleared to "0" (step S4622).

If the processing of step S4618 or step S4622 has been performed, the same processing as steps S4417 to S4418 of the common command transmission processing (FIG. 77) in the fourth embodiment is executed in steps S4623 to S4624. . Specifically, the data of the footer FT stored in the main ROM 73 is set in the write destination area corresponding to the value of the write pointer 113 in the transmission standby buffer 112 (step S4623). After that, as in steps S4609 and S4612, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4624), and the common command transmission processing ends.

In this way, when transmitting the start time command or the end time command, first, the lower area and upper area of the AT continuation counter 74u, the lower area and upper area of the continuous game number counter 74r, and the lower area and upper area of the total winning number counter 74s The process of setting the highest bit data in the upper area to the 0th to 5th bits of the highest aggregation area 74v (the highest aggregation process in step S4602) is performed, and then the start command is transmitted. For example, at the start of the game, the data required by the production side MPU 92 is set in the transmission standby buffer 112, and in the case of transmitting a command at the time of termination, the data required by the production side MPU 92 is on standby for transmission at the end of the game. Set in buffer 112 . In the configuration in which only part of the storage area in which data is set in the start command in the main RAM 74 is shared with the storage area in which data is set in the end command, the lower area and upper area of the AT continuation counter 74u, A process of setting the most significant bit data in the lower area and upper area of the continuous game number counter 74r and the lower area and upper area of the total winning number counter 74s to the 0th to 5th bits of the highest aggregation area 74v (step The highest level aggregation processing in S4602) is executed using the same subroutine program. This reduces the data capacity of the program stored in the main ROM 73 for executing the process.

Next, the command reception handling process executed by the effect side MPU 92 will be described with reference to the flow chart of FIG. As already explained in the first embodiment, the command reception handling process is repeatedly executed by the effect-side MPU 92 in a relatively short period (for example, a period of 4 milliseconds).

In the command reception handling process, in steps S4701 to S4707, the same processes as steps S3001 to S3007 of the command reception handling process (FIG. 52) in the first embodiment are executed. Specifically, when the data of the header HD and the data of the footer FT are set in the waiting buffer 122 after reception of the receiving circuit 87 (step S4701: YES, step S4702: YES), The head and tail of the command to be moved to the top setting area 134 of the RAM 94 or the command storage buffer 126 (command to be moved) are grasped (step S4703). In step S4703, the head of the command to be moved is grasped based on the value of the read pointer 128 in the waiting buffer 122 after reception, and the tail of the command to be moved is grasped based on the data of the footer FT of the command to be moved. Grasp. When a plurality of commands are stored in the post-reception standby buffer 122, based on the value of the read pointer 128, the first command among the plurality of commands stored in the post-reception standby buffer 122 is the command to be moved. becomes. After that, if the command to be moved ascertained in step S4703 has the data of the header HD of the command at start (step S4704: YES), it means that the command to be moved is the command at start. Therefore, the start reception correspondence table is read from the effect side ROM 93 (step S4705). On the other hand, if the command to be moved ascertained in step S4703 has the data of the header HD of the end command set (step S4704: NO, step S4706: YES), the command to be moved is the end command. Since it means that there is, the reception correspondence table at the end is read from the production side ROM 93 (step S4707).

If the process of step S4705 or step S4707 has been performed, the top setting process is executed (step S4708). FIG. 83 is a flow chart showing the highest level setting process (step S4708) executed by the MPU 92 on the effect side.

In the highest setting process, first, the start time command or the end time command stored in the waiting buffer 122 after reception is set in the highest setting area 134 in the effect side RAM 94 (step S4801). In step S4801, if a start command is stored in the post-reception waiting buffer 122, the first to eighth frames FR1 to FR8 of the start command are transferred to the first to eighth areas RC1 of the top setting area . . . . RC8, and when a termination command is stored in the waiting buffer 122 after reception, the 1st to 11th frames FR1 to FR11 of the termination command are set to the 1st to 11th frames FR1 to FR11 of the highest level setting area 134. 11 areas RC1 to RC11.

After that, the post-reception standby buffer 122 is cleared (step S4802). In the clear processing, the area in which the command at the start or the command at the end was stored in the standby buffer 122 after reception is cleared to "0". As a result, an empty area for storing the next command can be secured in the waiting buffer 122 after reception. After that, the value of the read pointer 128 in the standby buffer 122 after reception is updated to the value corresponding to the storage area next to the storage area in which the last command (data of the footer FT) of the start command or end command was stored. (Step S4803).

After that, if the command set in the highest setting area 134 in step S4801 is the start command (step S4804: YES), the address of the fourth area RC4 in the highest setting area 134 is transferred to the effect side RAM 94. The original counter is set (step S4805). As already explained, the fourth area RC4 is an area in which the highest aggregated frame SF of the start command is set. As already described in the first embodiment, the effect-side transfer source counter is a counter that enables the effect-side MPU 92 to grasp the storage area of the data transfer source. By setting the address of the fourth area RC4 in the effect side transfer source counter in step S4805, the fourth area RC4 can be set as the transfer source storage area.

Thereafter, the effect side bit designation counter in the effect side RAM 94 is cleared to "0" (step S4806). As already described in the first embodiment, the effect side bit designation counter is a counter that enables the effect side MPU 92 to grasp the transfer source bit in the transfer source storage area. By clearing the value of the effect side bit designation counter to "0" in step S4806, the 0th bit in the fourth area RC4 can be set as the transfer source bit.

As described above, the top-level setting process is a process that is executed when the start-time command or the end-time command is set in the top-level setting area 134 . If a negative determination is made in step S4804, it means that the command set in the highest level setting area 134 in step S4801 is the end command. The address ("γ+6") is set in the effect side transfer source counter of the effect side RAM 94 (step S4807). As a result, the sixth area RC6 becomes the transfer source storage area. As already explained, the sixth area RC6 is an area in which the highest aggregated frame SF (sixth frame FR6) of the termination command is set. Thereafter, "2" is set in the effect side bit designation counter of the effect side RAM 94 (step S4808). Thereby, the second bit of the sixth area RC6 can be set as the transfer source bit.

After performing the process of step S4806 or step S4808, the address of the second area RC2 in the highest setting area 134 is set to the effect side transfer destination counter in the effect side RAM 94 (step S4809). As already explained in the first embodiment, the effect-side transfer destination counter is a counter that enables the effect-side MPU 92 to grasp the transfer destination storage area. By setting the address of the second area RC2 in the effect-side transfer destination counter in step S4809, the second area RC2 can be used as the transfer destination storage area.

After that, the data "0" or "1" stored in the transfer source bit is set as the most significant bit in the transfer destination storage area (step S4810). After that, based on the value of the rendering-side bit designation counter, it is determined whether or not the process of setting the data aggregated in the highest aggregated frame SF to the highest bit of the corresponding frame has ended (step S4811). In step S4811, if the start time command is set in the highest setting area 134, affirmative determination is made if the value of the effect side bit designation counter is "1", and the end time command is set in the highest setting area 134. If the command is set and the value of the performance side bit designation counter is "5", affirmative determination is made.

If a negative determination is made in step S4811, the transfer source bit in the transfer source storage area (fourth area RC4 or sixth area RC6) is updated by adding 1 to the value of the effect side bit designation counter. (Step S4812). The processing of steps S4810 to S4813 is repeatedly executed until an affirmative determination is made in step S4811. In step S4812, when the start command is set in the highest setting area 134, the transfer source bits in the fourth area RC4 are updated in the order of 0th bit→1st bit, and the highest setting area 134 is updated. When the command at the time of termination is set in the area 134, the transfer source bits in the sixth area RC6 are updated in the order of the 2nd bit→the 3rd bit→the 4th bit→the 5th bit.

After that, by adding 1 to the effect-side transfer destination counter, the transfer destination storage area is updated (step S4813). In step S4813, if the start command is set in the highest setting area 134, the transfer destination storage areas in the highest setting area 134 are updated in the order of the second area RC2→the third area RC3. At the same time, when the end command is set in the highest setting area 134, the transfer in the highest setting area 134 is performed in the order of the second area RC2→third area RC3→fourth area RC4→fifth area RC5. The previous storage area is updated.

After that, the process proceeds to step S4810, and the processes of steps S4810 to S4813 are repeatedly executed until an affirmative determination is made in step S4811. As a result, when the command set in the highest level setting area 134 in step S4801 is the start command, the state in which the post-conversion start time command is set in the highest level setting area 134 can be achieved. If the command set in the highest level setting area 134 in S4801 is the end time command, the state in which the post-conversion end time command is set in the highest level setting area 134 can be set. If an affirmative determination is made in step S4811, the highest setting processing is terminated.

As described above, the data stored in the lower area and upper area of the AT continuation counter 74u are set in the consecutive second to third frames FR2 to FR3 in the start command. Therefore, by repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S4813), the storage area of the transfer destination in which the data aggregated in the highest aggregate frame SF is set is sequentially updated. can do. As a result, the effect-side MPU 92 converts the data aggregated into the 0th to 1st bits in the highest aggregated frame SF of the start command into the 2nd to 3rd frames FR2 to FR3 corresponding to the 0th to 1st bits. It is possible to simplify the processing configuration of the processing for setting the most significant bit. In addition, the data stored in the lower and upper areas of the continuous game number counter 74r and the lower and upper areas of the total winning number counter 74s are stored in consecutive second to fifth frames FR2 to FR5 in the end command. set. Therefore, by repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S4813), the storage area of the transfer destination in which the data aggregated in the highest aggregate frame SF is set is sequentially updated. can do. As a result, the effect-side MPU 92 converts the data aggregated into the 2nd to 5th bits in the highest aggregated frame SF of the end command into the 2nd to 5th frames FR2 to FR5 corresponding to the 2nd to 5th bits. It is possible to simplify the processing configuration of the processing for setting the most significant bit.

Returning to the description of the command reception handling process (FIG. 82), after performing the highest level setting process in step S4708, in steps S4709 to S4714, the steps of the command reception handling process (FIG. 52) in the first embodiment. Processing similar to that of steps S3010 to S3015 is performed. Specifically, the area of the write destination in the command storage buffer 126 is grasped by grasping the value of the second write pointer 129 (FIG. 80(a)) in the effect-side RAM 94 (step S4709). Thereafter, the post-conversion start time command or the post-conversion end time command stored in the highest setting area 134 is set in the write destination area grasped in step S4709 (step S4710). As a result, the post-conversion start time command or the post-conversion end time command is stored in the command storage buffer 126, and the effect side MPU 92 can use the post-conversion start time command or the post-conversion end time command. can do.

After that, the value of the second write pointer 129 is updated (step S4711). In step S4711, when the data of the post-conversion start command is written in the command storage buffer 126 in step S4710, the value of the second write pointer 129 is incremented by "8", which is the data capacity of the post-conversion start command. If the data of the post-conversion end command is written in the command storage buffer 126 in step S4710, the value of the second write pointer 129 is incremented by "11", which is the data capacity of the post-conversion end command. In step S4711, when the calculation result of the calculation for adding "8" or "11" exceeds the maximum value "63", a value smaller than the calculation result by "64" is set in the second write pointer 129. be in a state where For example, if the calculation result of adding "8" or "11" is "64" exceeding the maximum value "63", "0" is "64" less than the calculation result ("64"). is set in the second write pointer 129 .

After that, if the command stored in the command storage buffer 126 in step S4710 is the post-conversion start time command (step S4712: YES), the start time reception flag of the production side RAM 94 is set to "1" (step S4713). . As a result, the effect-side MPU 92 can grasp that the start command has been received. On the other hand, if the command stored in the command storage buffer 126 in step S4710 is not the post-conversion start command (step S4712: NO), that is, the command stored in the command storage buffer 126 in step S4710 is the post-conversion end command. If there is, "1" is set to the completion reception flag of the effect side RAM 94 (step S4714). As a result, the MPU 92 on the production side can grasp that the end command has been received. If the process of step S4713 or step S4714 has been performed, the first to eleventh areas RC1 to RC11 of the highest setting area 134 are cleared to "0" (step S4715), and this command reception handling process ends.

If a negative determination is made in step S4706, steps S4716 to S4723 execute the same processes as steps S3017 to S3024 of the command reception handling process (FIG. 52) in the first embodiment. Specifically, when the data of the header HD indicating the winning result command is stored in the wait buffer 122 after reception (step S4716: YES), the value of the second write pointer 129 in the effect side RAM 94 is grasped. As a result, the write destination area in the command storage buffer 126 is grasped (step S4717), and the winning result command stored in the waiting buffer 122 after reception is set in the write destination area grasped in step S4717 (step S4718). . As a result, the winning result command is stored in the command storage buffer 126, so that the effecting MPU 92 can use the winning result command.

After that, the value of the second write pointer 129 is updated (step S4719). In step S4719, the value of the second write pointer 129 is added to the data capacity of the winning result command written in the command storage buffer 126 in step S4718. In step S4719, when the calculation result of the calculation for adding "5" exceeds the maximum value "63", the second write pointer 129 is set to a value "64" smaller than the calculation result. . For example, when the calculation result of adding "5" is "64" which exceeds the maximum value "63", "0" which is "64" smaller than the calculation result ("64") is the second write. It is assumed that the pointer 129 is set.

After that, the post-reception standby buffer 122 is cleared (step S4720). In the clearing process of the post-reception standby buffer 122 in step S4720, the area in which the winning result command was stored in the post-reception standby buffer 122 is cleared to "0". As a result, an empty area for storing the next command can be secured in the waiting buffer 122 after reception. After that, the value of the read pointer 128 in the waiting buffer 122 after reception is updated to the value corresponding to the area next to the area in which the end of the winning result command (data of the footer FT) was stored (step S4721). The winning result reception flag in the side RAM 94 is set to "1" (step S4722), and this command reception handling process is terminated. When the winning result reception flag is set to "1" in step S4722, the processes after step S3402 are executed in the winning result reception handling process (FIG. 56).

If a negative determination is made in step S4716, other command reception handling processing is executed (step S4723), and this command reception handling processing ends. In the other command reception processing in step S4723, first, by grasping the value of the second write pointer 129 in the effect-side RAM 94, the write destination area in the command storage buffer 126 is grasped. In step S4703, the comprehended command (for example, power recovery command) is set as the command to be moved. After that, similarly to steps S4711 and S4719, the value of the second write pointer 129 is updated. After that, the area in which the command to be moved was stored in the waiting buffer 122 after reception is cleared to "0". As a result, an empty area for storing the next command can be secured in the waiting buffer 122 after reception. After that, the value of the read pointer 128 in the waiting buffer 122 after reception is updated to the value corresponding to the area next to the area in which the end of the command to be moved (data of the footer FT) was stored.

According to this embodiment detailed above, the following excellent effects are obtained.

A first set range and a second set range are set in the common data table 73f, and a first exclusion range and a second exclusion range are set. Data stored in a storage area grasped based on the addresses set in the first set range and the second set range are set in the command at the start, while the first exclusion range and the second exclusion range are set in the start command. The data stored in the storage area recognized based on the address set in is not set. As a result, it is possible to set only the data required by the effect-side MPU 92 at the start of the game in the start command.

Only the data required by the effect side MPU 92 at the start of the game is set in the command at the time of start, so that the data capacity of the command at the time of start transmitted from the main side MPU 72 to the effect side MPU 92 can be reduced. can. In addition, the process of extracting only the data required by the performance side MPU 92 at the start of the game from the data set in the start time command by the performance side MPU 92 receiving the start time command can be eliminated. This makes it possible to reduce the processing load of the effect-side MPU 92 when the command at start is received.

A third set range and a fourth set range are set in the common data table 73f, and a third exclusion range and a fourth exclusion range are set. Data stored in the storage area grasped based on the addresses set in the third set range and the fourth set range are set in the end command, while the third exclusion range and the fourth exclusion range are set in the end command. The data stored in the storage area recognized based on the address set in is not set. As a result, it is possible to set only the data required by the effect-side MPU 92 when the game ends in the end command.

Only the data required by the effect side MPU 92 at the end of the game is set in the end command, so that the data volume of the end command transmitted from the main side MPU 72 to the effect side MPU 92 can be reduced. can. In addition, the process of extracting only the data required by the performance side MPU 92 at the end of the game out of the data set in the command at the end by the performance side MPU 92 receiving the command at the end can be made unnecessary. This makes it possible to reduce the processing load of the effect-side MPU 92 when receiving the end command.

In the main side RAM 74, as storage areas in which the data of the highest bit is set in the highest aggregation area 74v, the lower area and upper area of the AT continuation counter 74u, the lower area and upper area of the continuous game number counter 74r, and the total There are a lower area and a higher area of the acquisition number counter 74s. Of the six storage areas, the storage area where data is set in the command at the start is the lower area and upper area of the AT continuation counter 74u, and the storage area where data is set in the command at the end is the number of continued games counter. 74r, and the lower and upper areas of the total win counter 74s. In this way, among the six storage areas for which the most significant bit data is aggregated in the highest aggregation area 74v, data is set in the storage area in which data is set in the command at the start and in the command at the end. In a configuration in which the storage areas are different, the most significant bit data in the six storage areas are aggregated into the highest aggregation area 74v in both cases of transmitting the command at the start and the command at the end. This is the configuration in which processing (the highest-level aggregation processing in step S4602) is executed. Therefore, when the start command is transmitted, the most significant bit data is set in the highest aggregation area 74v for only the storage area in which the data is set in the start command among the six storage areas. At the same time, when the termination command is to be transmitted, a process of setting the most significant bit data to the highest aggregation area 74v for only the storage area for which the data is set in the termination command among the six storage areas is executed. Compared with the configuration, the processing configuration of the processing for setting the most significant bit data in the most significant aggregation area 74v can be simplified.

When transmitting the start time command or end time command, first, the lower area and upper area of the AT continuation counter 74u, the lower area and upper area of the continuous game number counter 74r, and the lower area and upper area of the total winning number counter 74s. The processing of setting the data of the upper bits to the 0th to 5th bits of the highest aggregation area 74v (the highest aggregation processing in step S4602) is performed, and after that, if the start command is to be transmitted, the game starts. The data required by the production side MPU 92 are set in the transmission standby buffer 112 at the time, and the data required by the production side MPU 92 at the end of the game are set in the transmission standby buffer 112 in the case of transmitting a command at the end of the game. do. In the configuration in which only part of the storage area in which data is set in the start command in the main RAM 74 is shared with the storage area in which data is set in the end command, the lower area and upper area of the AT continuation counter 74u, A process of setting the most significant bit data in the lower area and upper area of the continuous game number counter 74r and the lower area and upper area of the total winning number counter 74s to the 0th to 5th bits of the highest aggregation area 74v (step The highest level aggregation processing in S4602) is executed using the same subroutine program. This reduces the data capacity of the program stored in the main ROM 73 for executing the process.

The data stored in the lower area and upper area of the AT continuation counter 74u are set in the consecutive second to third frames FR2 to FR3 in the start command. Therefore, by repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S4813), the storage area of the transfer destination in which the data aggregated in the highest aggregate frame SF is set is sequentially updated. can do. As a result, the effect-side MPU 92 converts the data aggregated into the 0th to 1st bits in the highest aggregated frame SF of the start command into the 2nd to 3rd frames FR2 to FR3 corresponding to the 0th to 1st bits. It is possible to simplify the processing configuration of the processing for setting the most significant bit. In addition, the data stored in the lower area and upper area of the continuous game number counter 74r and the lower area and upper area of the total winning number counter 74s are stored in consecutive second to fifth frames FR2 to FR5 in the end command. set. Therefore, by repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S4813), the storage area of the transfer destination in which the data aggregated in the highest aggregate frame SF is set is sequentially updated. can do. As a result, the effect-side MPU 92 converts the data aggregated into the 2nd to 5th bits in the highest aggregated frame SF of the end command into the 2nd to 5th frames FR2 to FR5 corresponding to the 2nd to 5th bits. It is possible to simplify the processing configuration of the processing for setting the most significant bit.

<Sixth embodiment>
This embodiment differs from the above-described fifth embodiment in the configuration of a common data table 73g that is referred to when transmitting the command at the start and the command at the end. The configuration different from that of the fifth embodiment will be described below. Note that the description of the same configuration as that of the fifth embodiment is basically omitted.

The common data table 73g is stored in the main ROM73. FIG. 84(a) is an explanatory diagram for explaining the configuration of the common data table 73g. As shown in FIG. 84(a), the common data table 73g is set in the continuous address range of "9101H" to "911AH" in the main ROM 73. As shown in FIG.

In the common data table 73g, the 11th setting range is set in the continuous address range of "9101H" to "910CH", and the 12th setting range is set in the continuous address range of "9109H" to "911AH". It is In the eleventh setting range, the addresses of a plurality of (specifically, six) storage areas in which data is set in the command at the time of start are set among the large number of 1-byte storage areas provided in the main RAM 74 . In addition, in the twelfth set range, addresses of a plurality of (specifically, nine) storage areas in which data is set in the command at the time of termination out of a large number of 1-byte storage areas provided in the main RAM 74 are stored. is set.

The storage areas in the main RAM 74 in which data is set in the command at the start are, as in the first embodiment, the lower area and upper area of the AT continuation counter 74u, the bet number setting counter 74b, the stop order type counter 74m, These are the gaming state area 77 and the top-level aggregation area 74v, and addresses for specifying these six storage areas are set in the eleventh set range. Hereinafter, the six storage areas are also referred to as "storage areas of the main-side RAM 74 included in the eleventh set range".

The storage areas in the main RAM 74 in which the data is set in the command at the time of termination are the game state area 77, the highest aggregation area 74v, the lower area and upper area of the continuous game number counter 74r, as in the first embodiment. , the lower and upper areas of the total winning number counter 74s, the game section area 76, the pseudo-bonus continuation counter 74t, and the awarding number counter 74e. is set. Hereinafter, the nine storage areas are also referred to as "storage areas of the main RAM 74 included in the twelfth set range".

Of the six storage areas in the main RAM 74 in which data is set in the command at the start, the gaming state area 77 and the top-level aggregation area 74v are also storage areas in which data is set in the command at the end. In this way, in the main RAM 74, only a part of the plurality of storage areas in which data is set in the start command overlaps with the plurality of storage areas in which data is set in the end command.

As already explained in the first embodiment, the lower area of the AT continuation counter 74u, the lower area of the continuous game number counter 74r, and the lower area of the total winning number counter 74s are the most significant bits (in the 0th to 7th bits). 7th bit) is a storage area in which "1" can be set. As shown in FIG. 84(a), in the 11th set range of the common data table 73g, the first aggregation range is set in the continuous address range of "9101H" to "9104H". In the first aggregation range, an AT continuation counter in which the data stored in the most significant bit of the six storage areas in which the data is set in the start command in the main RAM 74 is aggregated in the highest aggregation area 74v. The addresses of the lower area and upper area of 74u are set. The most significant bit data in the lower area of the AT continuation counter 74u is set to the 0th bit of the highest aggregation area 74v, and the most significant bit data in the upper area of the AT continuation counter 74u is set to the highest aggregation area 74v. is set to the first bit of Below, the lower area and upper area of the AT continuation counter 74u specified based on the address of the main side RAM 74 set in the first aggregation range are referred to as "storage areas of the main side RAM 74 included in the first aggregation range. ” is also called.

A second aggregation range is set in the continuous address range of "910DH" to "9114H" in the twelfth set range of the common data table 73g. The second aggregation range includes the number of continuous games in which the data stored in the most significant bit of the nine storage areas in which the data is set in the end command in the main RAM 74 is aggregated in the highest aggregation area 74v. The addresses of the lower area and upper area of the counter 74r and the lower area and upper area of the total acquisition number counter 74s are set. The most significant bit data in the lower area of the continuous game number counter 74r is set to the 0th bit of the highest aggregation area 74v, and the most significant bit data in the upper area of the continuous game number counter 74r is set to the highest aggregation area. Set to the first bit of area 74v. The most significant bit data in the lower area of the total acquisition number counter 74s is set to the second bit of the highest aggregation area 74v, and the most significant bit data in the upper area of the total acquisition number counter 74s is set to the highest bit. It is set in the third bit of the aggregation area 74v. Below, the lower area and upper area of the continuous game number counter 74r and the lower area and upper area of the total winning number counter 74s, which are specified based on the address of the main side RAM 74 set in the second aggregation range, will be referred to as the "second 2 storage area of the main side RAM 74 included in the aggregation range".

FIG. 84(b) is an explanatory diagram for explaining the data configuration of the start command, and FIG. 84(c) is an explanatory diagram for explaining the data configuration of the end command. As shown in FIG. 84(b), the command at the start includes the lower area of the AT continuation counter 74u, which is grasped based on the addresses set in the eleventh setting range ("9101H" to "910CH"), the AT Data are set for the upper area of the continuation counter 74u, the bet number setting counter 74b, the stop order type counter 74m, the gaming state area 77, and the top aggregate area 74v. These data are data required by the effect side MPU 92 at the start of the game. In this way, only the data required by the effect side MPU 92 at the start of the game is set in the start time command, thereby reducing the data capacity of the start time command transmitted from the main side MPU 72 to the effect side MPU 92. can be reduced. In addition, the process of extracting only the data required by the performance side MPU 92 at the start of the game from the data set in the start time command by the performance side MPU 92 receiving the start time command can be eliminated. This makes it possible to reduce the processing load of the effect-side MPU 92 when the start command is received.

As shown in FIG. 84(c), the end command includes a game state area 77 grasped based on the address set in the twelfth setting range ("9109H" to "911AH"), area 74v, lower area of continued game number counter 74r, higher area of continued game number counter 74r, lower area of total winning number counter 74s, upper area of total winning number counter 74s, game zone area 76, pseudo bonus continuation counter 74t, and The data of the grant number counter 74e is set. These data are data required by the effect side MPU 92 at the end of the game. In this way, by setting only the data required by the effect side MPU 92 at the end of the game in the end command, the data capacity of the end command transmitted from the main side MPU 72 to the effect side MPU 92 can be reduced. can be reduced. In addition, the process of extracting only the data required by the performance side MPU 92 at the end of the game out of the data set in the command at the end by the performance side MPU 92 receiving the command at the end can be eliminated. This makes it possible to reduce the processing load of the effect-side MPU 92 when the end command is received.

As in the fifth embodiment, the start command consists of eight frames (first to eighth frames FR1 to FR8). The effect side MPU 92 sets the first to eighth frames FR1 to FR8 of the received starting time command in the first to eighth areas RC1 to RC8 of the highest setting area 134 in the effect side RAM 94 . As shown in FIG. 84(b), the second frame FR2 in which the data in the lower area of the AT continuation counter 74u in the main RAM 74 is set is set in the second area RC2, and the data in the upper area of the AT continuation counter 74u is set in the second area RC2. is set in the third area RC3, and the highest aggregated frame SF (seventh frame FR7) in which the data of the highest aggregated area 74v is set is set in the seventh area RC7. be. As described above, the data stored in the most significant bit of the lower area of the AT continuation counter 74u in the main RAM 74 is set to the 0th bit of the highest aggregated frame SF, and the data stored in the upper area of the AT continuation counter 74u. The data stored in the most significant bit is set in the first bit of the most significant aggregated frame SF. The effect-side MPU 92 sets the 0th bit data in the seventh area RC7 as the most significant bit of the second area RC2, and sets the 1st bit data in the seventh area RC7 as the most significant bit of the third area RC3. By setting, a post-conversion start command is generated. Then, the generated post-conversion start command is stored in the command storage buffer 126 . As a result, the effect-side MPU 92 can be put into a state in which the post-conversion start time command can be used.

As in the fifth embodiment, the termination command consists of 11 frames (1st to 11th frames FR1 to FR11). The effect-side MPU 92 sets the first to eleventh frames FR1 to FR11 of the received termination command in the first to eleventh areas RC1 to RC11 of the highest setting area 134 . As shown in FIG. 84(c), the highest aggregated frame SF (third frame FR3) in which the data of the highest aggregated area 74v in the main RAM 74 is set is set in the third area RC3, and the number of continuous games is The fourth frame FR4 in which the data of the lower area of the counter 74r is set is set in the fourth area RC4, and the fifth frame FR5 in which the data of the upper area of the continuous game number counter 74r is set is set in the fifth area RC5. The sixth frame FR6, in which the lower area data of the total acquisition number counter 74s is set, is set in the sixth area RC6, and the seventh frame FR7, in which the upper area data of the total acquisition number counter 74s is set. is set in the seventh area RC7. As described above, the data stored in the most significant bit of the lower area of the number-of-continued-games counter 74r is set to the 0th bit of the most significant aggregated frame SF, and the most significant bit of the upper area of the number-of-continued-games counter 74r is set to the first bit of the highest aggregated frame SF, and the data stored in the highest bit of the lower area of the total acquisition number counter 74s is set to the second bit of the highest aggregated frame SF. The data stored in the highest bit of the upper area of the total acquisition number counter 74s is set in the third bit of the highest aggregated frame SF. The effect-side MPU 92 sets the 0th bit data in the third area RC3 as the most significant bit of the fourth area RC4, and sets the 1st bit data in the third area RC3 as the most significant bit of the fifth area RC5. By setting the second bit data in the third area RC3 as the most significant bit of the sixth area RC6 and setting the third bit data in the third area RC3 as the most significant bit of the seventh area RC7, Generate command at end after conversion. Then, the generated post-conversion termination command is stored in the command storage buffer 126 . As a result, the effect-side MPU 92 can be put into a state in which the post-conversion termination command can be used.

FIG. 85 is an explanatory diagram for explaining the structure of the main side RAM 74. As shown in FIG. The main RAM 74 is provided with a transfer destination counter 115, a bit designation counter 117, and a transfer source address counter 132, as in the fifth embodiment. A counter 114 is provided. As already described in the first embodiment, the transfer count counter 114 counts the number of times the data stored in the storage area included in the transfer target range in the common command transmission process is transferred to the transmission standby buffer 112, and A 1-byte counter that enables the main MPU 72 to grasp the number of times the data stored in the most significant bit of the storage area included in the transfer target range in the highest-level aggregation process is transferred to the highest-level aggregation area 74v. is.

In this embodiment, when the start command is transmitted, the transfer target range in the common command transmission process is the 11th set range, and the transfer target range in the highest level aggregation process is the first aggregation range. Further, when the end command is transmitted, the transfer target range in the common command transmission process is the twelfth setting range, and the transfer target range in the highest aggregation process is the second aggregation range.

Next, the common command transmission processing executed by the main MPU 72 will be described with reference to the flow chart of FIG. As already described in the first embodiment, the common command transmission process is performed when the start command flag of the main RAM 74 is set to "1" in the command output process (FIG. 44) (step S2707: YES). , or when "1" is set in the end command flag of the main RAM 74 (step S2708: YES), it is executed in step S2709.

In the common command transmission process, first, the common data table 73g stored in the main-side ROM 73 is read (step S4901), and the highest level aggregation process is executed (step S4902). FIG. 87 is a flow chart showing the highest level aggregation processing.

In the highest level aggregation process, the same processes as steps S4501 to S4503 of the highest level aggregation process (FIG. 78) in the fourth embodiment are executed in steps S5001 to S5003. Specifically, the address of the highest level aggregation area 74v in the main RAM 74 is set in the transfer destination counter 115 of the main RAM 74 (step S5001). As a result, the top-level aggregation area 74v can be set as the transfer destination storage area. After that, the highest level aggregation area 74v is cleared to "0" (step S5002), and the value of the bit designation counter 117 in the main side RAM 74 is cleared to "0" (step S5003). As a result, the 0th bit of the top-level aggregation area 74v can be set as the transfer destination bit.

After that, if "1" is set in the starting command flag of the main RAM 74 (step S5004: YES), that is, if the starting command is to be transmitted, the first aggregation range ("9101H" to "9104H" ) is set in the transfer source address counter 132 (step S5005). Thus, based on the addresses set in the address range of "9101H" to "9102H" in the common data table 73g, it is possible to recognize the lower area of the AT continuation counter 74u as the transfer source storage area. Thereafter, the number of storage areas of the main RAM 74 included in the first aggregation range, ie, "2" is set as the number of transfers in the transfer counter 114 of the main RAM 74 (step S5006).

On the other hand, if the starting command flag of the main RAM 74 is not set to "1" (step S5004: NO), that is, if the ending command is to be transmitted, the second aggregation range ("910DH" to "9114H" ) is set in the transfer source address counter 132 (step S5007). As a result, based on the addresses set in the address range of "910DH" to "910EH" in the common data table 73g, it is possible to grasp the lower area of the continuous game number counter 74r as the transfer source storage area. Thereafter, "4", which is the number of storage areas of the main RAM 74 included in the second aggregation range, is set in the transfer number counter 114 as the number of transfers (step S5008).

After the processing of step S5006 or step S5008 is performed, the data of the most significant bit in the storage area of the transfer source is transferred to the (step S5009). In step S5009, based on the data of the storage area corresponding to the address set in the transfer source address counter 132 in the common data table 73g, the address of the transfer source storage area in the main RAM 74 is identified, and the transfer destination counter 115 and the value of the bit designation counter 117, the transfer destination bit is specified. Thereafter, 1 is subtracted from the value of the transfer number counter 114 (step S5010), and it is determined whether or not the value of the transfer number counter 114 after the subtraction of 1 is "0" (step S5011).

If a negative determination is made in step S5011, the transfer source storage area is updated by adding 2 to the value of the transfer source address counter 132 (step S5012). The processing of steps S5009 to S5013 is processing that is repeatedly executed until an affirmative determination is made in step S5011. In step S5012, the addresses stored in the transfer source address counter 132 are updated in the order of "9101H" to "9103H" when the start command is transmitted, and "910DH" when the end command is transmitted. ” → “910FH” → “9111H” → “9113H”, the addresses stored in the transfer source address counter 132 are updated.

After that, the value of the bit designation counter 117 is incremented by 1 to update the transfer destination bit in the highest aggregation area 74v (step S5013). In step S5013, the transfer destination bit in the highest aggregation area 74v is updated in the order of the 0th bit→the 1st bit when the command at the start is transmitted, and the 0th bit is updated when the command at the end is transmitted. The transfer destination bits in the highest aggregation area 74v are updated in the order of →first bit→second bit→third bit.

Thereafter, the process proceeds to step S5009, and the processes of steps S5009 to S5013 are repeatedly executed until an affirmative determination is made in step S5011. As a result, when a start command is transmitted, the data stored in the most significant bit of the storage area of the main side RAM 74 included in the first aggregation range is transferred to the 0th to 1st of the highest aggregation area 74v. When a termination command is transmitted, the data stored in the most significant bit of the storage area of the main side RAM 74 included in the second aggregation range is transferred to the highest aggregation area 74v. can be set to the 0th to 3rd bits of If an affirmative determination is made in step S5011, this top-level aggregation processing ends.

As described above, in the common data table 73g, the first aggregation range is set to the continuous address range of "9101H" to "9104H". Therefore, by repeatedly executing the process of adding 2 to the value of the transfer source address counter 132 (the process of step S5012), the transfer source storage area can be sequentially updated. Also, the second aggregation range is set to a continuous address range of "910DH" to "9114H". Therefore, by repeatedly executing the process of adding 2 to the value of the transfer source address counter 132 (the process of step S5012), the transfer source storage area can be sequentially updated. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the first aggregation range is a continuous address range, the start address (“9101H”) of the first aggregation range is set in the transfer source address counter 132 in step S5005, and the address included in the first aggregation range is set in step S5006. The first aggregation range can be specified by setting the number of storage areas (“2”) of the main-side RAM 74 in the transfer count counter 114 . This simplifies the processing configuration for designating the first aggregation range. Since the second aggregation range is a continuous address range, the start address ("910DH") of the second aggregation range is set in the transfer source address counter 132 in step S5007, and the second aggregation range is set in step S5008. The second aggregation range can be specified by setting the number of storage areas (“4”) of the main RAM 74 included in the transfer number counter 114 . This simplifies the processing configuration for designating the second aggregation range.

As a command in which the data stored in the most significant bit is aggregated, the command at the start and the command at the start are the storage areas of the main RAM 74 where the data stored in the most significant bit are aggregated. There are different commands on exit. By changing the start address of the transfer target range (first aggregation range or second aggregation range) and information on the number of transfers in the highest-level aggregation process according to the type of command to be sent, the common highest-level aggregation process can be performed. When a command at the start is transmitted, the data stored in the most significant bit of the storage area of the main side RAM 74 included in the first aggregation range can be aggregated into the highest aggregation area 74v. In addition, when a termination command is transmitted, the data stored in the highest bit of the storage area of the main side RAM 74 included in the second aggregation range can be aggregated in the highest aggregation area 74v. . For this reason, the data stored in the most significant bit is aggregated when the end command is transmitted as a separate process from the process of aggregating the data stored in the most significant bit when the command at start is transmitted. Compared to a configuration in which a process for collecting data is provided, the data capacity of the program stored in the main ROM 73 can be reduced in order to execute the process of aggregating the data stored in the most significant bit.

Returning to the description of the common command transmission processing (FIG. 86), after executing the top-level aggregation processing in step S4902, the common command transmission processing (FIG. 81) in the fifth embodiment is executed in steps S4903 to S4905. The same processing as steps S4603 to S4605 is executed. Specifically, the write destination area in the transmission standby buffer 112 is grasped by grasping the value of the write pointer 113 in the transmission circuit 85 (step S4903). After that, if the start command flag in the main RAM 74 is set to "1" (step S4904: YES), that is, if the start command is to be transmitted, the start command stored in the main ROM 73 is used. The data of the header HD indicating that there is data is set in the write destination area ascertained in step S4903 (step S4905). Thereafter, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4906). In step S4906, steps S4911, S4917 and S4922 which will be described later, the value of the write pointer 113 is incremented by 1, and if the value of the write pointer 113 after the increment of 1 exceeds the maximum value "31", the Clear the write pointer 113 to "0".

Thereafter, "9101H", which is the start address of the eleventh setting range ("9101H" to "910CH"), is set in the transfer source address counter 132 of the main RAM 74 (step S4907). As a result, the lower area of the AT continuation counter 74u can be grasped as the transfer source storage area based on the addresses set in the address range of "9101H" to "9102H" in the common data table 73g. After that, "6", which is the number of storage areas of the main RAM 74 included in the eleventh set range, is set in the transfer number counter 114 as the number of transfers (step S4908), and the start command flag is cleared to "0". (Step S4909).

On the other hand, if the start command flag is not set to "1" (step S4904: NO), that is, if the end command is to be transmitted, it indicates that the end command is stored in the main ROM 73. The data of the header HD is set in the write destination area ascertained in step S4903 (step S4910). Thereafter, as in step S4906 described above, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4911).

Thereafter, "9109H", which is the start address of the twelfth set range ("9109H" to "911AH"), is set in the transfer source address counter 132 of the main RAM 74 (step S4912). As a result, it is possible to recognize the gaming state area 77 as the transfer source storage area based on the addresses set in the address range of "9109H" to "910AH" in the common data table 73g. After that, "9", which is the number of storage areas of the main RAM 74 included in the twelfth set range, is set in the transfer number counter 114 as the number of transfers (step S4913), and the end command flag is cleared to "0". (Step S4914).

After performing the processing of step S4909 or step S4914, in steps S4915 to S4917, the same processing as steps S4610 to S4612 of the common command transmission processing (FIG. 81) in the fifth embodiment is executed. Specifically, the data in the transfer source storage area is transferred to the write destination area in the transmission standby buffer 112 (step S4915). In step S4915, the address of the transfer source storage area in the main RAM 74 is specified based on the data of the storage area corresponding to the address set in the transfer source address counter 132 in the common data table 73g. Thereafter, the most significant bit (seventh bit) in the write destination area is set to "0" (step S4916). As a result, when a command at start is transmitted, the value of the most significant bit of the second to seventh frames FR2 to FR7 of the command at start can be set to "0", and based on the value of the most significant bit header HD and the second to seventh frames FR2 to FR7. Further, when transmitting a termination command, the value of the most significant bit of the second to tenth frames FR2 to FR10 of the termination command can be set to "0", and based on the value of the most significant bit The header HD can be made identifiable from the second to tenth frames FR2 to FR10.

Thereafter, similarly to steps S4906 and S4911 described above, the write destination area in the transmission standby buffer 112 is updated by updating the value of the write pointer 113 (step S4917). Thereafter, 1 is subtracted from the value of the transfer number counter 114 (step S4918), and it is determined whether or not the value of the transfer number counter 114 after the subtraction of 1 is "0" (step S4919).

If a negative determination is made in step S4919, the transfer source storage area is updated by adding 2 to the value of the transfer source address counter 132 (step S4920). The processing of steps S4915 to S4920 is processing that is repeatedly executed until an affirmative determination is made in step S4919. In step S4920, the addresses stored in the transfer source address counter 132 are updated in the order of "9101H"→"9103H"→...→"9109H"→"910BH" when the start command is transmitted. When the end command is transmitted, the addresses stored in the transfer source address counter 132 are updated in the order of "9109H"→"910BH"→...→"9117H"→"9119H".

Thereafter, the process proceeds to step S4915, and the processes of steps S4915 to S4919 are repeatedly executed until an affirmative determination is made in step S4919. As a result, when the start command is transmitted, the data stored in the storage area of the main RAM 74 included in the eleventh setting range can be set in the transmission standby buffer 112, and the end command can be transmitted. When transmitting, the data stored in the storage area of the main RAM 74 included in the twelfth set range can be set in the transmission standby buffer 112 .

After making an affirmative determination in step S4919, in steps S4921 and S4922, the same processes as steps S4623 and S4624 of the common command transmission process (FIG. 81) in the fifth embodiment are executed. Specifically, the data of the footer FT stored in the main ROM 73 is set in the write destination area corresponding to the value of the write pointer 113 in the transmission standby buffer 112 (step S4921). After that, as in steps S4906, S4911, and S4917 described above, the value of the write pointer 113 is updated to update the write destination area in the transmission standby buffer 112 (step S4922), and the common command transmission process is started. finish.

As described above, in the configuration in which only some of the plurality of storage areas in which data is set in the start command in the main RAM 74 overlap with the plurality of storage areas in which data is set in the end command. , the eleventh setting range of the common data table 73g is set to the continuous address range of "9101H" to "910CH". Therefore, by repeatedly executing the process of adding 2 to the value of the transfer source address counter 132 (the process of step S4920), the transfer source storage area can be sequentially updated. This makes it possible to simplify the processing configuration for transferring the data stored in the storage area of the main RAM 74 that is included in the eleventh set range to the transmission standby buffer 112 . Further, in the common data table 73g, the twelfth setting range is set to a continuous address range of "9109H" to "911AH". Therefore, by repeatedly executing the process of adding 2 to the value of the transfer source address counter 132 (the process of step S4920), the transfer source storage area can be sequentially updated. This makes it possible to simplify the processing configuration for transferring the data stored in the storage area of the main RAM 74 that is included in the twelfth set range to the transmission standby buffer 112 .

Based on the common data table 73g, the main MPU 72 identifies the storage area of the main RAM 74 in which data is set in the start command, and the storage area of the main RAM 74 in which data is set in the end command. identify. For this reason, the storage area of the main RAM 74 in which data is set in the end command is used as a separate data table from the data table referred to for specifying the storage area in the main RAM 74 in which the data is set in the start command. Compared to the configuration in which the data table referred to for specifying is stored in the main ROM 73, data is set in the storage area of the main RAM 74 in which data is set in the command at the start and in the command at the end The data capacity of the data table for specifying the storage area of the main RAM 74 can be reduced. As a result, the data capacity of the main ROM 73 that stores the data table can be reduced.

Since the 11th set range is a continuous address range, the start address (“9101H”) of the 11th set range is set in the transfer source address counter 132 in step S4908, and the address included in the 11th set range is set in step S4909. The eleventh setting range can be specified by setting the number of storage areas (“6”) of the main RAM 74 in the transfer count counter 114 . This simplifies the processing configuration for designating the eleventh setting range. Since the 12th set range is a continuous address range, the start address ("9109H") of the 12th set range is set in the transfer source address counter 132 in step S4912, and the 12th set range is set in step S4913. A twelfth setting range can be designated by setting the number of storage areas (“9”) of the main RAM 74 included in the transfer count counter 114 . This simplifies the processing configuration for designating the twelfth setting range.

By changing the start address of the transfer target range (11th set range or 12th set range) and information on the number of transfers in the common command transmission process according to the type of command to be sent, the common command transmission process can be performed. When transmitting the command at the start, the data stored in the storage area of the main RAM 74 included in the eleventh setting range can be set in the transmission standby buffer 112, and the command at the end can be set. , the data stored in the storage area of the main RAM 74 included in the twelfth setting range can be set in the transmission standby buffer 112 . For this reason, the data in the main RAM 74 is transferred to the transmission standby buffer 112 when the end command is transmitted, as a separate process from the process of transferring the data in the main RAM 74 to the transmission standby buffer 112 when the start command is transmitted. , the data capacity of the program stored in the main ROM 73 for executing the process of transferring the data in the main RAM 74 to the transmission standby buffer 112 can be reduced. can.

Next, referring to the flow chart of FIG. 88, the highest level setting process executed by the effect side MPU 92 will be described. As already described in the fifth embodiment, the highest level setting process is executed in step S4708 of the command reception handling process (FIG. 82).

In the highest level setting process, the same processes as steps S4801 to S4803 of the highest level setting process (FIG. 83) in the fifth embodiment are executed in steps S5101 to S5103. Specifically, first, the start time command or the end time command stored in the wait buffer 122 after reception is set in the uppermost setting area 134 of the effect side RAM 94 (step S5101). In step S5101, if a start command is stored in the post-reception waiting buffer 122, the first to eighth frames FR1 to FR8 of the start command are stored in the first to eighth areas RC1 of the top setting area . to RC8, and when a termination command is stored in the waiting buffer 122 after receiving, the first to eleventh frames FR1 to FR11 of the termination command are set to the first to the first to the highest level setting area 134. 11 areas RC1 to RC11.

After that, the post-reception standby buffer 122 is cleared (step S5102). In the clear processing, the area in which the command at the start or the command at the end was stored in the waiting buffer 122 after reception is cleared to "0". As a result, an empty area for storing the next command can be secured in the waiting buffer 122 after reception. After that, the value of the read pointer 128 in the standby buffer 122 after reception is updated to the value corresponding to the storage area next to the storage area in which the last command (data of the footer FT) of the start command or end command was stored. (Step S5103).

Thereafter, the value of the effect side bit designation counter in the effect side RAM 94 is cleared to "0" (step S5104). As already described in the first embodiment, the effect side bit designation counter is a counter that enables the effect side MPU 92 to grasp the transfer source bit in the transfer source storage area.

After that, if the command set in the highest setting area 134 in step S5101 is the start command (step S5105: YES), the address of the seventh area RC7 in the highest setting area 134 A counter is set (step S5106). As already explained, the seventh area RC7 is an area in which the highest aggregated frame SF of the start command is set. As already described in the first embodiment, the effect-side transfer source counter is a counter that enables the effect-side MPU 92 to grasp the storage area of the data transfer source. By setting the address of the seventh area RC7 in the effect side transfer source counter in step S5106, the seventh area RC7 can be set as the transfer source storage area. As described above, since the value of the rendering side bit designation counter is cleared to "0" in step S5104, the 0th bit in the seventh area RC7 can be set as the transfer source bit.

After that, the address of the second area RC2 in the highest setting area 134 is set in the effect side transfer destination counter in the effect side RAM 94 (step S5107). As already described in the first embodiment, the effect-side transfer destination counter is a counter that enables the effect-side MPU 92 to grasp the transfer destination storage area. By setting the address of the second area RC2 in the effect-side transfer destination counter in step S5107, the second area RC2 can be used as the transfer destination storage area.

On the other hand, if the command set in the highest setting area 134 in step S5101 is not the starting command but the ending command (step S5105: NO), the address of the third area RC3 in the highest setting area 134 (step S5108). As already explained, the third area RC3 is an area in which the highest aggregated frame SF of the start command is set. By setting the address of the third area RC3 in the effect side transfer source counter in step S5108, the third area RC3 can be set as the transfer source storage area. As described above, since the value of the rendering side bit designation counter is cleared to "0" in step S5104, the 0th bit in the third area RC3 can be set as the transfer source bit. After that, the address of the fourth area RC4 in the highest setting area 134 is set in the effect side transfer destination counter in the effect side RAM 94 (step S5109). As a result, the fourth area RC4 can be used as a transfer destination storage area.

After performing the process of step S5107 or step S5109, similarly to step S4810 of the highest level setting process (FIG. 83) in the fifth embodiment, "0" or "1" stored in the transfer source bit is set as the most significant bit in the transfer destination storage area (step S5110). After that, based on the value of the rendering side bit designation counter, it is determined whether or not the process of setting the data aggregated in the highest aggregated frame SF to the highest bit of the corresponding frame has ended (step S5111). In step S5111, if the command set in the highest setting area 134 is the start time command, affirmative determination is made if the value of the effect side bit designation counter is "1", and the highest setting area If the command set in 134 is a command at the time of termination, affirmative determination is made when the value of the effect side bit designation counter is "3".

If a negative determination is made in step S5111, the value of the rendering-side bit designation counter is incremented by 1, so that the area (seventh area RC7 or first area RC7) where the highest-level aggregated frame SF is set in the highest-level setting area 134 is selected. 3 area RC3) is updated (step S5112). The processes of steps S5110 to S5113 are repeatedly executed until an affirmative determination is made in step S5111. In step S5112, when the start command is set in the highest setting area 134, the transfer source bits in the seventh area RC7 are updated in the order of the 0th bit → the 1st bit, and the highest setting area 134 is updated. , the transfer source bits in the third area RC3 are updated in the order of the 0th bit→the 1st bit→the 2nd bit→the 3rd bit.

After that, by adding 1 to the value of the performance-side transfer destination counter, the transfer destination storage area is updated (step S5113). As a result, when the start command is set in the highest setting area 134, the transfer destination storage areas in the highest setting area 134 are updated in the order of the second area RC2→the third area RC3. , when the termination command is set in the highest setting area 134, the transfer destination in the highest setting area 134 is in the order of the fourth area RC4→fifth area RC5→sixth area RC6→seventh area RC7. area is updated.

After performing the process of step S5113, the process proceeds to step S5110, and the processes of steps S5110 to S5113 are repeatedly executed until an affirmative determination is made in step S5111. As a result, when the command at start is set in the highest level setting area 134, the data aggregated in the 0th to 1st bits of the highest level aggregated frame SF correspond to the 0th to 1st bits. It can be set to the most significant bits of the second to third frames FR2 to FR3, and if the end command is set in the top setting area 134, the 0th to 3rd bits of the highest aggregated frame SF The data aggregated into bits can be set to the most significant bits of the 4th to 7th frames FR4 to FR7 corresponding to the 0th to 3rd bits. If an affirmative determination is made in step S5111, the highest setting processing is terminated.

As described above, the data stored in the lower area and upper area of the AT continuation counter 74u are set in the consecutive second to third frames FR2 to FR3 in the start command. Therefore, by repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S5113), the storage area of the transfer destination in which the data aggregated in the highest aggregate frame SF is set is sequentially updated. can do. As a result, the effect-side MPU 92 converts the data aggregated into the 0th to 1st bits in the highest aggregated frame SF of the start command into the 2nd to 3rd frames FR2 to FR3 corresponding to the 0th to 1st bits. It is possible to simplify the processing configuration of the processing for setting the most significant bit. In addition, the data stored in the lower area and upper area of the continuous game number counter 74r and the lower area and upper area of the total win number counter 74s are stored in the consecutive fourth to seventh frames FR4 to FR7 in the end command. set. Therefore, by repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S5113), the storage area of the transfer destination in which the data aggregated in the highest aggregate frame SF is set is sequentially updated. can do. As a result, the effect-side MPU 92 converts the data aggregated into the 0th to 3rd bits in the highest aggregated frame SF of the end command into the 4th to 7th frames FR4 to FR7 corresponding to the 0th to 3rd bits. It is possible to simplify the processing configuration of the processing for setting the most significant bit.

According to this embodiment detailed above, the following excellent effects are obtained.

In the configuration in which only a part of the plurality of storage areas in which data is set in the start command in the main RAM 74 overlaps with the plurality of storage areas in which data is set in the end command, the common data table The 11th set range of 73g is set to the continuous address range of "9101H" to "910CH". Therefore, by repeatedly executing the process of adding 2 to the value of the transfer source address counter 132 (the process of step S4920), the transfer source storage area can be sequentially updated. This makes it possible to simplify the processing configuration for transferring the data stored in the storage area of the main RAM 74 that is included in the eleventh set range to the transmission standby buffer 112 . Further, in the common data table 73g, the twelfth setting range is set to a continuous address range of "9109H" to "911AH". Therefore, by repeatedly executing the process of adding 2 to the value of the transfer source address counter 132 (the process of step S4920), the transfer source storage area can be sequentially updated. This makes it possible to simplify the processing configuration for transferring the data stored in the storage area of the main RAM 74 that is included in the twelfth set range to the transmission standby buffer 112 .

Based on the common data table 73g, the main MPU 72 identifies the storage area of the main RAM 74 in which data is set in the start command, and the storage area of the main RAM 74 in which data is set in the end command. identify. For this reason, the storage area of the main RAM 74 in which data is set in the end command is used as a separate data table from the data table referred to for specifying the storage area in the main RAM 74 in which the data is set in the start command. Compared to the configuration in which the data table referred to for specifying is stored in the main ROM 73, data is set in the storage area of the main RAM 74 in which data is set in the command at the start and in the command at the end The data capacity of the data table for specifying the storage area of the main RAM 74 can be reduced. As a result, the data capacity of the main ROM 73 that stores the data table can be reduced.

Since the 11th set range is a continuous address range, the start address (“9101H”) of the 11th set range is set in the transfer source address counter 132 in step S4908, and the address included in the 11th set range is set in step S4909. The eleventh setting range can be specified by setting the number of storage areas (“6”) of the main RAM 74 in the transfer count counter 114 . This simplifies the processing configuration for designating the eleventh setting range. Since the 12th set range is a continuous address range, the start address ("9109H") of the 12th set range is set in the transfer source address counter 132 in step S4912, and the 12th set range is set in step S4913. A twelfth setting range can be specified by setting the number of storage areas (“9”) of the main RAM 74 included in the transfer count counter 114 . This simplifies the processing configuration for designating the twelfth setting range.

By changing the start address of the transfer target range (11th set range or 12th set range) and information on the number of transfers in the common command transmission process according to the type of command to be sent, the common command transmission process can be performed. When transmitting the command at the start, the data stored in the storage area of the main side RAM 74 included in the eleventh set range can be set in the transmission standby buffer 112, and the command at the end can be set. , the data stored in the storage area of the main RAM 74 and included in the twelfth setting range can be set in the transmission standby buffer 112 . For this reason, the data in the main RAM 74 is transferred to the transmission standby buffer 112 when the end command is transmitted, as a separate process from the process of transferring the data in the main RAM 74 to the transmission standby buffer 112 when the start command is transmitted. , the data capacity of the program stored in the main ROM 73 for executing the process of transferring the data in the main RAM 74 to the transmission standby buffer 112 can be reduced. can.

In the common data table 73g, the first aggregation range is set to a continuous address range of "9101H" to "9104H". Therefore, by repeatedly executing the process of adding 2 to the value of the transfer source address counter 132 (the process of step S5012), the transfer source storage area can be sequentially updated. Also, the second aggregation range is set to a continuous address range from "910DH" to "9114H". Therefore, by repeatedly executing the process of adding 2 to the value of the transfer source address counter 132 (the process of step S5012), the transfer source storage area can be sequentially updated. This simplifies the processing configuration for sequentially updating the storage area of the transfer source.

Since the first aggregation range is a continuous address range, the start address (“9101H”) of the first aggregation range is set in the transfer source address counter 132 in step S5005, and the address included in the first aggregation range is set in step S5006. The first aggregation range can be specified by setting the number of storage areas (“2”) of the main-side RAM 74 in the transfer count counter 114 . This simplifies the processing configuration for designating the first aggregation range. Since the second aggregation range is a continuous address range, the start address ("910DH") of the second aggregation range is set in the transfer source address counter 132 in step S5007, and the second aggregation range is set in step S5008. The second aggregation range can be specified by setting the number of storage areas (“4”) of the main RAM 74 included in the transfer count counter 114 . This simplifies the processing configuration for designating the second aggregation range.

As a command in which the data stored in the most significant bit is aggregated, the command at the start and the command at the start are the storage areas of the main RAM 74 where the data stored in the most significant bit are aggregated. There are different commands on exit. By changing the start address of the transfer target range (first aggregation range or second aggregation range) and information on the number of transfers in the highest-level aggregation process according to the type of command to be sent, the common highest-level aggregation process can be performed. When a command at the start is transmitted, the data stored in the most significant bit of the storage area of the main side RAM 74 included in the first aggregation range can be aggregated into the highest aggregation area 74v. In addition, when a termination command is transmitted, the data stored in the highest bit of the storage area of the main side RAM 74 included in the second aggregation range can be aggregated in the highest aggregation area 74v. . For this reason, the data stored in the most significant bit is aggregated when the end command is transmitted as a separate process from the process of aggregating the data stored in the most significant bit when the command at start is transmitted. Compared to a configuration in which a process for collecting data is provided, the data capacity of the program stored in the main ROM 73 can be reduced in order to execute the process of aggregating the data stored in the most significant bit.

The data stored in the lower area and upper area of the AT continuation counter 74u are set in the consecutive second to third frames FR2 to FR3 in the start command. Therefore, by repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S5113), the storage area of the transfer destination in which the data aggregated in the highest aggregate frame SF is set is sequentially updated. can do. As a result, the effect-side MPU 92 converts the data aggregated into the 0th to 1st bits in the highest aggregated frame SF of the start command into the 2nd to 3rd frames FR2 to FR3 corresponding to the 0th to 1st bits. It is possible to simplify the processing configuration of the processing for setting the most significant bit. The data stored in the lower area and upper area of the continuous game number counter 74r and the lower area and upper area of the total winning number counter 74s are stored in the continuous fourth to seventh frames FR4 to FR7 in the end command. set. Therefore, by repeatedly executing the process of adding 1 to the effect-side transfer destination counter (the process of step S5113), the storage area of the transfer destination in which the data aggregated in the highest aggregate frame SF is set is sequentially updated. can do. As a result, the effect-side MPU 92 converts the data aggregated into the 0th to 3rd bits in the highest aggregated frame SF of the end command into the 4th to 7th frames FR4 to FR7 corresponding to the 0th to 3rd bits. It is possible to simplify the processing configuration of the processing for setting the most significant bit.

<Seventh embodiment>
In this embodiment, when the start lever 41 is operated and the game is started, the left 7-segment display 66a and the right 7-segment display 66b of the dual-purpose display 66 are hidden. The difference from the first embodiment is that 66 all-off states occur. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

FIG. 89(a) shows the conditions under which the dual-use display section 66 is in a fully extinguished state, the conditions under which the dual-use display section 66 displays the stop order correspondence, the conditions under which the ratio display is executed, and the conditions under which the given number display is executed. It is an explanatory view for explaining. As shown in FIG. 89(a), the dual-use display unit 66 displays all lights out, a stop order corresponding display, and a given number display during a period in which the game is being executed. In either case, during a period in which the game is not executed, a state in which the ratio display is being executed or a state in which the given number is being displayed is entered. Here, the period during which the game is being executed is the period during which the in-game flag of the main RAM 74 is set to "1", and the period during which the game is not being executed is the value of the during-game flag. is "0".

During the period in which the game is being executed, the dual-purpose display section 66 is in a fully extinguished state on condition that the number counter 74e of the main side RAM 74 is set to "255" which is the extinguishing data. In addition, while the light-off data ("255") is not set in the given number counter 74e, the stop order type counter 74m in the main side RAM 74 has one of the stop order type numbers "1" to "9". Under the condition that it is in the set state, the display corresponding to the stop order is performed on the dual-purpose display section 66 .

During a period in which the game is not being executed, ratio display is executed on the dual-purpose display unit 66 on condition that the calculation result data of any one of "0" to "100" is set in the ratio display counter 74n. be. During both the period in which the game is being executed and the period in which the game is not being executed, the light-off data ("255") is not set in the grant number counter 74e, and "1" is set in the stop order type counter 74m. Under the condition that the stop order type number of "9" is not set and the calculation result data of "0" to "100" is not set in the ratio display counter 74n, At 66, an award number display is performed.

The game is executed during the period during which the light-off data ("255") is set in the grant number counter 74e and during the period during which one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m. and ends while the game is running. On the other hand, as already described in the first embodiment, the ratio display counter 74n displays the calculation result of "0" to "100" when the ratio display start operation is performed while the game is not being executed. Data is set. For this reason, the state in which the light-off data ("255") is set in the given number counter 74e and the state in which the calculation result data of "0" to "100" are set in the ratio display counter 74n overlap. never occurs. Also, the stop order type counter 74m is set to one of the stop order type numbers "1" to "9", and the ratio display counter 74n is set to the calculation result data of "0" to "100". This state cannot occur repeatedly.

The light-off data is set in the given number counter 74e when the start lever 41 is operated and the game is started. The extinguishing data set in the applied number counter 74e is cleared when the first acceleration period of the reels 32L, 32M, and 32R ends in reel control processing (see FIG. 90), which will be described later. Acceleration control of the reels 32L, 32M, 32R is executed in the first acceleration period and the second acceleration period. The first acceleration period is a period of about 290 milliseconds after the acceleration control of the reels 32L, 32M, 32R is started. A second acceleration period is a period of approximately 10 milliseconds following the first acceleration period.

FIG. 89(b) is an explanatory diagram for explaining the configuration of the main RAM 74. As shown in FIG. As shown in FIG. 89(b), the main RAM 74 is provided with an acceleration period counter 74γ. The acceleration period counter 74γ is a timer counter that enables the main side MPU 72 to grasp that the first acceleration period and the second acceleration period of the reels 32L, 32M, and 32R have ended. The value of the acceleration period counter 74γ is updated by being decremented by 1 in the timer subtraction process of step S208 in the timer interrupt process (FIG. 11). When starting the acceleration control of the reels 32L, 32M, 32R, the main MPU 72 sets "195" in the acceleration period counter 74γ as information corresponding to the first acceleration period. The value of the acceleration period counter 74γ becomes "0" about 290 milliseconds after the acceleration control of the reels 32L, 32M, 32R is started. As a result, the main MPU 72 can grasp that the first acceleration period has ended. When the first acceleration period ends, the main MPU 72 sets "7" in the acceleration period counter 74γ as information corresponding to the second acceleration period. The value of the acceleration period counter 74γ becomes "0" about 10 milliseconds after the start of the second acceleration period of the reels 32L, 32M, 32R. This enables the main MPU 72 to grasp that the second acceleration period has ended.

As described above, when the start lever 41 is operated to start a new game, the combined display section 66 is temporarily turned off. When the previous game ends without winning a small prize, the value of the awarded number counter 74e becomes "0" and the shared display unit 66 displays the awarded number of "00" corresponding to the value of the awarded number counter 74e. executed. After that, even if a bet operation or medal insertion for starting the game is performed, the state where the value of the award number counter 74e is "0" is continued, and the value of the award number counter 74e is displayed on the combined display unit 66. The display of the assigned number of "00" corresponding to is continued. In a game in which stop order correspondence display is not executed on the dual-purpose display unit 66, the display mode of the dual-purpose display unit 66 is not changed during the period from the start of the game to the winning determination process (step S5319 of the reel control process (FIG. 90) described later). With this configuration, when a small winning combination is not established in the game, the value of the awarded number counter 74e continues to be "0", and the dual-use display unit 66 displays the value of the awarded number counter 74e. The assigned number display of "00" corresponding to the value is continued. As described above, in a game in which display corresponding to the stop order is not executed on the dual-purpose display unit 66, if the display mode of the dual-purpose display unit 66 is not changed during the period from the start of the game to the prize determination process (step S5319), the game can be started. The state in which "00" is displayed on the dual-purpose display unit 66 continues from the beginning until the end of the game, and it may not be possible to grasp that the game has started based on the display of the dual-purpose display unit 66. occur. On the other hand, by setting the dual-purpose display section 66 to be temporarily turned off at the start of the game, the state in which "00" is displayed on the dual-purpose display section 66 continues before and after the game is executed. In addition, it is possible to prevent the state in which "00" is displayed on the dual-use display section 66 before and after the start of the game. As a result, the display mode of the dual-use display section 66 at the start of the game can be changed to the display mode corresponding to the start of the game. By changing the display mode of the combined display section 66 at the start of the game, it is possible to grasp that the game has started based on the display mode of the combined display section 66 .

As already described in the first embodiment, the display corresponding to the order of stopping is the lottery process for the combination in the game in which the gaming state is the pseudo-bonus state ST4 or the AT state ST5 and the number of bets is "3" (FIG. 18). is executed under the condition that one of the index values IV of "1" to "9" is won. In the game in which the display corresponding to the stopping order is executed on the combined display unit 66, as in the first embodiment, the stopping order type counter 74m is set to "1" before the acceleration control of the reels 32L, 32M, 32R is started. ” to “9” is set. Then, in a state where the stop order type counter 74m is set with the stop order type number, the given number counter 74e is cleared to "0" at the end of the first acceleration period, and then the port output process (FIG. 91) to be described later is performed. By executing this, the display content on the dual-use display unit 66 is switched from display of the number to be given to display corresponding to the stop order. Timer interrupt processing (FIG. 11) including port output processing is executed at a cycle of 1.49 milliseconds as in the first embodiment. The second acceleration period (approximately 10 milliseconds) is longer than the 1.49 milliseconds. is completed and the operation of the stop buttons 42 to 44 is enabled, port output processing is always executed. Therefore, in a game in which the display corresponding to the order of stopping is executed, the display corresponding to the order of stopping is reliably started on the combined display section 66 at a timing before the timing at which the operation of the stop buttons 42 to 44 is activated. be able to.

In both the game in which the stop order corresponding display is executed on the combined display section 66 and the game in which the stop order corresponding display is not executed, the combined display section 66 is temporarily turned off at the start of the game. Regardless of the result of the combination lottery process (FIG. 18), the process for turning off the dual-purpose display section 66 is executed. Therefore, when the game is started based on the operation of the start lever 41, the dual-purpose display section 66 is set to the all-off state at the timing prior to the timing at which the winning lottery process (FIG. 18) is executed. It is possible to execute processing for As a result, in the configuration in which the all-light-off state of the dual-use display section 66 is terminated at a timing prior to the timing at which the operation of the stop buttons 42 to 44 is activated, the duration of the all-light-off state can be ensured for a long time. .

As described above, the main MPU 72 puts the combined display section 66 into the all-light-off state on the condition that the light-off data ("255") is set in the given number counter 74e. The given number counter 74e is a counter in which information on the given number of game media is set, and is a counter in which light-off data for turning the dual-use display section 66 into the all-light-off state is set. For this reason, in addition to the number counter 74e to which information on the number of game media to be given is set, the main RAM 74 has a flag or the like set with information indicating that it is time to turn the dual-purpose display section 66 into the all-off state. Compared to the set configuration, the data capacity of the storage area provided in the main side RAM 74 so that the main side MPU 72 can grasp the number of game media to be given and the timing of turning off the dual-purpose display section 66 can be reduced.

Next, the setting process at the time of start executed by the main MPU 72 will be described with reference to the flowchart of FIG. 89(c). As already described in the first embodiment, the setting process at the start is executed in step S406, one step before step S407 in which the winning lottery process (FIG. 18) is executed in the normal process (FIG. 13). be done.

In the setting process at the start, "255", which is light-off data, is set in the grant number counter 74e of the main RAM 74 (step S5201). As a result, a state can be set in which a process for turning the dual-purpose display section 66 into the all off state is executed in the next port output process (FIG. 91). After that, in steps S5202 to S5205, the same processing as steps S801 to S804 of the setting processing (FIG. 17B) at the start in the first embodiment is executed. Specifically, the value of the index value counter 74f in the main RAM 74 is cleared to "0" (step S5202), and both the replay bet setting flag and the acceptance bet setting flag in the main RAM 74 are set to "0". ' is cleared (step S5203). After that, the in-game flag of the main RAM 74 is set to "1" (step S5204). Thereby, it is possible for the main MPU 72 to grasp that the game is being executed. After that, the value of the bet number setting counter 74b in the main RAM 74 is set in the bet number history counter 74c in the main RAM 74 (step S5205), and the setting process at the time of this start ends. By setting the value of the bet number setting counter 74b to the bet number history counter 74c in step S5205, it is possible for the main MPU 72 to grasp the number of bets in the game started this time after the end of the game.

Next, the reel control processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. As already explained in the first embodiment, the reel control process is executed in step S408 of the normal process (FIG. 13).

In the reel control process, as in step S1001 of the reel control process (FIG. 22) in the first embodiment, a rotation start process is executed (step S5301). In the rotation start process, it is checked whether or not a predetermined wait time (for example, 4.1 seconds) has elapsed since the reels 32L, 32M, and 32R started rotating in the previous game. waits until the wait time elapses. When the wait time has passed, the wait time for the next game is set again, and rotation start information is set in the motor control storage area provided in the main side RAM 74 . By performing such processing, the acceleration processing of the stepping motor is started in the stepping motor control processing of step S206 in the timer interrupt processing (FIG. 11), and the reels 32L, 32M, 32R start rotating.

After that, the first acceleration period setting process is executed (step S5302). In the first acceleration period setting process, the numerical value information "195" corresponding to the first acceleration period (approximately 290 milliseconds) of the reels 32L, 32M, 32R is set in the acceleration period counter 74γ of the main RAM 74. FIG. As described above, the value of the acceleration period counter 74γ is updated by being decremented by 1 in the timer subtraction process of step S208 in the timer interrupt process (FIG. 11). Then, it becomes "0" when about 290 milliseconds have passed. Thereafter, it is determined whether or not the first acceleration period for the reels 32L, 32M, and 32R has ended (step S5303). repeats the process of In step S5303, an affirmative determination is made when the value of the acceleration period timer counter in the main RAM 74 is "0".

When an affirmative determination is made in step S5303, the value of the grant number counter 74e in the main RAM 74 is cleared to "0" (step S5304). As a result, the state in which the light-off data ("255") is set in the given number counter 74e can be terminated, and in the next port output process (Fig. A state can be set in which a process for executing the display of the given number is executed. In the game in which the display corresponding to the stop order is executed, the dual-use display unit 66 is changed from the state in which all of the dual-use display unit 66 is turned off by executing the processing for executing the display corresponding to the stop order in the next port output processing. can be switched to the state in which the stop order correspondence display is being executed. Further, in a game in which the stop order display is not executed, the dual-purpose display unit 66 is changed from the state in which the dual-use display unit 66 is completely off by executing the processing for executing the display of the given number in the next port output processing. It is possible to switch to the state in which the number of grants is displayed by pressing.

After that, the process of setting the second acceleration period is executed (step S5305). In the setting process of the second acceleration period, numerical information "7" corresponding to the second acceleration period (approximately 10 milliseconds) of the reels 32L, 32M, 32R is set in the acceleration period counter 74γ. As described above, the value of the acceleration period counter 74γ is updated by being decremented by 1 in the timer subtraction process of step S208 in the timer interrupt process (FIG. 11). Then, it becomes "0" when about 10 milliseconds have passed. After that, it is determined whether or not the second acceleration period of the reels 32L, 32M, and 32R has ended (step S5306). repeats the process of In step S5306, an affirmative determination is made when the value of the acceleration period timer counter in the main RAM 74 is "0".

If an affirmative determination is made in step S5306, in steps S5307 to S5320, the same processes as steps S1003 to S1016 of the reel control process (FIG. 22) in the first embodiment are executed. Specifically, first, operation validation notification processing is executed (step S5307). In the operation activation notification process, lamps (not shown) provided in one-to-one correspondence with the stop buttons 42 to 44 are turned on to indicate that a stop command can be generated. Players, etc. are notified. After that, it is determined whether or not any of the stop buttons 42 to 44 has been operated (step S5308), and if none of the stop buttons 42 to 44 has been operated (step S5308: NO), 44 is operated repeatedly, the process of step S5308 is repeatedly performed. If it is determined that any one of the stop buttons 42 to 44 has been operated (step S5308: YES), it is determined whether or not the stop buttons 42 to 44 corresponding to the rotating reels 32L, 32M, 32R have been operated. It is determined whether or not a command has been issued (step S5309). If no stop command has been issued, the process returns to step S5308, and the processes of steps S5308 to S5309 are repeatedly executed until any one of the stop buttons 42 to 44 is operated.

When the stop command is generated (step S5309: YES), the operation invalidation notification process corresponding to the stop buttons 42 to 44 operated this time is executed (step S5310), and the stop command is transmitted to the production side MPU 92. (Step S5311). Thereafter, when a stop instruction command is transmitted, stop control processing shown in steps S5312 to S5318 is performed to stop the spinning reels. In the stop control process, the symbol number of the arrival symbol that has reached the base position (specifically, the lower stage) at the timing when the stop buttons 42 to 44 are operated is confirmed (step S5312), and stored in the main side RAM74. Based on the stop information received, the number of slips of the reels 32L, 32M, 32R to be stopped this time (any value from "0" to "4") is calculated (step S5313). After that, the calculated number of slips is added to the symbol number of the arrival symbol, and the symbol number of the stop symbol to be actually stopped at the base position is determined (step S5314). Then, it is determined whether or not the symbol numbers of the arrival symbols of the reels 32L, 32M, and 32R to be stopped this time and the symbol numbers of the stop symbols are equal (step S5315), and if they are equal (step S5315: YES) A reel stop process for stopping the rotation of the reels 32L, 32M, 32R is performed (step S5316). Thereafter, if all the reels 32L, 32M, 32R are not stopped (step S5317: NO), stop information second setting processing is performed (step S5318), and the process returns to step S5308. Then, the processes of steps S5308 to S5318 are repeatedly executed until an affirmative determination is made in step S5317.

When it is determined in step S5317 that all the reels 32L, 32M and 32R are stopped, winning determination processing is executed (step S5319). In the winning determination process, the types of symbols stopped on the main line ML on each of the reels 32L, 32M, 32R are grasped. Then, based on the contents of the winning data stored in the main RAM 74, the combination of symbols stopped and displayed on the main line ML on each of the reels 32L, 32M, 32R becomes the winning combination in the winning combination lottery process. It is determined whether or not there is a combination of corresponding symbols, and in the case of a combination of symbols corresponding to the winning combination, it is specified that the winning combination has been won. As already described in the first embodiment, in the winning determination process (step S5319), when it is specified that any minor winning combination has been established, information on the number of grants corresponding to the established minor winning combination ( "1", "2", "5" or "15") is set in the grant number counter 74e of the main side RAM 74, and the value of the stop order type counter 74m in the main side RAM 74 is cleared to "0". In addition, in the winning determination process (step S5319), when it is specified that any replay winning has been established, a flag for executing the replay setting process in the next start waiting process (FIG. 15) , and the value of the stop order type counter 74m is cleared to "0". Furthermore, in the winning determination process (step S5319), when it is determined that no winning has been established, the value of the stop order type counter 74m is cleared to "0". By clearing the value of the stop order type counter 74m to "0", the dual-purpose display unit 66 will be in a state where the processing for executing the display of the assigned number is executed in the next port output processing (FIG. 28). In the game in which the dual-use display unit 66 displays the corresponding stop order, the dual-use display unit 66 performs processing for displaying the awarded number in the next port output process (FIG. 28). The state in which the display unit 66 is displaying the stop order is switched to the state in which the dual-purpose display unit 66 is displaying the given number. In the case where none of the minor wins is won in a game in which the dual-use display unit 66 does not display the display corresponding to the stop order, the dual-use display unit 66 displays the awarded number in the next port output process (FIG. 28). Even if the process of 1 is executed, the state in which the display of the given number of "00" is executed on the dual-purpose display unit 66 is continued. In a game in which display corresponding to stop order is not executed on the dual-use display unit 66, when establishment of any of the minor winning prizes is specified, display of the awarded number is performed on the dual-use display unit 66 in the next port output process (FIG. 28). By executing the process for doing so, the display content of the display of the given number executed on the combined display unit 66 is switched from "00" to "01", "02", "05" or "15". After that, the winning result command flag of the main side RAM 74 is set to "1" (step S5320), and the present reel control processing ends.

As described above, in the game in which display corresponding to the stop order is executed on the dual-use display unit 66, the processing of clearing the number of grant counter 74e to "0" (the processing of step S5304) while the dual-use display unit 66 is in the all-off state ), the state in which the light-off data is set in the given number counter 74e can be ended, and the display corresponding to the stop order can be executed on the combined display unit 66 in the next port output process (FIG. 91). It can be in a state in which a process for doing so is executed. By executing the process for executing the display corresponding to the stop order in the next port output process, the display corresponding to the stop order is executed on the dual-purpose display section 66 from the state where the dual-use display section 66 is in the all-off state. switch to the state where For this reason, as a process different from the process of clearing the value of the number counter 74e to which the light-off data is set to "0" (the process of step S5304), in the next port output process, Compared to the configuration in which the processing for executing the processing for executing the corresponding display is set, the dual-purpose display unit 66 is displayed in the stop order from the state in which the dual-purpose display unit 66 is completely turned off. It is possible to simplify the processing configuration for switching to a state in which display is being performed.

In a game in which display corresponding to the stop order is not executed on the dual-purpose display unit 66, a process (step S5304) of clearing the given number counter 74e to "0" is executed in a state where the dual-purpose display unit 66 is in a completely unlit state. Thus, the state in which the light-off data is set in the given number counter 74e can be ended, and the given number display (display of "00") can be displayed on the shared display section 66 in the next port output process (FIG. 91). It can be in a state in which a process for execution is executed. By executing the processing for displaying the assigned number in the next port output process, the dual-purpose display unit 66 changes from the state in which the dual-use display unit 66 is completely turned off to the state in which the assigned number is being displayed on the dual-use display unit 66. switch to For this reason, as a process separate from the process of clearing the value of the given number counter 74e in which the extinguished data is set to "0" (the process of step S5304), the combined display unit 66 displays the given number in the next port output process. Compared to the configuration in which the processing for executing the processing for executing the display is set, the display of the given number on the dual-purpose display unit 66 from the state where the dual-purpose display unit 66 is completely turned off. The processing configuration for switching to the running state can be simplified.

Next, the port output processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. As already explained in the first embodiment, port output processing is executed in step S211 of timer interrupt processing (FIG. 11). As described above, timer interrupt processing (FIG. 11) is executed at a 1.49 millisecond cycle.

In the port output process, first, it is determined whether or not "255", which is extinguishing data, is set in the number counter 74e of the main side RAM 74 (step S5401). When the light-off data is set in the given number counter 74e (step S5401: YES), non-display data is set in the left dual-purpose display unit display area 74p and the right dual-purpose display unit display area 74q in the main RAM 74 ( step S5402). By outputting these non-display data set in the dual-purpose display section display areas 74p and 74q to the dual-purpose display section 66 in step S5411 described later, the dual-purpose display section 66 can be turned off completely.

If a negative determination is made in step S5401, the same processes as steps S1401 to S1411 of the port output process (FIG. 28) in the first embodiment are executed in steps S5403 to S5413. Specifically, it is determined whether or not one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m of the main RAM 74 (step S5403). If one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m (step S5403: YES), the stop order corresponding display data table stored in the main ROM 73 is displayed. 73a (step S5404), and referring to the read stop order display data table 73a, the display data corresponding to the value of the stop order type counter 74m is set in the right combined display section display area 74q, and the non-display display area 74q is set. The data is set in the display area 74p for the left side display (step S5405). These display data and non-display data set in the dual-purpose display section display areas 74p and 74q are output to the dual-purpose display section 66 in step S5411, which will be described later, so that the dual-purpose display section 66 displays the stop order correspondence. can be executed.

After making a negative determination in step S5403, if any calculation result data of "0" to "100" is set in the ratio display counter 74n of the main RAM 74 (step S5406: YES), the main The number display data table 73b stored in the side ROM 73 is read (step S5407), and the display data corresponding to the value of the ratio display counter 74n is displayed in the left side display area 74p by referring to the read number display data table 73b. and set in the right combined display section display area 74q (step S5408). These display data set in the dual-purpose display section display areas 74p and 74q are output to the dual-purpose display section 66 in step S5411, which will be described later, so that the dual-purpose display section 66 can perform ratio display.

The stop order type number of "1" to "9" is not set in the stop order type counter 74m (step S5403: NO), and the calculation result data of "0" to "100" is in the ratio display counter 74n. If it is not set (step S5406: NO), processing for displaying the number of grants on the combined display unit 66 (processing of steps S5409 to S5410) is executed. Specifically, similarly to step S5407, the number display data table 73b stored in the main ROM 73 is read (step S5409), and the read number display data table 73b is referenced to set the value of the given number counter 74e. The corresponding display data is set in the left combined display section display area 74p and the right combined display section display area 74q (step S5410). By outputting these display data set in the combined display section display areas 74p and 74q to the combined display section 66 in step S5411 described later, the combined display section 66 can display the given number.

If the processing of step S5402, step S5405, step S5408, or step S5410 is performed, the data (display data or non-display data) set in the left dual-purpose display unit display area 74p and the right dual-purpose display unit display area 74q is output to the combined display unit 66 (step S5411). As a result, when non-display data is set in the dual-purpose display section display areas 74p and 74q, the dual-purpose display section 66 is turned off. Further, when non-display data is set in the left dual-purpose display section display area 74p and display data for display corresponding to the stop order is set in the right dual-purpose display section display area 74q, the dual-purpose display section 66 Stop order corresponding display is executed. Furthermore, when the non-display data or the display data for ratio display is set in the left dual-purpose display area 74p and the display data for ratio display is set in the right dual-purpose display area 74q, A ratio display is performed on the combined display unit 66 . Further, when the display data for displaying the given number is set in the shared display section display areas 74p and 74q, the shared display section 66 displays the given number.

Thereafter, display control processing for the credit display unit 65 is executed (step S5412), other port output processing is executed (step S5413), and this port output processing ends. Other port output processing in step S5413 outputs data corresponding to the I/O device from the input/output port.

Next, the manner in which the dual-purpose display section 66 is in the fully extinguished state in a game in which display corresponding to the stop order is performed on the dual-purpose display section 66 will be described with reference to the time chart of FIG. FIG. 92(a) shows a period in which the dual-purpose display section 66 is in a fully extinguished state, FIG. ) indicates the execution period of the display of the given number in the combined display unit 66, FIG. 92(d) shows the period in which the given number counter 74e is set to "255", which is the extinguishing data, and FIG. 92(e) shows the stop FIG. 92(f) shows the first acceleration period of the reels 32L, 32M and 32R, and shows the period during which one of the stop order type numbers "1" to "9" is set in the order type counter 74m. 92(g) shows the timing at which the bet operation or the first medal insertion is performed while the game is not being executed, FIG. 92(h) shows the timing at which the game is started, and FIG. 92(i) shows the stop button. 92(j) shows the timing at which the winning determination process (step S5319 of the reel control process (FIG. 90)) is executed, and FIG. It shows the timing at which the output process (FIG. 91) is executed.

At the timing of t1 when the value of the award number counter 74e is "0" and the award number display of "00" is executed on the combined display unit 66, as shown in FIG. When medals are inserted, the value of the award number counter 74e is maintained at "0". After that, as shown in FIG. 92(k), when the port output process is executed at the timing of t2, as shown in FIG. state continues. Thereafter, at timing t3, when the game is started as shown in FIG. 92(h), the light-off data ("255") is set in the grant number counter 74e as shown in FIG. 92(d). After that, as shown in FIG. 92(k), the port output process is executed at the timing of t4, and as shown in FIGS. The dual-purpose display section 66 is put into a completely extinguished state.

Thereafter, at timing t5, one of the stop order classification numbers "1" to "9" is set in the stop order classification counter 74m as shown in FIG. 92(e). Thereafter, as shown in FIG. 92(f), the first acceleration period for the reels 32L, 32M, and 32R starts at timing t6, and ends at timing t7. At the timing of t7 when the first acceleration period ends, the grant number counter 74e is cleared to "0" as shown in FIG. . After that, when the port output process is executed at the timing t8 as shown in FIG. 92(k), the dual-use display section 66 is completely extinguished and the dual-purpose display unit 66 is turned off as shown in FIGS. The stop order correspondence display is started on the display unit 66 . After that, at timing t9, as shown in FIG. 92(j), the operation of the stop buttons 42 to 44 is validated.

After that, at the timing of t10, the winning determination process is executed as shown in FIG. 92(j). is maintained at "0". Also, at the timing of t10, the value of the stop order type counter 74m is cleared to "0" as shown in FIG. 92(e). After that, when the port output process is executed at the timing t11 as shown in FIG. It switches to the display of the given number (display of "00").

As described above, the combination display section 66 is temporarily turned off at the start of the game, so that the combination display section 66 displays the given number of "00" before and after the game starts. It is possible to prevent the state from continuing. By changing the display mode of the combined display section 66 at the start of the game, it is possible to recognize that the game has started based on the display mode of the combined display section 66 .

Result of lottery process (FIG. 18) for a winning combination in a configuration in which the dual-use display unit 66 is completely extinguished at timing t8, which is timing before timing t9 at which operation of the stop buttons 42 to 44 is validated. Regardless of this, a process for turning the dual-use display unit 66 into a fully extinguished state is executed. For this reason, at the timing t3, which is the timing before the timing at which the winning lottery process (FIG. 18) is executed, the dual-use display unit 66 is put into a completely extinguished state (set extinguishing data to the given number counter 74e process) can be executed. As a result, it is possible to ensure a long duration of the all-lights-out state.

Next, the manner in which the dual-purpose display section 66 is in the fully extinguished state in a game in which the dual-purpose display section 66 does not perform stop order display will be described with reference to the time chart of FIG. FIG. 93(a) shows a period in which the dual-purpose display section 66 is in a fully extinguished state, FIG. 93(b) shows a period in which the number of "00" to be given is displayed on the dual-purpose display section 66, and FIG. 93(c). indicates the period in which the number of grant counter 74e is set to "255", which is light-off data, FIG. 93(f) shows the timing at which the game is started, and FIG. 93(g) shows the operation of the stop buttons 42 to 44 is valid. FIG. 93(h) shows the timing at which any small combination winning is specified in the winning determination process (step S5319 of the reel control process (FIG. 90)), and FIG. 93(i) indicates the timing at which port output processing (FIG. 91) is executed.

At the timing of t1 when the value of the award number counter 74e is "0" and the award number display of "00" is executed on the combined display unit 66, as shown in FIG. When medals are inserted, the state where the value of the award number counter 74e is "0" is maintained. After that, as shown in FIG. 93(i), when the port output process is executed at the timing of t2, as shown in FIG. state continues. After that, when the game is started at the timing of t3 as shown in FIG. 93(f), the light-off data ("255") is set in the grant number counter 74e as shown in FIG. 93(c). After that, when the port output process is executed at the timing t4 as shown in FIG. 93(i), the display of the given number ends on the combined display section 66 as shown in FIGS. 93(a) and 93(b). At the same time, the dual-purpose display section 66 is put into a completely extinguished state.

Thereafter, as shown in FIG. 93(d), the first acceleration period for the reels 32L, 32M, and 32R starts at timing t5, and ends at timing t6. At the timing t6 when the first acceleration period ends, the grant number counter 74e is cleared to "0" as shown in FIG. 93(c). After that, when the port output process is executed at the timing t7 as shown in FIG. 93(i), as shown in FIGS. , display of the given number is started on the combined display section 66 . After that, at the timing of t8, the operation of the stop buttons 42-44 is validated. After that, at the timing of t9, the winning determination process is executed as shown in FIG. 93(h). is maintained at "0". After that, even if the port output process is executed at the timing t10 as shown in FIG. continue to exist.

As described above, in a game in which display corresponding to the stop order is not executed on the combined display section 66, when a bet operation or medal insertion is performed, the combined display section 66 displays the awarded number of "00". At the same time, the award determination process (step S5319) is executed in a state where the display of the awarded number of "00" is being executed on the dual-use display unit 66. FIG. By temporarily turning off the combined display section 66 at the start of the game, the combined display section 66 displays the given number of "00" over a period from before the start of the game to after the end of the game. It is possible to prevent the continuation of the state where the By changing the display mode of the combined display section 66 at the start of the game, it is possible to grasp that the game has started based on the display mode of the combined display section 66 .

Result of lottery process (FIG. 18) for a winning combination in a configuration in which the dual-purpose display section 66 is completely extinguished at timing t7, which is timing before timing t8 at which operation of the stop buttons 42 to 44 is validated. Regardless of this, a process for turning the dual-use display unit 66 into the all-off state is executed. For this reason, at the timing t3, which is the timing before the timing at which the winning lottery process (FIG. 18) is executed, the dual-use display unit 66 is put into a completely extinguished state (set extinguishing data to the given number counter 74e process) can be executed. As a result, it is possible to ensure a long duration of the all-lights-out state.

According to this embodiment detailed above, the following excellent effects are obtained.

The main MPU 72 puts the dual-use display section 66 into the all-light-off state on the condition that the light-off data ("255") is set in the number counter 74e. The given number counter 74e is a counter in which information about the given number of game media is set, and is a counter in which light-off data for turning the dual-purpose display section 66 into a completely light-off state is set. For this reason, in addition to the number counter 74e to which information on the number of game media to be given is set, the main RAM 74 has a flag or the like set with information indicating that it is time to turn the dual-purpose display section 66 into the all-off state. Compared to the set configuration, the data capacity of the storage area provided in the main side RAM 74 so that the main side MPU 72 can grasp the number of game media to be given and the timing of turning off the dual-use display section 66 can be reduced.

In the game in which display corresponding to the stop order is executed on the dual-purpose display unit 66, in a state where the dual-use display unit 66 is in the all-light-off state, the process of clearing the given number counter 74e to "0" (the process of step S5304) is executed. As a result, the state in which the light-off data is set in the given number counter 74e can be ended, and the processing for executing the stop order corresponding display on the combined display unit 66 in the next port output processing (FIG. 91). is executed. By executing the process for executing the display corresponding to the stop order in the next port output process, the display corresponding to the stop order is executed on the dual-purpose display section 66 from the state where the dual-use display section 66 is in the all-off state. switch to the state where For this reason, as a process different from the process of clearing the value of the number counter 74e to which the light-off data is set to "0" (the process of step S5304), in the next port output process, Compared to the configuration in which the processing for executing the processing for executing the corresponding display is set, the dual-purpose display unit 66 is displayed in the stop order from the state in which the dual-purpose display unit 66 is completely turned off. It is possible to simplify the processing configuration for switching to a state in which display is being performed.

In a game in which display corresponding to the stop order is not executed on the dual-purpose display unit 66, a process (step S5304) of clearing the given number counter 74e to "0" is executed in a state where the dual-purpose display unit 66 is in a completely unlit state. Thus, the state in which the light-off data is set in the given number counter 74e can be ended, and the given number display (display of "00") can be displayed on the shared display section 66 in the next port output process (FIG. 91). It can be in a state in which a process for execution is executed. By executing the processing for displaying the assigned number in the next port output process, the dual-purpose display unit 66 changes from the state in which the dual-use display unit 66 is completely turned off to the state in which the assigned number is being displayed on the dual-use display unit 66. switch to For this reason, as a process separate from the process of clearing the value of the given number counter 74e in which the extinguished data is set to "0" (the process of step S5304), the combined display unit 66 displays the given number in the next port output process. Compared to the configuration in which the processing for executing the processing for executing the display is set, the display of the given number on the dual-purpose display unit 66 from the state where the dual-purpose display unit 66 is completely turned off. The processing configuration for switching to the running state can be simplified.

Since the combined display unit 66 is temporarily turned off at the start of the game, the combined display unit 66 continues to display the given number of "00" before and after the game starts. You can prevent it from being lost. By changing the display mode of the combined display section 66 at the start of the game, it is possible to grasp that the game has started based on the display mode of the combined display section 66 .

In a game in which display corresponding to the order of stopping is not executed on the combined display unit 66, when a bet operation or a medal is inserted, the combined display unit 66 displays the awarded number of "00". Winning judgment processing (step S5319) is executed in a state in which the display of the awarded number of "00" is executed on the dual-purpose display section 66. FIG. By temporarily turning off the dual-use display unit 66 at the start of the game, the multi-purpose display unit 66 displays the number of ``00'' to be awarded over the period from before the start of the game to after the end of the game. It is possible to prevent the continuation of the state where the

In the configuration in which the dual-use display unit 66 is completely extinguished at a timing prior to the timing at which the operation of the stop buttons 42 to 44 is activated, the dual-use display is displayed regardless of the result of the lottery process (FIG. 18). A process for turning the unit 66 into the all-lights-out state is executed. Therefore, it is possible to execute the processing for turning the dual-purpose display section 66 into the all-light-out state at the timing before the timing at which the winning lottery processing (FIG. 18) is executed. As a result, it is possible to ensure a long duration of the all-lights-out state.

<Eighth embodiment>
In the present embodiment, on the condition that the display corresponding to the stopping order is not executed on the combined display section 66, the combined display section 66 is temporarily turned off when the acceleration control of the reels 32L, 32M, and 32R is started. is different from the seventh embodiment. The configuration different from that of the seventh embodiment will be described below. Note that the description of the same configuration as that of the seventh embodiment is basically omitted.

As already explained in the seventh embodiment, the conditions for executing the stop order corresponding display on the combined display unit 66 are that the gaming state is the pseudo-bonus state ST4 or the AT state ST5 and the number of bets is "3". Winning an index value IV from "1" to "9" in the lottery process (FIG. 18) for a certain game combination. In the all-light-off state, the left 7-segment display 66a and the right 7-segment display 66b of the combined display section 66 are not displayed, as in the seventh embodiment. As already described in the first embodiment, in a game in which display corresponding to stopping order is performed on the combined display unit 66, the image display device 63 performs stopping order notification.

As already described in the seventh embodiment, the condition for the dual-use display section 66 to be in the all-light-off state is that the number counter 74e of the main side RAM 74 is set to "255", which is the light-off data. The fully extinguished state of the dual-purpose display section 66 occurs only during the period in which the game is being executed. When the dual-purpose display unit 66 is set to the all-lights-out state, the main MPU 72 sets the number-of-lights-off counter 74e of the main RAM 74 to "255", as in the seventh embodiment. As a result, the processing (steps S5401, S5402, and S5411) for turning the dual-purpose display unit 66 into the all-off state can be executed in the next port output processing (FIG. 91).

As described above, if the execution condition of the display corresponding to the stop order on the combined display section 66 is not satisfied, the combined display section 66 is temporarily turned off when the acceleration control of the reels 32L, 32M, and 32R is started. As in the seventh embodiment, when the previous game ends without winning a small winning combination, the value of the awarded number counter 74e becomes "0" and the value of the awarded number counter 74e on the combined display unit 66 becomes "0". A corresponding number display of "00" is executed. After that, even if a bet operation or medal insertion for starting the game is performed, the state where the value of the award number counter 74e is "0" is continued, and the value of the award number counter 74e is displayed on the combined display unit 66. The display of the assigned number of "00" corresponding to is continued. As in the first embodiment, in a game in which display corresponding to stop order is not executed on the combined display unit 66, reel control processing is performed in a state where the combined display unit 66 displays the awarded number of "00". Winning determination processing (FIG. 26) is executed in step S1015 (FIG. 22). In a game in which display corresponding to the stop order is not executed, if the display mode of the dual-purpose display unit 66 is not changed during the period from the start of the game to the winning determination process (FIG. 26), when a minor win is not established in the game. 2, the value of the given number counter 74e continues to be "0", and the shared display unit 66 continues to display the given number of "00" corresponding to the value of the given number counter 74e. In this way, in a game in which display corresponding to the stop order is not executed on the dual-purpose display unit 66, if the display mode of the dual-purpose display unit 66 is not changed during the period from the start of the game to the winning determination process (FIG. 26), the game can be started. The state in which "00" is displayed on the dual-purpose display unit 66 continues from the beginning until the end of the game, and it may not be possible to grasp that the game has started based on the display of the dual-purpose display unit 66. occur. On the other hand, if the conditions for executing the display corresponding to the order of stopping on the combined display section 66 are not met, the combined display section 66 is temporarily turned off at the start of the acceleration control of the reels 32L, 32M, 32R. With this configuration, the state in which "00" is displayed on the dual-purpose display unit 66 is continued over the period from when the betting operation or medal insertion is performed until when the winning determination process (FIG. 26) is performed. You can prevent it from being lost. As a result, in a game in which stop order corresponding display is not executed on the dual-purpose display section 66, the display mode of the dual-purpose display section 66 can be changed in a mode corresponding to the start of the game.

FIG. 94(a) is an explanatory diagram for explaining the configuration of the main RAM 74. FIG. As shown in FIG. 94(a), the main RAM 74 is provided with a light-off time counter 74δ. The light-off time counter 74 δ is a counter that enables the main MPU 72 to grasp the end timing of the all-light-off state in the combined display section 66 . The extinguishing time counter 74δ consists of 1 byte. When the main MPU 72 sets the number counter 74e to "255", which is the extinguishing data, it sets the extinguishing time counter 74δ to "221" as information on the duration of the all extinguished state. "221" is numerical information for setting the all-lights-out state to approximately 330 milliseconds. As already described in the first embodiment, timer interrupt processing (FIG. 11) is executed at a cycle of 1.49 milliseconds, and timer subtraction processing is executed in step S208 of the timer interrupt processing. The details of the timer subtraction process (FIG. 95) in this embodiment will be described later, but the value of the light-off time counter 74δ is updated by subtracting 1 in the timer subtraction process, and the light-off data is set in the given number counter 74e. It becomes "0" after about 330 milliseconds from the set timing.

As already described in the first embodiment, the reel control process (FIG. 22) is executed in step S408 of the normal process (FIG. 13). In this embodiment, the acceleration period during which the reels 32L, 32M, and 32R are accelerated is approximately 300 milliseconds. As already described in the first embodiment, in the reel control process (FIG. 22), when the acceleration period of the reels 32L, 32M, and 32R ends (step S1002: YES), the stop buttons 42 to 44 are operated. Activated. Further, as already described in the first embodiment, in the reel control process (FIG. 22), when a stop command is issued to any of the reels 32L, 32M, 32R, the reels 32L, 32M, A reel stop process (step S1012) is executed to stop the rotation of the reels 32L, 32M, and 32R in a state where the symbol number of the arrival symbol of 32R and the symbol number of the stop symbol are equal. In the reel stop processing, stopping excitation pulses are output to the reels 32L, 32M, and 32R to be stopped. Specifically, in a configuration in which excitation pulses for one-phase excitation and two-phase excitation are output in acceleration control and constant-speed rotation control of the reels 32L, 32M, and 32R, in the reel stop processing (step S1012), excitation for stopping is performed. As a pulse, an excitation pulse of four-phase excitation having a weaker excitation force than the one-phase excitation and two-phase excitation is output. The state in which the stopping excitation pulse is output continues for 100 interrupts (approximately 149 milliseconds) of the timer interrupt process (FIG. 11).

As already described in the first embodiment, in the winning determination process (FIG. 26) executed in step S1015 of the reel control process (FIG. 22), if any minor win is established (step S1204: YES), the information of the number of awards corresponding to the minor win is set in the number of awards counter 74e of the main RAM 74 (step S1205). By executing the port output process (FIG. 91) in a state in which the information of the given number is set in the given number counter 74e, display of the given number on the combined display section 66 is started. If any of the minor wins is established in the game in which display corresponding to the stop order is not executed on the dual-purpose display section 66, a state in which the combined display section 66 displays the awarded number of "00" → the dual-purpose display section 66 are all extinguished → state in which the combined display unit 66 displays the awarded number of "00" → the combined display unit 66 displays the awarded number corresponding to the established minor winning combination. The display mode of the dual-use display unit 66 changes in order of the state of being present. In addition, in the winning determination process (FIG. 26), if none of the small wins is won in a game in which the display corresponding to the stop order is not executed, the value of the awarded number counter 74e is maintained at "0". , the state in which the display of the assigned number of "00" is executed on the combined display section 66 is maintained. In this way, in the case where none of the minor wins is established in the game in which the display corresponding to the stop order is not executed on the combined display unit 66, the state where the awarded number display of "00" is executed on the combined display unit 66 → Combined The display mode of the dual-purpose display unit 66 changes in the order of the state in which the display unit 66 is in the all-off state→the state in which the dual-purpose display unit 66 is executing the number display of “00”.

Next, the lottery result handling process executed by the main MPU 72 will be described with reference to the flowchart of FIG. 94(b). As already described in the first embodiment, the lottery result handling process is executed in step S914 of the winning lottery process (FIG. 18).

In the lottery result handling process, the same processes as steps S1101 to S1106 of the lottery result handling process (FIG. 25) in the first embodiment are executed in steps S5501 to S5506. Specifically, if the current gaming state is the pseudo-bonus state ST4 (step S5501: YES) or if it is the AT state ST5 (step S5502: YES), the value of the bet number setting counter 74b in the main side RAM74 is "3" (step S5503). If the value of the bet number setting counter 74b is "3" (step S5503: YES), that is, if the number of bets for this game is "3", refer to the index value counter 74f in the main RAM 74. It is determined whether or not any of the index values IV of "1" to "9" has been won in the lottery process (FIG. 18) (step S5504).

When an affirmative determination is made in step S5504, the value of the index value counter 74f is set in the stop order type counter 74m of the main side RAM 74 (step S5505). At step S5505, one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m, so that the stop order number is displayed on the shared display unit 66 in the next port output process (FIG. 91). A state can be set in which the processing for executing correspondence display (the processing of steps S5403 to S5405 and step S5411) is executed. By executing the processing for executing the stop order correspondence display in the next port output processing, the display content on the dual-purpose display unit 66 is set to the stop order type counter 74m from the number display of "00" The stop order display corresponding to one of the stop order classification numbers from 1 to 9 is displayed. The process of step 5505 is the process of setting one of the stop order classification numbers "1" to "9" in the stop order classification counter 74m, and the state in which the combined display unit 66 is displaying the given number. This is a process for switching from to a state in which display corresponding to the stop order is being executed. Therefore, in addition to the processing of step S5505 for setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m, the combined display unit 66 performs Compared to the configuration in which the process for switching from the state in which the number of grants is displayed to the state in which the display corresponding to the stop order is performed, the stop order type counter 74m has a value of "1" to "9". It is possible to simplify the processing configuration for setting one of the stopping order type numbers and switching from the state in which the number of grants is being displayed on the combined display unit 66 to the state in which the corresponding stopping order is being displayed. .

If a negative determination is made in step S5502, step S5503, or step S5504, that is, if it is specified that the stop order corresponding display is not executed on the combined display unit 66, the value of the stop order type counter 74m is set to "0". ' is cleared (step S5506). As a result, the current game is a game in which the stop order correspondence display on the combined display unit 66 and the stop order notification on the image display device 63 are not executed.

After that, "255", which is extinguishing data, is set in the given number counter 74e (step S5507). As a result, the processing (steps S5401, S5402, and S5411) can be executed to set the dual-purpose display unit 66 to the all-off state in the next port output processing (FIG. 91). In the next port output process, the dual-purpose display section 66 is changed from the state in which the dual-purpose display section 66 is displaying the assigned number of "00" by executing the process to turn the dual-purpose display section 66 into the all-off state. is switched to a state in which all lights are turned off. The process of step S5507 is a process of setting the extinguishing data (“255”) to the number counter 74e to be given, and changing the display number of “00” on the dual-purpose display unit 66 to is a process for switching to a state in which all lights are turned off. Therefore, in addition to the process of step S5507 for setting the extinguishing data to the number counter 74e to be given, as a separate process from the process of step S5507, the display of the given number of "00" is executed on the combined display unit 66. Compared to the configuration in which the dual-use display unit 66 is set to switch to a state in which it is all turned off, the number of “00”s given by the dual-purpose display unit 66 is set to the number of lights off data in the given number counter 74e. It is possible to simplify the processing configuration for switching from the state in which display is being performed to the state in which the dual-use display unit 66 is in the all-off state.

After that, numerical information "221" corresponding to the duration of the all-lights-out state (approximately 330 milliseconds) is set in the light-out time counter 74δ of the main RAM 74 (step S5508). Thereby, about 330 milliseconds can be set as the duration of the total extinguishing time in the combined display section 66 . As described above, the value of the light-off time counter 74δ is updated by subtracting 1 in the timer subtraction process (FIG. 95) described later, and after about 330 milliseconds from the timing when the light-off data is set in the number counter 74e to be applied, " 0”. When the process of step S5505 or step S5508 is performed, the starting command flag provided in the main side RAM 74 is set to "1" (step S5509), and the lottery result corresponding process is terminated.

In this way, when the execution condition of the display corresponding to the stop order on the dual-purpose display unit 66 is not satisfied (when a negative determination is made in step S5502, step S5503, or step S5504), the dual-purpose display unit 66 is completely closed. Processing (processing of step S5507) for turning off the light is executed. On the other hand, if the execution condition for display corresponding to the stop order on the combined display unit 66 is met (step S5501 or step S5502: YES, step S5503: YES, step S5504: YES), the combined display unit 66 is turned off. Therefore, the process (step S5507) is not executed, and the process (step S5505) is executed for executing the stop order corresponding display on the combined display unit 66. FIG.

In this configuration, the dual-purpose display unit 66 is set to a completely extinguished state when the conditions for executing the display corresponding to the stop order in the dual-purpose display unit 66 are not satisfied. As already explained, in the reel control process (FIG. 22), operation of the stop buttons 42 to 44 is validated based on the end of the acceleration period of the reels 32L, 32M, 32R. The dual-purpose display unit 66 is configured to be in a completely extinguished state regardless of the presence or absence of the stop order correspondence display on the dual-purpose display unit 66, and the timing at which the operation of the stop buttons 42 to 44 is validated or before the timing. If the display corresponding to the stop order is started at the timing, it becomes necessary to end the all-light-off state at the timing when the operation of the stop buttons 42 to 44 is activated or at the timing before the timing. On the other hand, if the condition for executing the display corresponding to the order of stopping is not satisfied on the dual-purpose display unit 66, the dual-purpose display unit 66 is set to the completely extinguished state, thereby accelerating the reels 32L, 32M, and 32R. Regardless of the timing at which the operation of the stop buttons 42 to 44 is activated after the period ends, the end timing of the all-light-off state on the combined display section 66 can be set.

If the conditions for execution of the stop order correspondence display are satisfied (step S5501 or step S5502: YES, step S5503: YES, step S5504: YES), one of the stop order classification numbers "1" to "9" is stopped. The order classification counter 74m is set (step S5505), and the dual-use display section 66 is set to perform the process for executing the stop order correspondence display in the next port output process (FIG. 91). Then, when the next port output process is executed, the dual-purpose display unit 66 is switched from the state in which all lights are off to the state in which the dual-purpose display unit 66 is displaying the corresponding stop order. Therefore, in a game in which display corresponding to the stop order is executed on the combined display section 66, even if the processing for turning the combined display section 66 into the all-off state is not executed when the acceleration control of the reels 32L, 32M, and 32R is started. Prevents the state in which "00" is displayed on the dual-use display unit 66 from being continued until the winning determination process (FIG. 26) is executed after the bet operation or medal insertion is performed. can. Thus, the display mode of the dual-purpose display section 66 can be changed in a mode corresponding to the start of the game on the dual-purpose display section 66 .

Next, the timer subtraction process executed by the main MPU 72 will be described with reference to the flowchart of FIG. As already explained, the timer subtraction process is executed in step S208 of the timer interrupt process (FIG. 11).

In the timer subtraction process, if the value of the light-off time counter 74δ (FIG. 94(a)) in the main RAM 74 is greater than or equal to "1" (step S5601: YES), the value of the light-off time counter 74δ is subtracted by 1 (step S5602). ), and it is determined whether or not the value of the extinguishing time counter 74δ after the subtraction of 1 is "0" (step S5603).

If an affirmative determination is made in step S5603, that is, if the continuation time of the all-lights-out state on the dual-use display unit 66 has ended, the value of the given number counter 74e is cleared to "0" (step S5604). As already described, in the lottery result handling process (Fig. 94(b)), when it is specified that the display corresponding to the stopping order is not executed on the combined display unit 66 (negative determination is made in step S5502, step S5503 or step S5504) is performed), the light-off data is set in the given number counter 74e (step S5507), and numerical information "221" corresponding to the duration of the all light-off state is set in the light-off time counter 74δ ( step S5508). Therefore, the state in which an affirmative determination is made in step S5601 is the state in which the light-off data is set in the grant number counter 74e. The process of step S5604 is a process executed in a state where the light-off data is set in the grant number counter 74e. 74e can end the state in which the light-off data is set, and the processing for executing the number display of "00" on the shared display unit 66 in the next port output processing (FIG. 91) (step S5409). to step S5411) can be executed. In the next port output process, by executing the processing for executing the number display of "00", "00" is added to the combined display unit 66 from the state where the combined display unit 66 is completely turned off. Switches to the state in which number display is being executed. The process of step S5604 is a process of clearing the light-off data set in the number counter 74e to be given, and displaying the number of "00" to be given on the dual-purpose display section 66 from the state in which the dual-purpose display section 66 is completely turned off. is a process for switching to the state in which is being executed. For this reason, in addition to the processing of step S5604 for clearing the light-off data set in the number counter 74e to be applied, as a separate processing from the step S5604, the dual-use display unit 66 In comparison with the configuration in which the processing for switching to the state in which the given number display is being executed is set, the light-off data set in the given number counter 74e is cleared and the combined display unit 66 is in the all-off state It is possible to simplify the processing configuration for switching from the state in which the display unit 66 is displaying the given number. On the other hand, in a game in which display corresponding to the stop order is executed on the dual-use display unit 66, even if the value of the number-of-charges counter 74e is cleared to "0" in step S5604, the value of the stop-order type counter 74m is set to "1" to "9". Since the state in which one of the stop order classification numbers is set is maintained, the state in which the stop order handling process is being executed on the combined display unit 66 is continued.

When a negative determination is made in step S5601, when a negative determination is made in step S5603, or when the process of step S5604 is performed, another timer subtraction process is executed (step S5605), and this timer End the subtraction process. In other timer subtraction processing (step S5605), the value of each counter and timer other than the turn-off time counter is subtracted.

In this way, the light-off data set in the grant number counter 74e in a game in which display corresponding to the stop order is not executed on the dual-purpose display unit 66 can be obtained when the value of the light-off time counter 74δ in the main RAM 74 becomes "0". cleared based on Then, the port output process (FIG. 91) is executed in a state in which the extinguishing data set in the provision number counter 74e is cleared. is switched to a state in which the display of the given number of "00" is executed.

The timing at which the first (first) stop command is generated varies according to the operation timing of the stop buttons 42 to 44 by the player, but the timing at which the all-lights-out state ends is when the first stop command is generated. Not affected by timing. Therefore, the numerical value information ("221") corresponding to the duration of the all-lights-out state (approximately 330 milliseconds) is set to the light-out time counter 74δ, and 1 is set to 1 at the timing before approximately 330 milliseconds have elapsed. When the first stop command is generated, the first stop command is generated when about 330 milliseconds have elapsed since the numerical information corresponding to the duration of the all-lights-out state was set in the light-out time counter 74δ. , and when the first stop command is generated at a timing after about 330 milliseconds have elapsed since the numerical information corresponding to the duration of the all-lights-out state was set in the light-out time counter 74δ. Also, the duration of the all-off state can be fixed at about 330 milliseconds. As a result, it is possible to prevent the duration of the all-lights-out state from being shortened due to the timing of the generation of the first stop command, and in any case, the player or the manager of the game hall can recognize the In this manner, the dual-purpose display section 66 can be brought into a fully extinguished state.

Next, the manner in which the dual-purpose display section 66 is turned off in a game in which the dual-purpose display section 66 does not perform stop order display will be described with reference to the time chart of FIG. FIG. 96(a) shows a period in which the dual-purpose display unit 66 is in a fully extinguished state, FIG. 96(b) shows a period during which the number of grants is displayed on the dual-purpose display unit 66, and FIG. 96(d) shows the acceleration period of the reels 32L, 32M and 32R, and FIG. 96(e) shows the betting operation in the state where the game is not executed. 96(f) shows the timing at which the lottery result handling process (FIG. 94(b)) is executed, and FIG. 96(g) shows the operation of the stop buttons 42-44. is activated, FIG. 96(h) shows the timing at which the stop control of the first reel ends, and FIG. 96(i) shows the winning determination at step S1015 of the reel control process (FIG. FIG. 96(j) shows the timing at which the port output process (FIG. 91) is executed. In this specification, the stop control of the first reel is the stop control of the reel for which the first (first) stop command is generated among the left reel 32L, middle reel 32M and right reel 32R.

At the timing of t1 when the value of the award number counter 74e is "0" and the award number display of "00" is executed on the combined display unit 66, as shown in FIG. When medals are inserted, the value of the award number counter 74e is maintained at "0". After that, as shown in FIG. 96(j), when the port output process is executed at the timing of t2, as shown in FIG. continue to exist.

After that, the game is started, and when the lottery result corresponding process is executed as shown in FIG. 96(f) at the timing of t3, as shown in FIG. ) is set. After that, as shown in FIG. 96(d), the acceleration period of the reels 32L, 32M and 32R is started at the timing of t4. After that, at the timing of t5, when the port output process is executed as shown in FIG. 96(j), as shown in FIGS. 00”) is being executed to a state in which the dual-use display section 66 is completely turned off.

Thereafter, at timing t6, the acceleration period of the reels 32L, 32M, 32R ends as shown in FIG. 96(d), and the operation of the stop buttons 42 to 44 is enabled as shown in FIG. 96(g). be. After that, at timing t7 when the continuation period (approximately 330 milliseconds) of the all-lights-off state in the combined display section 66 elapses, the value of the given number counter 74e is cleared to "0" as shown in FIG. 96(c). As a result, no light-off data is set in the provision number counter 74e. After that, at timing t8, when the port output process is executed as shown in FIG. 96(j), the dual-purpose display section 66 is in a state in which all lights are extinguished as shown in FIGS. 96(a) and (b). , the combined display unit 66 switches to a state in which the display of the given number (display of "00") is executed. The period (approximately 330 milliseconds) in which the extinguishing data is set in the number-of-provided tokens counter 74e is approximately 30 milliseconds longer than the acceleration period (approximately 300 milliseconds) of the reels 32L, 32M, and 32R. After the process of setting the light-off data in the number counter 74e (the process of step S5507 in the lottery result handling process (FIG. 94(b))) is executed, the process of accelerating the reels 32L, 32M, and 32R (reel control The processing (step S1001 in FIG. 22) is executed, but the difference (about 30 mm) between the period in which the extinguishing data is set in the number counter 74e and the acceleration period of the reels 32L, 32M, and 32R seconds) is longer than the period from the timing t3 when the process of setting the extinguishing data to the number counter 74e is executed to the timing t4 when the acceleration control of the reels 32L, 32M, and 32R is started. Therefore, after the acceleration control of the reels 32L, 32M, and 32R is completed, the state in which the extinguishing data is set in the number-of-delivery counter 74e ends.

After that, as shown in FIG. 96(h), the stop control of the first reel ends at the timing of t9. As already explained, it takes at least about 149 milliseconds (the period during which the excitation pulse of the four-phase excitation is output) to stop the reels 32L, 32M, and 32R. The total period (at least approximately 449 milliseconds) of the acceleration period (approximately 300 milliseconds) of the reels 32L, 32M, and 32R and the period (at least approximately 149 milliseconds) required for the stop control of the first reel is determined by the grant number counter. 74e for which the light-off data is set (approximately 330 milliseconds) and the period from the end of this period to the execution of port output processing (approximately 1.49 milliseconds at maximum). 331.5 milliseconds). Further, the timing t4 at which the acceleration control of the reels 32L, 32M, and 32R is started is the timing after the timing t3 at which the extinguishing data is set in the number-of-dealing counter 74e. Therefore, the timing t8 at which the all-lights-out state on the combined display section 66 ends is earlier than the timing t9 at which the stop control for the first reel ends.

After that, as shown in FIG. 96(i), the winning determination process (FIG. 26) is executed at the timing of t10. As described above, the stop control of the first reel ends after the timing t8 when the all-lights-out state of the dual-purpose display section 66 ends and the display of the awarded number of "00" on the dual-purpose display section 66 starts. Then, between the timing t9 when the stop control of the first reel ends and the timing t10 when the winning determination process specifies whether or not a minor winning combination is established, the second reel and the third reel reel stop control is executed. In this specification, the stop control of the second reel refers to the stop control of the reel for which the second stop command is generated among the left reel 32L, the middle reel 32M and the right reel 32R. The reel stop control is the stop control of the reel for which the last (third) stop command is issued among the left reel 32L, middle reel 32M and right reel 32R. The total period of the period (approximately 149 milliseconds) during which the stop control is executed for the second reel and the period (approximately 149 milliseconds) during which the stop control is executed for the third reel is approximately 298 milliseconds. For this reason, at least the period during which the stop control of the second reel is executed (approximately 149 milliseconds) is the time during which the combined display unit 66 displays the number of "00" to be given after the end of the all-light-out state. And the total period (about 298 milliseconds) of the period (about 149 milliseconds) during which the stop control of the third reel is executed can be secured. This makes it easier for the player or the manager of the game hall to grasp the display of the given number of "00".

As shown in FIG. 96(i), when it is determined in the winning determination process executed at the timing of t10 that none of the minor wins has been established, the value of the awarded number counter 74e is "0". is maintained. After that, at the timing of t11, even if the port output process is executed as shown in FIG. 96(j), the combined display unit 66 will display the assigned number of "00" as shown in FIG. 96(b). state continues.

As described above, during the period from the bet operation or medal insertion to the execution of the lottery result handling process (FIG. 94(b)) (timing t1 to timing t3), the combined display unit 66 displays "00". is executed. If the display corresponding to the stopping order is not executed, the combined display section 66 is temporarily turned off at the start of the acceleration control of the reels 32L, 32M, 32R. During the period from the end of the all-lights-out state to the execution of the prize determination process (FIG. 26) (timing t8 to timing t10), the combined display unit 66 displays the awarded number of "00". In this way, in a game in which display corresponding to the stop order is not executed on the dual-use display unit 66, when none of the small wins is won, the display of the awarded number of "00" is executed on the dual-use display unit 66. The display mode of the dual-purpose display section 66 changes in the order of →the state in which the dual-purpose display section 66 is completely turned off→the state in which the dual-purpose display section 66 displays the number of “00” to be given. Based on the fact that a bet operation or a medal is inserted, the combination display unit 66 displays the number of awards "00", and also displays the number of awards "00" on the combination display unit 66. In the configuration in which the winning judgment process (FIG. 26) is executed in the state, the combined display section 66 is temporarily turned off at the start of the acceleration control of the reels 32L, 32M, 32R, so that the betting operation or medal insertion can be performed. It is possible to prevent continuation of the state in which the display of the awarded number of "00" is executed on the combined display unit 66 over the period from the execution until the execution of the prize determination process (FIG. 26). As a result, even in a game in which stop order corresponding display is not executed on the dual-purpose display section 66, the display mode of the dual-purpose display section 66 can be changed in a mode corresponding to the start of the game.

The timing t8 at which the dual-purpose display section 66 is completely turned off is a timing after the timing t6 at which the operation of the stop buttons 42 to 44 is enabled after the acceleration period of the reels 32L, 32M, and 32R is completed. be. For this reason, compared to the configuration in which the dual-use display unit 66 is completely turned off at the timing when the operation of the stop buttons 42 to 44 is activated or at a timing before that timing, the dual-use display unit 66 is in the all-off state. You can set a longer period of time. As a result, it is possible for the player or the manager of the game hall to easily grasp the all-light-off state of the combined display section 66 .

In the configuration in which the dual-use display unit 66 is completely extinguished at a timing (timing t8) after the timing (timing t6) at which the operation of the stop buttons 42 to 44 is validated, there is only one all-extinguishing state. It ends at the timing (timing t8) before the timing t9 at which the stop control of the eye reel ends. For this reason, at least the period during which the stop control of the second reel is executed (approximately 149 milliseconds) is the time during which the combined display unit 66 displays the number of "00" to be given after the end of the all-light-out state. And the total period (about 298 milliseconds) of the period (about 149 milliseconds) during which the stop control of the third reel is executed can be secured. This makes it possible for the player or the manager of the game hall to easily grasp the display of the given number of "00".

The fully extinguished state of the combined display section 66 ends at a timing after the timing at which the operation of the stop buttons 42 to 44 is activated and at a timing before the timing at which the stop control of the first reel ends. do. Therefore, in a game in which display corresponding to the stop order is not executed on the dual-use display unit 66, the state in which the dual-purpose display unit 66 is in the all-lights-out state, and the winning judgment process (FIG. 26) after the all-lights-out state is completed. It is possible to create a state in which the display of the given number of "00" is executed on the dual-use display unit 66 until the execution of , in such a manner that the player and the manager of the game hall can recognize it.

According to this embodiment detailed above, the following excellent effects are obtained.

In a game in which the dual-purpose display unit 66 does not display the display corresponding to the stop order, the dual-purpose display unit 66 displays the awarded number of "00" based on the bet operation or medal insertion, and the dual-purpose display. In the configuration in which the award determination process (FIG. 26) is executed while the award number display of "00" is being executed in the unit 66, the combined display unit 66 is temporarily displayed when the acceleration control of the reels 32L, 32M, 32R is started. By automatically turning off all lights, the combined display unit 66 displays the number of "00" to be awarded over the period from the bet operation or medal insertion to the execution of the prize determination process (FIG. 26). It is possible to prevent the state in which is being executed from continuing. As a result, in a game in which stop order corresponding display is not executed on the dual-purpose display section 66, the display mode of the dual-purpose display section 66 can be changed in a mode corresponding to the start of the game.

The processing (step S5507) for temporarily putting the dual-purpose display unit 66 into the all-lights-out state is executed when it is specified that the dual-purpose display unit 66 does not perform the display corresponding to the stop order. Therefore, the end timing of the all-light-out state can be set independently of the timing at which the operation of the stop buttons 42 to 44 is validated after the acceleration period of the reels 32L, 32M, 32R ends. By adopting a configuration in which the fully extinguished state of the combined display unit 66 ends at a timing later than the timing at which the operation of the stop buttons 42 to 44 is validated, the timing at which the operation of the stop buttons 42 to 44 is validated or Compared to the configuration in which the dual-purpose display section 66 is completely extinguished at a timing earlier than this timing, the period in which the dual-purpose display section 66 is in the all-extinguishing state can be set longer. This makes it possible for the player or the manager of the game hall to easily grasp the all-light-off state of the combined display section 66 .

In a configuration in which the all-light-out state of the dual-use display section 66 ends at a timing after the timing at which the operation of the stop buttons 42 to 44 is validated, the all-light-out state is the timing at which the stop control of the first reel ends. ends at a timing earlier than For this reason, at least the period during which the stop control of the second reel is executed (approximately 149 milliseconds) is the time during which the combined display unit 66 displays the number of "00" to be given after the end of the all-light-out state. And the total period (about 298 milliseconds) of the period (about 149 milliseconds) during which the stop control of the third reel is executed can be secured. This makes it easier for the player or the manager of the game hall to grasp the display of the given number of "00".

The fully extinguished state of the combined display section 66 ends at a timing after the timing at which the operation of the stop buttons 42 to 44 is activated and at a timing before the timing at which the stop control of the first reel ends. do. Therefore, in a game in which display corresponding to the stop order is not executed on the dual-use display unit 66, the state in which the dual-purpose display unit 66 is in the all-lights-out state, and the winning judgment process (FIG. 26) after the all-lights-out state is completed. It is possible to create a state in which the display of the given number of "00" is executed on the dual-use display unit 66 until the execution of , in such a manner that the player and the manager of the game hall can recognize it.

The processing (step S5507) for turning off the dual-purpose display unit 66 when the acceleration control of the reels 32L, 32M, and 32R is started is executed in the game in which the dual-purpose display unit 66 does not perform display corresponding to the stop order. On the other hand, it is not executed in the game in which the stop order correspondence display is executed. In the game in which the display corresponding to the stopping order is executed, the stopping order type counter 74m is displayed at a timing before the timing at which the operation of the stop buttons 42 to 44 is validated based on the result of the lottery process (FIG. 18). is set to one of the stop order classification numbers "1" to "9", and the port output process (FIG. 28) is executed. As a result, the dual-purpose display unit 66 switches from the state in which the display of the assigned number of "00" is executed to the state in which the dual-purpose display unit 66 displays the stop order corresponding display corresponding to the stop order type number. For this reason, in a game in which display corresponding to the stop order is executed, even if the processing for turning off the combined display section 66 at the start of the acceleration control of the reels 32L, 32M, and 32R is not executed, the bet operation or the medal insertion can be performed. It is possible to prevent the state in which "00" is displayed on the dual-purpose display section 66 from continuing until the winning determination process (FIG. 26) is executed after is performed. As a result, the display mode of the combined display section 66 can be changed in a mode corresponding to the start of the game when the game is started.

<Ninth Embodiment>
This embodiment differs from the first embodiment in that non-leading display indicating that the display corresponding to the stopping order is not performed is performed on the combined display unit 66 in the game in which the display corresponding to the stopping order is not performed. ing. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

FIG. 97(a) is an explanatory diagram for explaining the display mode of the non-guidance display on the combined display section 66. FIG. As shown in FIG. 97(a), in the non-guidance display, the right 7-segment display 66b displays a display indicating that the stop order display is not executed, and the left 7-segment display 66b displays 66a becomes a non-display state. In this way, in a game in which the dual-use display unit 66 does not display the display corresponding to the order of stopping, the dual-use display unit 66 is configured to perform the non-leading display. It is possible to make it easy to identify that the game is not played.

As already described in the first embodiment, the main-side ROM 73 stores the stop order display data table 73a, and the stop order display data table 73a stores stop numbers "1" to "9". Display data for the stop order corresponding display corresponding to the order type number is set. Further, in the present embodiment, display data for non-guide display corresponding to the non-guide data of "10" is set in the stop order display data table 73a. When the main MPU 72 performs non-leading display on the shared display unit 66, the main MPU 72 reads the stop order display data table 73a, sets the display data for the non-guided display in the right side shared display unit display area 74q, and sets the display data for the left side shared display unit 74q. Non-display data is set in the display section display area 74p. By outputting the display data and the non-display data set in the dual-purpose display section display areas 74p and 74q to the dual-purpose display section 66, non-guide display is performed on the dual-purpose display section 66. FIG.

FIG. 97(b) explains the conditions under which the non-leading display is executed, the conditions under which the stop order correspondence display is executed, the conditions under which the ratio display is executed, and the conditions under which the given number display is executed on the dual-use display unit 66. It is an explanatory diagram for. As shown in FIG. 97(b), the dual-use display unit 66 displays a state in which the non-leading display is being executed, a state in which the display corresponding to the stop order is being executed, and a given number display are displayed during the period in which the game is being executed. In addition to a state in which the game is not being executed, a state in which the ratio display is being executed or a state in which the awarded number is being displayed is entered. Here, the period during which the game is being executed is the period during which the in-game flag of the main RAM 74 is set to "1", and the period during which the game is not being executed is the value of the during-game flag. is "0".

During the period in which the game is being executed, the combined display unit 66 performs non-leading display on the condition that the stop order type counter 74m of the main RAM 74 is set to "10", which is non-leading data. be. The non-induction data is set in the stop order type counter 74m when it is determined in the lottery result handling process (FIG. 97(c)) to be described later that the game does not display the stop order correspondence on the combined display unit 66. be done. During the period in which the game is being executed, the combined display is provided under the condition that one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m in the main side RAM 74. A stop order correspondence display is performed in a section 66 . As already described in the first embodiment, the stop order type counter 74m is cleared to "0" in step S1208 of the winning determination process (FIG. 26). As a result, when the non-leading display has been performed on the combined display unit 66, the non-guided display ends and the given number display is started, and the combined display unit 66 performs the display corresponding to the stop order. If it is, the display corresponding to the stop order ends and the display of the given number starts.

During a period in which the game is not being executed, ratio display is executed on the dual-purpose display unit 66 on condition that the calculation result data of any one of "0" to "100" is set in the ratio display counter 74n. be. Stop order type numbers of "1" to "9" and non-induction data of "10" are set in the stop order type counter 74m during both the period in which the game is being executed and the period in which the game is not being executed. On the condition that the ratio display counter 74n is not set to the calculation result data of "0" to "100", the dual-purpose display section 66 displays the given number.

The period during which the stop order type number of one of "1" to "9" or the non-induction data of "10" is set in the stop order type counter 74m occurs during execution of the game. finish. On the other hand, as already described in the first embodiment, the ratio display counter 74n displays the calculation result of "0" to "100" when the ratio display start operation is performed while the game is not being executed. Data is set. Therefore, the stop order type counter 74m is set to one of the stop order type numbers "1" to "9" or the non-induction data "10", and the ratio display counter 74n is set to "0" to " 100” will not be duplicated.

As described above, in the main MPU 72, when one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m, the combined display unit 66 displays the stop order correspondence. In addition, when the stop order type counter 74m is set to "10", which is the non-guide data, the combined display unit 66 is configured to perform non-guide display. The stop order type counter 74m is a counter in which a stop order type number from "1" to "9" is set, and non-leading data (" 10") is the counter that is set. For this reason, in addition to the stop order type counter 74m in which the stop order type number is set, the main side MPU 72 can grasp the state in which non-leading display should be executed by the combined display section 66 in the main side RAM 74. The data capacity of the storage area provided in the main-side RAM 74 for executing the non-guided display on the dual-use display unit 66 can be reduced compared to a configuration in which a flag or the like is provided for the display.

As described above, when the execution condition for the display corresponding to the stop order on the combined display section 66 is not satisfied, the combined display section 66 performs the non-leading display at the start of the acceleration control of the reels 32L, 32M, and 32R. As in the seventh embodiment, when the previous game ends without winning a small winning combination, the value of the awarded number counter 74e becomes "0" and the value of the awarded number counter 74e on the combined display unit 66 becomes "0". A corresponding number display of "00" is executed. After that, even if a bet operation or medal insertion for starting the game is performed, the state where the value of the award number counter 74e is "0" is continued, and the value of the award number counter 74e is displayed on the combined display unit 66. The display of the assigned number of "00" corresponding to is continued. In a game in which the dual-use display unit 66 does not display the order corresponding to the stopping order, if the display mode of the dual-use display unit 66 is not changed during the period from the start of the game to the winning determination process (FIG. 26), it is possible to win a minor role in the game. is not established, the state where the value of the given number counter 74e is "0" is continued, and the shared display unit 66 indicates the given number of "00" corresponding to the value of the given number counter 74e. Display continues. In this way, in a game in which display corresponding to the stop order is not executed on the dual-purpose display unit 66, if the display mode of the dual-purpose display unit 66 is not changed during the period from the start of the game to the winning determination process (FIG. 26), the game can be started. The state in which "00" is displayed on the dual-purpose display unit 66 continues from the beginning until the end of the game, and the start of the game cannot be grasped based on the display of the dual-purpose display unit 66. occur. On the other hand, when the execution condition of the display corresponding to the order of stopping on the combined display section 66 is not satisfied, the combined display section 66 executes the non-leading display at the start of the acceleration control of the reels 32L, 32M and 32R. As a result, the state in which "00" is displayed on the dual-purpose display unit 66 is continued over the period from when the bet operation or medal insertion is performed until when the prize determination process (FIG. 26) is performed. You can prevent it from slipping. As a result, it is possible to recognize that the game has started based on the display mode of the dual-purpose display unit 66 even in a game in which the dual-purpose display unit 66 does not display the stop order correspondence.

As already described in the first embodiment, in a game in which display corresponding to the order of stopping is executed, the reels 32L, 32M, and 32R are stopped on the combined display section 66 at a timing prior to the timing at which the acceleration control of the reels 32L, 32M, and 32R is started. Forward correspondence display is performed. As a result, the display content on the dual-use display unit 66 changes from the display of the assigned number of "00" to the stop order correspondence display corresponding to one of the stop order classification numbers "1" to "9" set in the stop order classification counter 74m. switch to Therefore, in a game in which display corresponding to the stop order is executed on the dual-purpose display unit 66, the dual-purpose display unit 66 is displayed for a period from the bet operation or medal insertion to the execution of the prize determination process (FIG. 26). It is possible to prevent the state in which "00" is displayed in 66 from continuing. Accordingly, it is possible to recognize that the game has started based on the display mode of the dual-purpose display section 66 .

FIG. 97(c) is a flow chart showing lottery result correspondence processing executed by the main MPU 72. FIG. As already described in the first embodiment, the lottery result handling process is executed in step S914 of the winning lottery process (FIG. 18).

In the lottery result handling process, in steps S5701 to S5705, the same processes as steps S1101 to S1105 of the lottery result handling process (FIG. 25) in the first embodiment are executed. Specifically, if the current gaming state is the pseudo-bonus state ST4 (step S5701: YES) or if it is the AT state ST5 (step S5702: YES), the value of the bet number setting counter 74b in the main side RAM 74 is " 3” (step S5703). When the value of the bet number setting counter 74b is "3" (step S5703: YES), that is, when the bet number of this game is "3", refer to the index value counter 74f of the main side RAM74. It is determined whether or not any of the index values IV of "1" to "9" has been won in the lottery process (FIG. 18) (step S5704).

When an affirmative determination is made in step S5704, the value of the index value counter 74f is set in the stop order type counter 74m in the main RAM 74 (step S5705). As a result, in the next port output process (FIG. 98), the dual-purpose display unit 66 can be put into a state in which the process for executing the stop order corresponding display is executed. By executing the processing for executing the display corresponding to the stop order in the next port output processing, the display corresponding to the stop order is executed from the state in which the display of the assigned number of "00" is being executed on the combined display unit 66. switch to the state of The process of step S5705 is a process of setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m, and a state in which the combined display unit 66 is displaying the given number. This is a process for switching from to the state in which the display corresponding to the stop order is being executed. Therefore, in addition to the processing of step S5705 for setting one of the stop order type numbers "1" to "9" in the stop order type counter 74m, the combined display unit 66 Compared to the configuration in which the processing for switching from the state in which the number of grants is displayed to the state in which the display corresponding to the stop order is performed, the stop order type counter 74m has a value of "1" to "9". It is possible to simplify the processing configuration for setting one of the stopping order type numbers and switching from the state in which the number of grants is being displayed on the combined display unit 66 to the state in which the corresponding stopping order is being displayed. . As already described with reference to FIG. 24(b) in the first embodiment, lottery processing for a game combination in which the pseudo-bonus state ST4 or AT state ST5 and the number of bets is "3" (FIG. 18) , the stop order type counter 74m is set to "n" ("n" is any integer from "1" to "9"). As a result, the display contents of the display corresponding to the stop order on the dual-use display unit 66 become the display corresponding to the n-th stop order.

If a negative determination is made in step S5702, step S5703, or step S5704, the stop order type counter 74m is set to "10", which is non-leading data for performing non-leading display on the combined display unit 66 ( step S5706). As a result, in the next port output process (FIG. 98), the combined display section 66 can perform the process for performing the non-guided display. By executing the processing for executing the non-leading display in the next port output processing, the non-leading display is executed from the state where the display of the assigned number of "00" is being executed on the combined display unit 66. You can switch to the The process of step S5706 is a process of setting the non-induction data of "10" to the stop order type counter 74m, and the non-induction display is executed from the state in which the number of grants is being displayed on the combined display unit 66. This is the processing for switching to the state where the Therefore, in addition to the processing of step S5706 for setting the non-induction data of "10" to the stop order type counter 74m, display of the given number is executed on the combined display unit 66 as a separate processing from this processing. Compared to the configuration in which the processing for switching from the state to the state in which the non-induction display is executed is set, the non-induction data is set in the stop order type counter 74m and the number of grants is displayed on the combined display unit 66. It is possible to simplify the processing configuration for switching from the state in which the display is being performed to the state in which the non-guidance display is being performed.

When the process of step S5705 or step S5706 is performed, the start command flag of the main RAM 74 is set to "1", similarly to step S1107 of the lottery result corresponding process (FIG. 25) in the first embodiment. Then (step S5707), the lottery result handling process is terminated.

As described above, in the game in which the display corresponding to the stopping order is executed on the dual-use display unit 66, the stopping order type counter 74m indicates "1" at a timing before the timing at which the acceleration control of the reels 32L, 32M, and 32R is started. ” to “9”, the dual-use display unit 66 will be in a state in which processing for executing the stop order corresponding display is executed in the next port output processing. Further, in a game in which the display corresponding to the stopping order is not executed on the dual-use display unit 66, the stopping order type counter 74m indicates "10" at a timing before the timing at which the acceleration control of the reels 32L, 32M, and 32R is started. By setting the guidance data, the dual-purpose display unit 66 will be in a state where the process for executing the non-guidance display is executed in the next port output process.

In the game in which the stop order correspondence display is executed, the stop order correspondence display is executed on the combined display unit 66 based on the stop order number set in the stop order counter 74m, and the stop order correspondence display is executed. In order to end the display, the process of clearing the value of the stop order type counter 74m to "0" (the process of step S1208 in the winning determination process (FIG. 26)) is executed. In addition, in the game in which the display corresponding to the stop order is executed, the non-leading display is executed on the combined display unit 66 based on the non-leading data set in the stop order type counter 74m, and the non-leading display is executed. is executed to clear the value of the stop order type counter 74m to "0" (the process of step S1208 in the winning judgment process (FIG. 26)). The process of step S1208 in the winning determination process (FIG. 26) is a process executed to end the stop order display in a game in which the stop order display is executed, and is also executed in a game in which the stop order display is not executed. This is a process executed to end the non-guided display in . Therefore, compared to the configuration in which the processing for terminating the non-guided display is set as a separate processing from the processing for terminating the stop order responsive display, the stop order responsive display and the non-guided display are terminated. The processing configuration for this can be simplified.

Next, the port output processing executed by the main MPU 72 will be described with reference to the flow chart of FIG. As already explained in the first embodiment, port output processing is executed in step S211 of timer interrupt processing (FIG. 11).

In the port output process, as in step S1401 of the port output process (FIG. 28) in the first embodiment, the stop order type counter 74m of the main RAM 74 is set to one of the stop orders "1" to "9". It is determined whether or not a type number is set (step S5801). When the stop order type number of "1" to "9" is not set in the stop order type counter 74m (step S5801: NO), the stop order type counter 74m of the main side RAM 74 is set to "10" which is non-inductive data. is set (step S5802).

When one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m (step S5801: YES), or when non-induction data is set in the stop order type counter 74m If (step S5802: YES), the stop order display data table 73a stored in the main ROM 73 is read (step S5803), and the stop order classification counter 74m is set by referring to the read stop order display data table 73a. The display data corresponding to the value of are set in the dual display display areas 74p and 74q (step S5804). In step S5804, if any stop order number from "1" to "9" is set in the stop order type counter 74m, display data corresponding to the value of the stop order type counter 74m is displayed on the right side display section. The data for non-display is set in the area 74q and the data for non-display is set in the display area 74p for the left side. These display data and non-display data set in the dual-purpose display section display areas 74p and 74q are output to the dual-purpose display section 66 in step S5810, which will be described later. can do. Further, when the stop order type counter 74m is set to "10" which is non-leading data, the display data for non-leading display is set in the display area 74q for both right side and the data for non-display is set for both for left side. It is set in the display section display area 74p. The display data and the non-display data set in the dual-purpose display section display areas 74p and 74q are output to the dual-purpose display section 66 in step S5810, which will be described later, so that non-leading display is performed on the dual-purpose display section 66. be able to.

In steps S5805 to S5812, the same processes as steps S1404 to S1411 of the port output process (FIG. 28) in the first embodiment are executed. Specifically, after making a negative determination in step S5802, if any calculation result data of "0" to "100" is set in the ratio display counter 74n (step S5805: YES), The number display data table 73b stored in the main ROM 73 is read (step S5806). After that, referring to the number display data table 73b read in step S5806, the display data corresponding to the value of the ratio display counter 74n is set in the left side display area 74p and the right side display area 74q (step S5807). ). These display data set in the dual-purpose display section display areas 74p and 74q are output to the dual-purpose display section 66 in step S5810, which will be described later, so that the dual-purpose display section 66 can perform ratio display.

The stop order type number "1" to "9" and the non-induction data are not set in the stop order type counter 74m (step S5801: NO, step S5802: NO), and the ratio display counter 74n is set to "0". If the calculation result data of ~ "100" is not set (step S5805: NO), the processing for displaying the number of grants on the combined display unit 66 (processing of steps S5808 to S5809) Execute. Specifically, similarly to step S5806, the number display data table 73b stored in the main ROM 73 is read (step S5808), and the read number display data table 73b is referenced to set the value of the given number counter 74e. The corresponding display data is set in the left combined display section display area 74p and the right combined display section display area 74q (step S5809). These display data set in the combined display section display areas 74p and 74q are output to the combined display section 66 in step S5810, which will be described later, so that the combined display section 66 can display the given number.

When the processing of step S5804, step S5807 or step S5809 is performed, the data (display data or non-display data) set in the left side display area 74p and the right side display area 74q are displayed. Output to unit 66 (step S5810). As a result, when the non-display data is set in the left dual-purpose display section display area 74p and the display data for display corresponding to the stop order is set in the right dual-purpose display section display area 74q, the dual-purpose display section 66 display corresponding to the stop order is executed. In addition, when the non-display data is set in the left combined display section display area 74p and the display data for non-guide display is set in the right combined display section display area 74q, the combined display section 66 A guidance display is performed. Furthermore, when the non-display data or the display data for ratio display is set in the left dual-purpose display area 74p and the display data for ratio display is set in the right dual-purpose display area 74q, A ratio display is performed on the dual-use display unit 66 . Further, when the display data for displaying the given number is set in the shared display section display areas 74p and 74q, the shared display section 66 displays the given number.

Thereafter, display control processing for the credit display unit 65 is executed (step S5811), other port output processing is executed (step S5812), and this port output processing ends. Other port output processing in step S5812 outputs data corresponding to the I/O device from the input/output port.

Next, the manner in which the non-guidance display is executed on the combined display unit 66 will be described with reference to the time chart of FIG. FIG. 99(a) shows a period during which non-leading display is performed on the dual-purpose display unit 66, and FIG. FIG. 99(c) shows a period in which non-induction data "10" is set in the stop order type counter 74m. 99(e) shows the timing at which the game is started, FIG. 99(f) shows the timing at which the stop buttons 42 to 44 are activated, and FIG. 99(g) shows FIG. 99(h) shows the timing at which the winning determination process (FIG. 26) is executed, and the timing at which the port output process (FIG. 98) is executed.

At the timing of t1 when the value of the award number counter 74e is "0" and the award number display of "00" is being executed on the combined display unit 66, a bet operation or the first bet operation is performed as shown in FIG. When medals are inserted, the state where the value of the award number counter 74e is "0" is maintained. After that, when the port output process is executed at the timing t2 as shown in FIG. continue to exist.

After that, the game is started at the timing t3 as shown in FIG. 99(e). Thereafter, as shown in FIG. 99(c), "10", which is non-induction data, is set in the stop order type counter 74m at the timing of t4. After that, at timing t5, port output processing is executed as shown in FIG. Switches from the display of the number of grants to non-induction display. After that, at the timing of t6, the operation of the stop buttons 42 to 44 is validated as shown in FIG. 99(f).

After that, at the timing of t7, the winning determination process (FIG. 26) is executed as shown in FIG. 99(g). The state where the value of 74e is "0" is maintained. Also, at the timing t7, as shown in FIG. 99(c), the value of the stop order type counter 74m is cleared to "0" by executing the process of step S1208 of the winning determination process (FIG. 26). . After that, at timing t8, port output processing is executed as shown in FIG. to display the number of grants of "00".

As described above, the combined display unit 66 displays the awarded number of "00" and the combined display unit 66 displays the awarded number of "00" based on the betting operation or medal insertion. Winning judgment processing (FIG. 26) is executed in the state where the game is played. In a game in which display corresponding to the order of stopping is not executed on the combined display unit 66, the combined display unit 66 is not guided at timing t4, which is the timing before the timing at which the acceleration control of the reels 32L, 32M, and 32R is started. Processing for executing display (processing for setting non-guided data in the stop order type counter 74m) is executed. As a result, the display of the awarded number of "00" is executed on the combined display unit 66 over the period from when the betting operation or medal insertion is performed until when the prize determination process (FIG. 26) is executed. It is possible to prevent continuation. Therefore, it is possible to recognize that the game has started based on the display mode of the dual-purpose display unit 66 even in a game in which the dual-purpose display unit 66 does not display the stop order correspondence.

According to this embodiment detailed above, the following excellent effects are obtained.

A state in which the combined display unit 66 displays the awarded number of "00" and the combined display unit 66 displays the awarded number of "00" based on the betting operation or medal insertion. In the configuration in which the prize determination process (FIG. 26) is executed in the combination display section 66, in a game in which the stop order corresponding display is not executed on the combination display section 66, when the acceleration control of the reels 32L, 32M, and 32R is started, the combination display section 66 is not displayed. A guidance display is performed. As a result, the display of the awarded number of "00" is executed on the combined display unit 66 over the period from when the betting operation or medal insertion is performed until when the prize determination process (FIG. 26) is executed. It is possible to prevent continuation. Therefore, it is possible to recognize that the game has started based on the display mode of the dual-purpose display unit 66 even in a game in which the dual-purpose display unit 66 does not display the stop order correspondence.

The main MPU 72 causes the dual-purpose display unit 66 to display the corresponding stop order when any one of the stop order type numbers "1" to "9" is set in the stop order type counter 74m. At the same time, when the stop order type counter 74m is set to "10" which is the non-guide data, the combined display unit 66 is configured to perform non-guide display. The stop order type counter 74m is a counter in which a stop order type number from "1" to "9" is set, and non-leading data for executing non-leading display on the combined display unit 66 is set. is a counter that For this reason, in addition to the stop order type counter 74m in which the stop order type number is set, the main side MPU 72 can grasp the state in which non-leading display should be executed by the combined display section 66 in the main side RAM 74. The data capacity of the storage area provided in the main-side RAM 74 for executing the non-guided display on the dual-use display unit 66 can be reduced compared to a configuration in which a flag or the like is provided for the display.

In the game in which the stop order correspondence display is executed, the stop order correspondence display is executed on the combined display unit 66 based on the stop order number set in the stop order counter 74m, and the stop order correspondence is displayed. In order to end the display, the process of clearing the value of the stop order type counter 74m to "0" (the process of step S1208 in the winning determination process (FIG. 26)) is executed. In addition, in the game in which the display corresponding to the stop order is executed, the non-leading display is executed on the combined display unit 66 based on the non-leading data set in the stop order type counter 74m, and the non-leading display is executed. is executed to clear the value of the stop order type counter 74m to "0" (the process of step S1208 in the winning judgment process (FIG. 26)). The process of step S1208 in the winning determination process (FIG. 26) is a process executed to end the stop order display in a game in which the stop order display is executed, and is also executed in a game in which the stop order display is not executed. This is a process executed to end the non-guided display in . Therefore, compared to the configuration in which the processing for terminating the non-guided display is set as a separate processing from the processing for terminating the stop order responsive display, the stop order responsive display and the non-guided display are terminated. The processing configuration for this can be simplified.

In a game in which display corresponding to the order of stopping is not performed on the dual-purpose display unit 66, the display corresponding to the order of stopping is not performed based on the display of the dual-purpose display unit 66 by configuring the dual-purpose display unit 66 to perform non-leading display. It can be made easy to identify that it is a game.

<Tenth Embodiment>
This embodiment differs from the above-described first embodiment in the processing content of the additional processing at the start and the program content for executing the additional processing at the start. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

As already described in the first embodiment, in the main MPU 72, the addition processing at the start is executed at step S2310 in the advantageous state processing (FIG. 40) at the start of the game. As in the first embodiment, the start-up addition process is executed in the AT state ST5. In the start-up addition processing in the present embodiment, the index value IV ("11") to which the first watermelon winning data is set and the index to which the second watermelon winning data is set in the winning lottery process (FIG. 18) Value IV (“12”), index value IV (“14”) set with first chance replay winning data, or index value IV (“15”) with second chance replay winning data set. If so, the first additional lottery table 73d (FIG. 43(a)) is selected as the lottery table to be referenced in the additional lottery. In addition, in the winning lottery process (FIG. 18), when the index value IV ("13") set with cherry winning data is won, the first addition lottery table is used as the reference lottery table in the addition lottery. A second additional lottery table 73e (FIG. 43(b)) that is more advantageous to the player than the lottery table 73d is selected.

FIG. 100 is an explanatory diagram of the contents of a program for adding processing at the time of start executed by the main MPU 72. As shown in FIG. As already described in the first embodiment, the start-up addition process is executed at step S2310 in the advantageous state process (FIG. 40) at the start of the game. As shown in FIG. 100, "1401" to "1409" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

Line numbers "1401" to "1405" are similar to line numbers "1301" to "1305" of the program for adding processing at start in the first embodiment (FIG. 69(b)). command is set. Specifically, the command "LD A, (INDXCNT)" is set at the line number "1401". "LD" is an LD instruction as a transfer instruction for 8-bit data, "A" is the A register 101b, and "(INDXCNT)" is the content specifying the index value counter 74f of the main RAM 74 as the transfer source. . By executing the instruction "LD A, (INDXCNT)" at the line number "1401", the data of the index value counter 74f is transferred to the A register 101b. As a result, when any of the index values IV of "1" to "17" is won in the winning lottery process (FIG. 18), the index value IV is set in the A register 101b, In the lottery process (FIG. 18), "0" is set in the A register 101b when none of the index values IV is won.

The command "SUB A, 0BH" is set at the line number "1402". "SUB" is a SUB instruction as an 8-bit data subtraction instruction, "A" is the A register 101b, and "0BH" is 1-byte numerical information indicating "11". As already explained, "11" is the minimum value of "11" to "15", which is the first lottery target range. By executing the instruction "SUB A, 0BH" at line number "1402", an operation is performed to subtract "11" from the value of the A register 101b, and the result of this operation is written to the A register 101b. . When a carry flag CF is set to "1" when a borrow to the most significant bit (seventh bit) occurs in the computation, the carry flag CF is set to "1", and If no borrowing occurs, the value of the carry flag CF becomes "0". As already described with reference to FIG. 69(a) in the first embodiment, if the value of the index value counter 74f is any of the first lottery target range "11" to "15", When the value of the A register 101b is less than "5" and the value of the index value counter 74f is not within the first lottery target range of "11" to "15", the value of the A register 101b is It becomes a value of "5" or more.

The command "CP A, 05H" is set at the line number "1403". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "05H" is 1-byte numerical information indicating "5". By executing the instruction "CP A, 05H" at the line number "1403", an operation of subtracting "5" from the value of the A register 101b is performed. As already described in the first embodiment, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. If the value of the A register 101b before the subtraction of "5" is less than "5", that is, if the value of the index value counter 74f is included in the first lottery target range ("11" to "15") , the value of the carry flag CF becomes "1" and the value of the jump flag JF becomes "1" as a result of borrowing to the most significant bit (the 7th bit among the 0th to 7th bits) in this operation. becomes. On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or more, that is, the value of the index value counter 74f is "0" to "10" and "16" which are not included in the first lottery target range. " to "17", the value of the carry flag CF is " 0", and the value of the jump flag JF also becomes "0". The operation result of subtracting "5" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 05H" is executed, the value of the A register 101b does not change. Therefore, the data stored in the A register 101b by subtracting "11" at line number "1402" can also be used at line number "1406", which will be described later.

A command "RET NC" is set at the line number "1404". "RET" is a RET instruction as an instruction to return from a subroutine, and "NC" is a content that sets the condition that the value of the carry flag CF is "0" as a condition for returning from the subroutine. . By executing the instruction "RET NC" at the line number "1404", the step of the advantageous state processing (FIG. 40) at the start of the game is performed on the condition that the value of the carry flag CF is "0". The process for addition at the start called in S2310 is ended, and the process returns to step S2311 following step S2310. As described above, the value of the index value counter 74f is any of "0" to "10" and "16" to "17" that are not included in the first lottery target range ("11" to "15"). In this case, the value of carry flag CF becomes "0" by executing the instruction of line number "1403". Therefore, by executing the command "RET NC" at the line number "1404", the addition process at the start is terminated, and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). . On the other hand, as described above, when the value of the index value counter 74f is included in the first lottery target range (“11” to “15”), the instruction of line number “1403” is executed to carry The value of the flag CF becomes "1". For this reason, even if the command "RET NC" is set in the line number "1404", the processing for addition at start will not end, and the process will proceed to the next line number "1405".

The command "LD HL, KSADD01" is set at the line number "1405". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD01" is the start address of the first addition lottery table 73d in the main ROM 73. be. The start address of the first addition lottery table 73d is transferred to the HL register 104 by executing the instruction "LD HL, KSADD01" at the line number "1405". As a result, the first additional lottery table 73d can be set as the lottery table to be referenced in the additional lottery. In this way, when the AT state ST5 is reached and the index value IV in the first lottery target range ("11" to "15") is won in the role lottery process (FIG. 18), the reference target A first additional lottery table 73d is set as the lottery table.

The command "CP A, 02H" is set at the line number "1406". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "02H" is 1-byte numerical information indicating "2". As described above, the A register 101b stores 1-byte numerical information calculated by subtracting "11" from the row number "1402". Specifically, when the value of the index value counter 74f is "13", the value of the A register 101b is "2", and the values of the index value counter 74f are "11", "12", and "14". or "15", the value of the A register 101b is "0", "1", "3" or "4". By executing the instruction "CP A, 02H" at the line number "1406", an operation of subtracting "2" from the value of the A register 101b is performed. When the value of the A register 101b before the subtraction of "2" is "2", that is, when the value of the index value counter 74f is "13", the result of the calculation becomes "0" and the zero flag ZF is set to "1". On the other hand, if the value of the A register 101b before the subtraction of "2" is not "2", that is, if the value of the index value counter 74f is "11", "12", "14" or "15", Since the calculation result of this calculation does not become "0", the value of the zero flag ZF becomes "0".

The command "JR NZ, ADR142" is set at the line number "1407". "JR" is a conditional jump instruction with a word length of 2 bytes; It specifies the program address "ADR142" of the line number "1409" as the jump destination program address. The instruction at line number "1407" is set to the program address "ADR141". In the JR instruction of line number "1407", a 2-byte jump destination program The address (ADR 142) is relatively specified. Compared to the configuration using the JP instruction with a word length of 3 bytes, the configuration for jumping to the program address of the jump destination using the JR instruction with a word length of 2 bytes makes it possible to jump to the program address at the jump destination. The data capacity of the machine language of the jump instruction is reduced. As described above, when the value of the index value counter 74f is "11", "12", "14" or "15", the value of the zero flag ZF is changed to "0". Therefore, the instruction "JR NZ, ADR142" is executed at line number "1407" to jump to the program address "ADR142" at line number "1409". On the other hand, as described above, when the value of the index value counter 74f is "13", the zero flag ZF is set to "1" by executing the instruction of the line number "1406". there is Therefore, even if the instruction "JR NZ, ADR142" is set in the line number "1407", the program address does not jump, and the program proceeds to the next line number "1408".

The command of the line number "1408" is executed when the player is in the AT state ST5 and the winning index value IV of "13" is won in the winning lottery process (FIG. 18). The command "LD HL, KSADD02" is set at the line number "1408". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second addition lottery table 73e in the main ROM 73. be. The start address of the second addition lottery table 73e is transferred to the HL register 104 by executing the instruction "LD HL, KSADD02" at the line number "1408". As a result, the lottery table to be referenced in the additional lottery can be changed to the second additional lottery table 73e. In this way, when the AT state ST5 is reached and the index value IV of "13" is won in the lottery process (FIG. 18), the lottery table to be referred to is the first additional lottery table 73d. The additional lottery table 73d is changed to a second additional lottery table 73e that is more advantageous for the player.

The instruction set at line number "1409" jumps from line number "1407" to the program address at line number "1409", or executes the instruction at line number "1408" to jump to line number "1409". Executed when advanced. Specifically, in the AT state ST5, the index value IV that is included in the first lottery target range ("11" to "15") and is not "13" in the role lottery process (Fig. 18) is won. If so, the JR instruction of line number "1407" jumps to the program address of line number "1409" and the instruction of line number "1409" is executed. Also, in the AT state ST5, when the index value IV of "13" included in the first lottery target range ("11" to "15") is won in the role lottery process (Fig. 18), , the instruction of line number "1409" is executed after the LD instruction of line number "1408" is executed.

The command "JP ADR133" is set at the line number "1409". "JP" is a JP instruction as an unconditional jump instruction with a word length of 3 bytes, and "ADR133" is set with an instruction for executing the processing of step S1802 in the unlock game number lottery processing (FIG. 35(b)). program address (2 bytes). By executing the instruction "JP ADR133" at the line number "1409", the program jumps to the program address "ADR133". Then, the process (lottery execution process) of steps S1802 to S1807 of the unlock game number lottery process (Fig. 35(b)) is executed, whereby the lottery for the remaining number of continuous games in the AT state ST5 is executed. . As already explained, it is in the AT state ST5, is included in the first lottery target range ("11" to "15") in the role lottery process (FIG. 18), and has an index value IV that is not "13". If the lottery is won, the additional lottery is executed with the first additional lottery table 73d set as the lottery table to be referred to. In addition, when the AT state ST5 and the index value IV of "13" included in the first lottery target range ("11" to "15") is won in the winning lottery process (Fig. 18) , the additional lottery is executed in a state in which the second additional lottery table 73e is set as the lottery table to be referred to.

The JP instruction at line number "1409" is an instruction for jumping to the program address "ADR133" after changing the lottery table to be referenced at line number "1408" to the second additional lottery table 73e. This instruction enables a jump to the program address of "ADR133" without fail when the JR instruction of number "1407" jumps to the program address of line number "1409". For this reason, after changing the lottery table to be referred to at line number "1408" to the second additional lottery table 73e, an instruction different from the instruction for jumping to the program address "ADR133" is executed at line number "1407". Compared to the configuration in which an instruction is set to reliably jump to the program address "ADR 133" when jumping with the JR instruction of , it is stored in the main ROM 73 in order to execute the additional processing at the start. The data capacity of the program can be reduced.

As already described, in the number-of-released-games lottery process (FIG. 35), after setting the number-of-released-games lottery table 73c as the lottery table to be referenced in step S1801, steps S1802 to S1807 are executed without calling the subroutine program. Lottery execution processing is executed. The lottery execution process (steps S1802 to step S1807) is a process executed after the process of step S1801 is executed in the unlocked game number lottery process (FIG. 35). ) is executed when jumping is performed by the JP instruction of line number “1409”. If the lottery execution process (steps S1802 to S1807) is configured to be a common subroutine called in the number-of-released-games lottery process (FIG. 35) and the start-up addition process (FIG. 100(a)), the number of unlocked games In the lottery process (FIG. 35), it is necessary to set a CALL instruction (3 bytes) for calling the lottery execution process after the instruction for executing the process of step S1801. In this configuration, a CALL instruction is set in place of the JP instruction at the line number "1409" of the start-up addition processing (FIG. 100(a)), but the word length (3 bytes) of the CALL instruction is It is the same as the word length (3 bytes) of the JP instruction. Therefore, if a common subroutine called lottery execution processing is called in the unlocked game number lottery process (FIG. 35) and the addition process at the start (FIG. 100(a)), then the unlocked game number lottery process (FIG. 35) The data capacity of the program stored in the main ROM 73 is increased by the amount of the set CALL command in order to execute the number-of-release-games lottery process (FIG. 35) and the extra process at the start (FIG. 100(a)). end up

In this embodiment, by executing the JP command "JP ADR133" at the line number "1409" of the process for addition at the start (Fig. 100(a)), the cancellation game number lottery process (Fig. 35(b)) is executed. The process configuration jumps to the program address (ADR133) where the instruction for executing the process of step S1802 is set, and the process of step S1801 is executed in the unlock game number lottery process (FIG. 35(b)). In this processing configuration, the processing of step S1802 is executed without calling the subroutine program when the subroutine program is called. For this reason, compared to a configuration in which a common subroutine called lottery execution processing is called in the number-of-released-games lottery process (FIG. 35) and the process for addition at start (FIG. 100(a)), the number-of-released-games lottery process (FIG. 35 ) and the processing for addition at the start (FIG. 100(a)), the data capacity of the program stored in the main ROM 73 can be reduced.

FIG. 100(b) is set to jump from the program address "ADR141" and the program address "ADR142" to the program address "ADR133" in the program for the additional processing at the start (FIG. 100(a)). FIG. 10 is an explanatory diagram for explaining a jump instruction; FIG. In the program for the addition processing at the start (Fig. 100(a)), the command "JP ADR133" is set at the line number "1409". As already explained, the JP instruction is a jump instruction with a word length of 3 bytes that designates the entire jump destination program address (2 bytes). Therefore, by using the JP instruction, it is possible to jump from the program address of "ADR142" where the JP instruction of line number "1409" is set to the program address of "ADR133". 100(a)) sets a JR instruction with a word length of 2 bytes to the line number "1407", jumps from the line number "1407" to the line number "1409", and executes the jump. This processing configuration jumps to the program address "ADR133" using the JP instruction set in the previous program address (ADR142).

FIG. 100(c) explains a jump instruction set to jump from the program address "ADR141" and the program address "ADR142" to the program address "ADR133" in the third comparative example of the process for addition at start. It is an explanatory view for doing. In the third comparative example (FIG. 100(c)) of the addition processing at the start, the command "JP NZ, ADR133" is set at the program address "ADR141". "JP" is a conditional jump instruction with a word length of 3 bytes; This is the contents of designating the program address "ADR133" as the jump destination program address. As already explained, by executing the instruction "CP A, 02H" at the line number "1406", the zero flag ZF is set to "1" when the value of the index value counter 74f is "13". be done. On the other hand, when the value of the index value counter 74f is "11", "12", "14" or "15", the value of the zero flag ZF becomes "0". When the value of the index value counter 74f is "11", "12", "14" or "15", the command "JP NZ, ADR133" is executed at line number "1407" to generate "ADR133". Jump directly to the program address. On the other hand, when the value of the index value counter 74f is "13", the process proceeds to the next line number "1408" without jumping.

As described above, the JP instruction at line number "1409" is an instruction for jumping to the program address "ADR133" after changing the lottery table to be referenced at line number "1408" to the second additional lottery table 73e. be. Therefore, even in a configuration in which line number "1407" directly jumps to the program address "ADR133", the JP instruction at line number "1409" cannot be omitted.

As shown in FIG. 100(c), in the third comparative example (FIG. 100(c)) of the additional processing at the start, a jump is made from the program address "ADR141" and the program address "ADR142" to the program address "ADR133". The total word length of the jump instruction set to do is 6 bytes. On the other hand, as shown in FIG. 100(b), in the program for additional processing at start (FIG. 100(a)), from the program address "ADR141" and the program address "ADR142" to the program address "ADR133" The total word length of the jump instruction set to jump to is 5 bytes.

As described above, the start-up addition process program (FIG. 100(a)) is executed by a JR instruction with a word length of 2 bytes on the condition that the value of the zero flag ZF is "0" at line number "1407". This processing configuration jumps to the number "1409" and jumps to the program address "ADR133" using the JP instruction set in the line number "1409" of the jump destination. As a result, as in the third comparative example (FIG. 100(c)) of the process for addition at the start, a word length of 3 bytes is obtained on the condition that the value of the zero flag ZF is "0" at the line number "1407". Reduce the total word length of the jump instruction set for jumping from the program address "ADR141" to the program address "ADR133" compared to the processing configuration in which the JP instruction jumps directly to the program address "ADR133". be able to. Therefore, it is possible to reduce the data capacity of the program (FIG. 100(a)) stored in the main ROM 73 for executing the start-up addition process.

According to this embodiment detailed above, the following excellent effects are obtained.

100(a)) executes a line number "1409" by a JR instruction with a word length of 2 bytes under the condition that the value of the zero flag ZF is "0" at the line number "1407". , and jumps to the program address "ADR133" using the JP instruction set in the jump destination line number "1409". As a result, as in the third comparative example (FIG. 100(c)) of the process for addition at the start, a word length of 3 bytes is obtained on the condition that the value of the zero flag ZF is "0" at the line number "1407". Reduce the total word length of the jump instruction set for jumping from the program address "ADR141" to the program address "ADR133" compared to the processing configuration in which the JP instruction jumps directly to the program address "ADR133". be able to. Therefore, it is possible to reduce the data capacity of the program (FIG. 100(a)) stored in the main ROM 73 for executing the start-up addition process.

<Eleventh Embodiment>
This embodiment differs from the above-described first embodiment in the processing content of the additional processing at the start and the program content for executing the additional processing at the start. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

FIG. 101(a) is an explanatory diagram for explaining a jump instruction execution circuit provided in the main MPU 72 in this embodiment. As shown in FIG. 101(a), the main MPU 72 includes the JP execution circuit 105 and the JR execution circuit 106 already described with reference to FIG. 61(a) in the first embodiment. The main MPU 72 can execute JP instructions and JR instructions as jump instructions. The main MPU 72 does not have the JRS execution circuit 107 in the first embodiment.

In this embodiment, the value of the carry flag CF does not change even if the JR instruction, which is a conditional jump instruction with a word length of 2 bytes, is executed. When the jump condition set in the JR instruction is satisfied and the program address of the jump destination is jumped to, the instruction set in the program address of the jump destination is executed while maintaining the value of the carry flag CF before the jump. can do. In addition, when the jump condition set in the JR instruction is not satisfied and the instruction set next to the JR instruction is proceeded to, the value of the carry flag CF is maintained while the value of the carry flag CF is set next to the JR instruction. can execute any instruction

The value of carry flag CF does not change even if the LD instruction as a 16-bit transfer instruction is executed. When an LD instruction (16-bit transfer instruction) is executed to proceed to the instruction set next to the LD instruction, the LD instruction is executed while maintaining the value of the carry flag CF before the LD instruction is executed. You can execute the command that is set next to .

As already described in the first embodiment, the addition process at the start is executed in step S2310 of the advantageous state process (FIG. 40) at the start of the game. The addition process at the start is executed in the AT state ST5. In this embodiment, the index value IV (“14”) in which the first chance replay winning data or the second chance replay winning data is set in the winning lottery process (FIG. 18) in the game executed in the AT state ST5 or "15"), the first additional lottery is executed, and the first watermelon winning data or the second watermelon winning data is obtained in the winning lottery process (FIG. 18) in the game executed in the AT state ST5. When the set index value IV ("11" or "12") is won, a second additional lottery is executed, and a cherry is selected in the winning lottery process (FIG. 18) in the game executed in the AT state ST5. A third extra lottery is executed when the index value IV (“13”) for which the winning data is set is won.

FIG. 101(b) is an explanatory diagram for explaining the configuration of the main-side ROM 73 for executing the additional lottery. As shown in FIG. 101(b), the main ROM 73 stores a first additional lottery table 73d selected as a reference lottery table in the first additional lottery, and a lottery table 73d selected as a reference lottery table in the second additional lottery. and a third addition lottery table 73h selected as a lottery table to be referred to in the third addition lottery.

As already described with reference to FIGS. 43(a) and 43(b) in the first embodiment, the first additional lottery table 73d and the second additional lottery table 73e have 10 games, 20 games and 50 games. The number of additional games is set. Further, "16" is set as the determination value in the first addition lottery table 73d, and "32" is set as the determination value in the second addition lottery table 73e. As in the first embodiment, when the first additional lottery is executed with the first additional lottery table 73d as a reference lottery table, 10 games are selected with a probability of 1/16, and the probability is 1/16. 20 games will be selected, 50 games will be selected with a probability of 1/16, and will be out with a probability of 13/16. Further, as in the first embodiment, when the second additional lottery is executed with the second additional lottery table 73e as the reference lottery table, 10 games are selected with a probability of 1/8, and the 10 games are selected with a probability of 1/8. 20 games are selected with a probability of , 50 games are selected with a probability of 1/8, and are out with a probability of 5/8. As in the first embodiment, the probability of winning the additional game number of 10 games, 20 games or 50 games in the second additional lottery table 73e is 10 games, 20 games or 50 games in the first additional lottery table 73d. It is set higher than the probability of winning the number of additional games. The second addition lottery table 73e is a lottery table more advantageous for the player than the first addition lottery table 73d.

FIG. 101(c) is an explanatory diagram for explaining the contents of the third addition lottery table 73h. As shown in FIG. 101(c), in the third addition lottery table 73h, 20 games, 40 games, and 80 games are set as the number of added games, and "32" is set as the determination value. When the third additional lottery is executed with the third additional lottery table 73h as a reference lottery table, 20 games are selected with a probability of 1/8, 40 games are selected with a probability of 1/8, and 40 games are selected with a probability of 1/8. 80 games will be selected with a probability of , and will be out with a probability of 5/8. The probability of winning 20 games, 40 games or 80 games in the third addition lottery table 73h is the same as the probability of winning 10 games, 20 games or 50 games in the second addition lottery table 73e. is. As described above, the second addition lottery table 73e is a lottery table that is more advantageous for the player than the first addition lottery table 73d, but the third addition lottery table 73h is more advantageous to the player than the second addition lottery table 73e. Advantageous lottery table.

Prior to the explanation of the start-up addition process (FIG. 102(a)), the contents of the process of selecting the addition lottery to be executed from among the first to third addition lotteries will be described. 102(a)) in the present embodiment, when the value of the index value counter 74f is any one of "11" to "15", the first additional lottery is used as the lottery table to be referred to. Select table 73d. After that, when it is determined that the value of the index value counter 74f is "11" or "12", the lottery table to be referred to is changed to the second additional lottery table 73e. As a result, the second addition lottery can be executed in steps S1802 to S1807 (lottery execution process) of the unlocked game number lottery process (FIG. 35(b)) already described in the first embodiment. Further, when it is determined that the value of the index value counter 74f is "13", the lottery table to be referred to is changed to the third additional lottery table 73h. As a result, the third additional lottery can be executed in steps S1802 to S1807 (lottery execution process) of the number-of-released-games lottery process (FIG. 35(b)). Furthermore, when the value of the index value counter 74f is "14" or "15", the state in which the first additional lottery table 73d is selected as the lottery table to be referred to is maintained. As a result, the first additional lottery can be executed in steps S1802 to S1807 (lottery execution process) of the number-of-released-games lottery process (FIG. 35(b)).

As already described with reference to FIG. 69(a) in the first embodiment, after the data of the index value counter 74f is transferred to the A register 101b, the operation of subtracting "11" from the value of the A register 101b is performed. When this is executed, if the winning index value IV is included in the numerical range of "11" to "15", the value obtained by shifting the index value IV to the smaller side by "11" is stored in the A register 101b. stored in The 1-byte numerical information stored in the A register 101b after the operation of subtracting "11" is "0" when the value of the index value counter 74f is "11", and the value of the index value counter 74f is "0". is "12", "2" if the value of the index value counter 74f is "13", and "3" if the value of the index value counter 74f is "14". , is "4" when the value of the index value counter 74f is "15". In the process for addition at the start of the present embodiment (FIG. 102(a)), the command "CP A, 02H" is executed at line number "1506" to be described later after executing the operation of subtracting "11". As a result, an operation of subtracting "2" from the value ("0" to "4") of the A register 101b is executed. The "2" is the minimum value ("0") and maximum value (" 4”).

FIG. 101(d) is an explanatory diagram for explaining the relationship between the value of the index value counter 74f and the values of the zero flag ZF and the carry flag CF after execution of the operation of subtracting "2". As shown in FIG. 101(d), in the row number "1506", the winning index value IV in which the first watermelon winning data or the second watermelon winning data is set in the winning lottery process (FIG. 18) is won. If the value of the index value counter 74f is "11" or "12", an operation of subtracting "2" from "0" or "1" stored in the A register 101b is executed. Borrowing to the most significant bit (the 7th bit among the 0th to 7th bits) occurs during execution of the operation. Therefore, the value of zero flag ZF becomes "0" and the value of carry flag CF becomes "1" after execution of the operation. The main MPU 72 changes the lottery table to be referred to to the second addition lottery table 73e based on the fact that the value of the zero flag ZF is "0" and the value of the carry flag CF is "1". This makes it possible to execute the second addition lottery.

In the row number "1506", when the index value IV for which cherry winning data is set in the lottery process (FIG. 18) is won, that is, when the value of the index value counter 74f is "13", An operation of subtracting "2" from "2" stored in the A register 101b is executed. The calculation result of this calculation is "0", and no borrowing to the most significant bit (seventh bit) occurs during execution of this calculation. Therefore, the value of the zero flag ZF becomes "1" and the value of the carry flag CF becomes "0" after the execution of the operation. The main MPU 72 changes the reference lottery table to the third additional lottery table 73h based on the fact that the value of the zero flag ZF is "1". This makes it possible to execute the third additional lottery.

In the line number "1506", when the winning index value IV for which the first chance replay winning data or the second chance replay winning data is set in the lottery process (FIG. 18), that is, the index value counter 74f is "14" or "15", an operation is performed to subtract "2" from "3" or "4" stored in the A register 101b. The calculation result of the calculation is "1" or "2", and no borrowing to the most significant bit (seventh bit) occurs during the execution of the calculation. Therefore, the value of the zero flag ZF and the value of the carry flag CF become "0" after execution of the operation. When the value of the zero flag ZF and the value of the carry flag CF are "0", the main MPU 72 maintains the state in which the first additional lottery table 73d is selected as the lottery table to be referred to. This makes it possible to execute the first additional lottery.

When the winning index value IV is "11" to "12", when the winning index value IV is "13", and when the winning index value IV is "14" to "15" Considering the configuration of performing an operation of subtracting "13" from the index value IV before subtracting "11" in order to specify which of the cases is, the value to be subtracted is "13". On the other hand, after performing a calculation to change the numerical range of "11" to "15" to the smaller side by "11" (calculation to subtract "11"), from the value after the calculation, "13" The value to be subtracted can be set to "2", which is a value smaller than "13", by performing an operation of subtracting "2", which is the value shifted to the smaller side by "11". . When the winning index value IV is '11' to '12', when the winning index value IV is '13', and when the winning index value IV is '14' to '15' The number of bits required to represent the value of "2" subtracted from the value obtained by shifting the index value IV downward by "11" is "2". Yes, and the number of bits is smaller than the number of bits ("4") required to represent the value "13" to be subtracted from the index value IV before the change. In this way, in a configuration in which the index value IV is subtracted by "11" in order to specify that the index value IV is included in the numerical range of "11" to "15", the index value IV is set to " If the index value before the change is "11" to "12", if the index value IV before the change is "13", and if the value after changing to the smaller side by 11" is used, In order to represent the value to be subtracted in the calculation for performing the determination by making a determination for specifying which of the cases the previous index value IV is "14" to "15" can be reduced. Thereby, the data capacity for storing the value can be reduced.

Next, the contents of the program for adding processing at the start executed by the main MPU 72 will be described with reference to the explanatory diagram of FIG. 102(a). As already explained, the addition processing at the start is executed in step S2310 of the advantageous state processing (FIG. 40) at the start of the game. As shown in FIG. 102(a), "1501" to "1511" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

Line numbers "1501" to "1505" contain instructions similar to line numbers "1301" to "1305" of the start-up addition process (FIG. 69(b)) in the first embodiment. is set. Specifically, the command "LD A, (INDXCNT)" is set at the line number "1501". "LD" is an LD instruction as a transfer instruction for 8-bit data, "A" is the A register 101b, and "(INDXCNT)" is the content specifying the index value counter 74f of the main RAM 74 as the transfer source. . By executing the instruction "LD A, (INDXCNT)" at the line number "1501", the data of the index value counter 74f is transferred to the A register 101b. As a result, when any of the index values IV of "1" to "17" is won in the winning lottery process (FIG. 18), the index value IV is set in the A register 101b, In the lottery process (FIG. 18), "0" is set in the A register 101b when none of the index values IV is won.

The command "SUB A, 0BH" is set at the line number "1502". "SUB" is a SUB instruction as an 8-bit data subtraction instruction, "A" is the A register 101b, and "0BH" is the minimum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating "11". By executing the instruction "SUB A, 0BH" at the line number "1502", an operation is performed to subtract "11" from the value of the A register 101b, and the result of the operation is written to the A register 101b. . When a carry flag CF is set to "1" when a borrow occurs in the most significant bit (7th bit) in the operation, the carry flag CF is set to "1", and If no borrowing occurs, the value of the carry flag CF becomes "0". As already described with reference to FIG. 69(a) in the first embodiment, when the value of the index value counter 74f is any one of "11" to "15", the value of the A register 101b is " 5” and the value of the index value counter 74f is any of “0” to “10” and “16” to “17” that are not included in “11” to “15” , the value of the A register 101b is "5" or more.

The command "CP A, 05H" is set at the line number "1503". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "05H" is the maximum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating a value (“5”) that is “1” larger than “4”, which is a value calculated by subtracting “11” from “15”. By executing the instruction "CP A, 05H" at the line number "1503", an operation of subtracting "5" from the value of the A register 101b is performed. As already described in the first embodiment, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. If the value of the A register 101b before the subtraction of "5" is less than "5", that is, if the value of the index value counter 74f is any of "11" to "15", the most significant bit in the operation The value of the carry flag CF becomes "1" due to the borrowing to the second bit (seventh bit), and the value of the jump flag JF also becomes "1". On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or more, that is, if the value of the index value counter 74f is "0" to "10" not included in "11" to "15", If the value is any one of "16" to "17", the value of the carry flag CF becomes "0" and the value of the carry flag CF becomes "0" because no borrowing to the most significant bit (seventh bit) occurs in the operation. , the value of the jump flag JF also becomes "0". The operation result of subtracting "5" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 05H" is executed, the value of the A register 101b does not change. Therefore, the data stored in the A register 101b by subtracting "11" at line number "1502" can also be used at line number "1506", which will be described later.

A command "RET NC" is set at the line number "1504". "RET" is a RET instruction as an instruction to return from a subroutine, and "NC" is a content that sets the condition that the value of the carry flag CF is "0" as a condition for returning from the subroutine. . By executing the instruction "RET NC" at the line number "1504", the step of the advantageous state processing (FIG. 40) at the start of the game is performed on the condition that the value of the carry flag CF is "0". The process for addition at the start called in S2310 is ended, and the process returns to step S2311 following step S2310. As described above, if the value of the index value counter 74f is any of "0" to "10" and "16" to "17" that are not included in "11" to "15", the line number " 1503" is executed, the value of the carry flag CF becomes "0". Therefore, by executing the command "RET NC" at the line number "1504", the addition process at the start is terminated, and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). . On the other hand, as described above, when the value of the index value counter 74f is any one of "11" to "15", the carry flag CF is set to "1" by executing the instruction of the line number "1503". ”. For this reason, even if the command "RET NC" is set in the line number "1504", the processing for addition at start will not end, and the process will proceed to the next line number "1505".

The command of line number "1505" is executed when the player is in AT state ST5 and one of the index values IV of "11" to "15" is won in the winning lottery process (FIG. 18). The command "LD HL, KSADD01" is set at the line number "1505". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD01" is the starting address of the first addition lottery table 73d in the main ROM 73. be. The start address of the first addition lottery table 73d is transferred to the HL register 104 by executing the instruction "LD HL, KSADD01" at the line number "1505". As a result, the first additional lottery table 73d can be set as the lottery table to be referred to in the additional lottery. In this way, when the AT state ST5 is set and any of the index values IV of "11" to "15" is won in the winning lottery process (FIG. 18), the lottery table to be referred to is first. A first addition lottery table 73d is set.

The command "CP A, 02H" is set at the line number "1506". "CP" is a CP instruction as an 8-bit data comparison instruction, and "A" is the A register 101b. "02H" is the minimum value ("0") and maximum value ("4 ”), which is 1-byte numerical information indicating “2” which is a numerical value other than “2”. As described above, the A register 101b stores 1-byte numerical information calculated by subtracting "11" from the row number "1502". Since the command of line number "1506" is executed when any of the index values IV of "11" to "15" is won in the winning lottery process (FIG. 18), the value of the A register 101b is Any of "0" to "4". By executing the instruction "CP A, 02H" at the line number "1506", an operation of subtracting "2" from the value of the A register 101b is performed. As already explained with reference to FIG. 101(d), when the value of the index value counter 74f is "11" or "12", the value from "0" or "1" stored in the A register 101b to "2" ' is performed. Borrowing to the most significant bit (the 7th bit among the 0th to 7th bits) occurs during execution of the operation. Therefore, the value of the zero flag ZF becomes "0" and the value of the carry flag CF becomes "1" after the execution of the operation. When the value of the index value counter 74f is "13", an operation of subtracting "2" from "2" stored in the A register 101b is executed. The calculation result of this calculation is "0", and no borrowing to the most significant bit (seventh bit) occurs during execution of this calculation. Therefore, the value of the zero flag ZF becomes "1" and the value of the carry flag CF becomes "0" after the execution of the operation. When the value of the index value counter 74f is "14" or "15", an operation is performed to subtract "2" from "3" or "4" stored in the A register 101b. The calculation result of the calculation is "1" or "2", and no borrowing to the most significant bit (seventh bit) occurs during the execution of the calculation. Therefore, the value of the zero flag ZF and the value of the carry flag CF become "0" after execution of the operation. As described above, if the index value before the change is between "11" and "12" using the value after the index value IV is changed to the smaller side by "11", the index value IV before the change is " 13” and the case where the index value IV before the change is between “14” and “15”. The number of bits to represent the value (“2”) to be subtracted in can be reduced. Thereby, the data capacity for storing the value can be reduced.

The command "JR NZ, ADR152" is set at the line number "1507". "JR" is a conditional jump instruction with a word length of 2 bytes; First, the program address of line number "1509" of "ADR152" is set. The instruction at line number "1507" is set to the program address "ADR151". As already explained, the range that can be jumped by the JR instruction is the range from "(the program address where the relevant JR instruction is set) + 2 - 128" to "(the program address where the relevant JR instruction is set) + 2 + 127". . As shown in FIG. 102(a), the word length of the instruction (LD instruction of line number "1508") set at the program address existing between the program addresses "ADR151" and "ADR152" is 3 bytes. "ADR152" is "(ADR151)+2+3", and is a program address that can be specified as a jump destination program address in the JR instruction based on the program address (ADR151) where the JR instruction of line number "1507" is set. is.

As described above, when the value of the index value counter 74f is "11", "12", "14" or "15", the value of the zero flag ZF is changed to "0". Therefore, the instruction "JR NZ, ADR152" is executed at line number "1507" to jump to the program address "ADR152" at line number "1509". On the other hand, as described above, when the value of the index value counter 74f is "13", the value of the zero flag ZF is "1" by executing the instruction of the line number "1506". Therefore, even if the instruction "JR NZ, ADR152" is set in the line number "1507", the program address does not jump, and the program proceeds to the next line number "1508".

The command of line number "1508" is executed when the player is in AT state ST5 and has won the index value IV of "13" in the winning lottery process (FIG. 18). A command "LD HL, KSADD03" is set at the line number "1508". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD03" is the third addition lottery table 73h (Fig. 101 ( b)) is the starting address. The start address of the third addition lottery table 73h is transferred to the HL register 104 by executing the instruction "LD HL, KSADD03" at the line number "1508". Thereby, the lottery table to be referred to can be changed from the first additional lottery table 73d to the third additional lottery table 73h. As already explained, the third additional lottery table 73h is a lottery table more advantageous for the player than the first additional lottery table 73d and the second additional lottery table 73e. In this way, when the AT state ST5 is reached and the winning index value IV of "13" is won in the combination lottery process (FIG. 18), the third extra lottery table is used as the lottery table to be referred to in the extra lottery. 73h is set.

The instruction set at line number "1509" is jumped to line number "1509" by the JR instruction of line number "1507", or when the LD instruction of line number "1508" is executed, line number "1509" Executed when proceeding to Specifically, in the AT state ST5, if the winning index value IV of "11", "12", "14" or "15" is won in the winning lottery process (FIG. 18), the row number The JR instruction of "1507" jumps to the program address of the line number "1509" and the instruction of the line number "1509" is executed. As already explained, the value of the carry flag CF does not change even if the JR instruction as a conditional jump instruction with a word length of 2 bytes is executed. Therefore, by executing the CP instruction of line number "1506", the instruction of line number "1509" is executed while maintaining the value set in the carry flag CF. As described above, when the index value IV of "11" or "12" is won, the value of the carry flag CF becomes "1" by executing the instruction of the line number "1506". When the index value IV of "14" or "15" is won, the value of the carry flag CF becomes "0" by executing the instruction of the line number "1506". In addition, in the AT state ST5, if the index value IV of "13" is won in the winning lottery process (FIG. 18), after executing the LD command of the line number "1508", the line number "1509" is executed. ' is executed. As already explained, the value of the carry flag CF indicates that the jump condition set in the JR instruction as a conditional jump instruction with a word length of 2 bytes is not satisfied, and the instruction set next to the JR instruction is reached. It is maintained when the LD instruction is executed as a 16-bit transfer instruction. Therefore, by executing the CP instruction of line number "1506", the instruction of line number "1509" is executed while maintaining the value set in the carry flag CF. As described above, when the "13" index value IV is won, the value of the carry flag CF becomes "0" by executing the instruction of the line number "1506".

The command "JR NC, ADR153" is set at the line number "1509". "JR" is a conditional jump instruction with a word length of 2 bytes; It is the contents of setting the program address of the line number "1511" of "ADR153" as the jump destination. As described above, the instruction at line number "1509" is set to the program address "ADR152". As already explained, the range that can be jumped by the JR instruction is the range from "(the program address where the relevant JR instruction is set) +2-128" to "(the program address where the relevant JR instruction is set) +2 + 127". . As shown in FIG. 102(a), the word length of the instruction (the LD instruction of line number "1510") set at the program address existing between the program addresses "ADR152" and "ADR153" is 3 bytes. "ADR153" is "(ADR152)+2+3", and is a program address that can be specified as a jump destination program address in the JR instruction based on the program address (ADR152) where the JR instruction of line number "1509" is set. is.

As described above, when the value of the index value counter 74f is any one of "13" to "15", the carry flag CF is maintained at "0". Therefore, by executing the instruction "JR NZ, ADR153" at the line number "1509", the program jumps to the program address "ADR153" at the line number "1511". On the other hand, as described above, when the value of the index value counter 74f is "11" or "12", the state where the value of the carry flag CF is "1" is maintained. Therefore, even if the instruction "JR NZ, ADR153" is set in the line number "1509", the program address does not jump, and the program proceeds to the next line number "1510".

The command of line number "1510" is executed when the player is in AT state ST5 and has won the index value IV of "14" or "15" in the winning lottery process (FIG. 18). The command "LD HL, KSADD02" is set at the line number "1510". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second addition lottery table 73e in the main ROM 73. be. The start address of the second addition lottery table 73e is transferred to the HL register 104 by executing the instruction "LD HL, KSADD02" at the line number "1510". Thereby, the lottery table to be referred to can be changed from the first additional lottery table 73d to the second additional lottery table 73e. As already explained, the second additional lottery table 73e is a lottery table more advantageous to the player than the first additional lottery table 73d and more disadvantageous to the player than the third additional lottery table 73h. In this way, when the AT state ST5 is reached and the winning index value IV of "11" or "12" is won in the winning lottery process (FIG. 18), the lottery table to be referred to in the additional lottery is the second lottery table. 2 addition lottery table 73e is set.

The instruction of line number "1511" jumps to the program address of line number "1511" by the JR instruction of line number "1509", or the LD instruction of line number "1510" is executed to jump to line number "1511". Executed when advanced. At the line number "1511", a command "JP ADR133" is set, like the line number "1309" of the process for addition at start (Fig. 69(b)) in the first embodiment. "JP" is a JP instruction as an unconditional jump instruction with a word length of 3 bytes, and "ADR133" is set with an instruction for executing the processing of step S1802 in the unlock game number lottery processing (FIG. 35(b)). program address (2 bytes). By executing the instruction "JP ADR133" at the line number "1511", the program jumps to the program address "ADR133". Then, one of the first to third addition lotteries is executed by executing the processes of steps S1802 to S1807 of the number-of-unlocked-games lottery process (FIG. 35(b)). As already explained, in the AT state ST5, if the winning index value IV of "14" or "15" is won in the combination lottery process (FIG. 18), the first lottery number is determined based on the first addition lottery table 73d. An additional lottery is executed, and when the index value IV of "11" or "12" is won in the winning lottery process (FIG. 18), the second additional lottery is executed based on the second additional lottery table 73e. Then, in the winning lottery process (FIG. 18), when the index value IV of "13" is won, the third addition lottery is executed based on the third addition lottery table 73h.

FIG. 102(b) is an explanatory diagram for explaining the contents of a program in the fourth comparative example of the addition processing at start. As shown in FIG. 102(b), "8201" to "8212" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

In the fourth comparative example of the addition processing at the start, the condition is that the index value IV of "11" to "15" is won in order to select the first to third addition lottery tables 73d, 73e, and 73h. After setting the start address of the second additional lottery table 73e in the HL register 104, when it is determined that the winning index value IV is "13" or more, the lottery table to be referred to is set to the second additional lottery table. 73e is changed to a third addition lottery table 73h, and when it is determined that the winning index value IV is "14" or more, the lottery table to be referred to is changed from the third addition lottery table 73h to the first addition lottery. This is the processing configuration for changing to the table 73d.

As shown in FIG. 102(b), in line number "8201" to line number "8204" in the fourth comparative example of the addition processing at start, the addition at start already described with reference to FIG. 102(a) Instructions similar to line numbers "1501" to "1504" of the processing are set. By executing the instruction "LD A, (INDXCNT)" at the line number "8201", the data of the index value counter 74f is transferred to the A register 101b. As a result, when any of the index values IV of "1" to "17" is won in the winning lottery process (FIG. 18), the index value IV is set in the A register 101b, In the lottery process (FIG. 18), "0" is set in the A register 101b when none of the index values IV is won. By executing the instruction "SUB A, 0BH" at the line number "8202", an operation is performed to subtract "11" from the value of the A register 101b, and the result of the operation is written to the A register 101b. . When the value of the index value counter 74f is any one of "11" to "15", the value of the A register 101b is less than "5", and the value of the index value counter 74f is "11" to "15". If it is any one of "0" to "10" and "16" to "17" that is not included in "15", the value of the A register 101b becomes "5" or more. By executing the instruction "CP A, 05H" at the line number "8203", an operation of subtracting "5" from the value of the A register 101b is performed. If the value of the A register 101b before the subtraction of "5" is less than "5", that is, if the value of the index value counter 74f is any of "11" to "15", the most significant bit in the operation The value of the carry flag CF becomes "1" due to borrowing to the second bit (seventh bit), and the value of the jump flag JF also becomes "1". On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or more, that is, if the value of the index value counter 74f is "0" to "10" which are not included in "11" to "15", If the value is any one of "16" to "17", the value of the carry flag CF becomes "0" and the value of the carry flag CF becomes "0" because no borrowing to the most significant bit (seventh bit) occurs in the operation. , the value of the jump flag JF also becomes "0".

By executing the command "RET NC" at the line number "8204", the step of the advantageous state processing (FIG. 40) at the start of the game is performed on the condition that the value of the carry flag CF is "0". The process for addition at the start called in S2310 is ended, and the process returns to step S2311 following step S2310. As described above, when the value of the index value counter 74f is one of "0" to "10" and "16" to "17", the carry flag is set by executing the instruction of line number "8203". The value of CF becomes "0". Therefore, by executing the command "RET NC" at the line number "8204", the addition process at the start is terminated, and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). . On the other hand, as described above, when the value of the index value counter 74f is any one of "11" to "15", the carry flag CF is set to "1" by executing the instruction of the line number "8203". ”. For this reason, even if the command "RET NC" is set in the line number "8204", the addition process at the start is not ended, and the process proceeds to the next line number "8205".

The command of line number "8205" is executed when the player is in AT state ST5 and one of the index values IV of "11" to "15" is won in the lottery process (FIG. 18). The command "LD HL, KSADD02" is set at the line number "8205". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second addition lottery table 73e in the main ROM 73. be. The start address of the second addition lottery table 73e is transferred to the HL register 104 by executing the instruction "LD HL, KSADD02" at the line number "8205". As a result, the second additional lottery table 73e is set as the lottery table to be referred to in the additional lottery.

In the line number "8206", a command "CP A, 02H" is set as in the line number "1506" of the process for addition at start (FIG. 102(a)). Since the instruction of line number "8206" is executed when any of the index values IV of "11" to "15" is won in the lottery process (FIG. 18), the value of the A register 101b is Any of "0" to "4". By executing the instruction "CP A, 02H" at the line number "8206", an operation of subtracting "2" from the value of the A register 101b is performed. When the value of the index value counter 74f is "11" or "12", an operation is performed to subtract "2" from "0" or "1" stored in the A register 101b. Borrowing to the most significant bit (seventh bit) occurs during execution of the operation. Therefore, the value of the carry flag CF becomes "1" after execution of the operation. On the other hand, when the value of the index value counter 74f is any one of "13" to "15", an operation of subtracting "2" from any one of "2" to "4" stored in the A register 101b is performed. executed. The calculation result of the calculation is any one of "0" to "2", and no borrowing to the most significant bit (seventh bit) occurs during the execution of the calculation. Therefore, the value of the carry flag CF becomes "0" after execution of the operation.

The command "JR C, ADR823" is set at the line number "8207". "JR" is a conditional jump instruction with a word length of 2 bytes; This is the contents of setting the program address of line number "8212" of "ADR823" as the jump destination. The instruction at line number "8207" is set to the program address "ADR821". "ADR823" is a program address that can be specified as a jump destination program address in the JR instruction based on the program address (ADR821) where the JR instruction of line number "8207" is set. As described above, when the value of the index value counter 74f is "11" or "12", the value of the carry flag CF is "1" by executing the instruction of the line number "8206". . Therefore, by executing the instruction "JR C, ADR823" at the line number "8207", the program jumps to the program address "ADR823" at the line number "8212". On the other hand, as described above, when the value of the index value counter 74f is any one of "13" to "15", the carry flag CF is set to "0" by executing the instruction of the line number "8206". ”. Therefore, even if the instruction "JR C, ADR823" is set in the line number "8207", the program address does not jump, and the program proceeds to the next line number "8208".

The command of line number "8208" is executed when the player is in AT state ST5 and one of the index values IV of "13" to "15" is won in the lottery process (FIG. 18). The command "LD HL, KSADD03" is set at the line number "8208". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD03" is the start address of the third addition lottery table 73h in the main ROM 73. be. The start address of the third addition lottery table 73h is transferred to the HL register 104 by executing the instruction "LD HL, KSADD03" at the line number "8208". As a result, the lottery table to be referenced in the additional lottery is changed from the second additional lottery table 73e to the third additional lottery table 73h.

The command "CP A, 03H" is set in the line number "8209". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "03H" is 1-byte numerical information indicating "3". Since the instruction of line number "8209" is executed when any of the index values IV of "13" to "15" is won in the winning lottery process (FIG. 18), the value of the A register 101b is Any of "2" to "4". By executing the instruction "CP A, 03H" at the line number "8209", an operation of subtracting "3" from the value of the A register 101b is performed. When the value of the index value counter 74f is "13", an operation of subtracting "3" from "2" stored in the A register 101b is executed. Borrowing to the most significant bit (seventh bit) occurs during execution of the operation. Therefore, the value of the carry flag CF becomes "1" after execution of the operation. On the other hand, if the value of the index value counter 74f is either "14" or "15", an operation of subtracting "3" from "3" or "4" stored in the A register 101b is executed. . The calculation result of the calculation is "0" or "1", and no borrowing to the most significant bit (seventh bit) occurs during the execution of the calculation. Therefore, the value of the carry flag CF becomes "0" after execution of the operation.

At the line number "8210", the command "JRC, ADR823" is set, like the line number "8207" described above. The instruction at line number "8210" is set to the program address "ADR822". "ADR823" is a program address that can be specified as a jump destination program address in the JR instruction based on the program address (ADR822) where the JR instruction of line number "8210" is set. As described above, when the value of the index value counter 74f is "13", the value of the carry flag CF is "1" by executing the instruction of the line number "8209". Therefore, by executing the instruction "JR C, ADR823" at the line number "8210", the program jumps to the program address "ADR823" at the line number "8212". On the other hand, as described above, when the value of the index value counter 74f is "14" or "15", the value of the carry flag CF becomes "0" by executing the instruction of the line number "8209". ing. Therefore, even if the instruction "JR C, ADR823" is set in the line number "8209", the program address does not jump, and the program proceeds to the next line number "8211".

The command of line number "8211" is executed when the player is in AT state ST5 and has won an index value IV of "14" or "15" in the winning lottery process (FIG. 18). At the line number "8211", a command "LD HL, KSADD01" is set, like the line number "1505" of the above-described process for addition at start (FIG. 102(a)). The start address of the first addition lottery table 73d is transferred to the HL register 104 by executing the instruction "LD HL, KSADD01" at the line number "8211". As a result, the lottery table to be referenced in the additional lottery is changed from the third additional lottery table 73h to the first additional lottery table 73d.

The instruction of line number "8212" jumps to the program address of line number "8212" by the JR instruction of line number "8210" when the JR instruction of line number "8207" jumps to the program address of line number "8212". or when the LD instruction of line number "8211" is executed to proceed to line number "8212". At the line number "8212", a command "JP ADR133" is set, like the line number "1511" of the above-described process for addition at start (FIG. 102(a)). By executing the instruction "JP ADR133" at the line number "8212", the program jumps to the program address "ADR133". Then, one of the first to third addition lotteries is executed by executing the processes of steps S1802 to S1807 of the number-of-unlocked-games lottery process (FIG. 35(b)).

FIG. 102(c) explains commands set for selecting the first to third addition lottery tables 73d, 73e, and 73h in the fourth comparative example of the addition processing at the start and the addition processing at the start. It is an explanatory diagram for. In the process for addition at the start (FIG. 102(a)), the commands for selecting the first to third addition lottery tables 73d, 73e, and 73h are set to line numbers "1505" to "1510". there is In addition, in the fourth comparative example (FIG. 102(b)) of the addition process at the start, the command for selecting the first to third addition lottery tables 73d, 73e, and 73h is from line number "8205" to line number It is set to "8211".

As shown in FIG. 102(c), there are three 3-byte LD instructions at line number “8205” to line number “8211” in the fourth comparative example of the process for addition at start (FIG. 102(b)). Two 2-byte CP instructions are set, and two 2-byte JR instructions are set. The total word length of the instructions set from line number "8205" to line number "8211" is 17 bytes. On the other hand, in line number "1505" to line number "1510" of the add-on processing at start (FIG. 102(a)), three 3-byte LD instructions are set, and 2-byte CP instruction is set, and two 2-byte JR instructions are set. The total word length of the instructions set from line number "1505" to line number "1510" is 15 bytes.

As already explained, in the process for addition at the start (FIG. 102(a)), in the state where any numerical value information of "0" to "4" is set in the A register 101b, the lottery table to be referred to A process for setting the first addition lottery table 73d and an operation for subtracting "2" from the value of the A register 101b are executed, and the combination of the values set in the zero flag ZF and the carry flag CF by the operation for subtracting "2" , the lottery table to be referenced is changed to the third additional lottery table 73h, the lottery table to be referenced is changed to the second additional lottery table 73e, and the lottery table to be referenced is the first additional lottery table 73e. It is a processing configuration that causes a case where a certain state is maintained in the table 73d and a case where the table 73d is maintained. As a result, as in the fourth comparative example (FIG. 102(b)) of the addition processing at the start, in a state where any numerical information of "0" to "4" is set in the A register 101b, the reference A process of setting the second additional lottery table 73e as the target lottery table is executed, and if an affirmative determination is made in the process of determining whether the value of the A register 101b is "2" or more, a lottery to be referenced is performed. When the table is changed from the second addition lottery table 73e to the third addition lottery table 73h, and the value of the A register 101b is "3" or more, when the affirmative determination is made, It is set to select the first to third additional lottery tables 73d, 73e, and 73h as compared with the processing configuration for changing the lottery table from the third additional lottery table 73h to the first additional lottery table 73d. The total instruction word length can be reduced. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 in order to execute the process for addition at start (FIG. 102(a)).

The value of the carry flag CF is maintained before and after execution of the JR instruction and before and after execution of the LD instruction. Therefore, in the process for addition at start (FIG. 102(a)), the values set in the zero flag ZF and the carry flag CF by executing the CP instruction of line number "1506" are used to When the value of the carry flag CF is "1", it is possible to execute the process of changing the reference target lottery table to the third additional lottery table 73h. A process of changing the lottery table to the second additional lottery table 73e can be executed. As a result, the value set in the carry flag CF is changed to When the value of the carry flag CF is "0", the process of changing the lottery table to be referenced to the third additional lottery table 73h is executed, and the second CP instruction (line number "8209") is executed. By executing the above, the value set in the carry flag CF is used, and when the value of the carry flag CF is "0", the lottery table to be referred to is changed to the first additional lottery table 73d. The number of CP instructions can be reduced compared to the processing architecture.

According to this embodiment detailed above, the following excellent effects are obtained.

In the start-up addition process (FIG. 102(a)), the first addition lottery table is used as a lottery table to be referred to in a state where any numerical value information from "0" to "4" is set in the A register 101b. 73d and an operation of subtracting "2" from the value of the A register 101b, and based on the combination of the values set in the zero flag ZF and the carry flag CF by the operation of subtracting "2", reference The target lottery table is changed to the third additional lottery table 73h, the reference lottery table is changed to the second additional lottery table 73e, and the reference lottery table is the first additional lottery table 73d. and a processing configuration that causes . As a result, as in the fourth comparative example (FIG. 102(b)) of the addition processing at the start, in a state where any numerical information of "0" to "4" is set in the A register 101b, the reference A process of setting the second additional lottery table 73e as the target lottery table is executed, and if an affirmative determination is made in the process of determining whether the value of the A register 101b is "2" or more, a lottery to be referenced is performed. When the table is changed from the second addition lottery table 73e to the third addition lottery table 73h, and the value of the A register 101b is "3" or more, when the affirmative determination is made, It is set to select the first to third additional lottery tables 73d, 73e, and 73h as compared with the processing configuration for changing the lottery table from the third additional lottery table 73h to the first additional lottery table 73d. The total instruction word length can be reduced. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 in order to execute the process for addition at start (FIG. 102(a)).

The value of the carry flag CF is maintained before and after execution of the JR instruction and before and after execution of the LD instruction. Therefore, in the process for addition at start (FIG. 102(a)), the values set in the zero flag ZF and the carry flag CF by executing the CP instruction of line number "1506" are used to When the value of the carry flag CF is "1", it is possible to execute a process of changing the reference target lottery table to the third additional lottery table 73h, and when the value of the carry flag CF is "1", the reference target lottery table can be changed. A process of changing the lottery table to the second additional lottery table 73e can be executed. As a result, the value set in the carry flag CF is changed to When the value of the carry flag CF is "0", the process of changing the lottery table to be referenced to the third additional lottery table 73h is executed, and the second CP instruction (line number "8209") is executed. By executing the above, the value set in the carry flag CF is used, and when the value of the carry flag CF is "0", the lottery table to be referred to is changed to the first additional lottery table 73d. The number of CP instructions can be reduced compared to the processing architecture.

In a configuration in which the index value IV is subtracted by "11" to specify that the index value IV is included in the numerical range of "11" to "15", the index value IV is decreased by "11". When the index value before the change is "11" to "12" using the value after being changed to the side, when the index value IV before the change is "13", and when the index value IV before the change is is between "14" and "15". After performing a calculation to shift the numerical range of "11" to "15" to the side smaller by "11" (calculation to subtract "11"), subtract "13" by "11" from the value after the calculation By adopting a configuration for performing an operation for subtracting "2" which is the value shifted to the side, the value to be subtracted can be "2" which is a value smaller than "13". When the winning index value IV is '11' to '12', when the winning index value IV is '13', and when the winning index value IV is '14' to '15' The number of bits required to represent the value "2" subtracted from the value obtained by shifting the index value IV to the smaller side by "11" in order to make a determination for specifying which case is '2', which is less than the number of bits required to represent the value '13' ('4'). As a result, the number of bits for representing the value to be subtracted in the calculation for making the determination can be reduced. Therefore, the data capacity for storing the value can be reduced.

<Twelfth Embodiment>
In the present embodiment, when the additional lottery is executed, the image display device 63 executes the lottery effect that makes the player expect that the number of remaining games to be continued in the AT state ST5 will be added. different from the form. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

The additional lottery is performed under the condition that any index value IV of "11" to "15" has been won in the lottery process (FIG. 18) for the game with the number of bets of "3" in the AT state ST5. executed. FIG. 103(a) is an explanatory diagram for explaining the configuration of the main-side ROM 73 for executing the additional lottery in this embodiment. As shown in FIG. 103(a), the main ROM 73 stores a first add-on lottery table 73d, a second add-on lottery table 73e, and a third add-on lottery table 73h.

In the present embodiment, when winning the index value IV of "11", "12", "14" or "15" in the winning lottery process (FIG. 18), the lottery table to be referred to is the first additional lottery table. A first additional lottery of 73d is executed. In addition, when the index value IV of "13" is won in the lottery process (FIG. 18) of the winning combination, the number of times the game with the number of bets "3" has been executed in the AT state ST5 is other than "10". The second addition lottery is executed with the lottery table to be referred to as the second addition lottery table 73e under the condition that the number of games in which the number of bets is "3" is executed in the AT state ST5 is "10". A third additional lottery is executed with the third additional lottery table 73h as the lottery table to be referenced under the condition that there is a third additional lottery table.

As already described with reference to FIGS. 43(a) and 43(b) in the first embodiment, the first additional lottery table 73d and the second additional lottery table 73e have 10 games, 20 games and 50 games. The number of additional games is set. Further, "16" is set as the determination value in the first addition lottery table 73d, and "32" is set as the determination value in the second addition lottery table 73e. As in the first embodiment, when the first additional lottery is executed with the first additional lottery table 73d as a reference lottery table, 10 games are selected with a probability of 1/16, and the probability is 1/16. 20 games will be selected, 50 games will be selected with a probability of 1/16, and will be out with a probability of 13/16. Further, as in the first embodiment, when the second additional lottery is executed with the second additional lottery table 73e as a reference lottery table, 10 games are selected with a probability of 1/8, and the 10 games are selected with a probability of 1/8. 20 games are selected with a probability of , 50 games are selected with a probability of 1/8, and are out with a probability of 5/8. As in the first embodiment, the probability of winning the additional game number of 10 games, 20 games or 50 games in the second additional lottery table 73e is 10 games, 20 games or 50 games in the first additional lottery table 73d. It is set higher than the probability of winning the number of additional games. The second addition lottery table 73e is a lottery table more advantageous for the player than the first addition lottery table 73d.

As already described with reference to FIG. 101(c) in the eleventh embodiment, the third addition lottery table 73h is set with 20 games, 40 games, and 80 games as the number of games to be added. "32" is set as the value. When the third additional lottery is executed with the third additional lottery table 73h as a reference lottery table, 20 games are selected with a probability of 1/8, 40 games are selected with a probability of 1/8, and 40 games are selected with a probability of 1/8. 80 games will be selected with a probability of , and will be out with a probability of 5/8. The probability of winning 20 games, 40 games or 80 games in the third addition lottery table 73h is the same as the probability of winning 10 games, 20 games or 50 games in the second addition lottery table 73e. is. As described above, the second addition lottery table 73e is a lottery table that is more advantageous for the player than the first addition lottery table 73d, but the third addition lottery table 73h is more advantageous to the player than the second addition lottery table 73e. Advantageous lottery table.

As described above, when the additional lottery is executed, the lottery effect is executed on the image display device 63 to make the player expect that the remaining number of continuous games in the AT state ST5 will be added. When the first addition lottery is executed, the first lottery performance is executed. In the first lottery effect, a cut-in image is displayed on the image display device 63 to indicate that there is a possibility that an addition will occur. A second lottery performance is executed when a second additional lottery more advantageous to the player than the first additional lottery is executed. In the second lottery effect, the image display device 63 displays a cut-in image indicating that there is a high possibility that an additional prize will be added. A third lottery performance is executed when a third additional lottery more advantageous to the player than the second additional lottery is executed. In the third lottery effect, similar to the second lottery effect, the image display device 63 displays a cut-in image indicating that there is a high possibility that an addition will occur. In addition, in the third lottery effect, a lottery sound is output from the speaker 62 to expect the occurrence of an additional lottery.

FIG. 103(b) is an explanatory diagram for explaining the configuration of the main side RAM 74 for executing the lottery effect. As shown in FIG. 103(b), the main RAM 74 is provided with an AT game number counter 141, an image type counter 142, and a sound type counter 143. As shown in FIG. The AT game number counter 141 is a 2-byte counter that enables the main side MPU 72 to grasp the number of times a game with a bet number of "3" has been executed in the AT state ST5. The value of the AT game number counter 141 is incremented by 1 each time a game with a bet number of "3" is executed in the AT state ST5, and is cleared to "0" when the AT state ST5 ends.

The image type counter 142 is a 1-byte counter in which an image type number indicating the type of cut-in image displayed on the image display device 63 in the first to third lottery effects is set. The image type counter 142 is set with an image type number of "1" when the first lottery effect is executed, and "2" to "6" when the second lottery effect or the third lottery effect is executed. One of the image type numbers is set. The sound type counter 143 is a 1-byte counter in which a sound type number indicating the type of lottery sound output from the speaker 62 in the third lottery effect is set. One of the sound type numbers “1” to “5” is set in the sound type counter 143 when the third lottery effect is executed.

The image type number set in the image type counter 142 and the sound type number set in the sound type counter 143 are set in the lottery effect command transmitted to the effect side MPU 92 . When receiving the lottery effect command, the effect side MPU 92 executes display control of the image display device 63 so that the cut-in image corresponding to the image type number set in the lottery effect command is displayed. Further, when any one of the sound type numbers "1" to "5" is set in the lottery effect command, the sound output control of the speaker 62 is performed so that the lottery sound corresponding to the sound type number is output. to run. As in the first embodiment, the effect-side MPU 92, based on the command at the start received from the main-side MPU 72, determines that the number of remaining games to be continued in the AT state ST5 has been added. An additional performance is executed after the third lottery performance. In the additional effect, a cut-in image corresponding to the number of additional games is displayed on the image display device 63. - 特許庁As a result, the player is notified of the number of additional games.

Next, the AT processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. 103(c). As already described in the first embodiment, the AT process is executed in step S1506 in the process for dealing with the end of the game (FIG. 32). Since the corresponding processing at the end of the game is executed after all the reels 32L, 32M and 32R have stopped rotating in one game, the AT processing is also executed after all the reels 32L, 32M and 32R have stopped rotating in one game. be.

In the AT process, first, as in step S2501 of the AT process (FIG. 42) in the first embodiment, the bet number setting counter 74b in the main side RAM 74 is referred to, and the bet number for the current game is "3". (step S5901). When the number of bets for this game is "3" (step S5901: YES), the value of the AT game number counter 141 in the main side RAM 74 is incremented by 1 (step S5902). This allows the main MPU 72 to grasp the number of times a game with the bet number of "3" has been executed in the AT state ST5.

After that, in steps S5903 and S5904, the same processes as steps S2502 and S2503 of the AT process (FIG. 42) in the first embodiment are executed. Specifically, 1 is subtracted from the value of the AT continuation counter 74u in the main RAM 74 (step S5903), and it is determined whether or not the value of the AT continuation counter 74u after the subtraction of 1 is "0" (step S5903). S5904). When the value of the AT continuation counter 74u is "0" (step S5904: YES), the value of the AT game number counter 141 in the main side RAM 74 is cleared to "0" (step S5905). As a result, the value of the AT game number counter 141 can be cleared to "0" when the AT state ST5 ends.

After that, in steps S5906 to S5912, the same processes as steps S2504 to S2510 of the AT process (FIG. 42) in the first embodiment are executed. Specifically, when the values of the first ending flag 76b and the second ending flag 76c in the game state area 77 of the main RAM 74 are both "0" (step S5906: NO), the game state area 77 of the main RAM 74 , the AT state flag 77d is cleared to "0" (step S5907). This enables the main MPU 72 to grasp that the AT state ST5 has ended. After that, a cancellation game number lottery process is executed by calling a subroutine program of a cancellation game number lottery process by a CALL command (step S5908). After that, the processing for setting the number-of-released-games counter is executed (step S5909). In the process of setting the unlocked game number counter, the unlocked game number lottery table 73c (FIG. 35(a)) is referred to, and the unlocked game number corresponding to the value of the determination target counter is set in the unlocked game number counter of the main RAM 74. FIG. After that, the value of the determination target counter is cleared to "0" (step S5910), and the process for this AT ends.

If "1" is set to either the first ending flag 76b or the second ending flag 76c (step S5906: YES), the process of setting the end preparation state ST6 is executed (step S5911). In the process of setting the end preparation state ST6, the AT state flag 77d in the game state area 77 of the main side RAM 74 is cleared to "0". Further, in the setting process of the end preparation state ST6, the end preparation state flag 77e in the game state area 77 of the main RAM 74 is set to "1". Thereafter, the termination preparation completion flag of the main RAM 74 is cleared to "0" (step S5912), and this AT processing is terminated.

Next, the start-time add-on processing executed by the main MPU 72 will be described with reference to the flowchart of FIG. 104 . As already described in the first embodiment, the addition process at the start is executed in step S2310 of the advantageous state process (FIG. 40) at the start of the game. As in the first embodiment, the start-up addition process is executed in the AT state ST5.

In the start-time addition processing, first, the image type counter 142 and the sound type counter 143 in the main RAM 74 are cleared to "0" (step S6001). After that, in steps S6002 to S6006, an instruction similar to the instruction set in line number "1301" to line number "1305" of the process for addition at start (FIG. 69(b)) in the first embodiment is executed. to run. Specifically, first, an instruction "LD A, (INDXCNT)" is executed (step S6001). "LD" is an LD instruction as a transfer instruction for 8-bit data, "A" is the A register 101b, and "(INDXCNT)" is the content specifying the index value counter 74f of the main RAM 74 as the transfer source. . The data of the index value counter 74f is transferred to the A register 101b by executing the instruction "LD A, (INDXCNT)" in step S6001. As a result, when any of the index values IV of "1" to "17" is won in the winning lottery process (FIG. 18), the index value IV is set in the A register 101b, In the lottery process (FIG. 18), "0" is set in the A register 101b when none of the index values IV is won.

After that, the instruction "SUB A, 0BH" is executed (step S6002). "SUB" is a SUB instruction as an 8-bit data subtraction instruction, "A" is the A register 101b, and "0BH" is the minimum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating "11". By executing the instruction "SUB A, 0BH" in step S6002, an operation is performed to subtract "11" from the value of the A register 101b, and the result of this operation is written to the A register 101b. When a carry flag CF is set to "1" when a borrow to the most significant bit (seventh bit) occurs in the computation, the carry flag CF is set to "1", and If no borrowing occurs, the value of the carry flag CF becomes "0". As already described with reference to FIG. 69(a) in the first embodiment, when the value of the index value counter 74f is included in the first lottery target range ("11" to "15"), The value of the A register 101b is less than "5", and the value of the index value counter 74f is "0" to "10" which is not included in the first lottery target range ("11" to "15"). If it is any one of "16" to "17", the value of the A register 101b is "5" or more.

After that, the command "CP A, 05H" is executed (step S6004). "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "05H" is the maximum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating a value (“5”) that is “1” larger than “4”, which is a value calculated by subtracting “11” from “15”. By executing the instruction "CP A, 05H" in step S6004, an operation of subtracting "5" from the value of the A register 101b is performed. If the value of the A register 101b before the subtraction of "5" is less than "5", that is, if the value of the index value counter 74f is included in the first lottery target range ("11" to "15") , the value of the carry flag CF becomes "1" due to borrowing to the most significant bit (the 7th bit among the 0th to 7th bits) in the calculation. On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or more, that is, the value of the index value counter 74f is not included in the first lottery target range ("11" to "15"). 0" to "10" and "16" to "17", no borrowing to the most significant bit (7th bit in 0th to 7th bits) occurs in the calculation Therefore, the value of the carry flag CF becomes "0". The operation result of subtracting "5" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 05H" is executed, the value of the A register 101b does not change. Therefore, the data stored in the A register 101b by subtracting "11" in step S6003 can also be used in step S6008, which will be described later.

After that, the command "RET NC" is executed (step S6005). "RET" is a RET instruction as an instruction to return from a subroutine, and "NC" is a content that sets the condition that the value of the carry flag CF is "0" as a condition for returning from the subroutine. . By executing the instruction "RET NC" in step S6005, on the condition that the value of the carry flag CF is "0", in step S2310 of the advantageous state processing at the start of the game (FIG. 40) The call-up addition process at the start is ended, and the process returns to step S2311 following step S2310. As described above, when the value of the index value counter 74f is one of "0" to "10" and "16" to "17", the value of the carry flag CF is becomes "0". Therefore, by executing the command "RET NC" in step S6005, the addition process at the start is terminated, and the process returns to step S2311 in the advantageous state process at the start of the game (FIG. 40). On the other hand, as described above, when the value of the index value counter 74f is included in the first lottery target range (“11” to “15”), the process of step S6004 is executed to reset the carry flag CF. The value becomes "1". For this reason, even if the command "RET NC" is set in step S6005, the addition process at the start is not ended, and the process proceeds to the next step S6006.

The command of step S6006 is executed when the AT state ST5 is established and any index value IV of "11" to "15" has been won in the winning lottery process (FIG. 18). In step S6006, the instruction "LD HL, KSADD01" is executed. "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD01" is the starting address of the first addition lottery table 73d in the main ROM 73. be. The start address of the first addition lottery table 73d is transferred to the HL register 104 by executing the instruction "LD HL, KSADD01" in step S6006. As a result, the first additional lottery table 73d can be set as the lottery table to be referred to in the additional lottery. As described above, when the AT state ST5 is reached and any one of the index values IV of "11" to "15" is won in the winning lottery process (FIG. 18), the lottery table to be referred to is the first lottery table. 1 addition lottery table 73d is set.

After that, the image type counter 142 of the main RAM 74 is set to "1" (step S6007). After that, the command "CP A, 02H" is executed (step S6008). "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "02H" is the index of "13" to be executed for the second or third extra lottery. This is 1-byte numerical information indicating "2" which is a value calculated by subtracting "11" from the value IV. By executing the instruction "CP A, 02H" in step S6008, an operation of subtracting "2" from the value of the A register 101b is performed. If the value of the A register 101b before the subtraction of "2" is "2", that is, if the second addition lottery or the third addition lottery is to be executed, the result of the calculation will be "0". , the value of the zero flag ZF becomes "1". On the other hand, if the value of the A register 101b before the subtraction of "2" is "0", "1", "3" or "4", that is, if the first addition lottery is to be executed, Since the operation result does not become "0", the value of the zero flag ZF becomes "0". The operation result of subtracting "2" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 02H" is executed, the value of the A register 101b does not change. Therefore, the data stored in the A register 101b by subtracting "11" in step S6003 can be used in step S6014, which will be described later.

After that, the instruction "JR NZ, ADR162" is executed (step S6009). "JR" is a conditional jump instruction with a word length of 2 bytes; The program address "ADR162" in step S6015 is designated as the jump destination program address. The instruction in step S6009 is set to the program address "ADR161". In the JR instruction in step S6009, a 2-byte jump destination program address (ADR162 ) are relatively specified. Compared to the configuration using the JP instruction with a word length of 3 bytes, the configuration for jumping to the program address of the jump destination using the JR instruction with a word length of 2 bytes makes it possible to jump to the program address at the jump destination. The data capacity of the machine language of the jump instruction is reduced. "ADR162" is a program address that exists within a range that can be specified as a jump destination program address for the JR instruction based on the program address (ADR161) set by the JR instruction in step S6009. As described above, when the first additional lottery is to be executed, the value of the zero flag ZF is set to "0" by executing the process of step S6008. Therefore, the command "JR NZ, ADR162" is executed in step S6009 to jump to the program address "ADR162" in step S6015. On the other hand, as described above, when the second addition lottery or the third addition lottery is to be executed, the zero flag ZF is set to "1" by executing the process of step S6008. . Therefore, even if the instruction "JR NZ, ADR162" is set in step S6009, the program address does not jump, and the process proceeds to the next step S6010.

In step S6010, the instruction "LD HL, KSADD02" is executed. "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD02" is the start address of the second addition lottery table 73e in the main ROM 73. be. The start address of the second addition lottery table 73e is transferred to the HL register 104 by executing the instruction "LD HL, KSADD02" in step S6010. As a result, the lottery table to be referred to is changed from the first additional lottery table 73d to the second additional lottery table 73e.

After that, an image type lottery process is executed (step S6011). In the image type lottery process, the image type lottery table provided in the main ROM 73 and the lottery counter periodically updated in the main RAM 74 are used to select cut-in images in the second lottery effect or the third lottery effect. Decide on the type. In the image type lottery process, an image type number of "2" is selected with a probability of 5/16, an image type number of "3" is selected with a probability of 1/4, and an image type number of "4" is selected with a probability of 3/16. An image type number of "5" is selected with a probability of 1/8, and an image type number of "6" is selected with a probability of 1/8. After that, setting processing of the image type counter 142 is executed (step S6012). In the image type counter 142 setting process, one of the image type numbers “2” to “6” selected in the image type lottery process (step S 6011 ) is set in the image type counter 142 of the main RAM 74 .

After that, the data of the AT game number counter 141 in the main RAM 74 is set in the A register 101b (step S6013). As a result, the number of times the game with the bet number of "3" has been executed in the AT state ST5 is set in the A register 101b. After that, the instruction "CP A, 0AH" is executed (step S6014). "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "0AH" is 1-byte numerical information indicating "10". By executing the instruction "CP A, 0AH" in step S6014, an operation of subtracting "10" from the value of the A register 101b is performed. If the value of the A register 101b before the subtraction of "10" is "10", that is, if the number of games with the bet number "3" in the AT state ST5 is "10", the calculation is "0", the value of the zero flag ZF is "1". On the other hand, if the value of the A register 101b before the subtraction of "10" is numerical information other than "10", that is, if the number of games with the bet number of "3" in the AT state ST5 is not "10" In some cases, the value of the zero flag ZF is "0" because the result of the calculation is not "0".

The process of step S6015 is executed when the JR instruction of step S6009 jumps to the program address of step S6015, or when the process of step S6014 is executed and the process proceeds to step S6015. First, the case where the JR instruction at step S6009 jumps to the program address at step S6015 will be described. As described above, in step S6009, the program jumps to the program address in step S6015 when the first additional lottery is to be executed. In step S6015, the command "JR NZ, ADR163" is executed. "JR" is a conditional jump instruction with a word length of 2 bytes; The program address "ADR163" in step S6019 is designated as the jump destination program address. The instruction in step S6015 is set to the program address "ADR162". In the JR instruction in step S6015, a 2-byte jump destination program address (ADR163 ) are relatively specified. Compared to the configuration using the JP instruction with a word length of 3 bytes, the configuration for jumping to the program address of the jump destination using the JR instruction with a word length of 2 bytes makes it possible to jump to the program address at the jump destination. The data capacity of the machine language of the jump instruction is reduced. As already explained, the value of the zero flag ZF is maintained even if the JR instruction, which is a conditional jump instruction with a word length of 2 bytes, is executed. Therefore, when jumping from the program address (ADR161) in step S6009 to the program address (ADR162) in step S6015 under the condition that the value of the zero flag ZF is "0", the jump condition of the JR instruction in step S6015 is Always satisfied and jumps to the program address (ADR163) in step S6019. "ADR163" is a program address that exists within a range that can be specified as a jump destination program address in the JR instruction based on the program address (ADR162) set by the JR instruction in step S6015. This is a program address that does not exist in the range that can be specified as the program address of the jump destination in the JR instruction based on the program address (ADR161) where the JR instruction is set.

Next, a case where the process of step S6014 is executed and the process proceeds to step S6015 will be described. As described above, when the number of times the game with the bet number of "3" has been executed in the AT state ST5 is other than "10", the value of the zero flag ZF is set to "0" by executing the process of step S6015. ”. Therefore, the command "JR NZ, ADR163" is executed in step S6016 to jump to the program address "ADR163" in step S6019. On the other hand, as described above, when the number of times the game with the bet number of "3" has been executed in the AT state ST5 is "10", the process of step S6015 is executed to set the zero flag ZF to "1". is set. Therefore, even if the instruction "JR NZ, ADR163" is set in step S6016, the program address does not jump, and the process proceeds to the next step S6016.

In step S6016, the instruction "LD HL, KSADD03" is executed. "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD03" is the start address of the third addition lottery table 73h in the main ROM 73. be. The start address of the third addition lottery table 73h is transferred to the HL register 104 by executing the instruction "LD HL, KSADD03" in step S6016. As a result, the lottery table to be referred to is changed from the second additional lottery table 73e to the third additional lottery table 73h.

After that, a sound type lottery process is executed (step S6017). In the sound type lottery process, the lottery counter periodically updated in the sound type lottery table provided in the main side ROM 73 and the main side RAM 74 is used to determine the type of lottery sound in the third lottery effect. In the sound type lottery process, the sound type number "1" is selected with a probability of 5/16, the sound type number "2" is selected with a probability of 1/4, and the sound type number "3" is selected with a probability of 3/16. A sound type number of "4" is selected with a probability of 1/8, and a sound type number of "5" is selected with a probability of 1/8. Thereafter, setting processing of the sound type counter 143 is executed (step S6018). In the setting process of the sound type counter 143, one of the sound type numbers "1" to "5" selected in the sound type lottery process (step S6017) is set in the sound type counter 143 of the main side RAM74.

When jumping to the program address (ADR163) of step S6019 by the JR command of step S6015, or when the processing of step S6018 is executed, the lottery effect command transmission setting processing is executed (step S6019). In the lottery effect command transmission setting process, the lottery effect command flag provided in the main side RAM 74 is set to "1". The lottery effect command flag is a flag that allows the main side MPU 72 to grasp that the lottery effect command should be transmitted to the effect side MPU 92 . By setting the lottery effect command flag to "1", the process of transmitting the lottery effect command to the effect side MPU 92 is executed in the command output process in step S210 of the timer interrupt process (FIG. 11). As already explained, when the effect-side MPU 92 receives the lottery effect command, it controls the display of the image display device 63 so that the cut-in image corresponding to the image type number set in the lottery effect command is displayed. Execute. Further, when any one of the sound type numbers "1" to "5" is set in the lottery effect command, the sound output control of the speaker 62 is performed so that the lottery sound corresponding to the sound type number is output. to run.

After that, the command "JP ADR133" is executed (step S6020) in the same manner as the line number "1309" of the process for addition at start (FIG. 69(b)) in the first embodiment. "JP" is a JP instruction as an unconditional jump instruction with a word length of 3 bytes, and "ADR133" is set with an instruction for executing the processing of step S1802 in the unlock game number lottery processing (FIG. 35(b)). program address (2 bytes). In step S6020, the instruction "JP ADR133" is executed to jump to the program address "ADR133". Then, one of the first to third addition lotteries is executed by executing the processes of steps S1802 to S1807 of the number-of-unlocked-games lottery process (FIG. 35(b)). As already explained, if the winning index value IV of "11", "12", "14" or "15" is won in the winning combination lottery process (FIG. 18), the first addition lottery table 73d is used. Then, the first additional lottery is executed. In addition, when the index value IV of "13" is won in the winning lottery process (FIG. 18), the number of times the game with the number of bets "3" has been executed in the AT state ST5 is other than "10". The second addition lottery is executed with the lottery table to be referred to as the second addition lottery table 73e on the condition that there is a second addition lottery table 73e, and the number of times the game with the bet number of "3" is executed in the AT state ST5 is "10". , the third addition lottery is executed with the lottery table to be referred to as the third addition lottery table 73h.

FIG. 105(a) explains the jump instructions set to jump from the program address "ADR161" and the program address "ADR162" to the program address "ADR163" in the process for addition at the start (FIG. 104). It is an explanatory diagram for. As already explained, the range that can be jumped by the JR instruction is the range from "(the program address where the relevant JR instruction is set) + 2 - 128" to "(the program address where the relevant JR instruction is set) + 2 + 127". . As described above, "ADR163" is a program address that exists within a range that can be specified as a jump destination program address for the JR instruction based on the program address (ADR162) where the JR instruction in step S6015 is set. In addition, it is a program address that does not exist in the range that can be specified as the program address of the jump destination in the JR instruction based on the program address (ADR161) where the JR instruction in step S6009 is set.

As already explained, the value of the zero flag ZF is maintained even if the JR instruction, which is a conditional jump instruction with a word length of 2 bytes, is executed. In the process for addition at the start (FIG. 104), if the value of the zero flag ZF is "0" and the jump is made from the program address (ADR161) of step S6009 to the program address (ADR162) of step S6015, step The jump condition of the JR instruction in S6015 is certainly satisfied, and the program jumps to the program address (ADR163) in step S6019.

FIG. 105(b) explains a jump instruction set for jumping from the program address "ADR161" and the program address "ADR162" to the program address "ADR163" in the fifth comparative example of the addition process at the start. It is an explanatory view for doing. In the fifth comparative example (FIG. 105(b)) of the addition processing at the start, the command "JP NZ, ADR163" is set to the program address "ADR161" in step S6009. "JP" is a jump instruction with a word length of 3 bytes, "NZ" is the content specifying the jump condition that the value of the zero flag ZF is "0", and "ADR163" is the jump destination. The content specifies the program address "ADR163" as the program address of . In the fifth comparative example (Fig. 105(b)) of the addition processing at the start, since the instruction "JP NZ, ADR163" is set at the program address "ADR161", the value of the zero flag ZF is "0". Under certain conditions, jump directly from "ADR161" to the program address "ADR163" without going through the program address "ADR162".

As described above, the JR command in step S6015 is a command for jumping from the program address "ADR162" to the program address "ADR163" when the third lottery effect is not to be executed. Therefore, the JR instruction in step S6015 cannot be omitted even in a configuration in which the program address "ADR161" is directly jumped to the program address "ADR163".

As shown in FIG. 105(b), in the fifth comparative example (FIG. 105(b)) of the additional processing at the start, a jump from the program address "ADR161" and the program address "ADR162" to the program address "ADR163" is performed. The total word length of the jump instruction set to do is 5 bytes. On the other hand, as shown in FIG. 105(a), in order to jump from the program address "ADR161" and the program address "ADR162" to the program address "ADR163" in the process for addition at the start (FIG. 104) The total word length of the set jump instructions is 4 bytes.

As described above, the process for addition at start (FIG. 104) jumps to the program address in step S6015 by a JR instruction with a word length of 2 bytes on the condition that the value of the zero flag ZF is "0" in step S6009. Utilizing the fact that the value of the zero flag ZF is maintained even when the JR instruction is executed, the processing configuration jumps to the program address "ADR163" by the JR instruction set in step S6015 of the jump destination. As a result, as in the fifth comparative example (FIG. 105(b)) of the addition processing at the start, on the condition that the value of the zero flag ZF is "0" in step S6009, a JP instruction with a word length of 3 bytes Compared to the processing configuration that directly jumps to the program address "ADR163", the word length of the jump instruction set to jump from the program address "ADR161" and the program address "ADR162" to the program address "ADR163" Total can be reduced. Therefore, it is possible to reduce the data volume of the program stored in the main ROM 73 in order to execute the processing for addition at start (FIG. 104).

According to this embodiment detailed above, the following excellent effects are obtained.

The value of the zero flag ZF is maintained even if a JR instruction as a conditional jump instruction with a word length of 2 bytes is executed. In the start-up addition processing (FIG. 104), on condition that the value of the zero flag ZF is "0" in step S6009, a JR instruction with a word length of 2 bytes jumps to the program address in step S6015, and the value of the zero flag ZF is is a processing configuration for jumping to the program address "ADR163" by the JR instruction set in step S6015 of the jump destination, using the fact that the above is maintained even if the JR instruction is executed. As a result, as in the fifth comparative example (FIG. 105(b)) of the addition process at the start, the JP instruction with a word length of 3 bytes is used on the condition that the value of the zero flag ZF is "0" in step S6009. Compared to the processing configuration that directly jumps to the program address "ADR163", the word length of the jump instruction set to jump from the program address "ADR161" and the program address "ADR162" to the program address "ADR163" total can be reduced. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 in order to execute the process for addition at start (FIG. 104).

<Thirteenth Embodiment>
This embodiment differs from the first embodiment in that the lottery execution process is called by a CALL command. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

The processing for addition at the time of start in this embodiment is a processing configuration in which the processing of steps S1802 to S1807 of the unlocked game number lottery processing (FIG. 35(b)) is called as a subroutine processing called lottery execution processing. In this embodiment, also in the number-of-released-games lottery process (FIG. 35(b)), after executing the process of step S1801, the process of the subroutine called the lottery execution process is called.

FIG. 106(a) is an explanatory diagram for explaining the program contents of the process for addition at start in this embodiment. As already described in the first embodiment, the start-up addition process is executed in step S2310 of the advantageous state process (FIG. 40) at the start of the game. As in the first embodiment, the start-up addition process is executed in the AT state ST5. As shown in FIG. 106(a), "1601" to "1609" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

In the line number "1601" to the line number "1608", the same processing as the line number "1301" to the line number "1308" of the start-up addition processing (FIG. 69(b)) in the first embodiment is executed. do. An instruction "LD A, (INDXCNT)" is set at the line number "1601". "LD" is an LD instruction as a transfer instruction for 8-bit data, "A" is the A register 101b, and "(INDXCNT)" is the content specifying the index value counter 74f of the main RAM 74 as the transfer source. . By executing the instruction "LD A, (INDXCNT)" at the line number "1601", the data of the index value counter 74f is transferred to the A register 101b. As a result, when any of the index values IV of "1" to "17" is won in the winning lottery process (FIG. 18), the index value IV is set in the A register 101b, In the lottery process (FIG. 18), "0" is set in the A register 101b when none of the index values IV is won.

The command "SUB A, 0BH" is set at the line number "1602". "SUB" is a SUB instruction as an 8-bit data subtraction instruction, "A" is the A register 101b, and "0BH" is the minimum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating "11". By executing the instruction "SUB A, 0BH" at line number "1602", an operation is performed to subtract "11" from the value of the A register 101b, and the result of this operation is written to the A register 101b. . When a carry flag CF is set to "1" when a borrow occurs in the most significant bit (7th bit) in the operation, the carry flag CF is set to "1", and If no borrowing occurs, the value of the carry flag CF becomes "0". As already described with reference to FIG. 69(a) in the first embodiment, when the value of the index value counter 74f is included in the first lottery target range ("11" to "15"), The value of the A register 101b is less than "5", and the value of the index value counter 74f is "0" to "10" which is not included in the first lottery target range ("11" to "15"). If it is any one of "16" to "17", the value of the A register 101b is "5" or more. Further, as already described with reference to FIG. 69(a) in the first embodiment, the value of the index value counter 74f is included in the first lottery target range ("11" to "15"). If it is any of "11" to "13" that is not included in the second lottery target range ("14" to "15"), the value of the A register 101b becomes a value less than "3" , when the value of the index value counter 74f is "14" or "15" which is included in the first lottery target range ("11" to "15") and is also included in the second lottery target range. , the value of the A register 101b is "3" or more.

The command "CP A, 05H" is set at the line number "1603". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "05H" is the maximum value of the first lottery target range ("11" to "15"). This is 1-byte numerical information indicating a value (“5”) that is “1” larger than “4”, which is a value calculated by subtracting “11” from “15”. By executing the instruction "CP A, 05H" at the line number "1603", an operation of subtracting "5" from the value of the A register 101b is performed. If the value of the A register 101b before the subtraction of "5" is less than "5", that is, if the value of the index value counter 74f is included in the first lottery target range ("11" to "15") , the value of the carry flag CF becomes "1" due to borrowing to the most significant bit (the 7th bit among the 0th to 7th bits) in the calculation. On the other hand, if the value of the A register 101b before the subtraction of "5" is "5" or more, that is, the value of the index value counter 74f is not included in the first lottery target range ("11" to "15"). 0" to "10" and "16" to "17", no borrowing to the most significant bit (7th bit in 0th to 7th bits) occurs in the calculation Therefore, the value of the carry flag CF becomes "0". The operation result of subtracting "5" from the value of the A register 101b is not written to the A register 101b. Even if the instruction "CP A, 05H" is executed, the value of the A register 101b does not change. Therefore, the data stored in the A register 101b by executing the operation of subtracting "11" at the line number "1602" can also be used at the line number "1606" which will be described later.

A command "RET NC" is set at the line number "1604". "RET" is a RET instruction as an instruction to return from a subroutine, and "NC" is a content that sets the condition that the value of the carry flag CF is "0" as a condition for returning from the subroutine. . By executing the instruction "RET NC" at the line number "1604", the step of the advantageous state processing (FIG. 40) at the start of the game is performed on the condition that the value of the carry flag CF is "0". The process for addition at the start called in S2310 is ended, and the process returns to step S2311 following step S2310. As described above, the value of the index value counter 74f is any of "0" to "10" and "16" to "17" that are not included in the first lottery target range ("11" to "15"). In this case, the value of carry flag CF becomes "0" by executing the instruction of line number "1603". Therefore, by executing the command "RET NC" at the line number "1604", the addition processing at the start is ended, and the process returns to step S2311 in the advantageous state processing at the start of the game (FIG. 40). . On the other hand, as described above, when the value of the index value counter 74f is included in the first lottery target range (“11” to “15”), the instruction of line number “1603” is executed to carry The value of the flag CF becomes "1". Therefore, even if the command "RET NC" is set in the line number "1604", the processing for addition at start will not end, and the process will proceed to the next line number "1605".

The command of line number "1605" is when the AT state is ST5 and the index value IV of the first lottery target range ("11" to "15") has been won in the winning lottery process (Fig. 18). executed. The command "LD HL, KSADD01" is set at the line number "1605". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD01" is the starting address of the first addition lottery table 73d in the main ROM 73. be. The start address of the first addition lottery table 73d is transferred to the HL register 104 by executing the instruction "LD HL, KSADD01" at the line number "1605". As a result, the first additional lottery table 73d can be set as the lottery table to be referred to in the additional lottery. In this way, when the AT state ST5 is reached and the index value IV in the first lottery target range ("11" to "15") is won in the role lottery process (FIG. 18), the reference target A first additional lottery table 73d is set as the lottery table.

The command "CP A, 03H" is set at the line number "1606". "CP" is a CP instruction as an 8-bit data comparison instruction, "A" is the A register 101b, and "03H" is the minimum value of the second lottery target range ("14" to "15"). This is 1-byte numerical information indicating a value (“3”) calculated by subtracting “11” from “14”. As described above, the A register 101b stores 1-byte numerical information calculated by subtracting "11" from the row number "1602". Since the instruction of line number "1606" is executed when the index value IV in the first lottery target range ("11" to "15") is won in the lottery process (Fig. 18), the A register The value of 101b is one of "0" to "4". By executing the instruction "CP A, 03H" at the line number "1606", an operation of subtracting "3" from the value of the A register 101b is performed. As already explained, when the CP instruction is executed, the jump flag JF has the same value as the carry flag CF. If the value of the A register 101b before the subtraction of "3" is less than "3", that is, the value of the index value counter 74f is "11" which is not included in the second lottery target range ("14" to "15"). to "13", the carry flag CF is set to "1" by borrowing to the most significant bit (the 7th bit among the 0th to 7th bits) in the operation. At the same time, the value of the jump flag JF also becomes "1". On the other hand, when the value of the A register 101b before the subtraction of "3" is "3" or more, that is, when the value of the index value counter 74f is "14" or "15" included in the second lottery target range. , the value of the carry flag CF becomes "0" and the value of the jump flag JF is changed to is also "0".

The command "JRS 1, ADR172" is set at the line number "1607". "JRS" is a conditional jump instruction with a word length of 1 byte; This is the contents of setting the program address of line number "1609" of "ADR172" as the jump destination. The instruction at line number "1607" is set to the program address "ADR171". As already explained, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)+1-16" to "(the program address where the JRS instruction is set)+1+15". . As shown in FIG. 106(a), the word length of the instruction (the LD instruction of line number "1608") set at the program address existing between the program addresses "ADR171" and "ADR172" is 3 bytes. "ADR172" is "(ADR171)+1+3", which is a program address that can be specified as a jump destination program address in the JRS instruction based on the program address (ADR171) where the JRS instruction of line number "1607" is set. is.

As described above, the value of the index value counter 74f is included in the first lottery target range (“11” to “15”) and is not included in the second lottery target range (“14” to “15”). If it is any one of "11" to "13", the value of the jump flag JF becomes "1" by executing the instruction of the line number "1606". Therefore, the instruction "JRS 1, ADR172" is executed at line number "1607" to jump to the program address "ADR172" at line number "1609". On the other hand, as described above, the value of the index value counter 74f is included in the first lottery target range (“11” to “15”) and is also included in the second lottery target range (“14” to “15”). If it is "14" or "15", the value of the jump flag JF becomes "0" by executing the instruction of the line number "1606". Therefore, even if the instruction "JRS 1, ADR172" is set in the line number "1607", the program address does not jump, and the program proceeds to the next line number "1608".

The command of line number "1608" is executed when the AT state is ST5 and the index value IV of the second lottery target range ("14" to "15") is won in the winning lottery process (FIG. 18). executed. A command "LD HL, KSADD02" is set at the line number "1608". "LD" is an LD instruction as a 16-bit transfer instruction, "HL" is the content for setting the HL register 104 as the transfer destination, and "KSADD02" is the second addition lottery table 73e (Fig. 43 ( b)) is the starting address. The start address of the second addition lottery table 73e is transferred to the HL register 104 by executing the instruction "LD HL, KSADD02" at the line number "1608". As a result, the lottery table to be referred to can be changed from the first additional lottery table 73d to the second additional lottery table 73e, which is more advantageous to the player than the first additional lottery table 73d. In this way, when the AT state ST5 and the index value IV of the second lottery target range ("14" to "15") are won in the role lottery process (FIG. 18), the additional lottery A second additional lottery table 73e is set as a lottery table to be referred to.

The instruction set to line number "1609" is jumped to line number "1609" by the JRS instruction of line number "1607", or when the LD instruction of line number "1608" is executed, line number "1609" Executed when proceeding to Specifically, in the AT state ST5, it is included in the first lottery target range ("11" to "15") and the second lottery target range ("14" to "15"), the JRS command of line number "1607" jumps to the program address of line number "1609" and the instruction is executed. In addition, in the AT state ST5, in the winning lottery process (FIG. 18), it is included in the first lottery target range ("11" to "15") and the second lottery target range ("14" to "15") ), the instruction of line number “1609” is executed after executing the LD instruction of line number “1608”.

The command "CALL TYSJSR" is set at the line number "1609". "TYSJSR" is lottery execution processing (number of unlocked game lottery processing (steps S1802 to S1807 in FIG. 35(b)), and "CALL" is a CALL command for calling a subroutine of the lottery execution processing. The subroutine for the lottery execution process is called by executing the command "CALL TYSJSR" at "1609", and the winning lottery process (FIG. 18) starts from "11". If any index value IV of "13" is won, an additional lottery is executed based on the first additional lottery table 73d, and "14" or " If the index value IV of "15" is won, an additional lottery is executed based on the second additional lottery table 73e.

FIG. 106(b) is an explanatory diagram for explaining a command set for calling the lottery execution process in the process for addition at the start (FIG. 106(a)). As shown in FIG. 106(b), in the process for addition at the start (FIG. 106(a)), the line number is set to "1607" under the condition that the value of the jump flag JF is "1". The JRS instruction, which is a conditional jump instruction with a word length of 1 byte, jumps to the program address (ADR172) of the line number "1609", and the CALL instruction with a word length of 3 bytes set at the jump destination line number "1609". calls the lottery execution process. The total word length of the instructions set to line number "1607" and line number "1609" for calling the lottery execution process is 4 bytes.

FIG. 106(c) is an explanatory diagram for explaining a command set for calling the lottery execution process in the sixth comparative example of the addition process at the start. As shown in FIG. 106(c), in the sixth comparative example of the addition processing at the start, the command "CALL TYSJSR" is set in the line number "1607" as well as the line number "1609". In the sixth comparative example of the addition process at the start, the total word length of the instructions set to the line numbers "1607" and "1609" for calling the lottery execution process is 6 bytes.

The processing for addition at the start (FIG. 106(a)) is a conditional jump instruction with a word length of 1 byte set at the line number "1607" on the condition that the value of the jump flag JF is "1". A certain JRS instruction jumps to the program address (ADR172) of line number "1609", and a CALL instruction with a word length of 3 bytes set at the jump destination line number "1609" calls the lottery execution process. As a result, a CALL instruction with a word length of 3 bytes is set to call the lottery execution process also in the line number "1607" as in the sixth comparative example (FIG. 106(c)) of the additional process at the start. Compared to the configuration, it is possible to reduce the total word length of the command set for calling the lottery execution process.

According to this embodiment detailed above, the following excellent effects are obtained.

The processing for addition at the start (FIG. 106(a)) is a conditional jump instruction with a word length of 1 byte set at the line number "1607" on the condition that the value of the jump flag JF is "1". A certain JRS instruction jumps to the program address (ADR172) of line number "1609", and a CALL instruction with a word length of 3 bytes set at the jump destination line number "1609" calls the lottery execution process. As a result, a CALL instruction with a word length of 3 bytes is set to call the lottery execution process also in the line number "1607", as in the sixth comparative example (Fig. 106(c)) of the additional process at the start. Compared to the configuration, it is possible to reduce the total word length of the command set for calling the lottery execution process. Therefore, it is possible to reduce the data capacity of the program stored in the main ROM 73 in order to execute the additional processing at the start.

<Other embodiments>
It should be noted that the present invention is not limited to the description of each embodiment described above, and various modifications and improvements can be made without departing from the spirit of the present invention. For example, it may be changed as follows. Incidentally, the configurations of the following different forms may be applied individually to the configurations of the above embodiments, or may be applied in combination. In addition, the configurations of the above embodiments may be applied in combination with each other, and the configurations of the following other forms may be applied individually or in combination to the configuration in which the configurations of the above embodiments are combined with each other. good.

(1) In each of the above-described embodiments, the stay ratio of the second section SC2 is calculated for each set value, and the combined display section 66 corresponds to the calculation result data of the stay ratio of the second section SC2 for each set value. A configuration in which ratio display is performed may be employed. The main RAM 74 is provided with a total game number counter corresponding to set values "1" to "6" and a second section game number counter corresponding to set values "1" to "6". When the ratio display start operation is performed, first, the total game number counter corresponding to the set value of "1" and the second section game number counter corresponding to the set value of "1" are referred to and set to "1". A calculation for calculating the stay ratio of the second section SC2 in the value is executed, and the calculation result data is set in the ratio display counter 74n. As a result, ratio display corresponding to the set value of "1" is started on the dual-use display unit 66. FIG. After that, when an operation to update the ratio display (for example, operation of one of the stop buttons 42 to 44) is performed, the total game number counter and the second section game number counter to be referred to are updated. Then, referring to the total number-of-games counter and the second-section number-of-games counter that have become reference targets after the update, the stay of the second section SC2 at the set value of "n" (n is any integer from 1 to 6) A calculation for calculating the ratio is executed, and the calculation result data is set in the ratio display counter 74n. As a result, ratio display corresponding to the set value of "n" is started on the dual-use display unit 66. FIG. In the combined display unit 66, the ratio display is updated in the order of "1"→"2"→"3"→"4"→"5"→"6"→"1" each time the ratio display is updated. The target setting value is updated. Accordingly, it is possible to check the stay ratio of the second section SC2 for each set value based on the ratio display of the combined display section 66 .

(2) In each of the above embodiments, the most significant bit data in the storage area set in the address range of "0001H" to "0006H" in the main RAM 74 is collected in the register of the main MPU 72 (for example, the B register 102a). Then, the data aggregated in the register may be set in the transmission standby buffer 112 . As a result, it is not necessary to provide a storage area in the main RAM 74 for collecting the most significant bit data in the storage area set in the address range of "0001H" to "0006H", while the start command and the end command are not required. The highest aggregated frame SF can be set in the hour command.

(3) In the first embodiment, the number of data transfers may be grasped by referring to the bit designation counter 117 in the top-level aggregation process (FIG. 51). Specifically, after transferring the most significant bit data in the transfer source storage area to the transfer destination bit in the highest order aggregation process, it is determined whether or not the value of the bit designation counter 117 is "5". , when the value of the bit designation counter 117 is "5", the highest level aggregation processing is terminated. As already described in the first embodiment, the value of the bit designation counter 117 is updated by being incremented by 1 each time the process of transferring the most significant bit data in the transfer source storage area to the transfer destination bit is executed. be done. Therefore, when the value of the bit designation counter 117 is "5" after executing the process of transferring the most significant bit data in the transfer source storage area to the transfer destination bit, "0001H" to "0001H" in the main RAM 74 This means that the most significant bit data in the storage area set in the address range of "0006H" is set in the 0th to 5th bits of the most significant aggregation area 74v. In this manner, the configuration for grasping the number of data transfers by referring to the bit designation counter 117 simplifies the processing configuration of the highest-level aggregation processing.

(4) In the first embodiment, information set in advance in a general-purpose register for the process of transferring data stored in the most significant bit of the storage area included in the transfer target range in the highest-level aggregation process. may be configured to be executed using Specifically, the address of the storage area of the transfer source is set in the BC register 102, and information on the number of times of transfer is set in the E register 103b. Also, the address of the storage area of the transfer destination is set in the HL register 104, and the information of the transfer destination bit is set in the D register 103a. The main-side RAM 74 is not provided with a dedicated storage area for setting the address of the storage area of the transfer source, the information of the number of transfers, the address of the storage area of the transfer destination, and the information of the transfer destination bit. In the process of transferring the data stored in the most significant bit in the storage area included in the transfer target range in the highest-level aggregation process, the main MPU 72 selects the transfer source based on the data set in the BC register 102. In addition, information on the number of transfers can be grasped based on the data set in the E register 103b. Further, the address of the storage area of the transfer destination can be grasped based on the data set in the HL register 104, and the information of the transfer destination bit can be grasped based on the data set in the D register 103a. can be done. In this manner, the address of the storage area of the transfer source, the information of the number of transfers, the address of the storage area of the transfer destination, and the information of the transfer destination bit are set in the general-purpose register, and these information are set in the main RAM 74. By adopting a configuration in which a dedicated storage area is not provided, the capacity of the storage area required for the main RAM 74 can be reduced.

(5) In the first embodiment, the process of transferring the data stored in the storage area included in the transfer target range in the common command transmission process to the transmission standby buffer 112 is preset in a general-purpose register. It may be configured to be executed using information. Specifically, the address of the transfer source storage area is set in the BC register 102, and the number of transfers is set in the E register 103b. The main-side RAM 74 is not provided with a dedicated storage area for setting the address of the storage area of the transfer source and the information on the number of transfers. In the process of transferring the data stored in the storage area included in the transfer target range in the common command transmission process to the transmission standby buffer 112, the main MPU 72 performs the transfer based on the data set in the BC register 102. The address of the original storage area can be grasped, and the number of transfers can be grasped based on the data set in the E register 103b. In this way, by setting the address of the storage area of the transfer source and information on the number of times of transfer in the general-purpose register and not providing a dedicated storage area for setting such information in the main RAM 74, The capacity of the storage area required for the main RAM 74 can be reduced.

(6) In the fifth embodiment, stored in the storage area of the main RAM 74 specified by the addresses set in the first set range and the second set range of the common data table 73f (FIG. 79(a)). In addition to the data set in the first exclusion range, the data stored in the storage area of the main RAM 74 specified by the address set in the first exclusion range may also be set in the start command. As a result, in the common data table 73f, the address range in which the address specifying the storage area of the main RAM 74 in which the data is set in the start command is set is changed to the address range in which the common data table 73f is set (" 9101H" to "911AH") and can be a continuous address range of "9101H" to "9114H". Therefore, it is possible to simplify the processing configuration for setting the data stored in the storage area of the main RAM 74 as the start command. In addition to the data stored in the storage area of the main RAM 74 specified by the addresses set in the third and fourth setting ranges of the common data table 73f (FIG. 79(a)), The data stored in the storage area of the main RAM 74 specified by the address set in the 4 exclusion range may also be set in the termination command. As a result, in the common data table 73f, the address range in which the address specifying the storage area of the main RAM 74 in which data is set in the end command is changed to the address range in which the common data table 73f is set (" 9101H" to "911AH") and can be a continuous address range of "9105H" to "911AH". Therefore, it is possible to simplify the processing configuration for setting the data stored in the storage area of the main RAM 74 as the end command.

(7) In the sixth embodiment, the first aggregated range and the second aggregated range in the common data table 73g (FIG. 84(a)) may be set to consecutive address ranges. Specifically, the data stored in the lower area and upper area of the AT continuation counter 74u is also set to the end command. The data stored in the lower area and upper area of . In this configuration, in the common data table 73g, the address of the bet number setting counter 74b is set in the address range of "9101H" to "9102H", and the stop order type counter 74m is set in the address range of "9103H" to "9104H". is set, the address of the gaming state area 77 is set in the address range of "9105H" to "9106H", and the address of the highest level aggregation area 74v is set in the address range of "9107H" to "9108H" is set, the address of the lower area of the AT continuation counter 74u is set in the address range of "9109H" to "910AH", and the upper area of the AT continuation counter 74u is set in the address range of "910BH" to "910CH". address is set. In this configuration, the address of the storage area of the main RAM 74 storing the data set in the command at the start is set in the continuous address range of "9101H" to "910CH". Among the storage areas of the main RAM 74 storing the data set in the start command, the addresses of the storage areas in which the most significant bit data is set in the highest aggregation area 74v are consecutive "9109H". It is set in the address range of "910CH". This simplifies the processing configuration for setting the data stored in the storage area of the main RAM 74 as the start command. The address of the storage area of the main RAM 74 storing the data set in the command at the time of termination is set in the continuous address range of "9105H" to "911AH". Among the storage areas of the main-side RAM 74 that store the data to be set in the end command, the addresses of the storage areas in which the data of the most significant bit are set in the highest aggregation area 74v are consecutive "9109H" to "9109H". It is set in the address range of "9114H". As a result, it is possible to simplify the processing configuration for setting the data stored in the storage area of the main RAM 74 as the termination command. Thus, by setting the address range of "9109H" to "910CH" as the first aggregation range in which the addresses of the lower area and the upper area of the AT continuation counter 74u are set, the consecutive "9109H" to "9114H" can be configured such that a first aggregation range and a second aggregation range are set in the address range of . As a result, it is possible to simplify the processing configuration for aggregating the most significant bit data in the storage areas of the main RAM 74 included in the first aggregation range and the second aggregation range into the highest aggregation area 74v. .

(8) In the above-described first to fourth embodiments, when the effect-side MPU 92 receives an end command, all the information set in the end command is used to execute the end reception handling process. In addition, when the effect-side MPU 92 receives the command at the start, only a part of the information set in the command at the start is used to execute the reception corresponding process at the start. good too.

(9) In the first to fourth embodiments described above, even if data not used in the start reception handling process is set in the received start command, the data necessary for the start reception handling process from the start command is set. The command at the start received by the effect side MPU 92 may be stored in the command storage buffer 126 of the effect side RAM 94 as it is without executing the process of extracting only the data. In addition, even if the received end command contains data that is not used in the end reception handling process, the process of extracting only the data required for the end reception handling process from the end command is not executed. Alternatively, the end command received by the effect side MPU 92 may be stored in the command storage buffer 126 of the effect side RAM 94 as it is. This makes it possible to reduce the processing load of the effecting side MPU 92 until the received start command is stored in the command storage buffer 126, and the start command is stored in the command storage buffer 126 after the start command is received. It is possible to shorten the time required for the data to be stored and made available by the performance side MPU 92. - 特許庁In addition, the processing load of the production side MPU 92 until the received end command is stored in the command storage buffer 126 can be reduced, and the end command is stored in the command storage buffer 126 after the end command is received. It is possible to shorten the time required until the performance side MPU 92 can use it.

(10) In the first to fourth embodiments, the post-conversion starting command including the first to fifteenth frames FR1 to FR15 of the starting command may be generated. A post-conversion completion command including the fifteenth frames FR1 to FR15 may be generated. When receiving the command at the start, the effect-side MPU 92 converts the data of the 0th to 5th bits in the highest aggregated frame SF included in the command at the start to the highest values of the corresponding 2nd to 7th frames FR2 to FR7. A post-conversion start command is generated by setting the upper bit, and the generated post-conversion start command is stored in the command storage buffer 126 . As a result, while reducing the processing load of the production-side MPU 92 for converting the command at start to the command at start after conversion, the most significant bit of the second to seventh frames FR2 to FR7 can be set to "1". A post-start command can be made available to the MPU 92 on the production side.

When receiving the termination command, the effect-side MPU 92 converts the 0th to 5th bit data in the highest aggregated frame SF included in the termination command to the corresponding 2nd to 7th frames FR2 to FR7. A post-conversion end command is generated by setting the upper bit, and the generated post-conversion end command is stored in the command storage buffer 126 . As a result, while reducing the processing load of the production-side MPU 92 for converting the ending command into the post-conversion ending command, the most significant bit of the second to seventh frames FR2 to FR7 can be set to "1". A post-end command can be made available to the MPU 92 on the production side.

(11) In the common command transmission process in the first to third embodiments, the storage area included in the transfer target range based on the information of the end address of the transfer target range and the number of times of transfer in the common command transmission process may be configured such that a process of setting the data stored in the transmission standby buffer 112 is executed. Specifically, in the first embodiment, the end address of the transfer target range (“0001H” to “000DH”) in the common command transmission process (FIG. 50) is set to “000DH” by 116 is set, and the transfer number counter 114 of the main RAM 74 is set to "13", which is the number of storage areas included in the transfer target range. Then, the processing of steps S2811 to S2816 is repeatedly executed until the value of the transfer number counter 114 becomes "0". In this configuration, 1 is subtracted from the value of the transfer source counter 116 when updating the transfer source storage area in step S2816. As a result, in step S2816, the address of the storage area to be the transfer source area can be updated in the order of "000DH"→"000CH"→"000BH"→...→"0002H"→"0001H". In this way, in a state in which the end address of the transfer target range and the information of the number of transfers in the common command transmission process are set, the processes of steps S2811 to S2816 are repeated until the value of the transfer number counter 114 becomes "0". By adopting the configuration for execution, the data stored in the storage area included in the transfer target range can also be set in the transmission standby buffer 112 .

(12) In the top-level aggregation process in the first to third embodiments, the storage area included in the transfer target range based on the information of the end address of the transfer target range and the number of transfers in the top-level aggregation process may be configured such that a process of aggregating the data stored in the most significant bit of is executed in the highest aggregating area 74v. Specifically, in the above-described first embodiment, the end address of the transfer target range (“0001H” to “0006H”) in the top-level aggregation process (FIG. 51) is set to “0006H” by 116 is set, and the transfer number counter 114 of the main RAM 74 is set to "6", which is the number of storage areas included in the transfer target range. Then, the processing of steps S2906 to S2910 is repeatedly executed until the value of the transfer number counter 114 becomes "0". In this configuration, 1 is subtracted from the value of the transfer source counter 116 when updating the transfer source storage area in step S2909. As a result, in step S2909, the address of the storage area to be the transfer source area can be updated in the order of "0006H"→"0005H"→"0004H"→...→"0002H"→"0001H". In this way, in a state in which the end address of the transfer target range and the number of transfers in the highest-level aggregation process are set, the processes of steps S2906 to S2910 are repeated until the value of the transfer number counter 114 becomes "0". By adopting the configuration for execution, the data stored in the storage area included in the transfer target range can also be set in the transmission standby buffer 112 .

(13) In the common command transmission process (FIG. 86) in the sixth embodiment, when transmitting the start command, the start address of the storage area existing at the end of the eleventh setting range in the common data table 73g and Based on the information on the number of transfers, the data stored in the storage area of the main side RAM 74 included in the eleventh setting target range is set in the transmission standby buffer 112. When the end command is transmitted, based on the start address of the storage area at the end of the twelfth set range in the common data table 73g and the information on the number of transfers, it is included in the twelfth set target range. A configuration may be employed in which a process of setting the data stored in the storage area of the main RAM 74 in the transmission standby buffer 112 is executed. Specifically, when the command at start is transmitted, the start address of the storage area existing at the end (“910BH” to “910CH”) of the eleventh set range (“9101H” to “910CH”) is “910BH”. ' is set in the transfer source address counter 132 of the main RAM 74, and "6", which is the number of storage areas of the main RAM 74 included in the 11th set range, is set in the transfer count counter 114 of the main RAM 74. . Then, the processes of steps S4915 to S4920 are repeatedly executed until the value of the transfer number counter 114 becomes "0". In this configuration, 2 is subtracted from the value of the transfer source address counter 132 when updating the transfer source storage area in step S4920. As a result, in step S4920, the addresses stored in the transfer source address counter 132 are updated in the order of "910BH"→"9109H"→...→"9103H"→"9101H" when the start command is transmitted. be. In this way, in the state where the start address of the storage area existing at the end of the eleventh setting range and the information on the number of transfers are set, steps S4915 to step S4915 are performed until the value of the transfer number counter 114 becomes "0". The data stored in the storage area of the main side RAM 74 included in the eleventh set range can be set in the transmission standby buffer 112 by configuring to repeatedly execute the processing of S4920. In addition, when transmitting the command at the time of termination, "9119H", which is the start address of the storage area existing at the end ("9119H" to "911AH") of the twelfth set range ("9109H" to "911AH"), is used as the main address. The transfer source address counter 132 of the side RAM 74 is set, and the transfer number counter 114 of the main side RAM 74 is set to "9", which is the number of storage areas of the main side RAM 74 included in the twelfth set range. Then, the processes of steps S4915 to S4920 are repeatedly executed until the value of the transfer number counter 114 becomes "0". As described above, in this configuration, 2 is subtracted from the value of the transfer source address counter 132 when updating the transfer source storage area in step S4920. As a result, in step S4920, the addresses stored in the transfer source address counter 132 are updated in the order of "9119H"→"9117H"→ . be. In this way, in a state in which the start address of the storage area at the end of the twelfth setting range and the information on the number of transfers are set, steps S4915 to S4915 are performed until the value of the transfer number counter 114 becomes "0". The data stored in the storage area of the main side RAM 74 included in the twelfth setting range can be set in the transmission standby buffer 112 by configuring to repeatedly execute the processing of S4920.

(14) In the highest aggregation processing (FIG. 87) in the sixth embodiment, when transmitting a start command, the start address of the storage area existing at the end of the first aggregation range in the common data table 73g and Based on the information on the number of transfers, a process of setting the data stored in the most significant bit in the storage area of the main side RAM 74 included in the first aggregation range in the highest aggregation area 74v is executed. In addition, when transmitting a command at the time of termination, based on the start address of the storage area at the end of the second aggregation range in the common data table 73g and the information on the number of transfers, A configuration may be employed in which a process of setting the data stored in the most significant bit in the storage area of the main RAM 74 included in the most significant aggregation area 74v is executed. Specifically, when the command at start is transmitted, the start address of the storage area existing at the end (“9103H” to “9104H”) of the first aggregation range (“9101H” to “9104H”) is “9103H”. ' is set in the transfer source address counter 132 of the main RAM 74, and "2", which is the number of storage areas of the main RAM 74 included in the first aggregation range, is set in the transfer count counter 114 of the main RAM 74. . Then, the processing of steps S5009 to S5013 is repeatedly executed until the value of the transfer number counter 114 becomes "0". In this configuration, the value of the transfer source address counter 132 is subtracted by 2 when updating the transfer source storage area in step S5012. As a result, in step S5012, the addresses stored in the transfer source address counter 132 are updated in the order of "9103H" to "9101H" when the start command is transmitted. In this way, in a state where the start address of the storage area existing at the end of the first aggregation range and the information on the number of transfers are set, step S5009 to step S5009 until the value of the transfer number counter 114 becomes "0". The data stored in the storage area of the main side RAM 74 included in the first aggregation range can also be set in the transmission standby buffer 112 by configuring to repeatedly execute the process of S5013. In addition, when transmitting the command at the time of termination, "9113H" which is the start address of the storage area existing at the end ("9113H" to "9114H") of the second aggregation range ("910DH" to "9114H") is used as the main address. The transfer source address counter 132 of the side RAM 74 is set, and the transfer number counter 114 of the main side RAM 74 is set to "4", which is the number of storage areas of the main side RAM 74 included in the second aggregation range. Then, the processing of steps S5009 to S5013 is repeatedly executed until the value of the transfer number counter 114 becomes "0". As described above, in this configuration, 2 is subtracted from the value of the transfer source address counter 132 when updating the transfer source storage area in step S5012. As a result, in step S5012, the addresses stored in the transfer source address counter 132 are updated in the order of "9113H"→"9111H"→"910FH"→"910DH" when the end command is transmitted. In this way, in a state where the start address of the storage area existing at the end of the second aggregation range and the information on the number of transfers are set, step S5009 to step S5009 until the value of the transfer number counter 114 becomes "0". The data stored in the storage area of the main RAM 74 included in the second aggregation range can also be set in the transmission standby buffer 112 by configuring to repeatedly execute the process of S5013.

(15) In each of the above embodiments, the frame (first frame FR1) in which the data of the header HD is set in the command (for example, start command and end command) transmitted from the main MPU 72 to the effect MPU 92 The upper bits may be set to "0" and the most significant bits of frames other than the frame in which the data of the header HD is set to "1". Also in this configuration, it is possible to distinguish between a frame in which the data of the header HD is set and a frame other than the frame in which the data of the header HD is set, based on the data of the most significant bit in the frame.

(16) In each of the above embodiments, the frame (first frame FR1) in which the data of the header HD is set in the command (for example, the command at the start and the command at the end) transmitted from the main MPU 72 to the effect MPU 92 and the header Any of the 0th to 6th bits may be configured to set data "0" or "1" for distinguishing frames other than frames in which HD data is set. good. Specifically, the least significant bit (0th bit) of the frame in which the data of the header HD is set is set to "1", and the frame other than the frame in which the data of the header HD is set is "0" is set to the least significant bit (0th bit). Also in this configuration, it is possible to distinguish between a frame in which the data of the header HD is set and a frame other than the frame in which the data of the header HD is set, based on the data of the least significant bit in the frame.

(17) In each of the above-described embodiments, the configuration is not limited to the configuration in which an address is set for each 1-byte storage area in the main RAM 74, and a configuration in which an address is set for each multiple-byte storage area. good too. Specifically, the main RAM 74 is provided with a plurality of 2-byte storage areas, and an address is set for each 2-byte storage area in the main RAM 74 . As already explained in the first embodiment, the command (specifically, the command at the start and the command at the end) transmitted from the main MPU 72 to the effect MPU 92 includes a plurality of 1-byte frames FRm. Information stored in a 2-byte storage area in the main RAM 74 is set over two consecutive frames in the command. The main RAM 74 may be provided with a plurality of storage areas each having a predetermined number of bytes of 3 bytes or more, and an address may be set for each storage area of the predetermined number of bytes in the main RAM 74 .

(18) In each of the above embodiments, the data capacity of the address set for each 1-byte storage area in the main RAM 74 is not limited to 2 bytes, and the data capacity of the address is 2 bytes. , or the data capacity of the address may be larger than 2 bytes. A 1-byte storage area that can be provided in the main RAM 74 by setting an address of a number of bytes larger than 2 bytes (for example, 3 bytes) for each 1-byte storage area in the main RAM 74. can be increased. In addition, by setting an address of a number of bytes smaller than 2 bytes (for example, 1 byte) for each 1-byte storage area in the main RAM 74, when transmitting the command at the start and the command at the end, It is possible to reduce the data capacity of the addresses set in the common data tables 73f and 73g to be referred to, and reduce the data capacity of the common data tables 73f and 73g.

(19) In each of the above embodiments, a configuration may be adopted in which bits other than the most significant bit in the 1-byte storage area provided in the main RAM 74 are aggregated. Specifically, the main-side RAM 74 has a second section area in which the second section flag 76a is set to the least significant bit (the 0th bit in the 0th to 7th bits) as a 1-byte storage area. A first ending area in which the first ending flag 76b is set in the lower bit and a second ending area in which the second ending flag 76c is set in the least significant bit are provided. The three areas are provided in a continuous address range in the main RAM 74 . When the data stored in the second section flag 76a, the first ending flag 76b, and the second ending flag 76c are set in the command to be sent to the effecting MPU 92, the main side MPU 72 stores the data stored in the main side RAM 74 in a continuous address range. 1-byte aggregated data is generated by aggregating the information stored in the least significant bits in the three provided areas, and the aggregated data is set in the command. As a result, the data capacity of the command to be transmitted to the effect-side MPU 92 can be reduced as compared with the case where a total of 3 bytes of data stored in the three areas are set in the command.

(20) In each of the above embodiments, information indicating the type of command transmitted from the main MPU 72 to the effect MPU 92 (header HD data) may be set in a frame other than the first frame. Specifically, the configuration may be such that information indicating that the command is a start command is set in the last frame of the start command. Also in this configuration, the most significant bit of the first frame in the start command is set to "1" and the most significant bit of frames other than the first is set to "0", Whether or not the frame is the first frame can be identified based on the information stored in the most significant bit.

(21) In the seventh embodiment, the trigger for starting the all-lights-out state on the dual-purpose display section 66 is not limited to the event that the game is started. Specifically, the all lights-out state may be started with the event that the winning lottery process (FIG. 18) is started as a trigger. In the configuration in which the dual-use display unit 66 is temporarily turned off regardless of the presence or absence of the display corresponding to the stopping order in the dual-use display unit 66, the timing at which the presence or absence of the display corresponding to the stopping order is specified, that is, the winning lottery process (Fig. The all-lights-out state can be started at a timing before the timing at which the lottery result of 18) is specified. As a result, operation of the stop buttons 42 to 44 is effective compared to the configuration in which the all-lights-out state is started at the timing when the lottery result of the winning lottery process (FIG. 18) is specified or at a timing after that timing. The continuation time of the all-lights-out state can be extended without delaying the end timing of the all-lights-out state on the basis of the timing at which the lights are turned off.

(22) In the above-described eighth embodiment, the configuration may be such that the duration of the all-light-off state in the combined display section 66 varies. Specifically, the configuration may be such that the all-lights-out state ends when the first stop command is issued. In the eighth embodiment, as already described, when the dual-purpose display unit 66 determines that the display corresponding to the stop order is not executed, the dual-purpose display unit 66 is temporarily turned off. . The timing at which the first stop command is generated varies according to the timing at which the player operates the stop buttons 42-44. By configuring the all-lights-out state to end based on the generation of the first stop command, the stop buttons 42 to 44 can be operated while the counter for measuring the duration of the all-lights-out state is imperfect. After the is activated, the all-lights-out state can be terminated, and the number of "00" given can be displayed from the time the first stop command is generated until all the reels are stopped. can.

(23) In the above-described eighth embodiment, the trigger for starting the all-light-out state on the combined display section 66 is not limited to the event that the acceleration control of the reels 32L, 32M, and 32R is started. Specifically, in a configuration in which the acceleration control of the reels 32L, 32M, and 32R is executed in a first half acceleration period of about 150 milliseconds and a second half acceleration period of about 150 milliseconds following the first half acceleration period, the first half acceleration period may be configured such that the combined display section 66 is turned off entirely upon occurrence of an event that the operation ends. In the configuration in which the dual-use display unit 66 is temporarily turned off only in games in which the stop order correspondence display is not executed on the dual-use display unit 66, the operation of the stop buttons 42 to 44 is activated after the timing. It is also possible to adopt a configuration in which the all-lights-out state ends at the timing. Therefore, even if the configuration is such that the all-light-out state is started with an event that occurs after the timing at which the acceleration control of the reels 32L, 32M, and 32R is started, the player and the manager of the game hall can recognize it. , the dual-use display unit 66 can be brought into a fully extinguished state.

(24) In the above-described eighth embodiment, the dual-purpose display section 66 may be configured to end the all-off state at the timing when the operation of the stop buttons 42 to 44 is activated or at the timing before that timing. . If the dual-purpose display unit 66 is set to the fully extinguished state in a manner that the player or the manager of the game hall can recognize, the dual-purpose display unit 66 will display "00" from before the game starts until after the game ends. ” can be prevented from being continued.

(25) In each of the above embodiments, the reset button 56 may not be operated to start the ratio display. Specifically, in a situation where the operation power of the slot machine 10 is supplied and the set value update process in step S107 of the main process (FIG. 10) is not executed, the front door 12 is opened and either The main MPU 72 may be configured to recognize that the ratio display start operation has been performed when the stop buttons 42 to 44 are operated. As a result, the operation of the reset button 56 for executing the all clear processing (step S106), the operation of the reset button 56 for updating the set value in the set value update processing (step S107), and the start operation of the ratio display are performed. can be easily identified.

(26) In each of the above-described embodiments, it may be configured such that when the receiving circuit 87 receives the header HD and then receives the next header HD without receiving the footer FT, it is possible to recognize that a communication error has occurred. When the receiving circuit 87 identifies the occurrence of a communication error, it outputs a retransmission request signal to the transmitting circuit. If the transmission circuit does not receive a retransmission request signal after completing the transmission of the command, the transmission circuit deletes the data of the command that has been transmitted this time from the transmission standby buffer 112 . Then, when the next command is set in the transmission standby buffer 112, transmission of the next command is started. On the other hand, if a retransmission request signal is received after command transmission is completed, the command stored in the transmission standby buffer 112 is transmitted again. The receiving circuit 87 is provided with a communication error counter that counts the number of consecutive communication errors. Numerical information of "0" to "3" is stored in the communication error counter. The receiving circuit 87 adds 1 to the value of the communication error counter when the resend request signal is output, and sets the communication error counter to " 0” clear. When the value of the communication error counter reaches "3", the production side MPU 92 performs light emission control of the upper lamp 61, sound output control of the speaker 62, and display control of the image display device 63 so that communication error notification is performed. . Thereby, it is possible to inform the manager of the game hall that the command transmission from the main side MPU 72 to the effect side MPU 92 is not normally performed. In this way, when the reception circuit 87 receives the next header HD without receiving the footer FT after receiving the header HD, it is possible to recognize that a communication error has occurred, so that the main MPU 72 can It is possible to prevent data different from the data contained in the command set in the transmission standby buffer 112 from being used by the effect side MPU 92. - 特許庁

(27) In a game in which the image display device 63 notifies the reels 32L, 32M, and 32R of the stopping order and the dual-use display unit 66 displays the corresponding stopping order of the reels 32L, 32M, and 32R, image display is performed. The stop order notification on the device 63 ends when a stop command is issued to all the reels 32L, 32M, and 32R in the game, and the stop order correspondence display on the combined display unit 66 is the corresponding processing at the end of the game (Fig. 32), the game may end when the in-game flag of the main RAM 74 is cleared to "0" in step S1510. In addition, the stop order correspondence display on the combined display unit 66 ends when a stop command is issued to all the reels 32L, 32M, and 32R in the game, and the stop order notification on the image display device 63 is displayed at the end of the game. The game may end when the in-game flag of the main RAM 74 is cleared to "0" at step S1510 in the corresponding process (FIG. 32).

(28) In each of the above embodiments, the range that can be jumped by the JRS instruction is "the program address where the JRS instruction is set + 1-p (p is an integer from 2 to 16)" to "the JRS instruction is A configuration in which the range is set program address + 1 + q (where q is an integer from 1 to 15) may be used. Of these, "+1" corresponds to the word length (1 byte) of the JRS instruction itself. Also, "-p to q" is a numerical range that can be designated by a total of 5 bits, ie, 1 sign bit and 4 numerical value bits.

(29) In each of the above-described embodiments, as the address that can be specified as the jump destination of the JRS instruction, only a program address having a larger value than the program address where the JRS instruction is set may be set. Specifically, as already described in the first embodiment, in the JRS instruction, based on the program address where the JRS instruction is set and the difference information (5 bits) set in the JRS instruction, A jump destination program address (2 bytes) is relatively specified. In this configuration, the difference information (5 bits) set in the JRS instruction does not include a sign bit, and the difference information is 5-bit numerical information (one of "0" to "31" ). As a result, the range that can be jumped by the JRS instruction can be set to the range from "(the program address where the JRS instruction is set) +1 + 0" to "(the program address where the JRS instruction is set) +1 + 31". Further, in each of the above-described embodiments, as an address that can be specified as a jump destination of a JRS instruction, only a program address having a smaller value than the program address where the JRS instruction is set may be set. In this configuration, the difference information (5 bits) set in the JRS instruction does not include a sign bit, and the difference information is 5-bit numerical information (one of "0" to "31" ). As a result, the range that can be jumped by the JRS instruction is the range from "(the program address where the JRS instruction is set)-1-0" to "(the program address where the JRS instruction is set)-1-31". can be

(30) In each of the above-described embodiments, the range that can be jumped by the JR instruction is "the program address where the JR instruction is set + 2-s (s is an integer from 3 to 128)" to "the JRS instruction is A configuration in which the range is set program address + 2 + t (t is an integer from 1 to 127) may be used. Of these, "+2" corresponds to the word length (2 bytes) of the JR instruction itself. Also, "-s to t" is a numerical range that can be specified by a total of 8 bits, ie, 1 sign bit and 7 numerical value bits.

(31) In each of the above embodiments, only a program address having a larger value than the program address where the JR instruction is set may be set as the address that can be specified as the jump destination of the JR instruction. Specifically, as already explained in the first embodiment, in the JR instruction, based on the program address where the JR instruction is set and the difference information (8 bits) set in the JR instruction, A jump destination program address (2 bytes) is relatively specified. In this configuration, the difference information (8 bits) set in the JR instruction does not include a sign bit, and the difference information is 8-bit numerical information (one of "0" to "255" ). As a result, the range that can be jumped by the JR instruction can be set to the range of "(program address where the relevant JR instruction is set)+2+0" to "(program address where the relevant JRS instruction is set)+2+255". Further, in each of the above-described embodiments, as an address that can be specified as a jump destination of the JR instruction, only a program address having a smaller value than the program address where the JR instruction is set may be set. In this configuration, the difference information (8 bits) set in the JR instruction does not include a sign bit, and the difference information is 8-bit numerical information (one of "0" to "255" ). As a result, the range that can be jumped by the JR instruction is the range from "(the program address where the relevant JR instruction is set)-2-0" to "(the program address where the relevant JR instruction is set)-2-255". can be

(32) In each of the above embodiments, the configuration is not limited to the configuration in which the condition for ending the pseudo-bonus state ST4 is defined by the number of games, and the configuration in which the condition for ending the pseudo-bonus state ST4 is defined by the number of payouts. A configuration in which the condition for ending the pseudo-bonus state ST4 is defined by the net increase number, or a configuration in which the condition for ending the pseudo-bonus state ST4 is defined by the conditional net increase number may be employed. In a configuration in which the termination condition of the pseudo-bonus state ST4 is defined by the number of payouts, the pseudo-bonus state ST4 ends when the total number of game media provided by the game executed while the pseudo-bonus state ST4 continues. The game ends when the standard payout number (for example, "100") is reached, or when the ending condition of the second section SC2 is met. In a configuration in which the termination condition of the pseudo-bonus state ST4 is defined by the net increase in the number of sheets, the pseudo-bonus state ST4 is defined as "the total number of game media awarded by the game executed while the pseudo-bonus state ST4 is continued ( "0" when game media are not awarded)" to "total number of game media consumed to execute the game in the situation where the pseudo-bonus state ST4 is continued (the game is not executed If the value obtained by subtracting "0" in the situation (the total number of net increase in the pseudo-bonus state ST4) reaches the ending reference number of net increase (for example, "50"), or if the ending condition of the second section SC2 is met. to end. In a configuration in which the termination condition of the pseudo-bonus state ST4 is defined by the conditional net increase number of sheets, the pseudo-bonus state ST4 is defined by the conditional net increase number of gaming media in the pseudo-bonus state ST4 as the conditional net increase number (for example, " 50") or when the ending condition of the second section SC2 is satisfied. The conditional net increase in the number of game media in the pseudo-bonus state ST4 is defined as “the total number of game media awarded by the game executed while the pseudo-bonus state ST4 continues (no game media awarded). Subtract "the total number of game media consumed to execute the game while the pseudo-bonus state ST4 is continuing ("0" if the game is not being executed)" from "0" in the situation). In the case where the value obtained is the difference number in the pseudo-bonus state ST4, the minimum value of the difference number in the pseudo-bonus state ST4 is used as a reference value, and the difference number in the above-mentioned pseudo-bonus state ST4 is increased from the reference value. be.

(33) In each of the above-described embodiments, the AT state ST5 end condition is not limited to the configuration in which the number of games is defined. A configuration in which the termination condition of ST5 is defined by the net increase number, or a configuration in which the termination condition of the AT state ST5 is defined by the conditional net increase number may be employed. In the configuration in which the termination condition of the AT state ST5 is defined by the number of payouts, the payout of the AT state ST5 is based on the total number of game media awarded by the game executed while the AT state ST5 continues. When the number of sheets (for example, "100") is reached, or when the ending condition of the second section SC2 is satisfied, the process ends. In a configuration in which the end condition of the AT state ST5 is defined as the net increase in the number of sheets, the AT state ST5 is defined as "the total number of game media awarded by the game executed while the AT state ST5 is continued (the number of game media "0" in the situation where no award has occurred)" to "total number of game media consumed for executing the game in the situation where AT state ST5 is continued ("0" in the situation where the game is not executed) )” (total net increase number in AT state ST5) reaches the end criterion net increase number (for example, “50”), or the ending condition of the second section SC2 is satisfied. In a configuration in which the condition for ending the AT state ST5 is defined as a conditional net increase number, the AT state ST5 is a conditional net increase number (for example, "50") whose termination criterion is the conditional net increase number of game media in the AT state ST5. or when the ending condition of the second section SC2 is satisfied. The conditional net increase in the number of game media in the AT state ST5 means "the total number of game media awarded by the game executed while the AT state ST5 continues (in the situation where no game media are awarded, The value obtained by subtracting the "total number of game media consumed to execute the game while the AT state ST5 is continuing ("0" when the game is not being executed)" from "0") In the case of the difference number in the AT state ST5, the minimum value of the difference number in the AT state ST5 is used as a reference value, and the difference number in the AT state ST5 is increased from the reference value.

In addition, in the configuration in which the end condition of the AT state ST5 is defined by the number of payouts, an additional lottery is executed to determine whether or not to increase the number of payouts based on the above end criteria, and if an additional lottery is won in the additional lottery. , a predetermined number (for example, "10") may be added to the payout number of the end criterion. In addition, in the configuration where the end condition of the AT state ST5 is defined by the number of net additions, if an additional lottery is executed to determine whether or not to increase the number of net additions based on the above end criteria, and winning is won in the additional lottery. may be configured such that a predetermined number of sheets (for example, "10") is added to the net increased number of sheets of the end criterion. Furthermore, in the configuration in which the condition for ending the AT state ST5 is defined by the conditional net increase in the number of sheets, an additional lottery is executed to determine whether or not to increase the conditional payout number of the ending criteria, and the additional lottery is performed. In the case of winning, a predetermined number (for example, "10") may be added to the conditional net increase number of the end criteria.

(34) In each of the above embodiments, the data configuration of the main ROM 73 is not limited to the configuration in which a 2-byte address is set for each 1-byte storage area. A 2-byte address may be set, or a 1-byte address may be set for each 1-byte storage area.

(35) The configuration is not limited to the configuration in which the effective line is only one main line ML, and the configuration may be such that the effective line is two, three, or four or more. In this case, the number of activated lines may increase as the number of betted game media increases, or the maximum number of activated lines may be set regardless of the number of betted game media.

(36) The type of information transmitted from the main side MPU 72 to the effect side MPU 92 is not limited to those in the above embodiments. Information on the number of game media played may be transmitted from the main side MPU 72 to the effect side MPU 92 . In this case, the information on the number of game media to be provided by winning can be notified on the image display device 63 or the like. Further, even if all the reels 32L, 32M, 32R are not stopped, if the rotation of some of the reels 32L, 32M, 32R is stopped or if the rotation is stopped, the information corresponding to that is sent to the main side. It may be configured to be transmitted from the MPU 72 to the effect side MPU 92 . In this case, the image display device 63 or the like can perform an effect corresponding to the rotation of the reels 32L, 32M, and 32R.

(37) In each of the above-described embodiments, the configuration is such that the privilege of paying out medals is given when a small winning combination is established, but the configuration is not limited to such a configuration, and a configuration in which some kind of privilege is given to the player. If it is For example, it may be configured such that prizes other than medals are paid out when a small winning combination is established. Further, in a slot machine that does not have actual medal insertion and medal payout functions and that manages the medals owned by the player as credits, an increase in the number of credited medals corresponds to the granting of benefits.

(38) The present invention may be applied to a so-called B-type slot machine, a C-type, a combination of A and C types, a combination of B and C types, as well as RT games, CT games or AT machines. The present invention may be applied to any slot machine, such as a type equipped with games. Also, a configuration may be adopted in which there is a bonus state that is advantageous to the player.

(39) The symbols on the reels 32L, 32M, and 32R are not limited to pictures, numbers, letters, etc., and may be geometric lines, graphics, and the like. In addition, it is possible to compose a pattern with light, color, etc., and it is also possible to compose a pattern with a three-dimensional shape, etc., and it is possible to compose a pattern with a combination of these. In other words, the pattern may be anything as long as it functions as identifiable information.

(40) In each of the above embodiments, a specific example of the slot machine 10 has been shown, but the present invention may be applied to a pachinko machine in which games are played using game balls as game media. You may apply it to the game machine of the form which fused with the machine.

<Invention group extracted from the above embodiment>
Hereinafter, the features of the group of inventions extracted from the above-described embodiments will be described while showing effects and the like as necessary. In the following, for ease of understanding, configurations corresponding to the above-described embodiments are appropriately shown in parentheses or the like, but are not limited to the specific configurations shown in parentheses or the like.

<Characteristic group A>
Feature A1. a predetermined storage means (main-side ROM 73 or main-side RAM 74) having a plurality of storage areas (storage areas) set in association with addresses;
A predetermined range of a plurality of storage areas provided in the predetermined storage means ("0001H" to "000DH" of the main RAM 74 when transmitting the command at the start or the command at the end in the first to third embodiments) Address range, the address range of "0021H" to "0028H" of the main RAM 74 when transmitting the BB transition command in the third embodiment, and when transmitting the start command or end command in the fourth embodiment The address range of "9101H" to "911AH" in the common data table 73f, the address range of "9101H" to "910CH" in the common data table 73g in the case of transmitting the start command in the sixth embodiment, and the end command are A predetermined information group (command at the start, command at the end, command, BB transition command), a predetermined transmission means (a function of executing a common command transmission process of the main side MPU 72);
with
A gaming machine, wherein the storage area of the predetermined range is set to a continuous address range.

According to feature A1, since the predetermined range of storage areas is set in a continuous address range, it is possible to easily grasp the predetermined range of storage areas. Thereby, when transmitting the predetermined information group, it is possible to simplify the processing configuration for setting information in the predetermined information group using the information stored in the storage area of the predetermined range.

Feature A2. The predetermined information group includes predetermined unit data set in the predetermined information group using information stored in the predetermined range of storage area (start command and end command in the first to fourth embodiments). 2nd to 7th frames FR2 to FR7 and 9th to 14th frames FR9 to FR14 of the sixth embodiment, the 2nd to 6th frames FR2 to FR6 of the start command in the sixth embodiment, the 2nd frame FR2 of the end command and has a plurality of unit data (frames FRm in units of 1 byte) including the 4th to 10th frames FR4 to FR10,
Information of a bit (most significant bit) at a predetermined position in the first unit data in the predetermined information group is specific bit information (information "1"),
The gaming machine according to feature A1, wherein the bit information at the predetermined position in the unit data other than the head in the predetermined information group is information (information of "0") other than the specific bit information.

According to the feature A2, it is possible to distinguish the first unit data and the other unit data in the predetermined information group based on the information of the bit at the predetermined position. This makes it possible to grasp the delimiter position between the predetermined information group and the other information group.

Feature A3. The gaming machine according to feature A2, wherein the bit at the predetermined position in the unit data is the most significant bit (the 7th bit among 0th to 7th bits) in the unit data.

According to feature A3, it is possible to distinguish between the first unit data and the other unit data in the predetermined information group based on the information of the most significant bit. By setting the bit at the predetermined position as the most significant bit, it is possible to easily grasp the position of the bit referred to for distinguishing between the first unit data and the other unit data. As a result, it is possible to simplify the processing configuration for identifying the unit data at the head and the unit data other than the head.

Feature A4. The predetermined transmission means is a predetermined information setting means for setting the information stored in the storage area of the predetermined range to the predetermined information group (executing the common command transmission processing of the main side MPU 72 in the first to third embodiments). The game machine according to any one of features A1 to A3, characterized by comprising a function to

According to feature A4, it is possible to transmit a predetermined information group including information stored in a predetermined range of storage areas set in a continuous address range.

Feature A5. The predetermined information setting means is a range including at least a part of a plurality of storage areas included in the predetermined range (" 0001H" to "0006H", address range of "0021H" to "0027H" of the main RAM 74 in the third embodiment). Aggregation setting means (first to third The gaming machine according to feature A4, characterized by comprising a function of executing the highest-level aggregation processing of the main side MPU 72 in the embodiment of 1).

According to the feature A5, when the predetermined information group is received, based on the aggregation information set in the predetermined information group, the data stored in the bits at the predetermined positions in the plurality of storage areas included in the aggregation target range It is possible to grasp the information that was previously used. In the configuration having the configuration of feature A1 above, in which the predetermined range of storage areas is set in a continuous address range, the aggregation target range is at least a part of the plurality of storage areas included in the predetermined range. is a range that includes Therefore, it is possible to easily grasp the storage areas included in the aggregation target range. This makes it possible to simplify the processing configuration for generating consolidated information.

Feature A6. Of the storage areas in the predetermined range, storage areas not included in the aggregation target range (in the first to third embodiments, the storage area of the main RAM 74 included in the address range "0008H" to "000DH") The information stored in the bit at the predetermined position in the area) is information (information "0") other than specific bit information (information "1"), and the specific bit stored in the bit at the predetermined position The gaming machine according to feature A5, wherein information other than information is not aggregated.

According to feature A6, information stored in bits at predetermined positions is not aggregated for storage areas that are not included in the aggregation target range among the storage areas in the predetermined range. The processing load for aggregating information stored in bits at predetermined positions is reduced compared to a configuration in which information stored in bits at predetermined positions is aggregated for all storage areas included in can be mitigated.

Feature A7. The aggregation target range includes a storage area (lower area of the AT continuation counter 74u, lower area of the continuous game number counter 74r, total win A gaming machine according to feature A5 or A6, characterized in that a lower area of the counter 74s) is included.

According to feature A7, by setting a range including a storage area in which specific bit information can be stored in a bit at a predetermined position as an aggregation target range, after receiving the predetermined information group, the storage area included in the aggregation target range It is possible to grasp whether or not specific bit information is stored in a bit at a predetermined position in .

Feature A8. Any one of features A5 to A7, wherein the storage area of the predetermined range includes a storage area (top-level aggregation area 74v, BB top-level aggregation area 74β) in which the aggregation information is set. 1. The gaming machine according to 1.

According to feature A8, in the configuration having the configuration of feature A1 and in which a predetermined range of storage areas is set in a continuous address range, the predetermined range of storage areas includes a storage area in which aggregate information is set. is Therefore, by executing processing for setting the information stored in the storage area of the predetermined range to the predetermined information group, the consolidated information can be set to the predetermined information group. This makes it possible to simplify the processing configuration for setting aggregated information in the predetermined information group.

Feature A9. Address information (address information for specifying a storage area of the main RAM 74) for specifying a storage area in which information set in the specified information group is stored is stored in the storage area of the predetermined range. and
The predetermined transmission means sets the information stored in the storage area (storage area of the main side RAM 74) specified by the address information stored in the storage area of the predetermined range to the predetermined information group. The gaming machine according to any one of features A1 to A3, characterized by comprising setting means (a function of executing common command transmission processing of the main side MPU 72 in the fourth to sixth embodiments).

According to feature A9, it is possible to transmit a predetermined information group including information stored in a storage area specified by address information set in a predetermined range of storage areas. Even if the addresses for specifying the storage areas in which the information set in the predetermined information group is stored are not consecutive, the address information stored in the continuous predetermined range of storage areas is used to set the predetermined information group. By specifying the storage area in which the information set in the predetermined information group is stored, it is possible to easily grasp the storage area in which the information set in the predetermined information group is stored. This makes it possible to simplify the processing configuration for setting information in the predetermined information group.

Feature A10. The specific information setting means sets an aggregation target range ("9101H" in the common data table 73f in the fourth embodiment), which is a range including at least a part of the plurality of storage areas included in the predetermined range. ~ "910CH", the first aggregation range of the common data table 73g when transmitting the command at the start in the sixth embodiment, the second aggregation range of the common data table 73g when transmitting the command at the end in the sixth embodiment) Aggregation information in which information stored in bits (most significant bits) at predetermined positions in storage areas specified by the address information stored in the plurality of storage areas stored in the storage area 74v is aggregated information to be set) in the predetermined information group (function for executing the highest-level aggregation processing of the main MPU 72 in the fourth and sixth embodiments). The gaming machine described in .

According to the feature A10, when the predetermined information group is received, based on the aggregation information set in the predetermined information group, the address information stored in the plurality of storage areas included in the aggregation target range It is possible to grasp the information stored in the bit at the predetermined position in the identified storage area. In the configuration having the configuration of feature A1 above, in which the predetermined range of storage areas is set in a continuous address range, the aggregation target range is at least a part of the plurality of storage areas included in the predetermined range. is a range that includes Therefore, it is possible to easily grasp the storage areas included in the aggregation target range. This makes it possible to simplify the processing configuration for generating consolidated information.

Feature A11. Among the storage areas in the predetermined range, storage areas not included in the aggregation target range (in the fourth embodiment, the storage area specified by the address information stored in the address range of "910FH" to "911AH") , the storage area specified by the address information stored in the address range of "9105H" to "910CH" when transmitting the start command in the sixth embodiment, and when transmitting the end command, " 9109H" to "910CH" and "9115H" to "911AH" address ranges specified by the address information stored in the memory area specified by the address information). is information (information of "0") other than the specific bit information (information of "1"), and information other than the specific bit information stored in the bit of the predetermined position is aggregated. The gaming machine according to feature A10, characterized in that it cannot be broken.

According to feature A11, for storage areas specified by address information stored in storage areas not included in the aggregation target range among the storage areas in the predetermined range, the information stored in the bits at the predetermined positions is By adopting a configuration in which aggregation is not performed, aggregation of information stored in bits at predetermined positions is performed for all storage areas specified by address information stored in the storage areas included in the predetermined range. In comparison with the configuration described above, the processing load for aggregating information stored in bits at predetermined positions can be reduced.

Feature A12. The aggregation target range includes a storage area (lower area of the AT continuation counter 74u, lower area of the continuous game number counter 74r, total win A gaming machine according to feature A10 or A11, characterized in that it includes a storage area in which address information for specifying the counter 74s) is stored.

According to feature A12, a range including a storage area in which address information for specifying a storage area in which specific bit information can be stored in a bit at a predetermined position is stored as an aggregation target range, whereby a predetermined information group is After receiving, it is possible to grasp whether or not the specific bit information is stored in the bit at the predetermined position in the storage area specified by the address information stored in the storage area of the aggregation target range.

Feature A13. The storage area of the predetermined range includes a storage area in which address information for specifying the storage area (top-level aggregation area 74v, BB top-level aggregation area 74β) in which the aggregation information is set is stored. The game machine according to any one of features A10 to A12, characterized in that

According to feature A13, in the configuration having the configuration of feature A1 and in which a predetermined range of storage areas is set in a continuous address range, a storage area in which aggregate information is set is specified in the predetermined range of storage areas. It includes a storage area in which address information for performing is stored. Therefore, by executing processing for setting information stored in a storage area specified by address information stored in a predetermined range of storage areas to a predetermined information group, aggregate information can be set in the predetermined information group. can be done. This makes it possible to simplify the processing configuration for setting aggregated information in the predetermined information group.

Feature A14. The predetermined transmitting means is
Based on the occurrence of the first transmission trigger (operating the start lever 41 while the game medium is bet), the information stored in the storage area of the predetermined range is transferred as the predetermined information group. 1st predetermined transmission means for transmitting a 1st predetermined information group (command at start) set using various information including various information (a function of executing the processing of step S1107 of the main MPU 72 in the first embodiment, the first ~ a function of executing a common command transmission process of the main side MPU 72 in the fourth and sixth embodiments);
The predetermined range in the case of transmitting the first predetermined information group as the predetermined information group based on the occurrence of the second transmission trigger (the end of the stop control of all the reels 32L, 32M, and 32R) A second predetermined transmission means (first A function of executing the processing of step S1508 of the main MPU 72 in the embodiment, a function of executing the common command transmission processing of the main MPU 72 in the first to fourth and sixth embodiments);
with
The aggregation setting means is
First aggregation setting means for setting the aggregation information to the first predetermined information group (the function of executing the processing of steps S2811 to S2816 of the main MPU 72 in the first embodiment, the main MPU 72 in the second embodiment , the function of executing the processing of steps S4207 to S4212 of the main MPU 72 in the third embodiment, and the step S4412 to step S4416 of the main MPU 72 in the fourth embodiment. function) and
Second aggregation setting means (steps S2811 to S2816 of the main MPU 72 in the first embodiment) for setting, in the second predetermined information group, the same aggregation information as the aggregation information set in the first predetermined information group , the function of executing the processing of steps S4011 to S4015 of the main MPU 72 in the second embodiment, the function of executing the processing of steps S4207 to S4212 of the main MPU 72 in the third embodiment , a function of executing the processing of steps S4412 to S4416 of the main MPU 72 in the fourth embodiment);
The gaming machine according to any one of features A5 to A8 and features A10 to A13, comprising:

According to feature A14, the predetermined range in the case of transmitting the second predetermined information group based on the occurrence of the second transmission trigger transmits the first predetermined information group based on the occurrence of the first transmission trigger. It is the same range as the predetermined range in the case. For this reason, a process of setting information in the first predetermined information group using information stored in a storage area of a predetermined range, and a process of setting information to a first predetermined information group using information stored in the storage area of the predetermined range. 2, the process of setting the predetermined information group can be executed using a common program. This makes it possible to reduce the data volume of the program for executing the process of transmitting the first predetermined information group and the process of transmitting the second predetermined information group.

The consolidated information set in the second predetermined information group is the same information as the consolidated information set in the first predetermined information group. Therefore, it is possible to use a common program to perform the process of generating aggregate information when transmitting the first predetermined information group and the process of generating aggregate information when transmitting the second predetermined information group. can. This makes it possible to reduce the data volume of the program for executing the process of transmitting the first predetermined information group and the process of transmitting the second predetermined information group.

Feature A15. Each of the first predetermined information group and the second predetermined information group is predetermined unit data set using information stored in the storage area of the predetermined range (starting data in the first to third embodiments). 2nd to 7th frames FR2 to FR7 and 9th to 14th frames FR9 to FR14 of the hour command and end command) and unit data including aggregation unit data (top aggregate frame SF) in which the aggregation information is set (frames FRm in units of 1 byte), and
When the first predetermined information group is received, some of the predetermined unit data among the plurality of predetermined unit data contained in the first predetermined information group are used to perform the first predetermined processing (corresponding to reception at start). process), a first predetermined process execution means (a function of executing the processes of steps S3301 to S3320 in the production side MPU 92);
When the second predetermined information group is received, some of the predetermined unit data among the plurality of predetermined unit data included in the second predetermined information group are used to perform a second predetermined process (response to reception at end). process), a second predetermined process execution means (a function of executing the processes of steps S3501 to S3521 in the effect side MPU 92);
The gaming machine according to feature A14, characterized by comprising:

According to feature A15, having the configuration of feature A14, the predetermined range in the case of transmitting the second predetermined information group based on the occurrence of the second transmission opportunity is set to It is possible to execute the first predetermined process based on the first predetermined information group when the first transmission trigger occurs while the range is the same as the predetermined range when transmitting the first predetermined information group. In addition, when the second transmission opportunity occurs, the second predetermined process can be executed based on the second predetermined information group.

Feature A16. The predetermined unit data used when the first predetermined process executing means executes the first predetermined process is stored in a part of a plurality of storage areas included in the aggregation target range. contains the first usage target information (information stored in the AT continuation counter 74u) set using the information in the
The predetermined unit data used when the second predetermined process executing means executes the second predetermined process is stored in a part of a plurality of storage areas included in the aggregation target range. second use target information (information stored in the continued game number counter 74r, information stored in the total winning number counter 74s) set by using the information The gaming machine according to feature A15.

According to feature A16, having the configuration of feature A14, the predetermined range in the case of transmitting the second predetermined information group based on the occurrence of the second transmission opportunity is set to While the range is the same as the predetermined range when transmitting the first predetermined information group, when the first transmission trigger occurs, part of the plurality of storage areas included in the aggregation target range is stored. The first predetermined processing can be executed using the first usage target information set using the information stored in the area, and when the second transmission trigger occurs, the The second predetermined process can be executed using the second usage target information set using the information stored in a part of the plurality of storage areas stored in the storage area.

Feature A17. The predetermined transmitting means is
Based on the occurrence of the first transmission trigger (operation of the start lever 41 while the game medium is being bet), first predetermined information among the plurality of storage areas provided in the predetermined storage means. The first predetermined range (included in the address range of "9101H" to "910CH" of the common data table 73g in the sixth embodiment), which is the predetermined range in the case of transmitting the group (start command in the sixth embodiment). The first predetermined information group set using various information including information stored in the storage area of the main RAM 74 specified by the address information stored in the storage area) a first predetermined transmission means for transmitting (function for executing common command transmission processing of the main side MPU 72 in the sixth embodiment);
Based on the occurrence of the second transmission trigger (end of stop control of all reels 32L, 32M, 32R), a second predetermined information group (second is included in the second predetermined range (the address range of "910DH" to "911AH" in the common data table 73g in the sixth embodiment), which is the predetermined range when transmitting the end command in the sixth embodiment). A storage area of the main side RAM 74 specified by address information stored in the storage area). 2 predetermined transmission means (function for executing common command transmission processing of the main side MPU 72 in the sixth embodiment);
and
Some of the storage areas included in the first predetermined range are also included in the second predetermined range,
The gaming machine according to any one of features A1 to A16, wherein each of the storage area of the first predetermined range and the storage area of the second predetermined range is set to a continuous address range.

According to feature A17, in a configuration in which some of the plurality of storage areas included in the first predetermined range are also included in the second predetermined range, the storage areas in the first predetermined range are contiguous. By setting the address range, it is possible to easily grasp the storage area of the first predetermined range, and by setting the storage area of the second predetermined range to a continuous address range, the second predetermined range It is possible to make it easier to grasp the storage area of the range. Thus, when transmitting the first predetermined information group, it is possible to simplify the processing configuration for setting information in the first predetermined information group using the information stored in the storage area of the first predetermined range. In addition, when transmitting the second predetermined information group, it is possible to simplify the processing configuration for setting information in the second predetermined information group using the information stored in the storage area of the second predetermined range. can.

Feature A18. The predetermined transmitting means is
A predetermined reference address that is an address for specifying one storage area included in the predetermined range (in the first to fourth embodiments, the start address of the range to be transferred in the common command transmission process; in the sixth embodiment, "9101H" when transmitting the command at the start time, and "9109H" when transmitting the command at the end time) in the predetermined setting target address (in the first to third embodiments, the storage area of the transfer source, the fourth and in the sixth embodiment, the predetermined reference address setting means (the processing of step S2809 of the main MPU 72 in the first embodiment is set in the storage area where the address information for specifying the transfer source storage area is set). Function to be executed, function of executing the process of step S4009 of the main MPU 72 in the second embodiment, function of executing the process of step S4205 of the main MPU 72 in the third embodiment, main side in the fourth embodiment A function of executing the processing of step S4410 of the MPU 72, a function of executing the processing of steps S4907 and S4912 of the main MPU 72 in the sixth embodiment);
Predetermined unit data setting processing for setting predetermined unit data (frame FRm data) in the predetermined information group using information stored in the storage area specified by the predetermined setting target address (the The process of step S2811, the process of step S4011 in the second embodiment, the process of step S4207 in the third embodiment, the process of step S4412 in the fourth embodiment, and the process of step S4915 in the sixth embodiment). Predetermined unit data setting means to be executed (function of executing the process of step S2811 of the main MPU 72 in the first embodiment, function of executing the process of step S4011 of the main MPU 72 in the second embodiment, third embodiment A function of executing the processing of step S4207 of the main MPU 72 in the embodiment, a function of executing the processing of step S4412 of the main MPU 72 in the fourth embodiment, and executing the processing of step S4915 of the main MPU 72 in the sixth embodiment function) and
Predetermined update processing for updating the predetermined setting target address (processing in step S2816 in the first embodiment, processing in step S4015 in the second embodiment, processing in step S4212 in the third embodiment, processing in step S4212 in the fourth embodiment) , the processing of step S4920 in the sixth embodiment) each time the predetermined unit data setting process is executed. A function of executing processing, a function of executing the processing of step S4015 of the main MPU 72 in the second embodiment, a function of executing the processing of step S4212 of the main MPU 72 in the third embodiment, A function of executing the processing of step S4416 of the main MPU 72, a function of executing the processing of step S4920 of the main MPU 72 in the sixth embodiment);
and
After the predetermined reference address is set as the predetermined setting target address, the predetermined unit data setting means performs the number of times corresponding to the number of storage areas included in the predetermined range (in the first to fourth embodiments, The predetermined unit data setting process is executed 13 times, 6 times when the command at the start is transmitted in the sixth embodiment, and 9 times when the command at the end is transmitted in the sixth embodiment). The gaming machine according to any one of features A1 to A17.

According to feature A18, after the predetermined reference address is set as the predetermined setting target address, the predetermined unit data setting process is executed a number of times corresponding to the number of storage areas included in the predetermined range. Data can be set in predetermined information groups. With the configuration for repeatedly executing the predetermined unit data setting process, the processing configuration for setting the predetermined unit data to the predetermined information group can be simplified.

Feature A19. The predetermined transmitting means is
Based on the occurrence of the first transmission trigger (operation of the start lever 41 while the game medium is being bet), first predetermined information among the plurality of storage areas provided in the predetermined storage means. The first predetermined range (included in the address range of "9101H" to "910CH" of the common data table 73g in the sixth embodiment), which is the predetermined range in the case of transmitting the group (start command in the sixth embodiment). The first predetermined information group set using various information including information stored in the storage area of the main RAM 74 specified by the address information stored in the storage area) a first predetermined transmission means for transmitting (function for executing common command transmission processing of the main side MPU 72 in the sixth embodiment);
Based on the occurrence of the second transmission trigger (end of stop control of all reels 32L, 32M, 32R), a second predetermined information group (second is included in the second predetermined range (the address range of "910DH" to "911AH" in the common data table 73g in the sixth embodiment), which is the predetermined range when transmitting the end command in the sixth embodiment). A storage area of the main side RAM 74 specified by address information stored in the storage area). 2 predetermined transmission means (function for executing common command transmission processing of the main side MPU 72 in the sixth embodiment);
and
The predetermined reference address setting means includes:
The predetermined setting of the first predetermined reference address ("9101H" in the case of transmitting the start command in the sixth embodiment) that is an address for specifying one storage area included in the first predetermined range. a first predetermined reference address setting means for setting the target address (function for executing the process of step S4907 of the main MPU 72 in the sixth embodiment);
The second predetermined reference address ("9109H" in the case of transmitting the termination command in the sixth embodiment), which is an address for specifying one storage area included in the second predetermined range, is set in the predetermined manner. a second predetermined reference address setting means for setting the target address (function for executing the process of step S4912 of the main MPU 72 in the sixth embodiment);
and
The predetermined unit data setting means is
As the predetermined unit data setting process, a first predetermined unit data setting process of setting the predetermined unit data in the first predetermined information group using information stored in a storage area specified by the predetermined setting target address. a first predetermined unit data setting means (function for executing the process of step S4915 of the main MPU 72 in the sixth embodiment) for executing (the process of step S4915 in the sixth embodiment);
As the predetermined unit data setting process, a second predetermined unit data setting process of setting the predetermined unit data in the second predetermined information group using information stored in a storage area specified by the predetermined setting target address. a second predetermined unit data setting means (function of executing the process of step S4915 of the main MPU 72 in the sixth embodiment) for executing (the process of step S4915 in the sixth embodiment);
and
The predetermined updating means is
a first predetermined update means (a function of executing the processing of step S4920 of the main MPU 72 in the sixth embodiment) that executes the predetermined update process each time the first predetermined unit data setting process is executed;
a second predetermined update means (a function of executing the processing of step S4920 of the main MPU 72 in the sixth embodiment) that executes the predetermined update process each time the second predetermined unit data setting process is executed;
and
The first predetermined unit data setting means sets the number of times corresponding to the number of storage areas included in the first predetermined range after the first predetermined reference address is set as the predetermined setting target address (sixth executing the first predetermined unit data setting process six times in the case of transmitting the command at the start in the embodiment),
The second predetermined unit data setting means sets the number of times corresponding to the number of storage areas included in the second predetermined range (sixth the second predetermined unit data setting process is executed nine times in the case of transmitting the command at the end in the embodiment),
The second predetermined unit data setting process is executed using a program for executing the first predetermined unit data setting process,
The gaming machine according to feature A18, wherein the predetermined updating process by the second predetermined updating means is executed using a program for the first predetermined updating means to execute the predetermined updating process.

According to feature A19, after the first predetermined reference address is set as the predetermined setting target address, the first predetermined unit data setting process is performed a number of times corresponding to the number of storage areas included in the first predetermined range. By executing it, the predetermined unit data can be set in the first predetermined information group. By adopting a configuration that repeatedly executes the first predetermined unit data setting process, it is possible to simplify the processing configuration for setting the predetermined unit data in the first predetermined information group. Further, after the second predetermined reference address is set as the predetermined setting target address, the second predetermined unit data setting process is executed a number of times corresponding to the number of storage areas included in the second predetermined range. , the predetermined unit data can be set in the second predetermined information group. Since the second predetermined unit data setting process is repeatedly executed, the processing configuration for setting the predetermined unit data in the second predetermined information group can be simplified.

By using the program for executing the first predetermined unit data setting process to execute the second predetermined unit data setting process, the program for executing the first predetermined unit data setting process is different from the program for executing the first predetermined unit data setting process. Compared to a configuration in which a program for executing the second predetermined unit data setting process is provided as a program, the data capacity of the program for executing these two processes can be reduced. Since the first predetermined update means executes the predetermined update process by using the program for executing the predetermined update process, the second predetermined update means executes the predetermined update process. To reduce the data capacity of the program for executing the predetermined updating process, compared with a configuration in which a program for executing the predetermined updating process by the second predetermined updating means is provided as a program separate from the program. can be done.

For the configuration of features A1 to A19, any one of features A1 to A19, features B1 to B9, features C1 to C13, features D1 to D7, features E1 to E6, features F1 to F9, and features G1 to G7 One or more configurations may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

<Characteristic group B>
Feature B1. A first information group (command at the start) having a plurality of unit data is transmitted based on occurrence of a first transmission trigger (operating the start lever 41 with a game medium bet). 1 transmission means (function for executing common command transmission processing of the main side MPU 72 in the fourth to sixth embodiments);
Second transmission means for transmitting a second information group (completion time command) having a plurality of unit data based on occurrence of a second transmission trigger (completion of stop control of all reels 32L, 32M, 32R). (a function of executing a common command transmission process of the main MPU 72 in the fourth to sixth embodiments);
with
The first transmission means transmits a predetermined reference information group ("9101H" to "911AH" of the common data table 73f in the fourth embodiment, "910DH" to "910EH" of the common data table 73f in the fifth embodiment, and By referring to "9113H" to "9114H", "9109H" to "910CH" of the common data table 73g in the sixth embodiment), the unit data transmitted as the first information group (in the fourth embodiment, " Information stored in the storage area of the main RAM 74 specified by the address information set in the address range of "9101H" to "911AH", in the fifth embodiment, "910DH" to "910EH" and "9113H" - information stored in the storage area of the main RAM 74 specified by the address information set in the address range of "9114H", in the sixth embodiment, set in the address range of "9109H" to "910CH" (information stored in the storage area of the main side RAM 74 specified by the address information stored in the main side RAM 74). , the function of executing the processes of steps S4610 to S4618 of the main MPU 72 in the fifth embodiment, the function of executing the processes of steps S4907 to S4909 and steps S4915 to S4920 of the main MPU 72 in the sixth embodiment. ),
The second transmission means transmits unit data as the second information group by referring to the predetermined reference information group. According to the information stored in the storage area of the main RAM 74 specified by the information, and the address information set in the address ranges of "910DH" to "910EH" and "9113H" to "9114H" in the fifth embodiment, Information stored in the specified storage area of the main side RAM 74, in the sixth embodiment, the storage area of the main side RAM 74 specified by the address information set in the address range of "9109H" to "910CH" stored information) (the function of executing the processing of steps S4410 to S4416 of the main MPU 72 in the fourth embodiment, the steps S4610 to S4610 of the main MPU 72 in the fifth embodiment) A gaming machine characterized by comprising a function of executing the processing of S4618, and a function of executing the processing of steps S4907 to S4909 and steps S4915 to S4920 of the main MPU 72 in the sixth embodiment.

According to feature B1, the predetermined reference information group is referred to for specifying unit data to be transmitted as the first information group, and is also referred to for specifying unit data to be transmitted as the second information group. Therefore, the information group referred to for specifying the unit data to be transmitted as the second information group is an information group different from the predetermined reference information group to be referred to for specifying the unit data to be transmitted as the first information group. To reduce the data capacity of the information group stored in order to be able to specify the unit data to be transmitted as the first information group and the unit data to be transmitted as the second information group, compared to the configuration stored as can be done.

Feature B2. An information storage means (main ROM 73) having a plurality of storage areas (storage areas of the main ROM 73) set in association with addresses,
The feature B1, characterized in that the predetermined reference information group is stored in a storage area of a continuous predetermined address range ("9101H" to "911AH" in the fourth embodiment) in the information storage means. game machine.

According to feature B2, it is possible to simplify the processing configuration for specifying unit data to be transmitted as the first information group by referring to the predetermined reference information group, and to simplify the processing configuration by referring to the predetermined reference information group. A processing configuration for specifying unit data to be transmitted as two information groups can be simplified.

Feature B3. The first identifying means is
A predetermined reference address setting means ( A function of executing the process of step S4410 of the main MPU 72 in the fourth embodiment);
Specific processing executing means (fourth embodiment) for executing predetermined data identifying processing (processing of step S4412 in the fourth embodiment) for identifying unit data to be transmitted as the first information group based on the predetermined address to be set. a function of executing the process of step S4412 of the main MPU 72 in
Predetermined update means (main side in the fourth embodiment) that executes the predetermined update process (the process of step S4416 in the fourth embodiment) for updating the predetermined setting target address each time the predetermined data specifying process is executed. a function of executing the processing of step S4416 of the MPU 72);
and
After the predetermined reference address is set as the predetermined setting target address, the specific process execution means performs the number of times corresponding to the number of storage areas included in the predetermined address range (13 times in the fourth embodiment). The gaming machine according to feature B2, wherein the predetermined data specifying process is executed over a period of time.

According to feature B3, after the predetermined reference address is set as the predetermined setting target address based on the occurrence of the first transmission trigger, the number of times corresponding to the number of storage areas included in the predetermined address range. unit data to be transmitted as the first information group can be specified by executing the predetermined data specifying process with the . By adopting a configuration that repeatedly executes the predetermined data specifying process, it is possible to simplify the processing configuration for specifying the unit data to be transmitted as the first information group.

Feature B4. The first transmission means stores a predetermined aggregation target range ("9101H" in the fourth embodiment) including at least a part of a plurality of storage areas in which the predetermined reference information group is stored in the information storage means. ∼ "910CH") in which the information of the bit (most significant bit) at the predetermined position in the information specified by referring to the plurality of storage areas is aggregated (in the highest aggregation area 74v stored data) as unit data to be transmitted as the first information group (a function for executing the processing of steps S4412 to S4416 of the main MPU 72 in the fourth embodiment). The game machine according to any one of features B2 or B3, characterized by comprising:

According to feature B4, the first information group is transmitted in a manner that enables grasping of information of bits at predetermined positions in the information specified by referring to the plurality of storage areas included in the predetermined aggregation target range. can be done. In the configuration having the configuration of characteristic B2, in which the predetermined reference information group is stored in the storage area of the continuous address range in the information storage means, the predetermined aggregation target range is stored in the information storage means. A range that includes at least some of the multiple storage areas in the Therefore, it is possible to easily grasp the storage areas included in the predetermined aggregation target range. This makes it possible to simplify the processing configuration for generating the predetermined consolidated information.

Feature B5. Predetermined storage means (main side RAM 74) having a plurality of storage areas (storage areas of main side RAM 74) set in association with addresses,
In the predetermined reference information group, information referred to for specifying unit data to be transmitted as the first information group and unit data to be transmitted as the second information group are stored in a plurality of storage areas in the predetermined storage means. Address information (address information of the main side RAM 74 set in the common data table 73f) corresponding to a part of the storage area is set,
The first transmission means transmits, as unit data to be transmitted as the first information group, information stored in a storage area of the predetermined storage means corresponding to information of the address set in the predetermined reference information group. identify,
The second transmission means transmits, as unit data to be transmitted as the second information group, information stored in a storage area of the predetermined storage means corresponding to information of the address set in the predetermined reference information group. The gaming machine according to any one of features B1 to B4, characterized in that it is specified.

According to feature B5, as the unit data to be transmitted as the first information group, information stored in a part of the plurality of storage areas in the predetermined storage means at the timing when the first information group is transmitted. Information that can be specified and is stored in a partial storage area of a plurality of storage areas in a predetermined storage means at the timing when the second information group is transmitted as unit data to be transmitted as the second information group can be specified.

Feature B6. The first transmitting means transmits a first predetermined reference information group ("9101H" to "9104H", "910FH" to "9112H" and "9113H" to "9114H" of the common data table 73f in the fifth embodiment, A third specifying means (main MPU 72 in the fifth embodiment) for specifying unit data to be transmitted as the first information group by referring to "9101H" to "9108H" of the common data table 73g in the embodiment of 6). function to execute the processing of steps S4610 to S4618, and the function of executing the processing of steps S4907 to S4909 and steps S4915 to S4920 of the main MPU 72 in the sixth embodiment),
The second transmitting means transmits a second predetermined reference information group ("9105H" to "910CH" and "9115H" to "911AH" of the common data table 73f in the fifth embodiment, the common data table in the sixth embodiment 73g "910DH" to "911AH") to specify the unit data to be transmitted as the second information group (steps S4610 to S4618 of the main MPU 72 in the fifth embodiment) and a function to execute the processing of steps S4907 to S4909 and steps S4915 to S4920 of the main MPU 72 in the sixth embodiment),
The first information group has unit data specified by the first specifying means and unit data specified by the third specifying means,
The gaming machine according to feature B1, wherein the second information group includes unit data specified by the second specifying means and unit data specified by the fourth specifying means.

According to feature B6, as the unit data to be transmitted as the first information group, in addition to the unit data specified by referring to the predetermined reference information group, the unit specified by referring to the first predetermined reference information group Data can be identified. Further, as the unit data to be transmitted as the second information group, in addition to the unit data specified by referring to the predetermined reference information group, the unit data specified by referring to the second predetermined reference information group is specified. be able to. Since the predetermined reference information group is commonly referred to when specifying the unit data to be transmitted as the first information group and when specifying the unit data to be transmitted as the second information group, it is transmitted as the first information group Compared to a configuration in which there is no overlap between the information group referred to when specifying unit data to be transmitted as the second information group and the information group referred to when specifying unit data to be transmitted as the second information group, the first information group It is possible to reduce the data capacity of the information group to be stored in order to be able to specify the unit data to be transmitted as the second information group and the unit data to be transmitted as the second information group.

Feature B7. An information storage means (main ROM 73) having a plurality of storage areas (storage areas of the main ROM 73) set in association with addresses,
The predetermined reference information group is stored in a storage area of a continuous predetermined address range ("9109H" to "910CH" of the common data table 73g in the sixth embodiment) in the information storage means,
The first predetermined reference information group is stored in a storage area of a continuous first predetermined address range ("9101H" to "9108H" of the common data table 73g) in the information storage means,
The second predetermined reference information group is stored in a storage area of a continuous second predetermined address range ("910DH" to "911AH" in the common data table 73g) in the information storage means,
The predetermined address range and the first predetermined address range are continuous address ranges (eleventh set range of the common data table 73g),
The gaming machine according to feature B6, wherein the predetermined address range and the second predetermined address range are consecutive address ranges (a twelfth setting range of the common data table 73g).

According to the characteristic B7, since the predetermined address range and the first predetermined address range are consecutive address ranges, the unit data to be transmitted as the first information group is determined by referring to the predetermined reference information group and the first predetermined reference information group. A processing configuration for specifying can be simplified. Further, since the predetermined address range and the second predetermined address range are continuous address ranges, the unit data to be transmitted as the second information group is specified by referring to the predetermined reference information group and the second predetermined reference information group. A processing configuration can be simplified.

Feature B8. The first identifying means is
A first predetermined reference address ("9101H" in the common data table 73g in the sixth embodiment), which is one of the continuous predetermined address range and the first predetermined address range, is set to a predetermined setting target address (transfer source a first predetermined reference address setting means (a function of executing the processing of step S4907 of the main side MPU 72 in the sixth embodiment) for setting the address for specifying the storage area;
A first specifying process executing means (first 6 function of executing the process of step S4915 of the main MPU 72 in the embodiment of 6);
First predetermined updating means (sixth embodiment) for executing predetermined update processing (processing of step S4920 in the sixth embodiment) for updating the predetermined setting target address each time the first predetermined data identification processing is executed. a function of executing the processing of step S4920 of the main MPU 72 in the form);
and
The second identifying means is
A second predetermined reference address ("9109H" in the common data table 73g in the sixth embodiment), which is one of the continuous predetermined address range and the second predetermined address range, is set as the predetermined setting target address. a second predetermined reference address setting means (a function of executing the processing of step S4912 of the main MPU 72 in the sixth embodiment);
Second specifying process execution means (second 6 function of executing the process of step S4915 of the main MPU 72 in the embodiment of 6);
a second predetermined update means (a function of executing the processing of step S4920 of the main MPU 72 in the sixth embodiment) that executes the predetermined update process each time the second predetermined data identification process is executed;
and
After the first predetermined reference address is set as the predetermined setting target address, the first specific process execution means performs the number of times corresponding to the number of storage areas included in the first predetermined address range (sixth In the embodiment, the first predetermined data specifying process is executed six times in the case of transmitting the command at the start,
After the second predetermined reference address is set as the predetermined setting target address, the second specific process execution means performs the number of times corresponding to the number of storage areas included in the second predetermined address range (sixth 9 times in the case of transmitting a termination command in the embodiment), executing the second predetermined data identification process,
the second predetermined data identifying process is executed using a program for executing the first predetermined data identifying process;
The gaming machine according to feature B7, wherein the predetermined updating process by the second predetermined updating means is executed using a program for the first predetermined updating means to execute the predetermined updating process.

According to feature B8, after the first predetermined reference address is set as the predetermined setting target address, the first predetermined address range and the number of storage areas included in the first predetermined address range are repeated for a number of times. By executing the data specifying process, it is possible to specify the unit data to be transmitted as the first information group. With a configuration that repeatedly executes the first predetermined data specifying process, it is possible to simplify the processing configuration for specifying the unit data to be transmitted as the first information group. Further, after the second predetermined reference address is set as the predetermined setting target address, the second predetermined data specifying process is performed a number of times corresponding to the number of storage areas included in the predetermined address range and the second predetermined address range. By executing this, the unit data to be transmitted as the second information group can be specified. By adopting a configuration that repeatedly executes the second predetermined data specifying process, it is possible to simplify the processing configuration for specifying unit data to be transmitted as the second information group.

By using the program for executing the first predetermined data identifying process to execute the second predetermined data identifying process, the program different from the program for executing the first predetermined data identifying process can be used as a program for executing the first predetermined data identifying process. Compared to a configuration in which a program for executing the two predetermined data specifying processes is provided, the data capacity of the program for executing these two processes can be reduced. Since the first predetermined update means executes the predetermined update process by using the program for executing the predetermined update process, the second predetermined update means executes the predetermined update process. To reduce the data capacity of the program for executing the predetermined updating process, compared with a configuration in which a program for executing the predetermined updating process by the second predetermined updating means is provided as a program separate from the program. can be done.

Feature B9. a first predetermined process (reception corresponding process at start) using a part of unit data among a plurality of unit data included in the first information group when the first information group is received; 1 predetermined processing execution means (function for executing the processing of steps S3301 to S3320 in the production side MPU 92);
a second predetermined process (end-time reception handling process) using a part of unit data among a plurality of unit data contained in the second information group when the second information group is received; 2 predetermined processing execution means (function for executing the processing of steps S3501 to S3521 in the production side MPU 92);
The gaming machine according to any one of features B1 to B8, characterized by comprising:

According to feature B9, having the configuration of feature B1, the unit data to be transmitted as the first information group is specified by referring to the predetermined reference information group, and the second data unit is specified by referring to the predetermined reference information group. In a configuration in which unit data to be transmitted as an information group is specified, when the first information group is received, some of the plurality of unit data included in the first information group are used to generate the first data. 1 predetermined processing can be executed, and when a second information group is received, a second predetermined processing is performed using a part of the plurality of unit data included in the second information group can be executed.

For the configuration of features B1 to B9, any one of features A1 to A19, features B1 to B9, features C1 to C13, features D1 to D7, features E1 to E6, features F1 to F9, and features G1 to G7 One or more configurations may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

According to the invention according to the characteristics of the characteristic group A and the characteristic group B, the following problems can be solved.

Pachinko game machines and slot machines are known as game machines. For example, a pachinko machine is provided with a storage section for storing game balls, and the game balls stored in the storage section are guided to a game ball launching device and directed to a game area in response to a player's shooting operation. is fired. Then, for example, when a game ball enters a ball entry section provided in the game area, for example, a lottery process is executed, or a process for increasing the number of game balls that can be used by the player is executed. be.

In a slot machine, when a game value such as medals is betted and a new game is started by operating a start lever, a lottery process is executed by a control means. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means Rotation of the reel is stopped by execution of rotation stop control. Then, when the stop result after the rotation of the reels is stopped corresponds to the winning combination in the lottery process, a privilege corresponding to the winning combination is given to the player.

Here, in the game machines such as those exemplified above, it is necessary to suitably execute the transmission of the information group, and there is still room for improvement in this respect.

<Characteristic group C>
Feature C1. Display control means for controlling the display of the display means (dual-use display unit 66) (function of executing the processing of steps S1401 to S1409 of the main MPU 72 in the first embodiment, step S5401 of the main MPU 72 in the seventh embodiment ~ a function of executing the process of step S5411, a function of executing the process of step S5801 to step S5810 of the main side MPU 72 in the ninth embodiment);
Predetermined display information (stop order classification numbers "1" to "9") that enables predetermined display (stop order correspondence display corresponding to the value of the stop order classification counter 74m) to be performed on the display means is first First storage execution means (the function of executing the processing of steps S1101 to S1105 of the main MPU 72 in the first embodiment, the main MPU 72 in the eighth embodiment A function of executing the processing of steps S5501 to S5505, a function of executing the processing of steps S5701 to S5705 of the main side MPU 72 in the ninth embodiment);
Specific display information ("0", "1", "2", "5" or "15 ”) in the second storage means (given number counter 74e) (the function of executing the processing of steps S604 to S612 of the main MPU 72 in the first embodiment, step S 1204 of the main MPU 72 to the function of executing the processing of step S1205, the function of executing the processing of step S5303 to step S5304 of the main MPU 72 in the seventh embodiment, and the processing of step S5601 to step S5604 of the main MPU 72 in the eighth embodiment. function) and
with
The display control means is
First display control means (step S1401 to step S1403 and A function of executing the processing of step S1409, a function of executing the processing of steps S5403 to S5405 and S5411 of the main MPU 72 in the seventh embodiment, steps S5801 and S5803 of the main MPU 72 in the ninth embodiment, a function of executing the processes of steps S5804 and S5810);
second display control for causing the display means to perform the specific display based on the specific display information stored in the second storage means when the predetermined display information is not stored in the first storage means; Means (the function of executing the processing of steps S1407 to S1409 of the main MPU 72 in the first embodiment, the function of executing the processing of steps S5409 to S5411 of the main MPU 72 in the seventh embodiment, the ninth implementation function of executing the processing of steps S5808 to S5810 of the main MPU 72 in the form);
A game machine characterized by comprising:

According to the feature C1, it is possible to grasp the situation in which the predetermined display should be executed by the display means based on the fact that the predetermined display information is stored in the first storage means, and the first storage means Based on the fact that the predetermined display information is not stored in the means, it is possible to grasp the situation in which the display means should execute the specific display. As a result, while the storage means such as a dedicated flag for setting information for switching between the state in which the predetermined display is performed and the state in which the specific display is performed on the display means is inadequate, these , and the processing configuration for switching these states can be simplified.

Feature C2. The first storage execution means causes the display means to store the predetermined display information in the first storage means in a predetermined situation (a situation in which the in-game flag of the main RAM 74 is set to "1"). Predetermined display information setting means for performing the predetermined display (function for executing the processing of steps S1101 to S1105 of the main MPU 72 in the first embodiment, steps S5501 to S5501 of the main MPU 72 in the eighth embodiment) a function of executing the processing of step S5505, a function of executing the processing of steps S5701 to S5705 of the main side MPU 72 in the ninth embodiment),
Based on the occurrence of the trigger for ending the predetermined situation (the occurrence of the third stop command), the display means uses the display means based on the specific display information stored in the second storage means. Third display execution means for performing display (function for executing the processing of steps S1407 to S1409 of the main MPU 72 in the first embodiment, processing of steps S5409 to S5411 of the main MPU 72 in the seventh embodiment function to execute, a function to execute the processing of steps S5808 to S5810 of the main MPU 72 in the ninth embodiment),
The second display control means controls the display means based on the specific display information stored in the second storage means when the predetermined display information is not stored in the first storage means in the predetermined situation. Specific display executing means for performing the specific display (function for executing the processing of steps S1407 to S1409 of the main MPU 72 in the first embodiment, steps S5409 to S5411 of the main MPU 72 in the seventh embodiment and a function of executing the processing of steps S5808 to S5810 of the main side MPU 72 in the ninth embodiment).

According to feature C2, the specific display is performed by the display means based on the occurrence of the trigger for ending the predetermined situation, and the specific display is performed by the display means when the predetermined display is not performed in the predetermined situation. In the configuration, a predetermined display may be performed by setting predetermined display information in the first storage means in a predetermined situation. By performing the predetermined display in the predetermined situation, it is possible to prevent the state in which the specific display is performed on the display means from continuing for a long time.

Feature C3. Predetermined state generating means (first 7, the function of executing the processing of steps S5401, S5402 and S5411 of the main MPU 72 in the embodiment 7, and the function of executing the processing of steps S5801 to S5804 and S5810 of the main MPU 72 in the ninth embodiment). prepared,
When the predetermined display is not performed in the predetermined situation started next to the predetermined situation after the specific display is performed based on the occurrence of the trigger for ending the predetermined situation In addition, predetermined state execution means (the main MPU 72 in the seventh embodiment) sets the display means to the predetermined state before the specific display execution means starts the specific display in the predetermined situation started next. a function of executing the processing of step S5201 of the main MPU 72, a function of executing the processing of steps S5401, S5402 and S5411 of the main MPU 72, a function of executing the processing of step S5507 of the main MPU 72 in the eighth embodiment, the ninth A function of executing the processing of step S5706 of the main MPU 72 in the embodiment of 1, and a function of executing the processing of steps S5801 to S5804 and S5810 of the main MPU 72). game machine.

According to feature C3, the specific display is performed on the display means based on the occurrence of the trigger for ending the predetermined situation, and the predetermined display is performed on the display means in the predetermined situation started next to the predetermined situation. In a configuration in which a specific display is performed when there is no specific display, between the specific display performed based on the occurrence of the trigger for ending the predetermined situation and the specific display performed in the predetermined situation that started next to the predetermined situation By setting the display means to the predetermined state, it is possible to prevent the state in which the specific display is performed on the display means from continuing for a long time before and after the start of the predetermined situation in which the predetermined display is not performed.

Feature C4. The predetermined state generating means stores predetermined state information (“255”, which is extinguishing data set in the given number counter 74e in the eighth embodiment) for setting the display means to the predetermined state, to the second storage means. (a function of executing the processing of step S5201 of the main MPU 72 in the seventh embodiment, a function of executing the processing of step S5507 of the main MPU 72 in the eighth embodiment). ,
The gaming machine according to feature C3, wherein the predetermined state executing means sets the display means to the predetermined state based on the fact that the predetermined state information is stored in the second storage means.

According to feature C4, since the predetermined state information is stored in the second memory means, a dedicated memory means for setting the predetermined state information is provided in addition to the first memory means and the second memory means. The display means can be placed in a predetermined state while eliminating the need for Further, switching from a state in which the specific display is performed on the display means to a state in which the display means is in a predetermined state, and from a state in which the display means is in the predetermined state to a state in which the specific display is performed on the display means It is possible to simplify the processing configuration for switching between.

Feature C5. pattern display means (reels 32L, 32M, 32R) for variably displaying patterns;
a start operation means (start lever 41) operated to start the variable display of patterns in the pattern display means;
Acceleration control of the pattern display means based on the operation of the start operation means (processing of steps S1001 and S1002 in the first embodiment, processing of steps S5301 and S5305 in the seventh embodiment) A predetermined acceleration control means (the function of executing the processing of steps S1001 to S1002 of the main MPU 72 in the first embodiment, the processing of steps S5301 to S5305 of the main MPU 72 in the seventh embodiment function) and
with
The predetermined situation is a situation that is started at a timing prior to the timing at which the acceleration control of the pattern display means is started based on the operation of the start operation means,
The gaming machine according to feature C3 or C4, wherein the predetermined state ends before the acceleration control of the picture display means is completed in the next started predetermined state.

According to the feature C5, by ending the state in which the display means is in the predetermined state before the acceleration control of the pattern display means is completed, the specific display is performed on the display means before the acceleration control of the pattern display means is completed. can be made possible.

Feature C6. Stop operation means (stop buttons 42 to 44) operated to stop the variable display of the pattern in the pattern display means,
The predetermined display information is information indicating the type of operation mode of the stop operation means (the order in which the stop buttons 42 to 44 are operated),
The predetermined display is a display that notifies an operation mode of the stop operation means,
The gaming machine according to feature C5, wherein the specific display execution means causes the display means to perform the specific display when the operation mode of the stop operation means is not notified in the predetermined situation.

According to the feature C6, it is possible to notify the operation mode of the stop operation means by performing a predetermined display on the display means. Further, a specific display is performed on the display means. With the feature C5, the predetermined state ends before the acceleration control of the picture display means is completed. Therefore, when the operation mode of the stop operation means is not notified in the predetermined situation, the specific display is not displayed on the display means. The acceleration control of the pattern display means can be completed in the state of being performed.

Feature C7. Predetermined state generating means for setting the display means to a predetermined state (all extinguished state in the seventh and eighth embodiments, and a state in which non-inductive display is performed on the dual-purpose display section 66 in the ninth embodiment) ,
The predetermined state generation means is a predetermined state switching means (main MPU 72 in the seventh embodiment) that switches from a state in which the specific display is performed on the display means to a state in which the display means is in a predetermined state. , a function of executing the processing of step S5507 of the main MPU 72 in the eighth embodiment, and a function of executing the processing of step S5706 of the main MPU 72 in the ninth embodiment). and
The second storage execution means stores the specific display information in the second storage means while the display means is in the predetermined state, thereby causing the display means to display the specific display information from the state in which the display means is in the predetermined state. Specific display information setting means for switching to the state in which the specific display is performed (the function of executing the processing of step S1208 of the main MPU 72 in the first embodiment; the main MPU 72 in the seventh embodiment; A function of executing the process of step S5304 of the side MPU 72, a function of executing the process of step S5604 of the main side MPU 72 in the eighth embodiment). game machine.

According to feature C7, the state in which the specific display is performed on the display means is maintained for a long time by setting the display means to the predetermined state in the middle of the state in which the specific display is performed on the display means. continuation can be prevented.

Feature C8. The predetermined state switching means stores the predetermined state information ("255", which is extinguishing data set in the given number counter 74e in the eighth embodiment), in the second storage means. Means for setting the display means to the predetermined state (the function of executing the processing of steps S5401, S5402 and S5411 of the main MPU 72), or predetermined state information (stop order type in the ninth embodiment) stored in the first storage means "10" which is non-induction data set in the counter 74m) is stored, means for setting the display means to the predetermined state (steps S5802 to S5804 and steps S5810 in the main MPU 72) The gaming machine according to feature C7, characterized by comprising a function of executing

According to feature C8, in both the configuration in which the predetermined state information is stored in the first storage means and the configuration in which the predetermined state information is stored in the second storage means, in addition to the first storage means and the second storage means, The display means can be set to the predetermined state without providing a dedicated storage means for setting the predetermined state information. In the configuration in which the predetermined state information is stored in the second storage means, switching from the state in which the specific display is performed on the display means to the state in which the display means is in the predetermined state, and from the state in which the display means is in the predetermined state It is possible to simplify the processing configuration for switching to the state in which the specific display is being performed on the display means.

Feature C9. Predetermined display determination processing for determining whether or not the execution condition for the predetermined display is satisfied in the state in which the specific display is being performed on the display means (the processing of steps S5501 to S5503 in the eighth embodiment, the processing of steps S5701 to S5703 in the ninth embodiment) (the function of executing the processing of steps S5501 to S5503 of the main MPU 72 in the eighth embodiment; a function to execute the processing of steps S5701 to S5703 of the main side MPU 72),
The first storage execution means causes the display means to store the predetermined display information in the first storage means when it is determined in the predetermined display determination process that the execution condition for the predetermined display is satisfied. to switch from the state in which the specific display is performed to the state in which the predetermined display is performed on the display means,
The predetermined state switching means switches the display means from a state in which the specific display is being performed on the display means when it is determined in the predetermined display determination process that the condition for executing the predetermined display is not satisfied. The gaming machine according to feature C7 or C8, wherein switching to the predetermined state is performed.

According to feature C9, the predetermined determination process is executed while the specific display is being performed on the display means, and when it is determined in the predetermined determination process that the execution condition for the predetermined display is satisfied, the display means , the state in which the specific display is performed is switched to the state in which the predetermined display is performed by the display means. Thereby, it is possible to prevent the specific display from being continued for a long time on the display means. Further, when it is determined in the predetermined determination process that the execution condition for the predetermined display is not satisfied, the state in which the specific display is performed on the display means is switched to the state in which the display means is in the predetermined state. will be As a result, even when it is determined that the execution condition for the predetermined display is not satisfied and the predetermined display is not executed by the display means, the state in which the specific display is performed by the display means is prevented from continuing for a long time. can do.

Feature C10. pattern display means (reels 32L, 32M, 32R) for variably displaying patterns;
a start operation means (start lever 41) operated to start the variable display of patterns in the pattern display means;
stop operation means (stop buttons 42 to 44) operated to stop the variable display of the pattern in the pattern display means;
A specific situation where the variable display of the pattern can be stopped by operating the stop operation means after the variable display of the pattern is started (situation in which the operation of the stop buttons 42 to 44 is enabled) ) (the function of executing the processing of steps S1002 and S1003 of the main MPU 72 in the first embodiment),
with
The specific display information setting means, when it is determined in the predetermined display determination process that the condition for executing the predetermined display is not satisfied, sets the timing (eighth implementation) after the timing at which the specific situation is started. When the value of the extinguishing time counter 74δ becomes "0" after the continuation time of the all extinguished state has passed in the form), the specific display information is stored in the second storage means, so that the display means is in the predetermined state. The gaming machine according to feature C9, characterized in that the state is switched to the state in which the specific display is performed on the display means.

According to the feature C10, the state in which the display means is in the predetermined state is switched to the state in which the display means is performing the specific display at a timing after the timing at which the specific situation is started. As a result, compared to a configuration in which the state in which the display means is in the predetermined state is switched to the state in which the display means is performing the specific display at the timing when the specific situation starts or at the timing before that timing. Therefore, the state in which the display means is in the predetermined state can be maintained for a long time. As a result, the state in which the display means is in the predetermined state can be easily recognized by the player or the manager of the game hall.

Feature C11. pattern display means (reels 32L, 32M, 32R) for variably displaying patterns;
a start operation means (start lever 41) operated to start the variable display of patterns in the pattern display means;
stop operation means (stop buttons 42 to 44) operated to stop the variable display of the pattern in the pattern display means;
with
The predetermined display information is information indicating the type of operation mode of the stop operation means (the order in which the stop buttons 42 to 44 are operated),
The gaming machine according to any one of the features C1 to C10, wherein the predetermined display is a display that notifies an operation mode of the stop operation means.

According to the characteristic C11, it is possible to grasp the operation mode of the stop operation means based on the display contents of the predetermined display performed by the display means.

Feature C12. The specific display information is information indicating the number of game values (medals, virtual medals, game media) given to the player,
The gaming machine according to any one of features C1 to C11, wherein the specific display is a display for notifying the number of game values awarded to the player.

According to the feature C12, it is possible to grasp the number of game values given to the player based on the display contents of the specific display performed by the display means.

Feature C13. The second storage execution means stores, as the specific display information, first specific display information (information of "0" set in the awarded number counter 74e) indicating that the game value has not been awarded to the player. It has a first specific display information setting means (a function of executing the processing of steps S607 and S612 of the main side MPU 72 in the first embodiment) to be stored in the second storage means,
When the predetermined display information is not stored in the first storage means and the first specific display information is stored in the second storage means, the second display control means and, based on the first specific display information, a first specific display indicating that the game value has not been awarded to the player as the specific display (display of number of awards of "00") is performed on the display means. The game machine according to feature C12, characterized in that

According to the feature C13, by confirming the first specific display performed by the display means, it is possible to grasp that the game value has not been awarded to the player. In the case where the configuration of the features C1 and C12 is provided and the predetermined display information is not stored in the first storage means, a In a configuration in which a specific display for notifying the number of given game values is performed, even when no game value is given to the player, the display means is based on the first specific display information stored in the second storage means. , the first specific display is performed. Thereby, when the predetermined display information is not stored in the first storage means, the processing configuration for performing the specific display on the display means based on the specific display information stored in the second storage means is simplified. be able to.

For the configuration of features C1 to C13, any one of features A1 to A19, features B1 to B9, features C1 to C13, features D1 to D7, features E1 to E6, features F1 to F9, and features G1 to G7 One or more configurations may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

According to the invention according to the characteristics of the characteristic group C, the following problems can be solved.

Pachinko game machines and slot machines are known as game machines. For example, a pachinko machine is provided with a storage section for storing game balls, and the game balls stored in the storage section are guided to a game ball launching device and directed to a game area in response to a player's shooting operation. is fired. Then, for example, when a game ball enters a ball entry section provided in the game area, for example, a lottery process is executed, or a process for increasing the number of game balls that can be used by the player is executed. be.

In a slot machine, when a game value such as medals is betted and a new game is started by operating a start lever, a lottery process is executed by a control means. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means Rotation of the reel is stopped by execution of rotation stop control. Then, when the stop result after the rotation of the reels is stopped corresponds to the winning combination in the lottery process, a privilege corresponding to the winning combination is given to the player.

Here, in the gaming machines such as the above examples, display control of the display means must be preferably executed, and there is still room for improvement in this respect.

<Characteristic group D>
Feature D1. The numerical information to be determined (the value of the index value counter 74f) has a predetermined minimum value ("0" in the first, tenth to thirteenth embodiments) and a predetermined maximum value (first, tenth to thirteenth "255" in the embodiment) and the reference numerical range that does not include both of these predetermined minimum and maximum values ("1" to "9 ”, and the numerical range of “11” to “15” in the start-time addition processing in the first, tenth to thirteenth embodiments). The function of executing the instructions of the line numbers "1213" to "1215" of the main MPU 72 in the embodiment of the above, the function of executing the instructions of the line numbers "1302" to "1304" of the main MPU 72, 10th The function of executing the instructions of line numbers "1402" to "1404" of the main MPU 72 in the embodiment, and the function of executing the instructions of line numbers "1502" to "1504" of the main MPU 72 in the eleventh embodiment. function to execute, the function to execute the processing of steps S6003 to S6005 of the main MPU 72 in the twelfth embodiment, and the commands of line numbers "1602" to "1604" of the main MPU 72 in the thirteenth embodiment. function) and
Based on the identification by the numerical value identifying means that the numerical information to be determined is included in the reference numerical range, a predetermined process (line number "1216" to line number "1217", the process of executing the instructions of line numbers "1305" to "1309", and the process of executing the instructions of line numbers "1405" to "1409" in the tenth embodiment. , the process of executing the commands of line number "1505" to line number "1511" in the eleventh embodiment, the process of steps S6006 to step S6020 in the twelfth embodiment, the line number "1605" in the thirteenth embodiment to execute the command of line number “1609”) (the function of executing the command of line number “1216” to line number “1217” of the main side MPU 72 in the first embodiment, the main The function of executing the instructions of the line numbers "1305" to "1309" of the side MPU 72, the function of executing the instructions of the line numbers "1405" to "1409" of the main side MPU 72 in the tenth embodiment, 11 embodiment of the main side MPU 72 line number "1505" to line number "1511" of the execution function, the main side MPU 72 in the twelfth embodiment of the function of executing the processing of step S6006 ~ step S6020, 13 embodiment of the main side MPU 72 line number "1605" to line number "1609" execution function),
with
The numerical value specifying means is
A first boundary value ("9" in the lottery result correspondence process, "11" in the start addition process), which is one of the minimum value and the maximum value of the reference numerical range, is the predetermined minimum value and the predetermined maximum value. A second boundary that is the other of the minimum value and the maximum value of the reference numerical range, which is the value on the corresponding side in the magnitude relationship (“255” in the lottery result correspondence process, and “0” in the start addition process). The value ("1" in the lottery result correspondence process, "15" in the process for addition at the start) is changed by the amount of variation for making the first boundary value the value on the corresponding side (lottery '247' in the result correspondence process, and '4' in the process for adding at the start) (the process of executing the SUB instruction of the line number "1302" in the first embodiment, The process of executing the ADD instruction of line number "1213", the process of executing the SUB instruction of line number "1402" in the tenth embodiment, the process of executing the SUB instruction of line number "1502" in the eleventh embodiment , the process of step S6003 in the twelfth embodiment, and the process of executing the SUB instruction of line number "1602" in the thirteenth embodiment) on the numerical information to be determined (the first The function of executing the SUB instruction of the line number "1302" of the main MPU 72 in the embodiment, the function of executing the ADD instruction of the line number "1213" of the main MPU 72 in the tenth embodiment, the line number of the main MPU 72 in the tenth embodiment The function of executing the SUB instruction of "1402", the function of executing the SUB instruction of line number "1502" of the main MPU 72 in the eleventh embodiment, and the processing of step S6003 of the main MPU 72 in the twelfth embodiment. function to execute the SUB instruction of the line number "1602" of the main MPU 72 in the thirteenth embodiment);
By specifying the magnitude relationship between the calculation result (numerical information stored in the A register 101b after calculation) after execution of the predetermined calculation for the numerical information to be determined and the post-variation boundary value, Specific execution means for specifying whether or not the numerical information is included in the reference numerical range (a function to execute the instructions of the line number "1214" to line number "1215" of the main MPU 72 in the first embodiment, the main The function of executing the instructions of the line numbers "1303" to "1304" of the side MPU 72, the function of executing the instructions of the line numbers "1403" to "1404" of the main side MPU 72 in the tenth embodiment, 11 embodiment of the main side MPU72 line number "1503" ~ line number "1504" of executing the command, the main side MPU72 in the twelfth embodiment of the function of executing the processing of step S6004 ~ step S6005, 13 embodiment of the main side MPU 72 line number "1603" to line number "1604" execution function),
A game machine characterized by comprising:

According to feature D1, a predetermined calculation is performed on the numerical information to be determined, and the magnitude relationship between the calculation result after execution of the predetermined calculation and the post-variation boundary value is specified, so that the numerical information to be determined is In order to specify whether the numerical information to be judged is included in the reference numerical range by specifying whether it is included in the reference numerical range, the numerical information to be judged is the minimum value of the reference numerical range In comparison with a configuration that executes processing to identify whether the numerical information to be judged is equal to or greater than the maximum value of the reference numerical value range, the numerical value to be judged It is possible to simplify the processing configuration for identifying whether the information is within the reference numerical range.

Feature D2. The predetermined arithmetic operation executing means performs a predetermined arithmetic operation (line number "1302 , the SUB instruction of line number "1402" in the tenth embodiment, the SUB instruction of line number "1502" in the eleventh embodiment, the processing of step S6003 in the twelfth embodiment, the thirteenth embodiment SUB instruction of line number "1602" in the form) (the function of executing the instruction of line number "1302" of the main side MPU 72 in the first embodiment, the main side in the tenth embodiment The function of executing the instruction of the line number "1402" of the MPU 72, the function of executing the instruction of the line number "1502" of the main MPU 72 in the eleventh embodiment, and the processing of step S6003 of the main MPU 72 in the twelfth embodiment and the function of executing the command of the line number "1602" of the main MPU 72 in the thirteenth embodiment),
In the predetermined arithmetic operation, when the numerical information to be determined is numerical information equal to or greater than the first boundary value, numerical information smaller than the numerical information to be determined by the first boundary value is used for the predetermined arithmetic operation. When the numerical information to be determined is the second boundary value that is the maximum value of the reference numerical range, the calculation result after execution is the second boundary value that is smaller than the second boundary value by the first boundary value. When the boundary value is the calculation result after execution of the predetermined arithmetic operation, and the numerical information to be determined is numerical information less than the first boundary value, the numerical information greater than the post-variation boundary value is calculated by the predetermined arithmetic operation. is an operation that is the result of the operation after execution of the operation,
The specifying execution means specifies that a calculation result after execution of the predetermined arithmetic operation on the numerical information to be determined is equal to or less than the post-variation boundary value, so that the numerical range to be determined is the reference numerical range. Numerical range specifying means (function to execute the command of line number "1303" to line number "1304" of the main side MPU 72 in the first embodiment, the main side in the tenth embodiment A function of executing the instructions of the line numbers "1403" to "1404" of the MPU 72, a function of executing the instructions of the line numbers "1503" to "1504" of the main MPU 72 in the eleventh embodiment, the twelfth function to execute the processing of steps S6004 to S6005 of the main MPU 72 in the embodiment, and a function to execute the instructions of the line number "1603" to line number "1604" of the main MPU 72 in the thirteenth embodiment). The gaming machine according to feature D1, characterized in that

According to feature D2, when the numerical information to be determined is numerical information greater than the second boundary value, which is the maximum value of the reference numerical range, the numerical information greater than the post-change boundary value becomes is the calculation result. Further, when the numerical information to be determined is numerical information less than the minimum value of the reference numerical value range, the numerical information greater than the post-variation boundary value becomes the calculation result after execution of the predetermined arithmetic operation. Therefore, when the numerical information to be determined is numerical information that is not included in the reference numerical range, the numerical information larger than the post-variation boundary value can be used as the calculation result after execution of the predetermined arithmetic operation. On the other hand, if the numerical information to be judged is numerical information included in the reference numerical range (numerical information that is equal to or greater than the first boundary value and equal to or less than the second boundary value), numerical information that is equal to or less than the post-change boundary value is the operation result after execution of the predetermined arithmetic operation. Therefore, it is determined whether or not the calculation result after execution of the predetermined arithmetic operation is equal to or less than the post-change boundary, and in the determination, it is specified that the calculation result after execution of the predetermined arithmetic operation is equal to or less than the post-change boundary. Thus, it can be specified that the numerical range to be determined is included in the reference numerical range. As a result, two determinations are made: determining whether the numerical information to be determined is greater than or equal to the minimum value of the reference numerical range, and determining whether or not the numerical information to be determined is less than or equal to the maximum value of the reference numerical range. can reduce the number of judgment processes required to identify whether the numerical information to be judged is included in the reference numerical range, and the numerical information to be judged is the reference It is possible to simplify the processing configuration for specifying that it is included in the numerical range.

Feature D3. A calculation result after execution of the predetermined arithmetic operation, and a predetermined boundary value that is a value greater than the predetermined minimum value and less than the post-variation boundary value (in the process for addition at start in the first embodiment, "3"), based on the magnitude relationship, the numerical information to be determined contains the first boundary value in the reference numerical range, the first reference numerical range (addition processing at the start in the first embodiment In the numerical range of "11" to "13") and the second reference numerical range including the second boundary value (numerical range of "14" to "15" in the processing for addition at start in the first embodiment) It is characterized by having a predetermined numerical value specifying means for specifying which one is included (function to execute the command of line number "1306" and line number "1307" of the main side MPU 72 in the first embodiment). The gaming machine according to feature D2.

According to the feature D3, after specifying that the numerical information to be determined is included in the reference numerical range based on the result of the execution of the predetermined arithmetic operation, the result of the execution of the predetermined arithmetic operation and the predetermined Based on the magnitude relationship with the boundary value, the numerical information to be judged is specified in which of the reference numerical range, the first reference numerical range or the second reference numerical range, to determine whether the numerical information to be judged is included. is greater than or equal to the minimum value of the predetermined reference numerical range, and whether or not the numerical information to be determined is less than or equal to the maximum value of the predetermined reference numerical range. , it is possible to simplify the processing configuration for specifying in which of the reference numerical value ranges the numerical information to be determined is included, the first reference numerical value range or the second reference numerical value range.

Feature D4. The number of bits required to represent the predetermined boundary value (2 bits in the process for addition at start in the first embodiment) is the boundary value between the first reference numerical range and the second reference numerical range ("14 ”), the number of bits is smaller than the number of bits (4 bits) required to represent the character D3.

According to feature D4, the configuration of feature D2 is provided, and the predetermined arithmetic operation is an operation of subtracting the minimum value of the reference numerical value range from the numerical information to be determined, so that the number of bits required to represent the predetermined boundary value is can be set to a smaller number of bits than the number of bits required to represent the boundary value between the first reference numerical range and the second reference numerical range. Data capacity of information to be stored in order to execute processing for determining whether or not the result of a predetermined arithmetic operation is equal to or greater than a predetermined boundary value by suppressing the number of bits of information indicating a predetermined boundary value. can be reduced.

Feature D5. Subtracting a specific boundary value (“2” in the eleventh embodiment) that is greater than the predetermined minimum value and less than the post-variation boundary value from the result of execution of the predetermined arithmetic operation specific arithmetic operation (CP instruction of line number "1506" in the eleventh embodiment) to execute a specific arithmetic operation means (function of executing the instruction of line number "1506" of the main side MPU 72 in the eleventh embodiment) and,
A specific process execution means (second 11 embodiment of the main side MPU 72 line number "1505" to line number "1511" execution function),
The gaming machine according to feature D2, characterized by comprising:

According to the feature D5, by generating information (result of the specific arithmetic operation) used for executing the specific processing using the result of the execution of the predetermined arithmetic operation, the determination can be made independently of the predetermined arithmetic operation. To simplify the processing configuration for generating information used for executing specific processing compared to the configuration for generating information used for executing specific processing using target numerical information. can be done.

Feature D6. A first event that occurs in the specific arithmetic operation when the operation result after the execution of the predetermined arithmetic operation is the same numerical information as the specific boundary value (the operation result of the CP instruction at line number "1506" is "0") A first information storage area (zero flag ZF) in which specific information (information "1") is set based on the occurrence of an event that becomes
A second event that occurs in the specific arithmetic operation when the operation result after the execution of the predetermined arithmetic operation is numerical information less than the specific boundary value a second information storage area (carry flag CF) in which the specific information is set based on the occurrence of a borrowing event);
with
The specific process execution means is
After execution of the specific arithmetic operation, when the specific information is set in the first information storage area, a first specific process (process for executing a third additional lottery in the eleventh embodiment) is executed. a first specific process executing means (a function of executing the commands of line numbers "1508", "1509" and "1511" of the main MPU 72 in the eleventh embodiment);
After executing the specific arithmetic operation, when the specific information is set in the second information storage area, a second specific process (a process for executing a second additional lottery in the eleventh embodiment) is executed. Second specific process execution means (line number "1510" and function to execute the command of line number "1511");
After the execution of the specific arithmetic operation, if the specific information is not set in either the first information storage area or the second information storage area, the third specific process (the first additional lottery in the eleventh embodiment process for executing a process) (line number "1505", line number "1507", line number "1509" and line number "1511" of the main MPU 72 in the eleventh embodiment). ”), and
The gaming machine according to feature D5, characterized by comprising:

According to feature D6, the first specific process is executed, the second specific process is executed, and the third specific process is executed in a manner corresponding to the numerical information to be determined. can be done. When it is specified that the numerical information to be judged is included in the reference numerical range based on the calculation result after execution of the predetermined arithmetic operation, the specific arithmetic operation is performed using the calculation result after execution of the predetermined arithmetic operation and executing any one of the first specific process, the second specific process, and the third specific process based on the states of the first information storage area and the second information storage area after the execution of the specific arithmetic operation. . For this reason, an operation for determining whether or not the numerical information to be judged is less than the minimum value of the reference numerical range by a specific boundary value, and is a value greater than a specific boundary value, compared to a configuration that performs two calculations, when the numerical information to be judged is included in the reference numerical range, the judgment target The number of operations required to cause the first specific process to be executed, the second specific process to be executed, and the third specific process to be executed in a manner corresponding to the numerical information of can be reduced. Accordingly, when the numerical information to be determined is included in the reference numerical range, the first specific process is executed in a manner corresponding to the numerical information to be determined, the second specific process is executed, and the It is possible to simplify the processing configuration for generating the case where the third specific processing is executed.

Feature D7. The number of bits required to represent the specific boundary value (2 bits in the eleventh embodiment) is a value larger than the minimum value of the reference numerical range by the specific boundary value ("11" in the eleventh embodiment). ), the number of bits is smaller than the number of bits (4 bits) required to represent ).

According to feature D7, the configuration of feature D2 is provided, and the predetermined arithmetic operation is an operation of subtracting the minimum value of the reference numerical value range from the numerical information to be determined, so that the number of bits required to represent the specific boundary value is can be less than the number of bits required to represent a value above the minimum value of the reference numerical range by a specified boundary value. By reducing the number of bits of the information indicating the specific boundary value, it is possible to reduce the data volume of the information stored for executing the specific arithmetic operation.

For the configuration of features D1 to D7, any one of features A1 to A19, features B1 to B9, features C1 to C13, features D1 to D7, features E1 to E6, features F1 to F9, and features G1 to G7 One or more configurations may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

<Characteristic group E>
Features E1. Depending on the contents of the command to be executed, the first state (the value of the jump flag JF is "1" in the power-off standby process in the first embodiment, the value of the jump flag JF is "1" in the AT state signal setting process). 0") and the second state (the state in which the value of the jump flag JF is "0" in the power-off standby process, and the state in which the value of the jump flag JF is "1" in the AT state signal setting process). a predetermined storage area (jump flag JF) that takes a state;
When a predetermined jump instruction (the JRS instruction of line number "1002" and the JRS instruction of line number "1110" in the first embodiment) becomes an instruction to be executed while the predetermined storage area is in the first state. jumps to a predetermined program address ("ADR101" in the power-off standby process and "ADR114" in the AT state signal setting process) set as a jump destination in the predetermined jump instruction, and the predetermined storage area is set to the second state. When the predetermined jump instruction becomes an instruction to be executed in a state, the instruction next to the predetermined jump instruction is set without jumping to the predetermined program address set as the jump destination for the predetermined jump instruction. Predetermined jump instruction execution means (JRS execution circuit 107, function to execute JRS instruction of line number "1002" in main MPU 72, JRS instruction of line number "1110" in main MPU 72 to be executed) function) and
with
A predetermined program (power-off standby processing program, AT state signal setting processing program) in which the predetermined jump instruction is set includes a predetermined process (first A predetermined instruction (executed by the main MPU 72 in the first embodiment) for executing the instruction of the line number "1001" and the process of executing the instruction of the line number "1109" in the embodiment of OUT instruction of line number "1001", XOR instruction of line number "1109") are set,
A gaming machine, wherein the predetermined storage area is set to the first state when the predetermined command is executed.

According to feature E1, in a configuration in which a jump to a predetermined program address is performed when a predetermined jump instruction becomes an instruction to be executed while the predetermined storage area is in the first state, the predetermined storage area is stored when the predetermined instruction is executed. becomes the first state. Further, in the predetermined program, the predetermined instruction is to be executed before the predetermined jump instruction. Therefore, when a predetermined jump instruction is to be executed in a predetermined program, it is possible to jump to the predetermined program address of the jump destination. The predetermined instruction is an instruction for executing a predetermined process and an instruction for setting the predetermined storage area to the first state before the predetermined jump instruction is executed. For this reason, compared to a configuration in which an instruction for setting a predetermined storage area to the first state before a predetermined jump instruction is executed is provided as an instruction separate from an instruction for executing a predetermined process, It is possible to reduce the data volume of the program for executing the predetermined process and setting the predetermined storage area to the first state before the predetermined jump instruction is executed.

Feature E2. Characteristic feature E1 according to feature E1, characterized in that when the predetermined instruction is executed, the predetermined storage area is in the first state regardless of the state of the predetermined storage area before execution of the predetermined instruction. game machine.

According to feature E2, the predetermined jump is performed both when the state of the predetermined storage area before execution of the predetermined instruction is the first state and when the state of the predetermined storage area before execution of the predetermined instruction is the second state. It is possible to jump to a predetermined program address when an instruction is to be executed.

Feature E3. the predetermined program address is a program address at which an instruction to be executed prior to the predetermined jump instruction is set when the predetermined program is executed from the first program address in the predetermined program;
The game machine according to feature E1 or E2, wherein instructions set between the predetermined program address and the program address at which the predetermined jump instruction is set are repeatedly executed.

According to feature E3, one predetermined jump instruction can be used to repeatedly execute instructions set between a predetermined program address and a program address at which the predetermined jump instruction is set. In the predetermined program having the configuration of feature E1, a predetermined instruction is set as an instruction to be executed prior to the predetermined jump instruction, and when the predetermined instruction is executed, the predetermined storage area is in the first state. Therefore, even if the predetermined jump instruction is executed in a state where the instructions set between the predetermined program address and the program address where the predetermined jump instruction is set are repeatedly executed It is possible to prevent the occurrence of a case where a jump to a predetermined program address is not performed.

Feature E4. The feature E3, characterized in that the instructions set between the predetermined program address and the program address at which the predetermined jump instruction is set are repeatedly executed until the supply of operating power is stopped. game machine.

According to feature E4, using one predetermined jump instruction, the instruction set between the predetermined program address and the program address where the predetermined jump instruction is set is stopped until the supply of operating power is stopped. It can be in a state of being repeatedly executed. As a result, regardless of the timing at which the supply of operating power is stopped, the supply of operating power can be stopped in such a manner that no abnormality occurs when the supply of operating power is resumed.

Feature E5. A specific state (program reset state) occurs when a predetermined event (an event in which an initial value is set in the watchdog timer 86a) does not occur for a predetermined period of time (240 milliseconds). Equipped with specific state generating means (abnormality monitoring circuit 86),
Instructions set between the predetermined program address and the program address at which the predetermined jump instruction is set include an instruction for causing the predetermined event (line number "1001" in the first embodiment). The gaming machine of feature E4, characterized in that it includes a command of

According to feature E5, when instructions set between a predetermined program address and a program address at which a predetermined jump instruction is set are repeatedly executed, there is a state in which a predetermined event does not occur. It is possible to prevent continuation over a predetermined period. As a result, after the instructions set between the predetermined program address and the program address at which the predetermined jump instruction is set are repeatedly executed, the operation power supply is stopped before the timing. It is possible to prevent the specific state from occurring at the timing of .

Feature E6. The predetermined instruction is an instruction for generating information (a value of "0") to be set in a predetermined storage means (AT state signal counter 74w) after jumping to the predetermined program address. A gaming machine according to any one of features E1 to E5.

According to feature E6, the predetermined instruction is an instruction for generating information to be set in the predetermined storage means, and the predetermined storage area is in the first state before the predetermined jump instruction is executed. This command is for Therefore, an instruction for setting a predetermined storage area to the first state before a predetermined jump instruction is executed is provided as a separate instruction from the instruction for generating the information set in the predetermined storage means. Compared to the configuration in which the above configuration is used, the data capacity of the program for generating the information to be set in the predetermined storage means and for setting the predetermined storage area to the first state before the predetermined jump instruction is executed is reduced. can do.

For the configuration of features E1 to E6, any one of features A1 to A19, features B1 to B9, features C1 to C13, features D1 to D7, features E1 to E6, features F1 to F9, and features G1 to G7 One or more configurations may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

<Feature group F>
Feature F1. In the specific program (program for additional processing at start), the first predetermined program address (“ADR131” in the first embodiment, “ADR141” in the tenth embodiment, “ADR152” in the eleventh embodiment, The second predetermined program address (“ADR132” in the first embodiment, “ADR142” in the tenth embodiment, “ADR153” in the eleventh embodiment, “ADR153” in the thirteenth embodiment, “ADR171” in the thirteenth embodiment), ("ADR172" in the embodiment) as the jump destination (the JRS instruction of line number "1307" in the first embodiment; the JR instruction of line number "1407" in the tenth embodiment; In the 11th embodiment, the JR instruction of the line number "1509", and in the 13th embodiment, the JRS instruction of the line number "1607") is set,
For the second predetermined program address, a third predetermined program address ("ADR133" in the first, tenth and eleventh embodiments, and the start address of the lottery execution processing program in the thirteenth embodiment) is set as a jump destination. second predetermined jump instruction (JP instruction of line number "1309" in the first embodiment, JP instruction of "1409" in the tenth embodiment, JP instruction of line number "1511" in the eleventh embodiment, In the thirteenth embodiment, a game machine characterized in that a CALL command of line number "1609") is set.

According to feature F1, in a configuration in which a second predetermined program address is set to a second predetermined program address as a jump destination, a second predetermined program address is set as a jump destination to the first predetermined program address. By setting the first predetermined jump instruction to jump to the third predetermined program address, the program address is changed until jumping to the third predetermined program address without setting the jump instruction to the third predetermined program address as the jump destination in the first predetermined program address. It is possible to jump from the first predetermined program address to the third predetermined program address via the second predetermined program address in such a manner that no processing other than the processing to be performed is executed. As a result, it is possible to set the second predetermined program address as the jump destination as the first predetermined jump instruction set to the first predetermined program address in order to jump from the first predetermined program address to the third predetermined program address. In addition, it is possible to select a jump instruction for which the third predetermined program address cannot be set as the jump destination.

Feature F2. When the first predetermined jump instruction set at the first predetermined program address is executed to jump to the second predetermined program address and the second predetermined jump instruction is executed, the third jump instruction is executed. The gaming machine according to feature F1, characterized by jumping to a predetermined program address.

According to feature F2, in the configuration having the configuration of feature F1, the first predetermined program address is set with a first predetermined jump instruction that jumps not to the third predetermined program address but to the second predetermined program address. , when jumping to the second predetermined program address by the first predetermined jump instruction, it is possible to jump to the third predetermined program address without jumping to the third predetermined program address.

Feature F3. The second predetermined jump instruction is an instruction (JP instruction as an unconditional jump instruction) that unconditionally jumps to the third predetermined program address when the second predetermined jump instruction is executed. The gaming machine according to feature F1 or F2.

According to feature F3, when the second predetermined jump instruction is to be executed, it is possible to jump to the third predetermined program address without causing a case where the jump to the third predetermined program address is not performed. It is possible to unconditionally jump to the third predetermined program address when the second predetermined jump instruction is executed while eliminating the need to set the instruction to a specific program. Therefore, when the second predetermined program address is jumped from the first predetermined program address to the second predetermined program address by the first predetermined jump instruction and the second predetermined jump instruction set at the second predetermined program address becomes the execution target, the third jump instruction is executed. It is possible to simplify the processing configuration for jumping to the third predetermined program address without causing a case where the jump is not made to the predetermined program address. Further, even when the second predetermined jump instruction set at the second predetermined program address is executed without jumping from the first predetermined program address to the second predetermined program address by the first predetermined jump instruction, It is possible to jump to the third predetermined program address without causing a case where the third predetermined program address is not jumped to.

Feature F4. Any one of the features F1 to F3, wherein the second predetermined jump instruction is executed in a case other than when the first predetermined jump instruction is executed to jump to the second predetermined program address. The gaming machine described in .

According to feature F4, the second predetermined jump instruction is set only to jump to a third predetermined program address when jumping from the first predetermined program address to the second predetermined program address by the first predetermined jump instruction. is not an order. Also in cases other than jumping from the first predetermined program address to the second predetermined program address by the first predetermined jump instruction, an instruction to be executed is used to jump from the first predetermined program address to the second predetermined program address by the first predetermined jump instruction. By jumping to a third predetermined program address when jumping to a predetermined program address, the number of jump instructions set to the specific program is suppressed, and the second program address set to the second predetermined program address is configured to jump to the third predetermined program address. A predetermined jump instruction can be used to jump to a third predetermined program address.

Feature F5. Information (1-bit code and The game machine according to any one of features F1 to F4, characterized in that difference information including 4-bit numerical information) is set.

According to the feature F5, compared with the configuration in which the information indicating the entire second predetermined program address is set in the first predetermined jump instruction, the first predetermined jump instruction is used to make it possible to specify the second predetermined program address. It is possible to reduce the data capacity of the information set to . As a result, the data volume of the first predetermined jump instruction can be reduced, and the data volume of the specific program in which the first predetermined jump instruction is set can be reduced.

Feature F6. The first predetermined jump instruction is set in a predetermined program address range ("program address where JRS instruction is set + 1-16" to "JRS It is an instruction that can set a program address existing in the range of program address + 1 + 15 where the instruction is set as a jump destination,
The gaming machine according to any one of features F1 to F5, wherein the third predetermined program address is a program address that does not exist in the predetermined program address range based on the first predetermined program address. .

According to feature F6, the program address that can be set as the jump destination of the first predetermined jump instruction is a program address that exists within a predetermined program address range with reference to the first predetermined program address, and the program address that is within the predetermined program address range jumps to a second predetermined program address by a first predetermined jump instruction set to the first predetermined program address in a configuration where the third predetermined program address does not exist, and is set to the second predetermined program address A second predetermined jump instruction can cause a jump to a third predetermined program address. Therefore, it is not necessary to set a jump instruction that can directly jump from the first predetermined program address to the third predetermined program address without going through another program address, at the first predetermined program address. can be done. As a result, the data volume of the jump instruction set at the first predetermined program address can be reduced.

Feature F7. The gaming machine according to any one of features F1 to F6, wherein the second predetermined jump instruction includes information indicating the entirety of the third predetermined program address of the jump destination.

According to feature F7, by using the second predetermined jump instruction, regardless of the program address (second predetermined program address) where the second predetermined jump instruction is set, the jump destination program address (third specified program address) can be specified. Therefore, even if there is a program address (third predetermined program address) that cannot be specified as a jump destination by the first predetermined jump instruction from the first predetermined program address, it is set to the first predetermined program address. By jumping to a second predetermined program address by a first predetermined jump instruction, jumping from the first predetermined program address to a program address that cannot be specified as a jump destination by the first predetermined jump instruction is performed by the second predetermined jump instruction. be able to. As a result, compared to a configuration in which a jump instruction in which information indicating the entirety of the third predetermined program address is set as information for designating the jump destination is set at the first predetermined program address, the first predetermined program It is possible to reduce the data capacity of the jump instruction set to the address.

Feature F8. Depending on the content of the instruction to be executed, a predetermined state (in the first and thirteenth embodiments, the value of the jump flag JF is "1"; in the tenth embodiment, the value of the zero flag ZF is "1"). state, the state where the value of the carry flag CF is "1" in the eleventh embodiment) and a specific state (the state where the value of the jump flag JF is "0" in the first and thirteenth embodiments, the tenth The predetermined storage areas (the first and thirteenth , a jump flag JF in the embodiment, a zero flag ZF in the tenth embodiment, and a carry flag CF in the eleventh embodiment,
The first predetermined jump instruction is an instruction to jump to the second predetermined program address of the jump destination when a jump condition that the state of the predetermined storage area is the predetermined state is satisfied. The game machine according to any one of F1 to F7.

According to feature F8, when the first predetermined jump instruction is executed in a state in which the state of the predetermined storage area is in the predetermined state due to an instruction executed before the first predetermined jump instruction, the second predetermined jump instruction is executed. It is possible to jump to a predetermined program address and jump to a third predetermined program address by a second predetermined jump instruction set at the second predetermined program address. Further, when the first predetermined jump instruction is executed in a state where the state of the predetermined storage area is in the specific state due to the instruction executed before the first predetermined jump instruction, the first predetermined jump instruction is executed to the second predetermined program address. You can avoid jumping. Depending on the state of the predetermined storage area when the first predetermined jump instruction is to be executed, jumping from the first predetermined program address to the third predetermined program address via the second predetermined program address; A case can occur where no jump is made to the program address. As a result, different processes can be executed according to the state of the predetermined storage area when the first predetermined jump instruction is to be executed.

Feature F9. In the specific program, when the jump condition set in the first predetermined jump instruction is not satisfied while the first predetermined jump instruction is an instruction to be executed, the first predetermined jump instruction is executed. After executing the predetermined setting process (the LD instruction of line number "1308") based on the instruction set after the next, advance to the second predetermined program address where the second predetermined jump instruction is set. A gaming machine according to any one of the characterizing features F1 to F8.

According to feature F9, depending on the situation in which the first predetermined jump instruction is to be executed, jumping to the second program address without executing the predetermined setting process, or jumping to the second program address after executing the predetermined setting process. When going to a program address can occur. As a result, a case of jumping to the third predetermined program address when the predetermined setting process is not executed and a case of jumping to the third predetermined program address after the predetermined setting process is executed can be generated.

For the configuration of features F1 to F9, any one of features A1 to A19, features B1 to B9, features C1 to C13, features D1 to D7, features E1 to E6, features F1 to F9, and features G1 to G7 One or more configurations may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

<Characteristic group G>
Feature G1. A predetermined first program address in a predetermined program (program for executing lottery result correspondence processing in the first embodiment, program for executing additional processing at start in the eleventh and twelfth embodiments) (“ADR122” in the first embodiment, “ADR151” in the eleventh embodiment, and “ADR161” in the twelfth embodiment) contains a predetermined second program address (“ADR125” in the first embodiment). , "ADR162" in the eleventh embodiment, and "ADR162" in the twelfth embodiment). In the embodiment, the JR instruction of line number "1507", in the twelfth embodiment, the JR instruction of step S6009) is set,
A predetermined third program address (in the first embodiment, A predetermined second jump instruction (a JRS instruction of line number "1215" in the first embodiment) whose jump destination is "ADR126", "ADR153" in the eleventh embodiment, and "ADR163" in the twelfth embodiment , JR instruction of line number "1509" in the eleventh embodiment, JR instruction of step S6015 in the twelfth embodiment) is set,
to specify whether jump conditions are satisfied when the predetermined first jump instruction is an instruction to be executed and when the predetermined second jump instruction is an instruction to be executed; Equipped with a predetermined reference storage area (zero flag ZF, carry flag CF, jump flag JF) to be referenced,
A gaming machine, wherein the state of the predetermined reference storage area is maintained before and after execution of the predetermined first jump instruction.

According to feature G1, in a configuration in which a predetermined second jump instruction with a predetermined third program address as a jump destination is set at a predetermined second program address, a predetermined second program is set at a predetermined first program address. By setting the predetermined first jump instruction whose jump destination is the address, the predetermined third program can be executed without setting the jump instruction whose jump destination is the predetermined third program address at the predetermined first program address. It is possible to jump from a predetermined first program address to a predetermined third program address via a predetermined second program address in such a manner that processing other than processing for changing the program address is not executed until jumping to the address. . Thereby, a predetermined second program address is set as a jump destination as a predetermined first jump instruction set to the predetermined first program address in order to jump from a predetermined first program address to a predetermined third program address. It is possible to select a jump instruction that allows the user to set a predetermined third program address as the jump destination.

Since the state of the predetermined reference storage area is maintained before and after execution of the predetermined first jump instruction, based on the state of the predetermined reference storage area at the timing when the predetermined first jump instruction is executed, When a predetermined second jump instruction is to be executed, whether or not a jump condition is satisfied in the predetermined second jump instruction is specified. Thereby, when the jump condition of the predetermined first jump instruction is satisfied at the predetermined first program address and the jump is made to the predetermined second program address, the jump condition of the predetermined second jump instruction is satisfied and the predetermined jump instruction is performed. The processing configuration for jumping to the third program address can be simplified.

In a configuration in which a predetermined second jump instruction with a predetermined third program address as a jump destination is set in a program address to be executed after a predetermined second program address is to be executed, a predetermined first program address is set. Jumped from an address to a predetermined second program address, and executed instructions set from the predetermined second program address to the program address one before the program address at which the predetermined second jump instruction is set. It can later jump to a predetermined third program address. Since the state of the predetermined reference storage area is maintained before and after the execution of the predetermined first jump instruction, the state of the predetermined second jump instruction is set from the predetermined second program address to the program address one before the predetermined second jump instruction. If the state of the predetermined reference storage area is maintained before and after the execution of the instruction set up to the program address, a predetermined is to be executed, it is specified whether or not the jump condition is met in the predetermined second jump instruction. As a result, the jump condition of the predetermined first jump instruction is satisfied at the predetermined first program address, the jump is made to the predetermined second program address, and the predetermined second jump instruction is set from the predetermined second program address. After executing the instructions set up to the program address one before the current program address, the jump condition of the predetermined second jump instruction is satisfied and the jump is made to the predetermined third program address. Configuration can be simplified.

Feature G2. When the predetermined second jump instruction is executed, the predetermined reference is the same as the predetermined reference storage area which is referenced when the predetermined first jump instruction is executed. is a storage area,
The state of the predetermined reference storage area in which the jump condition is satisfied in the predetermined second jump instruction (the state in which the value of the jump flag JF is "1") is the state in which the jump condition is satisfied in the predetermined first jump instruction. The game machine according to feature G1, wherein the state is the same as the state of the predetermined reference storage area (the state where the value of the jump flag JF is "1").

According to feature G2, when the predetermined second jump instruction is to be executed, the same predetermined reference storage area is referenced when the predetermined first jump instruction is to be executed. Since it is the predetermined reference storage area, the predetermined second jump instruction is executed as a predetermined reference storage area different from the predetermined reference storage area that is referenced when the predetermined first jump instruction is to be executed. The data capacity of the predetermined reference storage area can be reduced compared to the configuration in which the predetermined reference storage area is set to be referred to in the case.

In a configuration in which a predetermined second jump instruction is set at a predetermined second program address, a predetermined first jump instruction that jumps to a predetermined second program address is set at a predetermined first program address. With this configuration, when the jump condition in the predetermined first jump instruction is satisfied and the jump is made to the predetermined second program address, the jump condition in the predetermined second jump instruction is not satisfied. A jump condition in the second jump instruction may also be satisfied to jump to a predetermined third program address. As a result, the data capacity of the predetermined first jump instruction for jumping from the predetermined first program address to the predetermined second program address is directly determined from the predetermined first program address without going through another program address. If the data capacity of the jump instruction that can be jumped to the third program address is smaller than that of the jump instruction, the data capacity of the jump instruction that is set to the predetermined first program address can be reduced.

Feature G3. The state of the predetermined reference storage area referenced when the predetermined first jump instruction is executed depends on the contents of the instruction executed before the predetermined first jump instruction is executed. The game machine according to feature G1 or G2, characterized by changing.

According to feature G3, jumping from a predetermined first program address to a predetermined jump instruction changes according to the state of the predetermined reference storage area which changes according to the contents of the instruction executed before the predetermined first jump instruction becomes an execution target. A case of jumping to a predetermined third program address via two program addresses and a case of not jumping to the predetermined second program address can occur. As a result, compared to the configuration that requires providing an instruction to change the state of the predetermined reference storage area as a separate instruction from the instruction to be executed before the predetermined first jump instruction becomes an execution target, the predetermined jump instruction To simplify a processing configuration for jumping from one program address to a predetermined third program address via a predetermined second program address and not jumping to the predetermined second program address. In addition, the data capacity of a given program can be reduced.

Feature G4. When the predetermined first jump instruction is to be executed and the jump condition in the predetermined first jump instruction is not satisfied, predetermined processing (line number "1209" to line number "1214" is set to The game machine according to any one of the characteristics G1 to G3, wherein after executing the processing for executing the instruction in the game, the game machine advances to the predetermined second program address.

According to feature G4, when a predetermined first jump instruction is to be executed, jumping from a predetermined first program address to a predetermined second program address without executing predetermined processing; After executing the process, proceeding to a predetermined second program address can occur. As a result, it is possible to execute a process corresponding to a situation in which a predetermined first jump instruction is to be executed. A jump instruction (predetermined second jump instruction) to be executed after execution of predetermined processing is executed when jumping from a predetermined first program address to a predetermined second program address without executing predetermined processing. This is the same jump instruction as the target jump instruction (predetermined second jump instruction). Therefore, when jumping from a predetermined first program address to a predetermined second program address without executing predetermined processing, a jump instruction different from the jump instruction to be executed is executed after executing predetermined processing. The number of jump instructions can be suppressed, and the data volume of a predetermined program can be reduced, compared to a configuration in which target jump instructions are set.

Feature G5. In the predetermined first jump instruction, information ( Difference information including 1-bit code and 4-bit numerical information is set in the JRS instruction, and difference information including 1-bit code and 7-bit numerical information is set in the JR instruction. The game machine according to any one of G4.

According to feature G5, information for specifying a predetermined second program address based on a predetermined first program address is set in the predetermined first jump instruction. Compared to a configuration in which information indicating the entire program address is set, it is possible to reduce the data volume of the information set in the predetermined first jump instruction for designating the jump destination program address. As a result, the data volume of the predetermined first jump instruction can be reduced, and the data volume of the predetermined program in which the predetermined first jump instruction is set can be reduced.

Feature G6. The predetermined first jump instruction is set in a predetermined program address range ("program address where the JRS instruction is set + 1-16") based on the predetermined first program address where the predetermined first jump instruction is set. ~ "program address where JRS instruction is set + 1 + 15", range of "program address where JR instruction is set + 2-128" to "program address where JR instruction is set + 2 + 127") It is an instruction that can set the program address where
The predetermined third program address set as the jump destination of the predetermined second jump instruction is the predetermined program address based on the predetermined first program address at which the predetermined first jump instruction is set. The game machine according to feature G5, wherein the program address does not exist in the range.

According to feature G6, a jump instruction that can directly jump from a predetermined first program address to a predetermined third program address without going through another program address is set at a predetermined first program address. Even if there is not, by setting a predetermined first jump instruction whose jump destination is a predetermined second program address to a predetermined first program address, a predetermined second jump set to a predetermined second program address is performed. An instruction may be used to jump from a given first program address to a third given program address that is not in a given program address range relative to the given first program address. Therefore, the data capacity of the predetermined first jump instruction for jumping from the predetermined first program address to the predetermined second program address is directly determined from the predetermined first program address without going through another program address. If the data capacity of the jump instruction that can be jumped to the third program address is smaller than that of the jump instruction, the data capacity of the jump instruction that is set to the predetermined first program address can be reduced.

Feature G7. In the predetermined second jump instruction, information (1-bit difference information including a sign and 4-bit numerical information, and difference information including a 1-bit code and 7-bit numerical information in the JR instruction) is set. 1. The gaming machine according to 1.

According to feature G7, information for specifying a predetermined third program address based on a predetermined second program address is set in the predetermined second jump instruction. Compared to a configuration in which information indicating the entire program address is set, it is possible to reduce the data volume of the information set in the predetermined second jump instruction for designating the jump destination program address. As a result, the data volume of the predetermined second jump instruction can be reduced, and the data volume of the predetermined program in which the predetermined second jump instruction is set can be reduced.

For the configuration of features G1 to G7, any one of features A1 to A19, features B1 to B9, features C1 to C13, features D1 to D7, features E1 to E6, features F1 to F9, and features G1 to G7 One or more configurations may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

According to the inventions according to the feature group D, the feature group E, the feature group F, and the feature group G, the following problems can be solved.

Pachinko game machines and slot machines are known as game machines. For example, a pachinko machine is provided with a storage section for storing game balls, and the game balls stored in the storage section are guided to a game ball launching device and directed to a game area in response to a player's shooting operation. is fired. Then, for example, when a game ball enters a ball entry section provided in the game area, for example, a lottery process is executed, or a process for increasing the number of game balls that can be used by the player is executed. be.

In a slot machine, when a game value such as medals is betted and a new game is started by operating a start lever, a lottery process is executed by a control means. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means Rotation of the reel is stopped by execution of rotation stop control. Then, when the stop result after the rotation of the reels is stopped corresponds to the winning combination in the lottery process, a privilege corresponding to the winning combination is given to the player.

Here, in the game machines such as those exemplified above, it is necessary to execute the processing favorably, and there is still room for improvement in this respect.

The basic configuration of a game machine to which each of the above features can be applied is shown below.

Pachinko machine: an operation means operated by a player, a game ball shooting means for shooting game balls based on the operation of the operation means, a ball passage for guiding the shot game balls to a predetermined game area, and a game This game machine is provided with game parts arranged in an area, and gives a privilege to a player when a game ball passes through a predetermined passing part of the game parts.

Spindle-type game machine such as slot machine: The rotation of the rotating body is started based on the operation of the start operation means, the rotation of the rotating body is stopped based on the operation of the stop operation means, and the player responds to the pattern after the stop. A game machine that gives benefits to

10... slot machine 32L...left reel 32M...middle reel 32R...right reel 41...start lever 42 to 44...stop button 66...multipurpose display unit 72...main MPU 73...main ROM 73f...Common data table 73g...Common data table 74...Main side RAM 74e...Addition number counter 74f...Index value counter 74m...Stop order type counter 74r...Continued game number counter 74s...Total winning number counter , 74u... AT continuation counter, 74v... Top-level aggregation area, 74w... AT status signal counter, 74?... BB top-level aggregation area, 74? 101b A register 107 JRS execution circuit CF carry flag FRm m-th frame JF jump flag SF highest frame ZF zero flag.

Claims (1)

a first transmission means for transmitting a first information group having a plurality of unit data based on occurrence of a first transmission opportunity;
second transmission means for transmitting a second information group having a plurality of unit data based on occurrence of a second transmission trigger;
with
The first transmission means comprises a first identification means for identifying unit data to be transmitted as the first information group by referring to a predetermined reference information group,
The second transmission means comprises second identification means for identifying unit data to be transmitted as the second information group by referring to the predetermined reference information group ,
An information storage means having a plurality of storage areas set in association with addresses,
The predetermined reference information group is stored in a storage area of a continuous predetermined address range in the information storage means,
The first identifying means identifies a plurality of storage areas included in a predetermined aggregation target range including at least a part of a plurality of storage areas in which the predetermined reference information group is stored in the information storage means. A game machine characterized by comprising means for specifying, as unit data to be transmitted as the first information group, predetermined integrated information in which information of bits at predetermined positions in information specified by reference is aggregated.

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