JP7245042B2 - Circuit board inspection equipment - Google Patents

Description

The present invention relates to a circuit board inspection apparatus for inspecting the quality of a plurality of conductor patterns provided on a circuit board.

Patent Literature 1 discloses a circuit board inspection apparatus that includes a contact-type inspection probe and a control unit that determines the quality of a conductor pattern based on the capacitance of the conductor pattern detected by the inspection probe. It is

JP-A-2003-35739

In the circuit board inspection apparatus described in Patent Document 1, it is necessary to measure the reference capacitance in advance using the circuit board for calibration before starting the inspection of the circuit board. For this reason, it is not possible to start testing the circuit board until the measurement of the reference capacitance is completed. There is a risk of

SUMMARY OF THE INVENTION It is an object of the present invention to make it possible to quickly start inspection of a circuit board without measuring a reference capacitance in advance.

According to one aspect of the present invention, a circuit board inspection apparatus for inspecting the quality of a plurality of conductor patterns provided on a circuit board includes a plurality of inspection probes in contact with the conductor patterns, and a reference static detector for each of the conductor patterns. a control unit that stores a capacitance and determines whether the conductor pattern is good or bad based on the detection value detected by the inspection probe. The controller includes, for each conductor pattern, capacitance detection means for detecting the capacitance of the conductor pattern, and when the reference capacitance of the target conductor pattern to be inspected is not stored, the capacitance detection means first pass/fail judgment means for judging pass/fail of the object conductor pattern based on the capacitance of the object conductor pattern and the capacitances of the other conductor patterns detected by means; second quality determination means for determining quality of the target conductor pattern based on the capacitance detected by the capacitance detection means and the reference capacitance when the capacitance is stored; 1 permitting the capacitance detected by the capacitance detecting means to be stored as the reference capacitance of the target conductor pattern when the pass/fail determination means determines that the target conductor pattern is not abnormal; board quality determination means for determining quality of the circuit board based on the determination results of the first quality determination means and the second quality determination means; and quality of the circuit board by the board quality determination means. Regardless of the result of the determination, when the first pass/fail judgment means and the second pass/fail judgment means complete the pass/fail judgment of all the conductor patterns, the storage permitting means stores the reference capacitance of the target conductor pattern. and a reference determination means for determining the capacitance permitted to be used as the reference capacitance used in the second pass/fail determination means.

According to this aspect, when the reference capacitance used for determining the quality of the target conductor pattern to be inspected is not stored, the capacitance of the target conductor pattern detected by the capacitance detection means and other The quality of the target conductor pattern is determined based on the capacitance of the conductor pattern, and the capacitance of the target conductor pattern determined to be normal is stored as a reference capacitance. Since the capacitances of the target conductor patterns determined to have no abnormality are sequentially stored as the reference capacitance, there is no need to measure the reference capacitance in advance. Therefore, the inspection of the circuit board can be started promptly.

FIG. 1 is a configuration diagram showing the configuration of a circuit board inspection apparatus according to an embodiment of the present invention. 2 is a view showing a part of the side surface of the circuit board shown in FIG. 1. FIG. FIG. 3 is a flow chart showing board inspection processing by the circuit board inspection apparatus according to the present embodiment. FIG. 4 is a flow chart showing a continuation of the flow chart of FIG. FIG. 5 is a subroutine flowchart of step S14 shown in FIG. FIG. 6 is a subroutine flowchart of step S16 shown in FIG. FIG. 7 is a subroutine flowchart of step S19 shown in FIG. FIG. 8 is a flow chart showing the continuation of the subroutine flow chart of FIG.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of a circuit board inspection apparatus 100 according to an embodiment of the present invention, and FIG. 2 schematically shows a portion of a surface of a circuit board P to be inspected on which a conductor pattern CP is provided. It is a diagram showing.

The circuit board inspection apparatus 100 is an inspection apparatus for inspecting the quality of a plurality of conductor patterns CP provided on a circuit board P, and detects by a plurality of inspection probes 21 contacting the conductor patterns CP and the inspection probes 21. a control unit 10 for determining whether each conductor pattern CP is good or bad based on the detected value. A case will be described below in which the circuit board P to be inspected is a multi-layer board in which the conductor patterns CP are provided on both sides and the inner layer ground pattern GP is provided inside.

The inspection probes 21 are contact-type probes, and are provided as a pair on one surface of the circuit board P arranged along the vertical direction, and are also provided in a pair on the other surface. Inspection probe 21 is held by moving mechanism 23 via holder 22 . The moving mechanism 23 is a mechanism capable of moving the inspection probe 21 in three axial directions with respect to the circuit board P, and moves the inspection probe 21 to the measurement point TP according to a command from the control unit 10. Let

The control unit 10 is a controller that controls the operation of the circuit board inspection apparatus 100, and includes a CPU (Central Processing Unit) that performs arithmetic processing, and a ROM 11 (Read-Only Memory) that stores control programs and the like executed by the CPU. , and a RAM 12 (random access memory) for storing calculation results of the CPU and the like. The control unit 10 may be composed of a single microcomputer, or may be composed of a plurality of microcomputers.

The control unit 10 generates an inspection signal, measures electrical resistance and capacitance using the inspection probe 21, controls driving of the moving mechanism 23, Processing such as data generation processing of the effective capacitance CR for each conductor pattern CP is performed. In addition, the control unit 10 executes a setting process for appropriately selecting and setting one measurement mode from among a plurality of measurement modes for one measurement point TP when performing capacitance measurement.

The RAM 12 stores position data about the measurement point TP for each conductor pattern CP, measurement mode information set for each measurement point TP, specific capacitance CS measured for each measurement mode, and measured actual capacitance CTP. is stored temporarily. Further, the RAM 12 stores the actual capacitance CR calculated by the control unit 10, the reference capacitance CST determined for each conductor pattern CP, the information on the detected disconnection and short circuit locations, the calculation result of the control unit 10, and the like. are also temporarily stored.

The ROM 11 stores an operation program of the control unit 10 necessary for executing each process described later in the flow charts. That is, the ROM 11 is a storage medium recording a program for controlling the circuit board inspection apparatus 100, and is readable by a computer.

As shown in FIGS. 1 and 2, the circuit board P to be inspected has a plurality of conductor patterns CP1, CP2, . ) was formed. Note that the conductor pattern CP shown in FIG. 2 is an example, and a plurality of conductor patterns CP are provided on the other surface of the circuit board P as well. The base material of the circuit board P is not limited to the glass epoxy base material, and may be any base material as long as it is used in general circuit boards.

As shown in FIG. 2, lands are formed at each end point of each conductor pattern CP, and these lands are measurement points TP1, TP2, . function as

Further, a ground conductor pattern GP1 electrically connected to the inner layer ground pattern GP is provided on the surface on which the conductor pattern CP is provided. A measurement point TPG on the ground conductor pattern GP1 functions as a ground electrode when measuring the capacitance of each conductor pattern CP. Note that a separate probe may be provided to always connect the inner layer ground pattern GP and the control unit 10 .

Next, inspection processing of the circuit board P by the circuit board inspection apparatus 100 will be described with reference to the flow charts of FIGS. 3 to 8. FIG.

The inspection process of the circuit board P is started with the circuit board P fixed in the circuit board inspection apparatus 100 along the vertical direction.

First, in step S10, the control unit 10 conducts a continuity test on all conductor patterns CP. For example, when checking the continuity of the conductor pattern CP1 shown in FIG. 2, the movement mechanism 23 is controlled to bring one of the pair of inspection probes 21 into contact with the measurement point TP1 and the other to the other measurement point. TP2 and TP3 are sequentially contacted. Further, the control unit 10 brings one inspection probe 21 into contact with the measurement point TP2 and brings the other inspection probe 21 into contact with the measurement point TP3, so that both inspections are performed for all combinations of the measurement points TP of the conductor patterns CP. Measure the resistance value between the probes 21 .

If there are disconnection points B between the measurement points TP1 and TP2 and between the measurement points TP2 and TP3, as in the conductor pattern CP1, the distance between the measurement points TP1 and TP2 Both the resistance value and the resistance value between the measurement point TP2 and the measurement point TP3 become infinite or nearly infinite, and the disconnection position is identified. The presence or absence of disconnection and the location of disconnection are stored in the RAM 12 as disconnection information for each conductor pattern CP. The continuity test performed by the control unit 10 in step S10 corresponds to disconnection determination means.

When it is determined in step S11 that the continuity test has been completed for all the conductor patterns CP provided on both sides of the circuit board P, the process advances to step S12 to perform a capacitance test. The capacitance inspection performed by the control unit 10 after step S12 corresponds to capacitance detection means.

When inspecting the capacitance of the conductor pattern CP determined as not broken in the continuity test, the process proceeds to step S13, and when it is determined that the conductor pattern CP to be inspected is broken in the continuity test, step Proceed to S20.

In step S<b>13 , the control unit 10 determines whether or not the reference capacitance CST of the conductor pattern CP to be inspected has already been determined and stored in the RAM 12 . As will be described later, the reference capacitance CST is determined sequentially for the conductor patterns CP in which no abnormality is found, and is not determined yet when the first circuit board P is inspected. Even if an abnormality is found in the In this way, when the reference capacitance CST has not been determined, the process proceeds to step S14 and subsequent steps in order to determine the reference capacitance CST while inspecting the conductor pattern CP for quality.

Next, the measurement of the effective capacitance CR of the conductor pattern CP performed in step S14 will be described with reference to FIG.

First, in step S40, the controller 10 measures the specific capacitance CS. The inherent capacitance CS means an inherent capacitance (also referred to as stray capacitance) determined by components of the measurement system such as the movement mechanism 23 and the type of inspection signal (for example, the frequency of the inspection signal).

Specifically, the control unit 10 controls the moving mechanism 25 to move the inspection probe 21 away from the measurement point TP and the measurement point TPG by a predetermined distance, and in this state, applies an AC voltage as an inspection signal. do. The capacitance measured at this time is stored in the RAM 12 as a specific capacitance CS for each conductor pattern CP.

Next, in step S41, the controller 10 performs actual measurement of the capacitance of the conductor pattern CP. The capacitance measured in the main measurement is stored in the RAM 12 for each conductor pattern CP as the measured capacitance CTP.

In subsequent step S42, the control unit 10 subtracts the specific capacitance CS from the stored measured capacitance CTP, and calculates the difference as the normal capacitance of the conductor pattern CP from which the influence of the specific capacitance CS is eliminated. It is calculated as a certain effective capacitance CR. The calculated effective capacitance CR is stored in the RAM 12 for each conductor pattern CP.

Thus, when the measurement of the effective capacitance CR of the conductor pattern CP in step S14 is completed, the process returns to the processing procedure shown in FIG. 3 and proceeds to step S15.

In step S15, the control unit 10 determines whether or not the inspection of the capacitance of all the conductor patterns CP has been completed. If there is still a conductor pattern CP for which capacitance inspection has not been completed, the process returns to step S12 to complete the capacitance inspection. It should be noted that the capacitance test is performed for all conductor patterns CP regardless of whether or not they are determined to be disconnected in the continuity test.

In step S15, when it is determined that the inspection of the capacitance of all the conductor patterns CP is completed, the process proceeds to step S16, and based on the actual capacitance CR calculated in step S14, the inspection target is The quality of the conductor pattern CP is determined.

Next, referring to FIG. 6, the quality determination of the conductor pattern CP performed in step S16 will be described.

First, in step S50, the control unit 10 compares the effective capacitance CR calculated in step S14 with the allowable range. Here, the allowable range means a value in the range normally measured as capacitance on the circuit board P, with the upper limit of the maximum measurement range being the upper limit of the allowable range and the lower limit of the minimum measurement range being the upper limit of the allowable range. The lower limit of the allowable range. For example, when the conductor pattern CP is short-circuited to the inner layer ground pattern GP and the capacitance becomes infinite, or when the inspection probe 21 is not properly brought into contact with the measurement point TP, the capacitance becomes very large. If the value is not small, it is determined to be within the allowable range.

When it is determined in step S50 that the effective capacitance CR of the conductor pattern CP is within the allowable range, the process proceeds to step S51 and subsequent steps to determine the quality of the conductor pattern CP.

In step S51, it is determined whether or not there is another conductor pattern CP having a substantial capacitance CR that is mutually approximate to the substantial capacitance CR of the conductor pattern CP to be inspected. When the substantial capacitances CR are close to each other, the substantial capacitances CR are equal by forming one conductor pattern by conducting at the short circuit point A, such as the conductor pattern CP1 and the conductor pattern CP2 shown in FIG. There is a possibility that

That is, in step S51, it is determined whether or not there is another conductor pattern CP that may be short-circuited with the conductor pattern CP to be inspected. Specifically, the difference between the effective capacitance CR of the conductor pattern CP to be inspected and the effective capacitance CR of the conductor pattern CP to be inspected is, for example, within 10% of the effective capacitance CR of the conductor pattern CP to be inspected. Other conductor patterns CP are extracted as conductor patterns CP that may be short-circuited. It should be noted that the degree of approximation is set arbitrarily.

In step S51, if it is determined that there is another conductor pattern CP having a substantial capacitance CR that is mutually approximate to the substantial capacitance CR of the conductor pattern CP to be inspected, the process proceeds to step S52, where the conductor pattern CP is inspected. An insulation test is performed between the conductor pattern CP and another conductor pattern CP.

In step S52, the control unit 10 controls the moving mechanism 23 to bring one of the pair of inspection probes 21 into contact with the conductor pattern CP to be inspected and the other into contact with the other conductor pattern CP. A resistance value between the inspection probes 21 is measured. If there is no short circuit, the measured resistance value will be infinite or a value close to it. The resistance value is less than or equal to a predetermined small value.

Based on such a difference in resistance value, the control unit 10 determines the state of insulation between the conductor pattern CP to be inspected and the other conductor pattern CP. The determined result is stored in the RAM 12 as short-circuit information for each conductor pattern CP.

If it is determined in step S52 that the conductor pattern CP to be inspected and the other conductor pattern CP are in an insulated state, the process proceeds to step S53. If it is determined in step S51 that there is no other conductor pattern CP having a substantial capacitance CR that is mutually similar to the substantial capacitance CR of the conductor pattern CP to be inspected, the process proceeds to step S53.

In step S53, based on the determination results in steps S51 and S52, the control unit 10 determines that there is no abnormality such as disconnection or short circuit in the conductor pattern CP to be inspected. The determined result is stored in the RAM 12 for each conductor pattern CP. The processing performed by the control unit 10 in steps S51 and S52 corresponds to the first pass/fail determination means, the processing performed by the control unit 10 in step S51 is performed by the first approximation determination unit, and the processing performed by the control unit 10 in step S52 The processing performed respectively corresponds to the first insulation confirmation means.

In subsequent step S54, the control unit 10 converts the actually measured capacitance CTP of the conductor pattern CP to be inspected, which has been determined to have no abnormality, to a reference static capacitance which is one criterion for determining whether or not there is an abnormality in the conductor pattern CP. Temporarily determined as the capacitance CST. Specifically, the measured capacitance CTP of the conductor pattern CP is allowed to be stored in the RAM 12 as a provisional value of the reference capacitance CST. As will be described later, the tentatively determined reference capacitance CST is finalized when determination of all conductor patterns CP is completed. The processing performed by the control unit 10 in step S54 corresponds to storage permitting means.

On the other hand, if it is determined in step S52 that the conductor pattern CP to be inspected and the other conductor pattern CP are not in an insulated state, the process proceeds to step S55.

In step S55, based on the determination result in step S52, the control unit 10 determines that there is a short-circuit abnormality in the conductor pattern CP to be inspected and the other conductor patterns CP. The determined result is stored in the RAM 12 for each conductor pattern CP.

In this way, the measured capacitance CTP of both the conductor pattern CP to be inspected and the other conductor pattern CP determined to have a short-circuit abnormality is Since it corresponds to the capacitance when one conductor pattern is formed by short-circuiting, it is not suitable as the reference capacitance CST for determining the presence or absence of abnormality in each conductor pattern CP.

Therefore, in subsequent step S56, the control unit 10 sets the reference capacitance CST of the conductor pattern CP to be inspected to an undetermined state, and sets the other conductor pattern CP electrically connected to the conductor pattern CP to be inspected. The reference capacitance CST is also undetermined.

Next, the case where it is determined in step S50 that the effective capacitance CR of the conductor pattern CP is equal to or less than the lower limit of the allowable range will be described. In this case, the determination made by the control unit 10 in step S50 corresponds to lower limit determination means.

If the effective capacitance CR of the conductor pattern CP is equal to or less than the lower limit of the allowable range, the controller 10 determines in step S57 that the measurement of the effective capacitance CR has failed for some reason. For example, if one of the inspection probes 21 does not properly contact the conductor pattern CP, it is determined that the measurement has failed.

Here, since the actual substantial capacitance CR of the conductor pattern CP is unknown, it is conceivable to handle the conductor pattern CP as being abnormal, assuming that the conductor pattern CP may be abnormal. However, it is conceivable that there is no abnormality in the conductor pattern CP, even though the measurement is defective.

Therefore, in the present embodiment, even if the measurement of the effective capacitance CR fails, the conductor pattern CP is not treated as abnormal, and other conductor patterns CP that may be short-circuited with the conductor pattern CP to be inspected. and the conductor pattern CP to be inspected, the presence or absence of abnormality in the conductor pattern CP is confirmed.

Specifically, in step S58 following step S57, the control unit 10 controls the conductor pattern CP, which is provided within a predetermined range, for example, 1 mm, from the conductor pattern CP to be inspected on the circuit board P, and the conductor to be inspected. An insulation test is performed between another conductor pattern CP that may be short-circuited with the pattern CP and the conductor pattern CP to be inspected. In the insulation test, similarly to the insulation test in step S52, the moving mechanism 23 is controlled to bring one of the pair of inspection probes 21 into contact with the conductor pattern CP to be inspected and the other to the other conductor pattern CP. This is done by bringing them into contact with each other and measuring the resistance value between the two inspection probes 21 . The predetermined range is an arbitrary range, and may be set to a distance of less than 1 mm, or may be set to a distance of greater than 1 mm.

If there is no short circuit, the measured resistance value will be infinite or a value close to it. The resistance value is less than or equal to a predetermined small value. Based on such a difference in resistance value, the control unit 10 determines the state of insulation between the conductor pattern CP to be inspected and the other conductor pattern CP. The determined result is stored in the RAM 12 as short-circuit information for each conductor pattern CP.

If it is determined in step S58 that the conductor pattern CP to be inspected and the other conductor pattern CP are in an insulated state, the process proceeds to step S59. It is determined that there is no abnormality such as a short circuit. The determined result is stored in the RAM 12 for each conductor pattern CP.

In this way, even if the measurement of the effective capacitance CR fails, it is possible to prevent the circuit board P from being unintentionally determined to be defective by inspecting the presence or absence of a short circuit in the conductor pattern CP. . The processing performed by the control unit 10 in step S58 corresponds to third insulation checking means.

Even if it is determined in step S59 that there is no abnormality in the conductor pattern CP to be inspected, the correct real capacitance CR of the conductor pattern CP to be inspected is not measured.

Therefore, in subsequent step S60, the control unit 10 sets the reference capacitance CST of the conductor pattern CP to be inspected to an undetermined state.

Moreover, it is considered that there is no short-circuit abnormality in the other conductor patterns CP that have been confirmed to be insulated from the conductor pattern CP to be inspected. Accordingly, in subsequent step S61, the control unit 10 tentatively determines the measured capacitance CTP of another conductor pattern CP determined to be normal as the reference capacitance CST of the conductor pattern CP, Store in RAM 12 .

On the other hand, if it is determined in step S58 that the conductor pattern CP to be inspected and the other conductor pattern CP are not in an insulated state, the process proceeds to step S62.

In step S62, based on the determination result in step S58, the control unit 10 determines that there is a short-circuit abnormality in the conductor pattern CP to be inspected and the other conductor patterns CP. The determined result is stored in the RAM 12 for each conductor pattern CP.

In this way, the measured capacitance CTP between the conductor pattern CP to be inspected and the other conductor pattern CP, which is determined to have a short-circuit abnormality, is calculated as follows: Since it corresponds to the capacitance in the case where each conductor pattern CP is formed into one conductor pattern, it is not suitable as the reference capacitance CST for determining the presence or absence of abnormality in each conductor pattern CP. Therefore, in subsequent step S63, the control unit 10 sets the reference capacitance CST of the conductor pattern CP to be inspected to an undetermined state, and sets the other conductor pattern CP electrically connected to the conductor pattern CP to be inspected. The reference capacitance CST is also undetermined.

Next, the case where it is determined in step S50 that the effective capacitance CR of the conductor pattern CP is equal to or greater than the upper limit of the allowable range will be described. In this case, the determination made by the control unit 10 in step S50 corresponds to upper limit determination means.

If the effective capacitance CR of the conductor pattern CP is equal to or greater than the upper limit of the allowable range, the controller 10 determines in step S64 that the conductor pattern CP to be inspected is electrically connected to the inner layer ground pattern GP.

Therefore, in subsequent step S<b>65 , the control unit 10 determines that there is a short-circuit abnormality in the conductor pattern CP to be inspected, and stores the result in the RAM 12 .

Further, of course, the accurate real capacitance CR of the conductor pattern CP to be inspected has not yet been measured. Therefore, in subsequent step S66, the control unit 10 sets the reference capacitance CST of the conductor pattern CP to be inspected to an undetermined state.

Here, the capacitance of the other conductor pattern CP measured when the conductor pattern CP to be inspected is electrically connected to the inner layer ground pattern GP is not only the inner layer ground pattern GP but also the inner layer ground pattern GP. The pattern including the conductive pattern CP that is connected is grounded and measured. In other words, the capacitances of all the other conductor patterns CP are values measured in a state where the patterns on the ground side are different from those of the normal circuit board P, and are not accurate values.

Therefore, in subsequent step S67, the control unit 10 changes all the reference capacitances CST of the other conductor patterns CP in the provisionally determined state to the undetermined state, and the inner layer ground pattern GP and any conductor pattern It is prohibited to store the actual capacitance CTP measured in the state where CP is conductive as the reference capacitance CST in the RAM 12 . The processing performed by the control unit 10 in step S67 corresponds to first storage prohibiting means.

In this way, when the quality determination of the conductor pattern CP based on the effective capacitance CR in step S16 is completed, the processing procedure shown in FIG. 3 is returned to, and the process proceeds to step S23 shown in FIG.

Next, the case where it is determined in step S13 shown in FIG. 3 that the reference capacitance CST has already been determined and stored in the RAM 12 will be described.

When inspecting the second and subsequent circuit boards P, there are cases where the reference capacitance CST of the conductor pattern CP to be inspected has already been determined. In such a case, it is possible to shorten the judgment time by judging the quality of the conductor pattern CP based on the reference capacitance CST stored in the RAM 12 .

If it is determined in step S13 that the reference capacitance CST has already been determined, the process advances to step S17 to measure the capacitance of the conductor pattern CP to be inspected. The measured capacitance is stored in the RAM 12 for each conductor pattern CP as the measured capacitance CTP.

In subsequent step S18, it is determined whether or not the inspection of the capacitance of all the conductor patterns CP has been completed. If there is still a conductor pattern CP for which capacitance inspection has not been completed, the process returns to step S12 to complete the capacitance inspection.

When it is determined in step S18 that the inspection of the capacitance of all the conductor patterns CP has been completed, the process proceeds to step S19, where the reference capacitance CST stored in the RAM 12 and the measured capacitance measured in step S17 are Based on CTP, the quality of the conductor pattern CP to be inspected is determined.

Next, with reference to FIGS. 7 and 8, the quality determination of the conductor pattern CP performed in step S19 will be described.

First, in step S70, the controller 10 compares the actually measured capacitance CTP measured in step S17 with the allowable range in the same manner as in step S50 described above.

If it is determined in step S70 that the measured capacitance CTP of the conductor pattern CP is within the allowable range, the process proceeds to step S71 and subsequent steps to determine whether the conductor pattern CP is good or bad.

In step S71, it is determined whether or not the measured capacitance of the conductor pattern CP is within a predetermined range of the reference capacitance CST. Specifically, when the difference between the measured capacitance CTP of the conductor pattern CP to be inspected and the reference capacitance CST is, for example, within 10% of the reference capacitance CST, the conductor pattern CP to be inspected has electrical characteristics equivalent to those of the conductor pattern CP when the reference capacitance CST is set, and it is determined that there is no abnormality.

If it is determined in step S71 that the measured capacitance CTP of the conductor pattern CP is within the predetermined range of the reference capacitance CST, the process proceeds to step S72.

In step S72, similarly to step S51 shown in FIG. 6, it is determined whether or not there is another conductor pattern CP having a measured capacitance CTP that is mutually similar to the measured capacitance CTP of the conductor pattern CP to be inspected. is done. When the measured capacitances CTP are close to each other, the measured capacitances CTP are equal to each other by forming one conductor pattern by conducting at the short circuit location A, such as the conductor pattern CP1 and the conductor pattern CP2 shown in FIG. There is a possibility that

That is, in step S72, it is determined whether or not there is another conductor pattern CP that may be short-circuited with the conductor pattern CP to be inspected. Specifically, the difference between the measured capacitance CTP of the conductor pattern CP to be inspected and the measured capacitance CTP is, for example, within 10% of the measured capacitance CTP of the conductor pattern CP to be inspected. Other conductor patterns CP are extracted as conductor patterns CP that may be short-circuited. It should be noted that the degree of approximation is set arbitrarily. Further, for the above determination, the actual capacitance CR may be used instead of the measured capacitance CTP.

In step S72, if it is determined that there is another conductor pattern CP having a measured capacitance CTP that is mutually similar to the measured capacitance CTP of the conductor pattern CP to be inspected, the process proceeds to step S73, where the conductor pattern CP is inspected. An insulation test is performed between the conductor pattern CP and another conductor pattern CP.

In step S73, the control unit 10 controls the moving mechanism 23 to bring one of the pair of inspection probes 21 into contact with the conductor pattern CP to be inspected, and the other to the other. It is brought into contact with the conductor pattern CP and the resistance value between both inspection probes 21 is measured. If there is no short circuit, the measured resistance value will be infinite or a value close to it. The resistance value is less than or equal to a predetermined small value.

Based on such a difference in resistance value, the control unit 10 determines the state of insulation between the conductor pattern CP to be inspected and the other conductor pattern CP. The determined result is stored in the RAM 12 as short-circuit information for each conductor pattern CP.

If it is determined in step S73 that the conductor pattern CP to be inspected is insulated from another conductor pattern CP, the process proceeds to step S74. If it is determined in step S72 that there is no other conductor pattern CP having a measured capacitance CTP that is mutually similar to the measured capacitance CTP of the conductor pattern CP to be inspected, the process proceeds to step S74.

In step S74, the control unit 10 determines that there is no abnormality such as disconnection or short circuit in the conductor pattern CP to be inspected based on the determination results in steps S71, S72, and S73. The determined result is stored in the RAM 12 for each conductor pattern CP.

The processing performed by the control unit 10 in these steps S71, S72, and S73 corresponds to the second good/bad judgment means. corresponds to the second approximation determination means, and the process performed by the control unit 10 in step S73 corresponds to the second insulation confirmation means.

Moreover, it is considered that there is no short-circuit abnormality in the other conductor patterns CP that have been confirmed to be insulated from the conductor pattern CP to be inspected. Therefore, in subsequent step S75, if the reference capacitance CST of another conductor pattern CP that has been determined to be normal has not been determined, the controller 10 determines that the measured capacitance CTP of the conductor pattern CP is tentatively determined as the reference capacitance CST and stored in the RAM 12 .

On the other hand, if it is determined in step S73 that the conductor pattern CP to be inspected and the other conductor pattern CP are not in an insulated state, the process proceeds to step S76.

In step S76, based on the determination result in step S73, the control unit 10 determines that there is a short-circuit abnormality in the conductor pattern CP to be inspected and the other conductor patterns CP. The determined result is stored in the RAM 12 for each conductor pattern CP.

In this way, the measured capacitance CTP of another conductor pattern CP determined to have a short-circuit abnormality is the same as when the conductor pattern CP to be inspected and the other conductor pattern CP are short-circuited to form one conductor pattern. Therefore, it is unsuitable as the reference capacitance CST for determining whether each conductor pattern CP is abnormal. Therefore, in subsequent step S77, if the reference capacitance CST of the other conductor pattern CP is in the tentatively determined state, the controller 10 changes it to the undetermined state.

Further, in step S71 described above, when it is determined that the measured capacitance CTP of the conductor pattern CP is not within the predetermined range of the reference capacitance CST, the process proceeds to step S78, where the measured capacitance CTP of the conductor pattern CP is It is determined whether the reference capacitance CST deviates from the predetermined range to the smaller side or the larger side.

Here, when the measured capacitance CTP of the conductor pattern CP is a relatively small value and deviates from the predetermined range of the reference capacitance CST to the smaller side, the area of the conductor pattern CP is small. That is, there is a possibility that a part of the conductor pattern CP is disconnected or damaged. On the other hand, when the measured capacitance CTP of the conductor pattern CP is relatively large and deviates from the predetermined range of the reference capacitance CST to the larger side, the area of the conductor pattern CP is large. That is, there is a possibility that it is electrically connected to another conductor pattern CP.

Therefore, when it is determined in step S78 that the measured capacitance CTP of the conductor pattern CP is out of the predetermined range of the reference capacitance CST in the smaller direction, the process proceeds to step S79, and the control unit 10 selects the inspection object. It is determined that there is a possibility that the conductor pattern CP to be the target has an abnormality such as disconnection, and the determination result is stored in the RAM 12 .

Further, when it is determined in step S78 that the measured capacitance CTP of the conductor pattern CP is out of the predetermined range of the reference capacitance CST to the larger side, the process proceeds to step S80, and the control unit 10 selects the inspection target. It is determined that the conductor pattern CP may have an abnormality such as a short circuit, and the determination result is stored in the RAM 12 .

Next, the case where it is determined in step S70 that the actually measured capacitance CTP of the conductor pattern CP is equal to or less than the lower limit of the allowable range will be described. In this case, the determination made by the control unit 10 in step S70 corresponds to lower limit determination means.

If the measured capacitance CTP of the conductor pattern CP is equal to or less than the lower limit of the allowable range, the control unit 10 determines that the measured capacitance CTP cannot be measured for some reason in step S81, similar to step S57 shown in FIG. judged to have failed.

Here, since the actual measured capacitance CTP of the conductor pattern CP is unknown, it may be considered that there is a possibility that the conductor pattern CP is abnormal and that the conductor pattern CP is abnormal. However, it is conceivable that there is no abnormality in the conductor pattern CP, even though the measurement is defective.

Therefore, in the present embodiment, even if the measurement of the actually measured capacitance CTP fails, the conductor pattern CP is not treated as abnormal, and other conductor patterns CP that may be short-circuited with the conductor pattern CP to be inspected. and the conductor pattern CP to be inspected, the presence or absence of abnormality in the conductor pattern CP is confirmed.

Specifically, in step S82 subsequent to step S81, the control unit 10 moves the conductor pattern CP to be inspected on the circuit board P within a predetermined range, for example, within 1 mm, in the same manner as in step S58 shown in FIG. An insulation test is performed between another conductor pattern CP which is provided and may be short-circuited with the conductor pattern CP to be inspected, and the conductor pattern CP to be inspected. The control unit 10 determines the state of insulation between the conductor pattern CP to be inspected and the other conductor pattern CP based on the magnitude of the resistance value between the inspection probes 21, and uses the determined result as short-circuit information to detect the conductor. It is stored in the RAM 12 for each pattern CP.

If it is determined in step S82 that the conductor pattern CP to be inspected and the other conductor pattern CP are in an insulated state, the process proceeds to step S83. It is determined that there is no abnormality such as a short circuit. The determined result is stored in the RAM 12 for each conductor pattern CP. In this way, even if the measurement of the actually measured capacitance CTP fails, it is possible to avoid inadvertently determining that the circuit board P is defective by inspecting the presence or absence of a short circuit in the conductor pattern CP. . The processing performed by the control unit 10 in step S82 corresponds to third insulation checking means.

Moreover, it is considered that there is no short-circuit abnormality in the other conductor patterns CP that have been confirmed to be insulated from the conductor pattern CP to be inspected. Therefore, in subsequent step S84, if the reference capacitance CST of another conductor pattern CP that has been determined to be normal has not been determined, the controller 10 determines that the measured capacitance CTP of the conductor pattern CP is tentatively determined as the reference capacitance CST and stored in the RAM 12 .

On the other hand, if it is determined in step S82 that the conductor pattern CP to be inspected and the other conductor pattern CP are not in an insulated state, the process proceeds to step S85.

In step S85, based on the determination result in step S82, the control unit 10 determines that there is a short-circuit abnormality in the conductor pattern CP to be inspected and the other conductor patterns CP. The determined result is stored in the RAM 12 for each conductor pattern CP.

In this way, the measured capacitance CTP of another conductor pattern CP determined to have a short-circuit abnormality is the same as when the conductor pattern CP to be inspected and the other conductor pattern CP are short-circuited to form one conductor pattern. Therefore, it is unsuitable as the reference capacitance CST for determining whether each conductor pattern CP is abnormal. Therefore, in subsequent step S86, if the reference capacitance CST of the other conductor pattern CP is in the tentatively determined state, the controller 10 changes it to the undetermined state.

Next, the case where it is determined in step S70 that the actually measured capacitance CTP of the conductor pattern CP is equal to or greater than the upper limit of the allowable range will be described. In this case, the determination made by the control unit 10 in step S70 corresponds to upper limit determination means.

If the measured capacitance CTP of the conductor pattern CP is equal to or greater than the upper limit of the allowable range, the controller 10 determines that the conductor pattern CP to be inspected is electrically connected to the inner layer ground pattern GP in step S87.

Therefore, in subsequent step S<b>88 , the control unit 10 determines that there is a short-circuit abnormality in the conductor pattern CP to be inspected, and stores the result in the RAM 12 .

Here, the capacitance of the other conductor pattern CP measured when the conductor pattern CP to be inspected is electrically connected to the inner layer ground pattern GP is not only the inner layer ground pattern GP but also the inner layer ground pattern GP. The pattern including the conductive pattern CP that is connected is grounded and measured. In other words, the capacitances of all the other conductor patterns CP are values measured in a state where the patterns on the ground side are different from those of the normal circuit board P, and are not accurate values.

Therefore, in subsequent step S89, the control section 10 changes all the reference capacitances CST of the other conductor patterns CP in the provisionally determined state to the undetermined state. Then, the control unit 10 prohibits the RAM 12 from storing the actually measured capacitance CTP measured in a state in which the inner layer ground pattern GP and any conductor pattern CP are electrically connected as the reference capacitance CST. The processing performed by the control unit 10 in step S89 corresponds to first storage prohibiting means.

When the quality determination of the conductor pattern CP based on the reference capacitance CST in step S19 is completed in this way, the process returns to the processing procedure shown in FIG. 3, and proceeds to step S23 shown in FIG.

Next, a case where it is determined that the conductor pattern CP to be inspected is broken in the continuity inspection in step S10 will be described.

As described above, the capacitance of the other conductor patterns CP measured when the conductor pattern CP to be inspected is electrically connected to the inner layer ground pattern GP is The pattern including the conductor pattern CP that is electrically connected to the ground is measured as the ground. This is the same when it is determined that the conductor pattern CP to be inspected is broken.

Therefore, when it is determined that the conductor pattern CP to be inspected is disconnected, the process proceeds to step S20, and an inspection is performed to confirm whether or not the conductor pattern CP is electrically connected to the inner layer ground pattern GP. . Specifically, the capacitance of the conductor pattern CP to be inspected is measured, and if the measured capacitance is equal to or higher than the upper limit of the allowable range, it is determined that the conductor pattern CP is electrically connected to the inner layer ground pattern GP. be judged. Instead of measuring the capacitance of the conductor pattern CP, it is determined whether or not the conductor pattern CP is electrically connected to the inner layer ground pattern GP based on the resistance value between the conductor pattern CP and the inner layer ground pattern GP. may The process performed by the control unit 10 in step S20 corresponds to upper limit determination means.

In step S20, when continuity between the conductor pattern CP to be inspected and the inner layer ground pattern GP is confirmed, the process proceeds to step S21.

In step S21, similarly to steps S67 and S89, the control unit 10 changes all the reference capacitances CST of the other conductor patterns CP in the provisionally determined state to the undetermined state. Then, the control unit 10 prohibits the RAM 12 from storing the actually measured capacitance CTP measured in a state in which the inner layer ground pattern GP and any conductor pattern CP are electrically connected as the reference capacitance CST. The processing performed by the control unit 10 in step S21 corresponds to first storage prohibiting means.

On the other hand, if it is confirmed in step S20 that the conductor pattern CP to be inspected and the inner layer ground pattern GP are not electrically connected, the process proceeds to step S22.

Here, even the conductor pattern CP that is determined not to be electrically connected to the inner layer ground pattern GP in step S20 may be short-circuited to another surrounding conductor pattern CP. If such a short-circuit abnormality occurs, the area of the conductor pattern CP changes, which may affect the measurement of the capacitance of the conductor pattern CP provided around it.

For this reason, in step S22, the control unit 10 sets the reference capacitance For other conductor patterns CP whose CST is tentatively determined, the reference capacitance CST is changed to an undetermined state, and the actually measured capacitance CTP is prohibited from being stored in the RAM 12 as the reference capacitance CST. do. The processing performed by the control unit 10 in step S22 corresponds to second storage prohibiting means.

When the processing in steps S21 and S22 is completed, the process returns to the processing procedure shown in FIG. 3 and proceeds to step S23 shown in FIG.

When all the processes in the above steps are completed, in subsequent step S23, the control unit 10 sets the measured capacitance CTP of each conductor pattern CP whose reference capacitance CST is in the tentatively determined state to the RAM 12 as the reference capacitance CST. to determine the reference capacitance CST of these conductor patterns CP. The processing performed by the control unit 10 in step S23 corresponds to reference determination means.

With respect to the conductor pattern CP for which the reference capacitance CST has been determined in this way, it is possible to omit the measurement of the actual capacitance CR performed in step S14 in the subsequent inspection of the circuit board P. The time required for inspecting the circuit board P can be shortened. In addition, as in step S71 described above, the quality of the conductor pattern CP can be easily determined by comparing the reference capacitance CST and the measured capacitance CTP.

In the subsequent step S24, it is determined whether or not all the conductor patterns PC provided on the circuit board P are normal. The process performed by the control unit 10 in step S24 corresponds to board quality determination means.

In step S24, when it is determined that there is no abnormality in all the conductor patterns PC, the process proceeds to step S25, and the controller 10 displays on a monitor (not shown) that the circuit board P is a non-defective product, and the measurement data of each conductor pattern PC. etc. are displayed, and the inspection process of the circuit board P is finished. On the other hand, if it is determined in step S24 that there is an abnormality in any of the conductor patterns PC, the process proceeds to step S26, and the control unit 10 displays on the monitor that the circuit board P is a defective product and the abnormal conductor The position of the pattern PC and the like are displayed, and the inspection process of the circuit board P is completed.

As described above, the inspection process of the circuit board P is performed while determining whether the conductor pattern PC is abnormal and determining the reference capacitance CST of the normal conductor pattern PC.

Next, the effects of this embodiment will be described in detail.

According to this embodiment, the circuit board inspection apparatus 100 inspects the quality of the plurality of conductor patterns CP provided on the circuit board P. FIG. This circuit board inspection apparatus 100 stores a plurality of inspection probes 21 in contact with the conductor patterns CP and a reference capacitance CST for each conductor pattern CP. a control unit 10 for determining whether the pattern CP is good or bad; the control unit 10 includes, for each conductor pattern CP, capacitance detection means for detecting the capacitance of the conductor pattern CP (step S12); When the reference capacitance CST of the target conductor pattern CP is not stored, the target conductor pattern CP is detected based on the capacitance of the target conductor pattern CP detected by the capacitance detection means and the capacitance of the other conductor pattern CP. First pass/fail judgment means (steps S51 and S52) for judging the pass/fail of CP; Second quality determination means (steps S71, S72, and S73) for determining quality of the target conductor pattern CP based on the capacitance CST, and determination that the target conductor pattern CP is not abnormal by the first quality determination means. storage permitting means (step S54) for permitting the capacitance detected by the capacitance detecting means to be stored as the reference capacitance CST of the target conductor pattern CP when the capacitance is detected.

According to this configuration, when the reference capacitance CST used for determining the quality of the target conductor pattern CP to be inspected is not stored, the capacitance of the target conductor pattern CP detected by the capacitance detection means and the capacitances of other conductor patterns CP, the quality of the target conductor pattern CP is determined, and the capacitance of the target conductor pattern CP determined to be normal is stored as a reference capacitance CST. be. Since the capacitance of the target conductor pattern CP determined as having no abnormality is sequentially stored as the reference capacitance CST, it is necessary to measure the reference capacitance CST for each conductor pattern CP in advance. do not have. Therefore, the inspection of the circuit board P can be started promptly.

Further, according to the present embodiment, the control unit 10 includes board quality determination means (step S24) for determining quality of the circuit board P based on the determination results of the first quality determination means and the second quality determination means; Regardless of the quality determination result of the circuit board P by the quality determining means, when the quality determination of all the conductor patterns CP is completed by the first quality determining means and the second quality determining means, the storage permitting means sets the reference of the predetermined conductor pattern CP. It further includes reference determination means (step S23) for determining the capacitance permitted to be stored as the capacitance CST as the reference capacitance CST used in the second quality determination means.

In this configuration, regardless of the quality of the circuit board P, the capacitance permitted to be stored as the reference capacitance CST of the predetermined conductor pattern CP by the storage permission means is used in the second quality determination means. It is established as the reference capacitance CST. That is, for example, even if there is an abnormality in one of the conductor patterns CP and the circuit board P is defective, the capacitance measured in the conductor pattern CP determined to be normal is It is used as a reference capacitance CST used in the quality judgment of . Therefore, regardless of the quality of the circuit board P, as the inspection of the circuit board P proceeds, the reference capacitance CST of each conductor pattern CP is determined in sequence, thereby gradually shortening the time required for the inspection of the circuit board P. can continue.

Further, according to the present embodiment, the first pass/fail determination means determines whether or not there is another conductor pattern CP having a capacitance similar to the capacitance of the target conductor pattern CP detected by the capacitance detection means. and if the first approximation determination means determines that there is another conductor pattern CP, the insulation between the other conductor pattern CP and the target conductor pattern CP is confirmed. and a first insulation confirmation means (step S52), and when the first approximation determination means determines that there is no other conductor pattern CP, and the first insulation confirmation means confirms that the conductor pattern is in an insulated state. If so, it is determined that there is no abnormality in the target conductor pattern CP.

In this configuration, when it is determined that there is no other conductor pattern CP whose capacitances are close to each other and may be short-circuited, and when it is determined that there is no other conductor pattern CP whose capacitances are close to each other, the target conductor pattern CP and other conductors whose capacitances are close to each other When insulation from the pattern CP is confirmed, it is determined that there is no abnormality in the target conductor pattern CP. Thus, even if the reference capacitance CST of the target conductor pattern CP is not stored, it is possible to reliably confirm that there is no short-circuit abnormality in the target conductor pattern CP, and proceed with the inspection of the circuit board P. .

Further, according to the present embodiment, the second good/bad judging means determines whether or not the capacitance of the target conductor pattern CP detected by the capacitance detecting means is within a predetermined range of the stored reference capacitance CST. If the abnormality determination means determines that the capacitance is not within a predetermined range of the reference capacitance CST, there is an abnormality in the target conductor pattern CP. I judge.

In this configuration, when it is determined that the capacitance of the target conductor pattern CP is not within the predetermined range of the reference capacitance CST, it is determined that the target conductor pattern CP is abnormal. As for the target conductor pattern CP in which the reference capacitance CST is stored in this way, it is possible to easily determine whether the target conductor pattern CP is abnormal.

Further, according to the present embodiment, the second good/bad judging means has a capacitance similar to the capacitance of the target conductor pattern CP judged to be within the predetermined range of the reference capacitance CST by the abnormality judging means. a second approximation determining means (step S72) for determining whether or not there is another conductor pattern CP having a capacitance; a second insulation confirmation means (step S73) for confirming insulation between the pattern CP and the target conductor pattern CP, when the second approximation determination means determines that there is no other conductor pattern CP; If the second insulation confirming means confirms that the object conductor pattern CP is in an insulated state, it is determined that there is no abnormality in the target conductor pattern CP.

In this configuration, even if the reference capacitance CST of the target conductor pattern CP was stored, it was determined that there was no other conductor pattern CP whose capacitances were close to each other and could cause a short circuit. In this case, it is determined that there is no abnormality in the target conductor pattern CP when it is confirmed that the target conductor pattern CP and another conductor pattern CP whose capacitances are close to each other are insulated. In this way, even when the reference capacitance CST is stored, the presence or absence of other conductor patterns CP that may be short-circuited and the insulation from other conductor patterns CP that may be short-circuited are determined. By confirming the state, it is possible to improve the abnormality determination accuracy of the target conductor pattern CP.

Further, according to the present embodiment, the control unit 10 includes the lower limit determination means (step S50, step S70), and when the lower limit determination means determines that the capacitance is equal to or less than the predetermined lower limit, another conductor pattern CP provided within a predetermined range from the target conductor pattern CP on the circuit board P and the target conductor pattern. and a third insulation confirming means (steps S58, S82) for confirming whether or not the CP is in an insulated state.

In this configuration, when it is determined that the capacitance of the target conductor pattern CP is equal to or less than the predetermined lower limit, the other conductor pattern CP provided within a predetermined range from the target conductor pattern CP on the circuit board P and the target conductor The state of insulation with the pattern CP is confirmed. In this way, even if the measurement of the capacitance of the object conductor pattern CP fails, the insulation from other conductor patterns CP provided around is confirmed, and the object conductor pattern CP is confirmed to be normal. By doing so, it is possible to prevent a normal target conductor pattern CP from being erroneously determined to be abnormal.

Further, according to the present embodiment, the control unit 10 includes upper limit determination means (step S20, step S50, step S70), and when the upper limit determination means determines that the capacitance is equal to or greater than the predetermined upper limit, the capacitance of all the conductor patterns CP detected by the capacitance detection means is equal to the reference capacitance CST. and a first storage prohibiting means (step S21, step S67, step S89) for prohibiting the storage of the .

In this configuration, when the capacitance of the target conductor pattern CP is determined to be equal to or greater than the predetermined upper limit, the capacitance of all the conductor patterns CP detected by the capacitance detection means is stored as the reference capacitance CST. is prohibited. In this way, by prohibiting the storage of the capacitance measured in a state where the pattern on the ground side is different from that of the normal circuit board P as the reference capacitance CST, the reference capacitance CST is inaccurate. It is possible to prevent an incorrect value from being stored, and improve the accuracy of the pass/fail determination of the conductor pattern CP based on the reference capacitance CST.

Further, according to the present embodiment, the control unit 10 uses the disconnection determination means (step S10) to determine whether or not there is a disconnection in the target conductor pattern CP based on the detection value detected by the inspection probe 21, and the disconnection determination means. When it is determined that the object conductor pattern CP is disconnected, at least the capacitance of all the conductor patterns CP detected by the capacitance detection means is provided within a predetermined range from the object conductor pattern CP on the circuit board P. a second storage prohibiting means (step S22) for prohibiting the capacitance of the other conductor pattern CP to be stored as the reference capacitance CST.

In this configuration, it is prohibited to store the measured capacitance as the reference capacitance CST for the other conductor patterns CP provided around the target conductor pattern CP determined to have the disconnection abnormality. . In this way, when the possibility that the target conductor pattern CP is short-circuited cannot be ruled out, it is prohibited to store the capacitance measured in the other conductor pattern CP provided around it as the reference capacitance CST. By doing so, it is possible to prevent an inaccurate value from being stored as the reference capacitance CST and improve the accuracy of the quality determination of the conductor pattern CP based on the reference capacitance CST.

Although the embodiments of the present invention have been described above, the above embodiments merely show a part of application examples of the present invention, and the technical scope of the present invention is not limited to the specific configurations of the above embodiments. do not have.

For example, the circuit board P inspected by the circuit board inspection apparatus 100 in the above embodiment is a double-sided board. The circuit board P is not limited to these, and may be a single-sided board having conductor patterns on only one side or a double-sided board having conductor patterns on both sides.

In the above embodiment, in step S56, the control unit 10 controls two reference capacitances CST of the conductor pattern CP to be inspected and another conductor pattern CP electrically connected to the conductor pattern CP to be inspected. is in an undetermined state. However, when the conductor pattern CP to be inspected is electrically connected to another conductor pattern CP, the area of the conductor pattern CP changes, which may affect the capacitance measurement of the conductor pattern CP provided around it. be. Therefore, in step S56, the reference capacitance CST of another conductor pattern CP provided within a predetermined range, eg, 1 mm, from the conductor pattern CP may also be in an undetermined state.

100 circuit board inspection device 10 control section 11 ROM
12 RAMs
21 inspection probe 23 moving mechanism P circuit board

Claims (10)

A circuit board inspection device for inspecting the quality of a plurality of conductor patterns provided on a circuit board,
a plurality of inspection probes in contact with the conductor pattern;
a control unit that stores a reference capacitance for each conductor pattern and determines whether the conductor pattern is good or bad based on the detection value detected by the inspection probe;
The control unit
Capacitance detection means for detecting the capacitance of each conductor pattern,
When the reference capacitance of the target conductor pattern to be inspected is not stored, based on the capacitance of the target conductor pattern detected by the capacitance detection means and the capacitance of other conductor patterns a first pass/fail judgment means for judging the pass/fail of the target conductor pattern;
determining whether the target conductor pattern is acceptable based on the reference capacitance and the capacitance detected by the capacitance detection means when the reference capacitance of the target conductor pattern is stored; 2 pass/fail judgment means;
The capacitance detected by the capacitance detection means is stored as the reference capacitance of the target conductor pattern when the first pass/fail determination means determines that there is no abnormality in the target conductor pattern. a storage permitting means for permitting
Board quality determination means for determining quality of the circuit board based on the determination results of the first quality determination means and the second quality determination means;
Regardless of the quality determination result of the circuit board by the board quality determination means, when the quality determination of all the conductor patterns is completed by the first quality determination means and the second quality determination means, the storage permitting means a reference determination means for determining the capacitance permitted to be stored as the reference capacitance of the conductor pattern as the reference capacitance used in the second pass/fail judgment means. Device. A circuit board inspection device for inspecting the quality of a plurality of conductor patterns provided on a circuit board,
a plurality of inspection probes in contact with the conductor pattern;
a control unit that stores a reference capacitance for each conductor pattern and determines whether the conductor pattern is good or bad based on the detection value detected by the inspection probe;
The control unit
Capacitance detection means for detecting the capacitance of each conductor pattern,
When the reference capacitance of the target conductor pattern to be inspected is not stored, based on the capacitance of the target conductor pattern detected by the capacitance detection means and the capacitance of other conductor patterns a first pass/fail judgment means for judging the pass/fail of the target conductor pattern;
determining whether the target conductor pattern is acceptable based on the reference capacitance and the capacitance detected by the capacitance detection means when the reference capacitance of the target conductor pattern is stored; 2 pass/fail judgment means;
The capacitance detected by the capacitance detection means is stored as the reference capacitance of the target conductor pattern when the first pass/fail determination means determines that there is no abnormality in the target conductor pattern. and storage permitting means for permitting
The first pass/fail judgment means is
a first approximation determination means for determining whether or not there is another conductor pattern having a capacitance that is mutually approximate to the capacitance of the target conductor pattern detected by the capacitance detection means;
a first insulation confirmation means for confirming insulation between the other conductor pattern and the target conductor pattern when the first approximation determination means determines that there is the other conductor pattern;
When the first approximation determination means determines that there is no other conductor pattern, and when the first insulation confirmation means confirms that the object conductor pattern is in an insulated state, it is determined that there is no abnormality in the target conductor pattern. Judge, circuit board inspection equipment. The circuit board inspection apparatus according to claim 1 ,
The first pass/fail judgment means is
a first approximation determination means for determining whether or not there is another conductor pattern having a capacitance that is mutually approximate to the capacitance of the target conductor pattern detected by the capacitance detection means;
a first insulation confirmation means for confirming insulation between the other conductor pattern and the target conductor pattern when the first approximation determination means determines that there is the other conductor pattern;
When the first approximation determination means determines that there is no other conductor pattern, and when the first insulation confirmation means confirms that the object conductor pattern is in an insulated state, it is determined that there is no abnormality in the target conductor pattern. Judge, circuit board inspection equipment. The circuit board inspection apparatus according to any one of claims 1 to 3,
The second pass/fail determination means is
Abnormality determination means for determining whether the capacitance of the target conductor pattern detected by the capacitance detection means is within a predetermined range of the stored reference capacitance,
A circuit board inspection apparatus that determines that there is an abnormality in the target conductor pattern when the abnormality determining means determines that the capacitance is not within a predetermined range of the reference capacitance. The circuit board inspection apparatus according to claim 4,
The second pass/fail determination means is
Determining whether or not there is another conductor pattern having a capacitance similar to the capacitance of the target conductor pattern determined to be within the predetermined range of the reference capacitance by the abnormality determining means. a second approximation determination means for
a second insulation confirmation means for confirming insulation between the other conductor pattern and the target conductor pattern when the second approximation determination means determines that there is the other conductor pattern;
When the second approximation determination means determines that there is no other conductor pattern, and when the second insulation confirmation means confirms that the object conductor pattern is in an insulated state, it is determined that there is no abnormality in the target conductor pattern. Judge, circuit board inspection equipment. The circuit board inspection apparatus according to any one of claims 1 to 5,
The control unit
lower limit determination means for determining whether the capacitance of the target conductor pattern detected by the capacitance detection means is equal to or less than a predetermined lower limit;
When the lower limit determination means determines that the capacitance is equal to or less than the predetermined lower limit, the target conductor pattern and another conductor pattern provided within a predetermined range from the target conductor pattern on the circuit board are separated from each other. A circuit board inspection apparatus, further comprising third insulation confirmation means for confirming whether or not the circuit board is in an insulated state. A circuit board inspection device for inspecting the quality of a plurality of conductor patterns provided on a circuit board,
a plurality of inspection probes in contact with the conductor pattern;
a control unit that stores a reference capacitance for each conductor pattern and determines whether the conductor pattern is good or bad based on the detection value detected by the inspection probe;
The control unit
Capacitance detection means for detecting the capacitance of each conductor pattern,
When the reference capacitance of the target conductor pattern to be inspected is not stored, based on the capacitance of the target conductor pattern detected by the capacitance detection means and the capacitance of other conductor patterns a first pass/fail judgment means for judging the pass/fail of the target conductor pattern;
determining whether the target conductor pattern is acceptable based on the reference capacitance and the capacitance detected by the capacitance detection means when the reference capacitance of the target conductor pattern is stored; 2 pass/fail judgment means;
The capacitance detected by the capacitance detection means is stored as the reference capacitance of the target conductor pattern when the first pass/fail determination means determines that there is no abnormality in the target conductor pattern. a storage permitting means for permitting
lower limit determination means for determining whether the capacitance of the target conductor pattern detected by the capacitance detection means is equal to or less than a predetermined lower limit;
When the lower limit determination means determines that the capacitance is equal to or less than the predetermined lower limit, the target conductor pattern and another conductor pattern provided within a predetermined range from the target conductor pattern on the circuit board are separated from each other. and a third insulation confirming means for confirming whether or not the circuit board is in an insulated state . The circuit board inspection apparatus according to any one of claims 1 to 7,
The control unit
upper limit determination means for determining whether the capacitance of the target conductor pattern detected by the capacitance detection means is greater than or equal to a predetermined upper limit;
When the upper limit determination means determines that the capacitance is equal to or greater than a predetermined upper limit, the capacitance of all the conductor patterns detected by the capacitance detection means is stored as the reference capacitance. and a first storage prohibiting means for prohibiting the circuit board inspection apparatus. A circuit board inspection device for inspecting the quality of a plurality of conductor patterns provided on a circuit board,
a plurality of inspection probes in contact with the conductor pattern;
a control unit that stores a reference capacitance for each conductor pattern and determines whether the conductor pattern is good or bad based on the detection value detected by the inspection probe;
The control unit
Capacitance detection means for detecting the capacitance of each conductor pattern,
When the reference capacitance of the target conductor pattern to be inspected is not stored, based on the capacitance of the target conductor pattern detected by the capacitance detection means and the capacitance of other conductor patterns a first pass/fail judgment means for judging the pass/fail of the target conductor pattern;
determining whether the target conductor pattern is acceptable based on the reference capacitance and the capacitance detected by the capacitance detection means when the reference capacitance of the target conductor pattern is stored; 2 pass/fail judgment means;
The capacitance detected by the capacitance detection means is stored as the reference capacitance of the target conductor pattern when the first pass/fail determination means determines that there is no abnormality in the target conductor pattern. a storage permitting means for permitting
upper limit determination means for determining whether the capacitance of the target conductor pattern detected by the capacitance detection means is greater than or equal to a predetermined upper limit;
When the upper limit determination means determines that the capacitance is equal to or greater than a predetermined upper limit, the capacitance of all the conductor patterns detected by the capacitance detection means is stored as the reference capacitance. and a first storage prohibiting means for prohibiting the circuit board inspection device. A circuit board inspection device for inspecting the quality of a plurality of conductor patterns provided on a circuit board,
a plurality of inspection probes in contact with the conductor pattern;
a control unit that stores a reference capacitance for each conductor pattern and determines whether the conductor pattern is good or bad based on the detection value detected by the inspection probe;
The control unit
Capacitance detection means for detecting the capacitance of each conductor pattern,
When the reference capacitance of the target conductor pattern to be inspected is not stored, based on the capacitance of the target conductor pattern detected by the capacitance detection means and the capacitance of other conductor patterns a first pass/fail judgment means for judging the pass/fail of the target conductor pattern;
determining whether the target conductor pattern is acceptable based on the reference capacitance and the capacitance detected by the capacitance detection means when the reference capacitance of the target conductor pattern is stored; 2 pass/fail judgment means;
The capacitance detected by the capacitance detection means is stored as the reference capacitance of the target conductor pattern when the first pass/fail determination means determines that there is no abnormality in the target conductor pattern. a storage permitting means for permitting
disconnection determination means for determining the presence or absence of disconnection in the target conductor pattern based on the detection value detected by the inspection probe;
When the disconnection determination means determines that the target conductor pattern is disconnected, at least the target conductor pattern in the circuit board out of the capacitances of all the conductor patterns detected by the capacitance detection means and a second storage prohibiting means for prohibiting the storage of the capacitance of another conductor pattern provided within a predetermined range from (1) to (1) as the reference capacitance.

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