JP7237687B2 - Wiring substrates, electronic devices and electronic modules - Google Patents

Description

The present disclosure relates to wiring boards, electronic devices, and electronic modules.

In order to mount an electronic component such as an LD on a package or module substrate, there is a wiring substrate interposed between the electronic component and the package or between the electronic component and the module substrate. Such a wiring board is also called a submount. The wiring substrate has functions such as transmission of electric signals, grounding of electronic components, and release of heat from the electronic components to the module substrate.

Patent Document 1 discloses a substrate having a metal film ohmic-bonded to a SiC (silicon carbide) substrate, and an optical device using such a substrate.

JP 2007-149983 A

A wiring board that employs single-crystal SiC as a substrate and requires conduction from one substrate surface to the SiC layer is examined. In such a wiring board, a metal layer to be ohmically bonded and a metal layer on which a bonding agent such as gold tin, solder, gold wire or gold bump is disposed are formed on the substrate surface of the SiC substrate. An adhesion layer for improving adhesion and a barrier layer for preventing element diffusion between layers may be formed between these metal layers. In such a configuration in which a plurality of types of metal layers are formed on the SiC substrate, stress due to, for example, a difference in thermal expansion occurs between the layers. Therefore, it is desired to improve resistance to stress so that the stress does not cause interfacial or bulk damage to the metal layer.

An object of the present disclosure is to improve resistance to stress caused by a difference in thermal expansion between layers in a wiring board including a SiC substrate and a NiSi layer ohmic-bonded thereto. An object of the present disclosure is to provide an electronic device and an electronic module having improved reliability by including such a wiring board.

A wiring board according to the present disclosure includes:
a SiC substrate;
a NiSi layer ohmic-bonded to the SiC substrate and having a porous structure;
a conductor layer connected to the NiSi layer;
with
Carbon is contained in the pores of the porous structure,
Positioned between the center of the NiSi layer and the interface side of the NiSi layer and the conductor layer, the vacancy has a larger amount of carbon distribution than the interface side of the NiSi layer and the conductor layer. It was configured.
A wiring board according to another aspect of the present disclosure includes:
a SiC substrate;
a NiSi layer ohmic-bonded to the SiC substrate and having a porous structure;
a conductor layer connected to the NiSi layer;
with
Carbon is contained in the pores of the porous structure,
It is configured to have a pore located between the center of the NiSi layer and the interface between the NiSi layer and the conductor layer and having a larger amount of carbon distribution than the outside of the pore of the NiSi layer.

An electronic device according to the present disclosure includes:
the above wiring board;
an electronic component mounted on the wiring board;
It was configured to include

An electronic module according to the present disclosure includes:
the electronic device described above;
a module substrate on which the electronic device is mounted;
It was configured to include

According to the present disclosure, in a wiring substrate including a SiC substrate and a NiSi layer ohmic-bonded thereto, resistance to stress caused by a difference in thermal expansion between layers can be improved. According to the present disclosure, by providing such a wiring substrate, it is possible to provide an electronic device and an electronic module with improved reliability.

1 is a vertical cross-sectional view showing a wiring board according to an embodiment of the present disclosure; FIG. 2(A) is a transmission electron micrograph of the NiSi layer, FIG. 2(B) is a mapping image of Ni element, FIG. 2(C) is a mapping image of Si element, and FIG. 2(D) is a mapping image of C element. is. It is a figure explaining the manufacturing method of the wiring board of embodiment. 1 illustrates an electronic device and an electronic module according to embodiments of the present disclosure; FIG.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. FIG. 1 is a vertical cross-sectional view showing a wiring board according to an embodiment of the present disclosure.

The wiring board 1 of this embodiment is interposed between the electronic component and the package or between the electronic component and the module substrate in order to mount the electronic component on the package or module substrate. Alternatively, conduct to the module board. Further, when the electronic component generates heat, the wiring board 1 releases heat from the electronic component to the package or module substrate. The wiring board 1 may be called a submount.

Wiring substrate 1 includes SiC (silicon carbide) substrate 10 , NiSi (nickel silicide) layer 11 ohmically bonded to SiC substrate 10 , and conductor film 20 formed on NiSi layer 11 . The conductor film 20 may include, for example, an adhesion layer 21, a barrier layer 22 and a conductor layer 23 in order from the NiSi layer 11 side. Furthermore, the wiring board 1 may have a bonding agent pattern 25 such as AuSn (gold tin) on the conductor film 20 . The NiSi layer 11 and the conductor film 20 may be provided on both substrate surfaces of the wiring substrate 1, or may be provided on only one substrate surface.

The adhesion layer 21 contains, for example, Ti (titanium), Cr (chromium), or both as main components. The barrier layer 22 contains, for example, Pt (platinum) as a main component. The conductor layer 23 contains, for example, Au (gold) as a main component.

2A is a transmission electron micrograph of the NiSi layer, FIG. 2B is a mapping image of Ni (nickel) element, FIG. 2C is a mapping image of Si (silicon) element, and FIG. 2D is a mapping image of C (carbon) element. FIGS. 2(B) to 2(D) show the same parts as FIG. 2(A).

NiSi layer 11 has conductivity and is in ohmic contact with SiC substrate 10 . The NiSi layer 11 has a porous structure and contains a plurality of holes D, as shown in FIG. The pores D may be mainly those having a diameter of 5 to 50 nm, and may be distributed at a rate of 10 to 50% in terms of area ratio of the longitudinal section. The vacancies D mean spaces in which Ni and Si do not exist or spaces in which the distribution of Ni and Si is very small compared to other portions of the NiSi layer 11 .

A large number of holes D are distributed in a plurality of specific layers such as the first layer Ly1, the second layer Ly2, and the third layer Ly3. That is, the distribution amount of the vacancies D contained in these specific multiple layers is larger than the distribution amount of the vacancies D in the other layers in terms of area ratio in the longitudinal section. The diameter of the holes D distributed in the layer closer to the SiC substrate 10 (eg, the first layer Ly1) is larger than the diameter of the holes D distributed in the layer farther from the SiC substrate 10 (eg, the third layer Ly3). Large on average.

As shown in FIG. 2 (D) , a large amount of carbon is distributed in the vacancies D. As shown in FIG. In the NiSi layer 11, on the side of the interface with the conductor film 20, there is a low carbon concentration layer Ly4 having a lower carbon distribution amount than other layers (for example, the central layer).

<Manufacturing method>
FIG. 3 is a diagram illustrating an example of a method for manufacturing a wiring board according to the embodiment.

The wiring board 1 of this embodiment can be manufactured by the following manufacturing method. This manufacturing method includes, in chronological order, a Ni film vapor deposition step J1 for vapor-depositing a Ni film 11Pr on the substrate surface of a SiC substrate 10 made of single crystal SiC, and a heating (annealing) step J2 for heating the substrate surface using light, for example. , a conductor film forming step J3 for forming a conductor film 20 on the substrate surface, a resist processing step J4 for processing a resist pattern Rg corresponding to the adhesive pattern 25, and a pattern for forming the adhesive pattern 25 using AuSn or the like. It includes a forming step J5 and a rinsing step J6 for removing the resist. The conductor film forming step J3 may be a step of sequentially forming the adhesion layer 21, the barrier layer 22, and the conductor layer 23 by vapor deposition. The pattern forming step J5 may be a step of forming an AuSn film by vapor deposition.

In the heating step J2, for example, the substrate surface is spot-irradiated with a laser beam, and the laser beam is scanned along the substrate surface to heat each portion of the substrate surface. The heating causes the Ni film and the surface layer of the SiC substrate 10 to react to form a NiSi layer. Then, ohmic contact between NiSi layer 11 and SiC substrate 10 is achieved. A porous structure of the NiSi layer 11 having a plurality of vacancies D can be realized by adjusting the annealing conditions (annealing temperature and annealing time of each part) of the substrate surface.

As described above, according to the wiring substrate 1 of the present embodiment, the NiSi layer 11 having a porous structure is provided between the SiC substrate 10 and the conductor film 20 . Therefore, the ohmic contact between the NiSi layer 11 and the SiC substrate 10 can realize electrical conductivity of the wiring substrate 1 with less Schottky barrier. Furthermore, the porous structure of the NiSi layer 11 can improve the resistance to stress caused by the difference in thermal expansion between the SiC substrate 10 and the conductor film 20 . That is, when the temperature changes, stress is generated between the SiC substrate 10 and the conductor film 20 due to the difference in thermal expansion between them. buffered. This improves the resistance of the NiSi layer 11 against interfacial breakdown or bulk breakdown due to stress, thereby suppressing peeling of the conductor film 20 .

Furthermore, according to the wiring board 1 of the present embodiment, the holes D of the NiSi layer 11 contain a large amount of C (carbon). Carbon has a high thermal conductivity. Therefore, even if the NiSi layer 11 contains a large number of holes D, the large number of holes D extend from one substrate surface of the wiring board 1 to the other substrate surface. It is suppressed that it becomes a barrier of heat conduction to. Thereby, when an electronic component is mounted on the wiring board 1, high heat dissipation of the electronic component through the wiring board 1 can be realized.

Furthermore, according to the wiring board 1 of the present embodiment, since the amount of carbon distributed in the NiSi layer 11 on the side of the interface with the conductor film 20 is small, the adhesion strength between the conductor film 20 and the NiSi layer can be improved.

Furthermore, according to the wiring substrate 1 of the present embodiment, the NiSi layer 11 includes a plurality of specific layers (the first layer Ly1, the second layer Ly2 and the third layer) in which more holes D are distributed than in other layers. Ly3). Since many holes D are distributed in a plurality of layers in this way, even if stress is generated in the NiSi layer 11 due to the difference in thermal expansion between the SiC substrate 10 and the conductor film 20, bulk damage of the NiSi layer 11 is prevented. stress can be effectively buffered while suppressing For example, in a structure in which the vacancies D continue vertically, the resistance to stress of the NiSi layer 11 is reduced, and the risk of bulk fracture increases. can.

Furthermore, according to the wiring board 1 of the present embodiment, the average diameter of the holes D in the first layer Ly1 closer to the SiC substrate 10 side is larger than the average diameter of the holes D in the third layer Ly3 farther from the SiC substrate 10. big. When stress occurs between the SiC substrate 10 and the conductor film 20 due to the difference in thermal expansion, the stress is relatively concentrated on the interface side of the adhesion layer 21 . Therefore, since the holes D of the third layer Ly3 on the interface side of the adhesion layer 21 have a smaller diameter, the resistance of the NiSi layer 11 to bulk breakdown is improved. As a result, peeling of the conductor film 20 due to bulk breakdown can be suppressed.

<Electronic device and electronic module>
FIG. 6 is a cross-sectional view showing an electronic device and an electronic module according to an embodiment of the disclosure.

An electronic device 60 according to this embodiment is configured by mounting an electronic component 50 on a wiring substrate 1 . Electronic component 50 may be bonded onto bonding agent pattern 25 . Another conductor pattern insulated from the conductor film 20 may be formed on the substrate surface of the wiring board 1, and this conductor pattern and the electrodes of the electronic component 50 may be connected via bonding wires. Furthermore, the electronic device 60 may have a configuration having a package that accommodates the wiring board 1 and the electronic component 50 .

As the electronic component 50, optical elements such as LD (Laser Diode), PD (Photo Diode), LED (Light Emitting Diode), CCD (Charge Coupled Device) type, CMOS (Complementary Metal Oxide Semiconductor) type imaging device, Various electronic components such as piezoelectric vibrators such as crystal vibrators, surface acoustic wave devices, semiconductor devices such as semiconductor integrated circuit devices (IC: Integrated Circuit), electric capacitive devices, inductor devices, and resistors can be applied.

The electronic module 100 according to this embodiment is configured by mounting an electronic device 60 on a module board 110 . In addition to the electronic device 60 , other electronic devices, electronic elements, electric elements, and the like may be mounted on the module substrate 110 . An electrode pad 111 is provided on the module substrate 110, and the electronic device 60 may be bonded to the electrode pad 111 via a bonding material 113 such as solder or gold tin. Moreover, when the electronic device 60 has a package, the wiring conductors of the package may be joined to the electrode pads 111 of the module substrate 110 .

According to the electronic device 60 and the electronic module 100 of the present embodiment, reliability can be improved by mounting the wiring substrate 1 on which peeling of the conductor film 20 is suppressed.

The embodiments of the present disclosure have been described above. However, the present invention is not limited to the above embodiments. For example, the size, distribution ratio, uneven distribution, etc. of the pores D in the porous structure shown in the embodiment are merely examples. Also, the number or types of conductor layers bonded to the NiSi layer can be changed as appropriate. Other details shown in the embodiments can be changed as appropriate without departing from the scope of the invention.

REFERENCE SIGNS LIST 1 wiring board 10 SiC substrate 11 NiSi layer 20 conductor film 21 adhesion layer 22 barrier layer 23 conductor layer 25 bonding agent pattern Ly1 first layer Ly2 second layer Ly3 third layer Ly4 low carbon concentration layer D hole 50 electronic component 60 electron Apparatus 100 Electronic module 110 Substrate for module

Claims (7)

a SiC substrate;
a NiSi layer ohmic-bonded to the SiC substrate and having a porous structure;
a conductor layer connected to the NiSi layer;
with
Carbon is contained in the pores of the porous structure,
Positioned between the center of the NiSi layer and the interface side of the NiSi layer and the conductor layer, having a hole with a larger amount of carbon distribution than the interface side of the NiSi layer and the conductor layer,
wiring board. a SiC substrate;
a NiSi layer ohmic-bonded to the SiC substrate and having a porous structure;
a conductor layer connected to the NiSi layer;
with
Carbon is contained in the pores of the porous structure,
Positioned between the center of the NiSi layer and the interface between the NiSi layer and the conductor layer, having a vacancy with a larger amount of carbon distribution than outside the vacancy of the NiSi layer,
wiring board. The amount of carbon distributed on the interface side between the NiSi layer and the conductor layer is less than the amount of carbon distributed in the center of the NiSi layer.
The wiring board according to claim 1 or 2. The porous structure of the NiSi layer has a plurality of specific layers in which more holes are distributed than other layers,
The wiring board according to any one of claims 1 to 3. The average diameter of the pores contained in the specific layer closer to the SiC substrate is larger than the average diameter of the pores contained in the specific layer far from the SiC substrate,
5. The wiring board according to claim 4. A wiring board according to any one of claims 1 to 5;
an electronic component mounted on the wiring board;
An electronic device comprising an electronic device according to claim 6;
a module substrate on which the electronic device is mounted;
electronic module with

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