JP7236342B2 - Semiconductor integrated circuit for switch monitoring - Google Patents

Description

The present invention relates to technology for monitoring the state of switches.

2. Description of the Related Art Conventionally, various switch monitoring circuits have been proposed for monitoring the states of switches.

JP 2018-14206 A

The switch monitoring semiconductor integrated circuit disclosed in Patent Document 1 monitors the state of the switch using the output current of the built-in current source. However, the semiconductor integrated circuit for switch monitoring of Patent Document 1 has a problem that it cannot detect a failure of the built-in current source.

The switch monitoring semiconductor integrated circuit is mounted on a vehicle, for example. In recent years, various vehicle manufacturers are vigorously promoting efforts for functional safety. For example, if the above problem can be solved in a switch monitoring semiconductor integrated circuit mounted on a vehicle, it will lead to ensuring the functional safety of the vehicle.

SUMMARY OF THE INVENTION In view of the above situation, it is an object of the present invention to provide a switch monitoring semiconductor integrated circuit capable of detecting failure of a built-in current source, an electronic control unit and a vehicle having the same.

A switch monitoring semiconductor integrated circuit disclosed in this specification includes: a switch input terminal configured to be connectable to a switch to be monitored; a current source configured to be connectable to the switch input terminal; a first determination unit that determines a voltage level of a terminal; and a generation unit that generates a control signal for switching an output path of the current source from the first path including the monitored switch to the second path including the load. It is a configuration (first configuration) provided.

In the switch monitoring semiconductor integrated circuit having the first configuration, the load, and a first open/close switch provided between the current source and the first determination unit and the load, The opening/closing switch may be configured to be closed by the control signal (second configuration).

Further, in the switch monitoring semiconductor integrated circuit having the first or second configuration, a second open/close switch is provided between the current source and the first determination unit and the switch input terminal, The switch may be configured to be opened by the control signal (third configuration).

Further, in the semiconductor integrated circuit for switch monitoring having any one of the first to third configurations, a configuration comprising: a backup current source; and a switching unit capable of using the backup current source instead of the current source. (Fourth configuration).

In the switch monitoring semiconductor integrated circuit of the fourth configuration, the backup current source may have a lower current capability than the current source (fifth configuration).

Further, in the switch monitoring semiconductor integrated circuit having the fourth or fifth configuration, a plurality of sets of the switch input terminal, the current source, and the first determination section are provided, and at least two of the plurality of sets have the preliminary current. A configuration (sixth configuration) in which a source is shared may be used.

Further, in the switch monitoring semiconductor integrated circuit having any one of the first to sixth configurations, a second determination section for determining a voltage level of the switch input terminal; and a third open/close switch provided between the second determination unit (seventh configuration).

In the switch monitoring semiconductor integrated circuit of the seventh configuration, the third opening/closing switch may be closed by the control signal (eighth configuration).

The switch monitoring semiconductor integrated circuit of the seventh or eighth configuration further includes a confirming unit for confirming whether or not the determination result of the first determination unit and the determination result of the second determination unit match. A configuration (a ninth configuration) may be used.

The electronic control unit disclosed in this specification includes a switch monitoring semiconductor integrated circuit having any one of the first to ninth configurations, and a microcomputer receiving monitoring results transmitted from the switch monitoring semiconductor integrated circuit. and a configuration (tenth configuration).

The vehicle disclosed in this specification has a configuration (eleventh configuration) including the electronic control unit of the tenth configuration and the monitoring target switch.

According to the switch monitoring semiconductor integrated circuit and the electronic control unit and vehicle provided with the switch monitoring semiconductor integrated circuit disclosed in this specification, it is possible to detect a failure of the current source incorporated in the switch monitoring semiconductor integrated circuit.

A diagram showing a configuration example of an electronic control unit FIG. 4 is a diagram showing a first configuration example of a switch monitoring semiconductor integrated circuit; A diagram showing a second configuration example of the semiconductor integrated circuit for switch monitoring. A diagram showing a third configuration example of the semiconductor integrated circuit for switch monitoring A diagram showing a fourth configuration example of the semiconductor integrated circuit for switch monitoring A diagram showing a fifth configuration example of the semiconductor integrated circuit for switch monitoring. External view of a vehicle equipped with an electronic control unit

<Electronic control unit>
FIG. 1 is a diagram showing a configuration example of the electronic control unit U1. The electronic control unit U<b>1 includes a switch monitoring semiconductor integrated circuit 101 , a power supply circuit 201 , a microcomputer 301 and a bus interface 401 .

The switch monitoring semiconductor integrated circuit 101 monitors the state of the switch to be monitored.

The power supply circuit 201 converts the main voltage VPUB into a sub-voltage VPUA and an output voltage VOUT, and outputs the sub-voltage VPUA and the output voltage VOUT. The sub-voltage VPUA is used in the semiconductor integrated circuit 101 for switch monitoring. The output voltage VOUT is used as the input/output power supply voltage VDDI in the switch monitoring semiconductor integrated circuit 101, used as the microcomputer power supply voltage MVDD in the microcomputer 301, and used as the bus interface power supply voltage BVDD in the bus interface 401. be.

A bus interface 401 communicates with the outside via a communication bus 501 such as a CAN (Controller Area Network) or LIN (Local Interconnect Network) bus.

<First Configuration Example of Switch Monitoring Semiconductor Integrated Circuit>
FIG. 2 is a diagram showing a first configuration example of the semiconductor integrated circuit 101 for switch monitoring. A switch monitoring semiconductor integrated circuit 101A (hereinafter abbreviated as “switch monitoring semiconductor integrated circuit 101A”) according to the first configuration example includes sub-voltage system switch input terminals T1 to T8 and sub-voltage system switch input terminals T1 to T8. 8 sub-voltage system detection units D1A in one-to-one correspondence with , sub-voltage system switch input terminals T9-T16, and eight sub-voltage system detection units in one-to-one correspondence with sub-voltage system switch input terminals T9-T16. A section D2A, main voltage system switch input terminals T17 to T22, and six main voltage system detection sections D3A in one-to-one correspondence with the main voltage system switch input terminals T17 to T22.

<Sub voltage system detection unit D1A>
The sub-voltage system detection unit D1A includes current sources IS1 and IS2, switches SW1 to SW5, resistors R1 and R2, a comparator COM1, and a voltage dividing circuit DIV1.

Since the switch SW3 is required to have high ESD (Electro-Static Discharge) resistance, it is preferable to use, for example, a DMOS (Double-Diffused MOSFET).

A sub-voltage VPUA is applied to one end of the current source IS1, and the other end of the current source IS1 is connected to the non-inverting input end of the comparator COM1 via the switch SW1. One end of the current source IS2 is connected to the non-inverting input terminal of the comparator COM1 via the switch SW2, and the other end of the current source IS2 is grounded. The output terminal of the voltage dividing circuit DIV1 is connected to the inverting input terminal of the comparator COM1.

As described above, the eight sub-voltage system detection units D1A correspond one-to-one to the sub-voltage system switch input terminals T1 to T8. The non-inverting input terminal of the comparator COM1 provided in the sub-voltage system detection section D1A corresponding to the sub-voltage system switch input terminal T1 is connected to the sub-voltage system switch input terminal T1 via the switch SW3. Also, the non-inverting input terminal of the comparator COM1 provided in the sub-voltage system detection section D1A corresponding to the sub-voltage system switch input terminal T2 is connected to the sub-voltage system switch input terminal T2 via the switch SW3. The same applies to the non-inverting input terminals of the comparators COM1 provided in the six sub-voltage system detection units D1A corresponding one-to-one to the sub-voltage system switch input terminals T3 to T8.

One end of the resistor R1 is connected to the non-inverting input terminal of the comparator COM1 through the switch SW4, and the other end of the resistor R1 is grounded. A sub-voltage VPUA is applied to one end of the resistor R2, and the other end of the resistor R2 is connected to the non-inverting input terminal of the comparator COM1 via the switch SW5.

The comparator COM1 is driven by the analog power supply voltage AVDD. The voltage dividing circuit DIV1 divides the reference voltage VREF to generate a divided voltage Va. The divided voltage Va is smaller than the sub-voltage VPUA. Details of the analog power supply voltage AVDD and the reference voltage VREF will be described later.

Here, as shown in FIG. 2, the case where the pole p of the mechanical switch M1 is externally attached to the sub-voltage system switch input terminal T1 via the harness H1 will be described as an example. The mechanical switch M1 selects a first mode for selectively switching between being OPEN and connecting the pole p to the first contact f, and selecting whether to be OPEN or connecting the pole p to the second contact s. and a second mode that switches temporarily, and is a three-point switch that can select either the first mode or the second mode. A sub-voltage VPUA is applied to the first contact f of the mechanical switch M1, and the second contact s of the mechanical switch M1 is grounded.

First, the case where the switches SW1 and SW3 are on and the switches SW2, SW4, and SW5 are off in the sub-voltage system detection unit D1A corresponding one-to-one to the sub-voltage system switch input terminal T1 will be described. In this case, the mechanical switch M1 is set to the second mode. If the mechanical switch M1 is OPEN, no current flows from the sub-voltage system switch input terminal T1 to the mechanical switch M1, and the potential of the sub-voltage system switch input terminal T1 substantially matches the sub-voltage VPUA. becomes high level. On the other hand, if the mechanical switch M1 is in a state where the pole p is connected to the second contact s, a current flows from the sub-voltage system switch input terminal T1 to the mechanical switch M1, and the potential of the sub-voltage system switch input terminal T1 increases. Since it is almost the same as the ground potential, the output of the comparator COM1 becomes low level.

Next, a case where the switches SW2 and SW3 are on and the switches SW1, SW4, and SW5 are off in the sub-voltage system detection section D1A corresponding to the sub-voltage system switch input terminal T1 one-to-one will be described. In this case, the mechanical switch M1 is set to the first mode. When the mechanical switch M1 connects the pole p to the first contact f, current flows from the mechanical switch M1 to the sub-voltage system switch input terminal T1, and the potential of the sub-voltage system switch input terminal T1 changes to the sub-voltage. Since it substantially matches VPUA, the output of comparator COM1 becomes high level. On the other hand, if the mechanical switch M1 is open, no current flows from the mechanical switch M1 to the sub-voltage system switch input terminal T1, and the potential of the sub-voltage system switch input terminal T1 substantially matches the ground potential. Output goes low.

Next, the case where the switches SW1 and SW4 are on and the switches SW2, SW3, and SW5 are off in the sub-voltage system detection section D1A corresponding to the sub-voltage system switch input terminal T1 one-to-one will be described. In this case, the switch monitoring semiconductor integrated circuit 101A can determine whether the current source IS1 is faulty regardless of the state of the mechanical switch M1.

If the current source IS1 does not fail, a current flows from the current source IS1 to the resistor R1, and the potential of the sub-voltage system switch input terminal T1 becomes higher than the divided voltage Va, so the output of the comparator COM1 becomes high level. For example, the output current of the current source IS1 should be 15 mA, the resistance value of the resistor R1 should be 220Ω, and the divided voltage Va should be 3V. On the other hand, if the current source IS1 fails, no current flows from the current source IS1 to the resistor R1, and the potential of the sub-voltage system switch input terminal T1 substantially matches the ground potential, so the output of the comparator COM1 is low level. become. That is, it is possible to determine whether or not the current source IS1 is faulty using the comparator COM1 that determines the state of the mechanical switch M1. The logic control unit 3 can transmit this determination result to the outside using the SPI communication unit 4 .

Next, a case where the switches SW2 and SW5 are on and the switches SW1, SW3, and SW4 are off in the sub-voltage system detection section D1A corresponding to the sub-voltage system switch input terminal T1 one-to-one will be described. In this case, the switch monitoring semiconductor integrated circuit 101A can determine whether the current source IS2 is faulty regardless of the state of the mechanical switch M1.

If the current source IS2 does not fail, current flows from the resistor R2 to the sub-voltage system switch input terminal T1, and the potential of the sub-voltage system switch input terminal T1 substantially matches the ground potential, so the output of the comparator COM1 goes low. become a level. On the other hand, if the current reducer IS2 fails, no current flows from the resistor R2 to the sub-voltage system switch input terminal T1, and the potential of the sub-voltage system switch input terminal T1 substantially matches the sub-voltage VPUA. output goes high. That is, it is possible to determine whether or not the current source IS2 is faulty using the comparator COM1 that determines the state of the mechanical switch M1. The logic control unit 3 can transmit this determination result to the outside using the SPI communication unit 4 .

The voltage applied to the first contact f of the mechanical switch M1 may be the main voltage VPUB instead of the sub-voltage VPUA.

<Sub voltage system detection unit D2A>
The sub-voltage system detection unit D2A includes a current source IS3, switches SW6 to SW8, a resistor R3, a comparator COM2, and a voltage dividing circuit DIV2.

Since the switch SW7 is required to have high ESD resistance, it is preferable to use DMOS, for example.

A sub-voltage VPUA is applied to one end of the current source IS3, and the other end of the current source IS3 is connected to the non-inverting input end of the comparator COM2 via the switch SW6. The output terminal of the voltage dividing circuit DIV2 is connected to the inverting input terminal of the comparator COM2.

As described above, the eight sub-voltage system detection units D2A correspond one-to-one to the sub-voltage system switch input terminals T9 to T16. The non-inverting input terminal of the comparator COM2 provided in the sub-voltage system detection section D2A corresponding to the sub-voltage system switch input terminal T9 is connected to the sub-voltage system switch input terminal T9 via the switch SW7. Also, the non-inverting input terminal of the comparator COM2 provided in the sub-voltage system detection section D2A corresponding to the sub-voltage system switch input terminal T10 is connected to the sub-voltage system switch input terminal T10 via the switch SW7. The same applies to the non-inverting input terminals of the comparators COM2 provided in the six sub-voltage system detection units D2A corresponding one-to-one to the sub-voltage system switch input terminals T11 to T16.

One end of the resistor R3 is connected to the non-inverting input end of the comparator COM2 via the switch SW8, and the other end of the resistor R3 is grounded.

The comparator COM2 is driven by the analog power supply voltage AVDD. The voltage dividing circuit DIV2 divides the reference voltage VREF to generate a divided voltage Va. The divided voltage Va is smaller than the sub-voltage VPUA. Details of the analog power supply voltage AVDD and the reference voltage VREF will be described later.

Here, as shown in FIG. 2, the case where one end of the mechanical switch M2 is externally attached to the sub voltage system switch input terminal T9 via the harness H2 will be described as an example. The other end of the mechanical switch M2 is grounded.

A case will be described where the switches SW6 and SW7 are on and the switch SW8 is off in the sub-voltage system detection unit D2A corresponding to the sub-voltage system switch input terminal T9 on a one-to-one basis. In this case, if the mechanical switch M2 is in the OFF state (OPEN), no current flows from the sub-voltage system switch input terminal T9 to the mechanical switch M2, and the potential of the sub-voltage system switch input terminal T9 substantially matches the sub-voltage VPUA. Therefore, the output of the comparator COM2 becomes high level. On the other hand, if the mechanical switch M2 is in the ON state (CLOSE), a current flows from the sub-voltage system switch input terminal T9 to the mechanical switch M2, and the potential of the sub-voltage system switch input terminal T9 substantially matches the ground potential. The output of comparator COM2 becomes low level.

Next, the case where the switches SW6 and SW8 are in the ON state and the switch SW7 is in the OFF state in the sub-voltage system detection section D2A corresponding to the sub-voltage system switch input terminal T9 on a one-to-one basis will be described. In this case, the switch monitoring semiconductor integrated circuit 101A can determine whether the current source IS3 is faulty regardless of the state of the mechanical switch M2.

If the current source IS3 does not fail, a current flows from the current source IS3 to the resistor R3 and the potential of the sub-voltage system switch input terminal T9 becomes higher than the divided voltage Va, so that the output of the comparator COM2 becomes high level. For example, the output current of the current source IS3 should be 15 mA, the resistance value of the resistor R3 should be 220Ω, and the divided voltage Va should be 3V. On the other hand, if the current source IS3 fails, no current flows from the current source IS3 to the resistor R3, and the potential of the sub-voltage system switch input terminal T9 substantially matches the ground potential, so the output of the comparator COM2 is low level. become. That is, it is possible to determine whether or not the current source IS3 is faulty using the comparator COM2 that determines the state of the mechanical switch M2. The logic control unit 3 can transmit this determination result to the outside using the SPI communication unit 4 .

<Main voltage system detector D3A>
The main voltage system detection unit D3A includes a current source IS4, switches SW9 to SW11, a resistor R4, a comparator COM3, and a voltage dividing circuit DIV3.

Since the switch SW01 is required to have high ESD resistance, it is preferable to use DMOS, for example.

A main voltage VPUB is applied to one end of the current source IS4, and the other end of the current source IS4 is connected to the non-inverting input end of the comparator COM3 via the switch SW9. The output terminal of the voltage dividing circuit DIV3 is connected to the inverting input terminal of the comparator COM3.

As described above, the six main voltage system detection units D3A are in one-to-one correspondence with the main voltage system switch input terminals T17 to T22. The non-inverting input terminal of the comparator COM3 provided in the main voltage system detection section D3A corresponding to the main voltage system switch input terminal T17 is connected to the main voltage system switch input terminal T17 via the switch SW10. Also, the non-inverting input terminal of the comparator COM3 provided in the main voltage system detection section D3A corresponding to the main voltage system switch input terminal T18 is connected to the main voltage system switch input terminal T18 via the switch SW10. The same applies to the non-inverting input terminals of the comparators COM3 provided in the four main voltage system detection units D3A corresponding one-to-one to the main voltage system switch input terminals T19 to T22.

One end of the resistor R4 is connected to the non-inverting input terminal of the comparator COM3 via the switch SW11, and the other end of the resistor R4 is grounded.

The comparator COM3 is driven by the analog power supply voltage AVDD. A voltage dividing circuit DIV3 divides the reference voltage VREF to generate a divided voltage Va. The divided voltage Va is smaller than the main voltage VPUB. Details of the analog power supply voltage AVDD and the reference voltage VREF will be described later.

Here, as shown in FIG. 2, the case where one end of the mechanical switch M3 is externally attached to the main voltage system switch input terminal T17 via the harness H3 will be described as an example. The other end of the mechanical switch M3 is grounded.

A case will be described where the switches SW9 and SW10 are on and the switch SW11 is off in the main voltage system detection section D3A corresponding one-to-one to the main voltage system switch input terminal T17. In this case, if the mechanical switch M3 is in the OFF state (OPEN), no current flows from the main voltage system switch input terminal T17 to the mechanical switch M3, and the potential of the main voltage system switch input terminal T17 substantially matches the main voltage VPUB. Therefore, the output of the comparator COM3 becomes high level. On the other hand, if the mechanical switch M3 is in the ON state (CLOSE), a current flows from the main voltage system switch input terminal T17 to the mechanical switch M3. The output of comparator COM3 becomes low level.

Next, a case will be described where the switches SW9 and SW11 are on and the switch SW10 is off in the main voltage system detection section D3A corresponding one-to-one to the main voltage system switch input terminal T17. In this case, the switch monitoring semiconductor integrated circuit 101A can determine whether the current source IS4 is faulty regardless of the state of the mechanical switch M3.

If the current source IS4 does not fail, a current flows from the current source IS4 to the resistor R4 and the potential of the main voltage system switch input terminal T17 becomes higher than the divided voltage Va, so that the output of the comparator COM3 becomes high level. For example, the output current of the current source IS4 should be 15 mA, the resistance value of the resistor R4 should be 220Ω, and the divided voltage Va should be 3V. On the other hand, if the current source IS4 fails, no current flows from the current source IS4 to the resistor R4, and the potential of the main voltage system switch input terminal T17 substantially matches the ground potential, so the output of the comparator COM3 is low level. become. That is, it is possible to determine whether or not the current source IS4 is faulty using the comparator COM3 which determines the state of the mechanical switch M3. The logic control unit 3 can transmit this determination result to the outside using the SPI communication unit 4 .

<Power supply unit 1, etc.>
The switch monitoring semiconductor integrated circuit 101A further includes a power supply unit 1, an oscillator 2, a logic control unit 3, an SPI (Serial Peripheral Interface) communication unit 4, and terminals T23 to T33.

Terminal T33 is connected to the ground potential. Input/output power supply voltage VDDI is applied to terminal T28. The SPI communication unit 4 is driven by the input/output power supply voltage VDDI.

A sub-voltage VPUA is applied to the terminal T23. The sub-voltage VPUA is supplied to each part using the sub-voltage VPUA. A main voltage VPUB is applied to terminal T24. The main voltage VPUB is supplied to each part using the main voltage VPUB. The power supply unit 1 steps down the main voltage VPUB to generate a reference voltage VREF (for example, a DC voltage of 5V). The reference voltage VREF is supplied to each section using the reference voltage VREF and to the terminal T25.

Further, the analog power supply voltage AVDD applied to the terminal T26 is supplied to each section using the analog power supply voltage AVDD, and the logic power supply voltage LVDD applied to the terminal T27 is supplied to the logic control section 4. Since the terminals T25, T26, and T27 are short-circuited outside the switch monitoring semiconductor integrated circuit 101A, the analog power supply voltage AVDD and the logic power supply voltage LVDD become the same voltage as the reference voltage VREF. The terminals T25 to T27 may be grounded via a common capacitor. The reason why the terminals T25 to T27 are provided is that a line to which the reference voltage VREF is applied, a line to which the analog power supply voltage AVDD is applied, and a line to which the logic power supply voltage AVDD is applied are connected to each other, unless short-circuited outside the switch monitoring semiconductor integrated circuit 101A. This is because the line to which the power supply voltage LVDD is applied can be electrically separated, which is convenient when performing an evaluation test of the switch monitoring semiconductor integrated circuit 101A.

The oscillator 2 supplies the clock signal CK to the logic controller 3 .

The logic control unit 3 operates based on the clock signal CK according to the setting written in the register. The logic control unit 3 performs SPI communication with the outside using the SPI communication unit 4 and terminals T29 to T32. A chip select bar input signal CSB is input from the outside to the SPI communication section 4 via a terminal T29. A serial clock input signal SCLK is input from the outside to the SPI communication section 4 via a terminal T30. A serial data input signal SI is input from the outside to the SPI communication section 4 via a terminal T31. The serial data output signal SO is output from the SPI communication section 4 to the outside through the terminal T32. When the chip select bar input signal CSB is at low level, the serial clock input signal SCLK, serial data input signal SI and serial data output signal SO are enabled. The serial data input signal SI includes register addresses, setting information to be written to the registers, and CRC calculation values. The serial data output signal SO includes flags, state information of each mechanical switch, failure information of each current source, and CRC calculation value.

When the logic control unit 3 is instructed from the outside via SPI communication to perform self-diagnosis on the current source IS1 of the sub-voltage system detection unit D1A corresponding to the sub-voltage system switch input terminal T1 one-to-one, the logic control unit 3 outputs the current source IS1. A control signal is generated for switching the path from the path including the mechanical switch M1 to the path including the resistor R1. That is, when the logic control unit 3 is instructed from the outside via SPI communication to execute self-diagnosis regarding the current source IS1 of the sub-voltage system detection unit D1A corresponding to the sub-voltage system switch input terminal T1 one-to-one, the logic control unit 3 turns on the switch SW3. A control signal is generated to turn off (open) the switch SW4 and turn on (close) the switch SW4, and the switches SW3 and SW4 are controlled using the control signal.

When the logic control unit 3 is instructed from the outside via SPI communication to perform self-diagnosis on the current source IS2 of the sub-voltage system detection unit D1A corresponding to the sub-voltage system switch input terminal T1 one-to-one, the logic control unit 3 outputs the current source IS2. A control signal is generated for switching the path from the path including the mechanical switch M1 to the path including the resistor R2. That is, when the logic control unit 3 is instructed from the outside via SPI communication to execute self-diagnosis regarding the current source IS2 of the sub-voltage system detection unit D1A corresponding to the sub-voltage system switch input terminal T1 one-to-one, the logic control unit 3 turns on the switch SW3. A control signal is generated to turn off (open) the switch SW5 and turn on (close) the switch SW5, and the switches SW3 and SW5 are controlled using the control signal.

When the logic control unit 3 is instructed from the outside via SPI communication to execute self-diagnosis regarding the current source IS3 of the sub-voltage system detection unit D2A corresponding to the sub-voltage system switch input terminal T9 one-to-one, the logic control unit 3 outputs the current source IS3. A control signal is generated for switching the path from the path including the mechanical switch M2 to the path including the resistor R3. That is, when the logic control unit 3 is instructed from the outside via SPI communication to perform self-diagnosis on the current source IS3 of the sub-voltage system detection unit D2A corresponding to the sub-voltage system switch input terminal T9 on a one-to-one basis, the switch SW7 is turned on. A control signal is generated to turn off (open) the switch SW8 and turn on (close) the switch SW8, and the switches SW7 and SW8 are controlled using the control signal.

When the logic control unit 3 is instructed from the outside via SPI communication to perform self-diagnosis on the current source IS4 of the main voltage system detection unit D3A corresponding to the main voltage system switch input terminal T17 one-to-one, the logic control unit 3 outputs the current source IS4. A control signal is generated for switching the path from the path including the mechanical switch M3 to the path including the resistor R4. That is, when the logic control unit 3 is instructed from the outside through SPI communication to execute self-diagnosis regarding the current source IS4 of the main voltage system detection unit D3A corresponding to the main voltage system switch input terminal T17 one-to-one, the switch SW10 is turned on. A control signal is generated to turn off (open) the switch SW11 and turn on (close) the switch SW11, and the switches SW10 and SW11 are controlled using the control signal.

<Second Configuration Example of Switch Monitoring Semiconductor Integrated Circuit>
FIG. 3 is a diagram showing a second configuration example of the semiconductor integrated circuit 101 for switch monitoring. The switch monitoring semiconductor integrated circuit 101B (hereinafter abbreviated as "switch monitoring semiconductor integrated circuit 101B") according to the second configuration example replaces the sub voltage system detection unit D1A with the sub voltage system detection unit in the switch monitoring semiconductor integrated circuit 101A. D1B, sub-voltage system detection unit D2A is replaced with sub-voltage system detection unit D2B, main voltage system detection unit D3A is replaced with main voltage system detection unit D3B, switches SW3, SW7, and SW10 are externally attached, and terminals This is a configuration in which T34 is newly provided.

The sub-voltage system detection unit D1B has a configuration in which the switch SW3 is removed from the sub-voltage system detection unit D1A. A switch SW3 is externally connected to one of the terminals T1 to T8 to which a mechanical switch is externally connected.

The sub-voltage system detection unit D2B has a configuration obtained by removing the switch SW7 from the sub-voltage system detection unit D2A. A switch SW7 is externally connected to one of the terminals T9 to T16 to which a mechanical switch is externally connected.

The main voltage system detection section D3B has a configuration in which the switch SW10 is removed from the main voltage system detection section D3A. A switch SW10 is externally connected to one of the terminals T17 to T22 to which a mechanical switch is externally connected.

The logic control unit 3 includes a current source IS1 or IS2 of the sub-voltage system detection unit D1B corresponding to the sub-voltage system switch input terminal T1 one-to-one, and a sub-voltage system detection unit corresponding to the sub-voltage system switch input terminal T9 one-to-one. A control signal is generated when an external instruction is issued via SPI communication to perform a self-diagnosis regarding the current source IS3 of D2B and the current source IS4 of the main voltage system detection unit D3B corresponding to the main voltage system switch input terminal T17 one-to-one. . The control signal is output from the terminal T33 and supplied to each control end of the switches SW3, SW7, and SW10. The control signal switches the output path of the current source IS1 or IS2 from the path including the mechanical switch M1 to the path including the resistor R1 or R2, and switches the output path of the current source IS3 from the path including the mechanical switch M2 to the path including the resistor R3. , and switches the output path of the current source IS4 from the path including the mechanical switch M3 to the path including the resistor R4. When the switches SW3, SW7, and SW10 are switches that turn off (open) when a high level signal is supplied to the control terminal, the control signal is a high level signal. On the other hand, when the execution of the self-diagnosis described above is not instructed from the outside by the SPI communication to the logic control unit 3, a low level signal is output from the terminal T34 and supplied to the respective control terminals of the switches SW3, SW7, and SW10. be.

As described above, the current source IS1 or IS2 of the sub-voltage system detection section D1B corresponding to the sub-voltage system switch input terminal T1 on a one-to-one basis, and the sub-voltage system detection section D2B corresponding to the sub-voltage system switch input terminal T9 on a one-to-one basis. and the current source IS4 of the main voltage system detector D3B corresponding to the main voltage system switch input terminal T17 on a one-to-one basis. , an increase in the number of terminals from the switch monitoring semiconductor integrated circuit 101A can be minimized.

<Third Configuration Example of Switch Monitoring Semiconductor Integrated Circuit>
FIG. 4 is a diagram showing a third configuration example of the semiconductor integrated circuit 101 for switch monitoring. A switch monitoring semiconductor integrated circuit 101C (hereinafter abbreviated as “switch monitoring semiconductor integrated circuit 101C”) according to the third configuration example replaces the sub voltage system detection unit D1B with the sub voltage system detection unit in the switch monitoring semiconductor integrated circuit 101B. D1C, the sub voltage system detection unit D2B is replaced with the sub voltage system detection unit D2C, the main voltage system detection unit D3B is replaced with the main voltage system detection unit D3C, switches SW4, SW5, SW8, and SW11 and resistors R1 to This is a configuration in which R4 is attached externally.

The sub-voltage system detection section D1C has a configuration obtained by removing the switches SW4 and SW5 and the resistors R1 and R2 from the sub-voltage system detection section D1B. A resistor R1 is externally connected through a switch SW4, and a resistor R2 is externally connected through a switch SW5 to the terminal to which the mechanical switch is externally connected among the terminals T1 to T8.

The sub-voltage system detection unit D2C has a configuration obtained by removing the switch SW8 and the resistor R3 from the sub-voltage system detection unit D2B. A resistor R3 is externally connected via a switch SW8 to one of the terminals T9 to T16 to which a mechanical switch is externally connected.

The main voltage system detection section D3C has a configuration obtained by removing the switch SW11 and the resistor R4 from the main voltage system detection section D3B. A resistor R4 is externally connected via a switch SW11 to one of the terminals T17 to T22 to which a mechanical switch is externally connected.

The logic control unit 3 includes a current source IS1 or IS2 of the sub-voltage system detection unit D1C corresponding to the sub-voltage system switch input terminal T1 one-to-one, and a sub-voltage system detection unit corresponding to the sub-voltage system switch input terminal T9 one-to-one. A control signal is generated when an external instruction is given via SPI communication to execute a self-diagnosis regarding the current source IS3 of the D2C and the current source IS4 of the main voltage system detection unit D3C corresponding to the main voltage system switch input terminal T17 on a one-to-one basis. . The control signal is output from the terminal T33 and supplied to each control end of the switches SW3, SW7, and SW10. The control signal switches the output path of the current source IS1 or IS2 from the path including the mechanical switch M1 to the path including the resistor R1 or R2, and switches the output path of the current source IS3 from the path including the mechanical switch M2 to the path including the resistor R3. , and switches the output path of the current source IS4 from the path including the mechanical switch M3 to the path including the resistor R4. When the switches SW3, SW4, SW5, SW7, SW8, SW10, and SW11 are switches that turn off (open) when a high level signal is supplied to the control terminal, the control signal is a high level signal. becomes. Then, a NOT gate (not shown) that inverts the logic level of the control signal and outputs it is externally connected to the terminal T34, and the output signal of the NOT gate is sent to each control end of the switches SW4, SW5, SW8, and SW11. supply. However, when the output signal of the NOT gate is a low level signal, the conversion unit for converting only the signal supplied to either one of the switches SW4 and SW5 to a high level signal is connected to the NOT gate and the switch SW4. and SW5. On the other hand, when the execution of the self-diagnosis described above is not instructed from the outside by the SPI communication to the logic control unit 3, a low-level signal is output from the terminal T33 and supplied to the respective control terminals of the switches SW3, SW7, and SW10. , a high-level signal is supplied to each control end of the switches SW4, SW5, SW8, and SW11 from the NOT gate.

With the above configuration, the switch monitoring semiconductor integrated circuit 101C can have the same number of terminals as the switch monitoring semiconductor integrated circuit 101B.

<Fourth Configuration Example of Switch Monitoring Semiconductor Integrated Circuit>
FIG. 5 is a diagram showing a fourth configuration example of the semiconductor integrated circuit 101 for switch monitoring. A switch monitoring semiconductor integrated circuit 101D (hereinafter abbreviated as "switch monitoring semiconductor integrated circuit 101D") according to the fourth configuration example replaces the sub voltage system detection section D1A with the sub voltage system detection section in the switch monitoring semiconductor integrated circuit 101A. D1D, the sub-voltage system detection unit D2A is replaced with the sub-voltage system detection unit D2D, and the main voltage system detection unit D3A is replaced with the main voltage system detection unit D3D. In addition, in FIG. 5, illustration of the power supply unit 1 and the like is omitted.

The sub-voltage system detection unit D1D is configured by adding backup current sources IS5 and IS6 and switches SW12 and SW13 to the sub-voltage system detection unit D1A. A series circuit of standby current source IS5 and switch SW12 is connected in parallel to the series circuit of current source IS1 and switch SW1. A series circuit of standby current source IS6 and switch SW13 is connected in parallel to a series circuit of current source IS2 and switch SW2.

The sub-voltage system detection section D2D is configured by adding a standby current source IS7 and a switch SW14 to the sub-voltage system detection section D2A. A series circuit of standby current source IS7 and switch SW14 is connected in parallel to a series circuit of current source IS3 and switch SW6.

The main voltage system detection section D3D is configured by adding a standby current source IS8 and a switch SW15 to the main voltage system detection section D3A. A series circuit of standby current source IS8 and switch SW15 is connected in parallel to a series circuit of current source IS4 and switch SW9.

The logic control unit 3 turns on (closes) the switch corresponding to the current source in which the failure has been detected among the switches SW12 to SW15, so that the backup current source can be used instead of the current source in which the failure has been detected. can. It should be noted that a plurality of detection units may share a backup current source. For example, the auxiliary current source IS5 may be shared by the sub-voltage system detection unit D1D corresponding to the terminal T1 one-to-one and the sub-voltage system detection unit D1D corresponding to the terminal T2 one-to-one.

Also, the current capability of the standby current source may be lower than the current capability of the corresponding current source (for example, the current source IS1 in the case of the standby current source IS5). If a backup current source with a low current capability is used, the effect of removing the oxide film adhering to the monitored switch will be low, and the ability to prevent malfunction of the monitored switch itself will be reduced. Therefore, it is desirable to reduce the circuit scale of the standby current source by lowering the current capability. The current capability means the maximum value of current that the current source can output.

<Fifth Configuration Example of Switch Monitoring Semiconductor Integrated Circuit>
FIG. 6 is a diagram showing a fifth configuration example of the semiconductor integrated circuit 101 for switch monitoring. A switch monitoring semiconductor integrated circuit 101E (hereinafter abbreviated as "switch monitoring semiconductor integrated circuit 101E") according to the fifth configuration example replaces the sub voltage system detection unit D1A with the sub voltage system detection unit in the switch monitoring semiconductor integrated circuit 101A. D1E, the sub-voltage system detection unit D2A is replaced with the sub-voltage system detection unit D2E, and the main voltage system detection unit D3A is replaced with the main voltage system detection unit D3E. 6, illustration of the power supply unit 1 and the like is omitted.

The sub-voltage system detection unit D1E has a configuration in which a switch SW16, a comparator COM4, and a voltage dividing circuit DIV4 are added to the sub-voltage system detection unit D1A.

The non-inverting input terminal of the comparator COM4 is connected to the non-inverting input terminal of the comparator COM1 and the switches SW1 to SW5 via the switch SW16. The output terminal of the voltage dividing circuit DIV4 is connected to the inverting input terminal of the comparator COM4. The comparator COM4 is driven by the analog power supply voltage AVDD. The logic control unit 3 turns the switch SW16 on (closed) when performing self-diagnosis on the comparator COM1, and turns the switch SW16 off (open) otherwise. Therefore, the comparator COM4 is less likely to be damaged by ESD than the comparator COM1, and is less likely to fail than the comparator COM1.

If comparators COM1 and COM4 are not faulty, the output of comparator COM1 and the output of comparator COM4 will match. On the other hand, when the comparator COM1 is out of order and the comparator COM4 is not out of order, the output of the comparator COM1 and the output of the comparator COM4 may not match.

In this configuration example, the logic control unit 3 includes a negative exclusive OR gate 31 to which the output of the comparator COM1 and the output of the comparator COM4 are input. If the output of negative exclusive OR gate 31 is at a low level, it can be assumed that comparator COM1 is faulty. Note that, unlike this configuration example, the logic control unit 3 does not include the negative exclusive OR gate 31, and is configured to transmit information regarding the output of the comparator COM1 and the output of the comparator COM4 to the outside via the SPI communication unit 4. can be In this case, it may be determined externally whether or not the output of the comparator COM1 and the output of the comparator COM4 match.

The sub-voltage system detection unit D2E is configured by adding a switch SW17, a comparator COM5, and a voltage dividing circuit DIV5 to the sub-voltage system detection unit D2A.

The non-inverting input terminal of comparator COM5 is connected to the non-inverting input terminal of comparator COM2 and switches SW7 and SW8 via switch SW17. The output terminal of the voltage dividing circuit DIV5 is connected to the inverting input terminal of the comparator COM5. The comparator COM5 is driven by the analog power supply voltage AVDD. The logic control unit 3 turns the switch SW17 on (closed) when performing self-diagnosis on the comparator COM2, and turns the switch SW17 off (open) otherwise. Therefore, the comparator COM5 is less likely to be damaged by ESD than the comparator COM2, and is less likely to fail than the comparator COM2.

If comparators COM2 and COM5 are not faulty, the output of comparator COM2 and the output of comparator COM5 will match. On the other hand, when the comparator COM2 is out of order and the comparator COM5 is not out of order, the output of the comparator COM2 may not match the output of the comparator COM5.

In this configuration example, the logic control unit 3 includes a negative exclusive OR gate 32 to which the output of the comparator COM2 and the output of the comparator COM5 are input. If the output of NEX-OR gate 32 is at a low level, it can be assumed that comparator COM2 has failed. Note that, unlike this configuration example, the logic control unit 3 does not include the negative exclusive OR gate 32, and transmits information about the output of the comparator COM2 and the output of the comparator COM5 to the outside via the SPI communication unit 4. can be In this case, it may be determined externally whether or not the output of the comparator COM2 and the output of the comparator COM5 match.

The main voltage system detection section D3E is configured by adding a switch SW18, a comparator COM6, and a voltage dividing circuit DIV6 to the main voltage system detection section D3A.

The non-inverting input terminal of comparator COM6 is connected to the non-inverting input terminal of comparator COM3 and switches SW10 and SW11 via switch SW18. The output terminal of the voltage dividing circuit DIV6 is connected to the inverting input terminal of the comparator COM6. The comparator COM6 is driven by the analog power supply voltage AVDD. The logic control unit 3 turns the switch SW18 on (closed) when performing self-diagnosis on the comparator COM3, and turns the switch SW18 off (open) otherwise. Therefore, the comparator COM6 is less likely to be damaged by ESD than the comparator COM3, and is less likely to fail than the comparator COM3.

If comparators COM3 and COM6 are not faulty, the output of comparator COM3 and the output of comparator COM6 will match. On the other hand, when the comparator COM3 is out of order and the comparator COM6 is not out of order, the output of the comparator COM3 may not match the output of the comparator COM6.

In this configuration example, the logic control unit 3 includes a negative exclusive OR gate 33 to which the output of the comparator COM3 and the output of the comparator COM6 are input. If the output of negative exclusive OR gate 33 is at a low level, it can be assumed that comparator COM3 has failed. Note that, unlike this configuration example, the logic control unit 3 does not include the negative exclusive OR gate 33, and transmits information about the output of the comparator COM3 and the output of the comparator COM6 to the outside via the SPI communication unit 4. can be In this case, it may be determined externally whether or not the output of the comparator COM3 and the output of the comparator COM6 match.

<Application>
The electronic control unit U1 described above can be mounted, for example, on a vehicle X1 shown in FIG. In this case, as the mechanical switches connected to the main voltage system switch input terminals T17 to T22, for example, a door opening/closing switch, a door lock switch, etc. can be considered. Mechanical switches connected to the sub-voltage system switch input terminals T1 to T16 include, for example, power window switches, door mirror switches, cam signal switches, air flow switches, throttle opening/closing switches, and the like. When the electronic control unit U1 is installed in the vehicle X1 shown in FIG. 7, the main voltage VPUB may be the output voltage of the battery installed in the vehicle X1.

Further, the electronic control unit U1 may be applied to, for example, the field of industrial machinery other than the vehicle.

<Points to note>
Various modifications can be made to the various technical features disclosed in this specification without departing from the gist of the technical creation in addition to the above-described embodiments. Also, multiple embodiments and modifications may be implemented in combination within a possible range. For example, in the above embodiment, SPI communication is used for communication between the switch monitoring semiconductor integrated circuit 101 and the microcomputer 301, but other serial communication (for example, I2C communication) may be used. may be used. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments. It is to be understood that a range and equivalents are meant to include all changes that fall within the range.

101, 101A to 101E Switch monitoring semiconductor integrated circuit COM1 to COM6 Comparator IS1 to IS4 Current source IS5 to IS8 Standby current source M1 to M3 Mechanical switch T1 to T16 Sub voltage system switch input terminal T17 to T22 Main voltage system switch input terminal U1 Electronic control unit X1 vehicle

Claims (11)

a switch input terminal to which a switch to be monitored can be connected;
a current source configured to be connectable to the switch input terminal;
a first determination unit that determines the voltage level of the switch input terminal;
a generator that generates a control signal for switching an output path of the current source from a first path including the monitored switch to a second path including a load;
A semiconductor integrated circuit for switch monitoring. the load;
a first open/close switch provided between the current source and the first determination unit and the load,
2. The semiconductor integrated circuit for switch monitoring according to claim 1, wherein said first open/close switch is closed by said control signal. a second open/close switch provided between the current source and the first determination unit and the switch input terminal;
3. The switch monitoring semiconductor integrated circuit according to claim 1, wherein said second switch is opened by said control signal. a backup current source;
a switching unit that enables the backup current source to be used instead of the current source;
4. The semiconductor integrated circuit for switch monitoring according to claim 1, comprising: 5. The semiconductor integrated circuit for switch monitoring according to claim 4, wherein said standby current source has a lower current capability than said current source. A plurality of sets of the switch input terminal, the current source, and the first determination unit,
6. The switch monitoring semiconductor integrated circuit according to claim 4, wherein at least two of said plurality of sets share said spare current source. a second determination unit that determines the voltage level of the switch input terminal;
7. The semiconductor integrated circuit for switch monitoring according to claim 1, comprising said switch input terminal and a third open/close switch provided between said first determination section and said second determination section. . 8. The semiconductor integrated circuit for switch monitoring according to claim 7, wherein said third open/close switch is closed by said control signal. 9. The semiconductor integrated circuit for switch monitoring according to claim 7, further comprising a confirmation unit for confirming whether or not the determination result of said first determination unit and the determination result of said second determination unit match. a switch monitoring semiconductor integrated circuit according to any one of claims 1 to 9;
and a microcomputer that receives a monitoring result transmitted from the switch monitoring semiconductor integrated circuit. an electronic control unit according to claim 10;
and the monitored switch.

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